feat(ras): Add support for FFH CPU CE error injection

Enable CPU CE(Corrected Error) injection by writing expected
value to ERXMISC0 register, inducing a Corrected error.
ERXPFGCTL.MV bit is set to ensure ERXMISC0 register is flagged
as valid in the ERXSTATUS register, allowing proper handling by
error handler.

Signed-off-by: Glen Yeldho <glen.yeldho@arm.com>
Change-Id: I6ebe926b3d60793752e9a1e48853b69d37135db5