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Commit 6de9b336 authored by Eleanor Bonnici's avatar Eleanor Bonnici Committed by Jeenu Viswambharan
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Cortex-A72: Implement workaround for erratum 859971 



Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.

Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: default avatarEleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
parent 45b52c20
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