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  1. Mar 07, 2023
  2. Mar 06, 2023
    • Wu, Jiaxin's avatar
      OvmfPkg/SmmCpuFeaturesLib: Check SmBase relocation supported or not · a1d595fc
      Wu, Jiaxin authored
      REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337
      
      
      
      This patch is to check SmBase relocation supported or not.
      If gSmmBaseHobGuid found, means SmBase info has been relocated
      and recorded in the SmBase array. ASSERT it's not supported in OVMF.
      
      Cc: Eric Dong <eric.dong@intel.com>
      Cc: Ray Ni <ray.ni@intel.com>
      Cc: Zeng Star <star.zeng@intel.com>
      Cc: Laszlo Ersek <lersek@redhat.com>
      Cc: Gerd Hoffmann <kraxel@redhat.com>
      Cc: Rahul Kumar <rahul1.kumar@intel.com>
      Signed-off-by: default avatarJiaxin Wu <jiaxin.wu@intel.com>
      Reviewed-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Reviewed-by: default avatarRay Ni <ray.ni@intel.com>
      a1d595fc
    • Wu, Jiaxin's avatar
      UefiCpuPkg/SmmCpuFeaturesLib: Skip SMBASE configuration · f6b86eec
      Wu, Jiaxin authored
      REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337
      
      
      
      This patch is to avoid configure SMBASE if SmBase relocation has been
      done. If gSmmBaseHobGuid found, means SmBase info has been relocated
      and recorded in the SmBase array. No need to do the relocation in
      SmmCpuFeaturesInitializeProcessor().
      
      Cc: Eric Dong <eric.dong@intel.com>
      Cc: Ray Ni <ray.ni@intel.com>
      Cc: Zeng Star <star.zeng@intel.com>
      Cc: Laszlo Ersek <lersek@redhat.com>
      Acked-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Cc: Rahul Kumar <rahul1.kumar@intel.com>
      Signed-off-by: default avatarJiaxin Wu <jiaxin.wu@intel.com>
      Reviewed-by: default avatarRay Ni <ray.ni@intel.com>
      f6b86eec
    • Wu, Jiaxin's avatar
      UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info · ec07fd0e
      Wu, Jiaxin authored
      REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337
      
      
      
      Existing SMBASE Relocation is in the PiSmmCpuDxeSmm driver, which
      will relocate the SMBASE of each processor by setting the SMBASE
      field in the saved state map (at offset 7EF8h) to a new value.
      The RSM instruction reloads the internal SMBASE register with the
      value in SMBASE field when each time it exits SMM. All subsequent
      SMI requests will use the new SMBASE to find the starting address
      for the SMI handler (at SMBASE + 8000h).
      
      Due to the default SMBASE for all x86 processors is 0x30000, the
      APs' 1st SMI for rebase has to be executed one by one to avoid
      the processors over-writing each other's SMM Save State Area (see
      existing SmmRelocateBases() function), which means the next AP has
      to wait for the previous AP to finish its 1st SMI, then it can call
      into its 1st SMI for rebase via Smi Ipi command, thus leading the
      existing SMBASE Relocation has to be running in series. Besides, it
      needs very complex code to handle the AP exit semaphore
      (mRebased[Index]), which will hook return address of SMM Save State
      so that semaphore code can be executed immediately after AP exits
      SMM for SMBASE relocation (see existing SemaphoreHook() function).
      
      With SMM Base Hob support, PiSmmCpuDxeSmm does not need the RSM
      instruction to do the SMBASE Relocation. SMBASE Register for each
      processors have already been programmed and all SMBASE address have
      recorded in SMM Base Hob. So the same default SMBASE Address
      (0x30000) will not be used, thus the processors over-writing each
      other's SMM Save State Area will not happen in PiSmmCpuDxeSmm driver.
      This way makes the first SMI init can be executed in parallel and
      save boot time on multi-core system. Besides, Semaphore Hook code
      logic is also not required, which will greatly simplify the SMBASE
      Relocation flow.
      
      Mainly changes as below:
      * Assume the biggest possibility of tile size is 8k.
      * Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one
      (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths:
      one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core
      Entry Point.
      * Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for first
      SMI init before normal SMI sources happen.
      * Call SmmCpuFeaturesInitializeProcessor() in parallel.
      
      Cc: Eric Dong <eric.dong@intel.com>
      Cc: Ray Ni <ray.ni@intel.com>
      Cc: Zeng Star <star.zeng@intel.com>
      Cc: Laszlo Ersek <lersek@redhat.com>
      Acked-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Cc: Rahul Kumar <rahul1.kumar@intel.com>
      Signed-off-by: default avatarJiaxin Wu <jiaxin.wu@intel.com>
      Reviewed-by: default avatarRay Ni <ray.ni@intel.com>
      ec07fd0e
    • Wu, Jiaxin's avatar
      UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data · 7b8c5a8e
      Wu, Jiaxin authored
      REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337
      
      
      
      The default SMBASE for the x86 processor is 0x30000. When
      SMI happens, processor runs the SMI handler at SMBASE+0x8000.
      Also, the SMM save state area is within SMBASE+0x10000.
      
      One of the SMM initialization from processor perspective is to
      relocate and program the new SMBASE (in TSEG range) for each
      processor. When the SMBASE relocation happens in a PEI module,
      the PEI module shall produce the SMM_BASE_HOB in HOB database
      which tells the PiSmmCpuDxeSmm driver (runs at a later phase)
      about the new SMBASE for each processor. PiSmmCpuDxeSmm driver
      installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000
      for processor Index. When the HOB doesn't exist, PiSmmCpuDxeSmm
      driver shall relocate and program the new SMBASE itself.
      
      This patch adds the SMM Base HOB for any PEI module to do
      the SmBase relocation ahead of PiSmmCpuDxeSmm driver and
      store the relocated SmBase address in array for each
      processor.
      
      Cc: Eric Dong <eric.dong@intel.com>
      Cc: Ray Ni <ray.ni@intel.com>
      Cc: Zeng Star <star.zeng@intel.com>
      Cc: Laszlo Ersek <lersek@redhat.com>
      Cc: Gerd Hoffmann <kraxel@redhat.com>
      Cc: Rahul Kumar <rahul1.kumar@intel.com>
      Signed-off-by: default avatarJiaxin Wu <jiaxin.wu@intel.com>
      Acked-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Reviewed-by: default avatarRay Ni <ray.ni@Intel.com>
      7b8c5a8e
    • Wu, Jiaxin's avatar
      UefiCpuPkg/PiSmmCpuDxeSmm: Replace mIsBsp by mBspApicId check · 85c6c14c
      Wu, Jiaxin authored
      
      
      This patch is to replace mIsBsp by mBspApicId check.
      mIsBsp becomes the local variable (IsBsp), then it can be
      checked dynamically in the function. Instead, we define the
      mBspApicId, which is to record the BSP ApicId used for
      compare in SmmInitHandler. With this change, SmmInitHandler
      can be run in parallel during SMM init.
      
      Note:
      This patch is the per-prepared work by refining the
      SmmInitHandler, then, we can do the next step to
      combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate)
      into one (gcSmiHandlerTemplate), the new SMI handler
      will call the SmmInitHandler in parallel to do the init.
      
      Cc: Eric Dong <eric.dong@intel.com>
      Cc: Ray Ni <ray.ni@intel.com>
      Cc: Zeng Star <star.zeng@intel.com>
      Cc: Laszlo Ersek <lersek@redhat.com>
      Cc: Gerd Hoffmann <kraxel@redhat.com>
      Cc: Rahul Kumar <rahul1.kumar@intel.com>
      Signed-off-by: default avatarJiaxin Wu <jiaxin.wu@intel.com>
      Reviewed-by: default avatarRay Ni <ray.ni@intel.com>
      Reviewed-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      85c6c14c
    • Wu, Jiaxin's avatar
      UefiCpuPkg/PiSmmCpuDxeSmm: Fix invalid InitializeMpSyncData call · cb4820b6
      Wu, Jiaxin authored
      REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4338
      
      
      
      No need call InitializeMpSyncData during normal boot SMI init,
      because mSmmMpSyncData is NULL at that time. mSmmMpSyncData is
      allocated in InitializeMpServiceData, which is invoked after
      normal boot SMI init (SmmRelocateBases).
      
      Cc: Eric Dong <eric.dong@intel.com>
      Cc: Ray Ni <ray.ni@intel.com>
      Cc: Zeng Star <star.zeng@intel.com>
      Cc: Laszlo Ersek <lersek@redhat.com>
      Cc: Gerd Hoffmann <kraxel@redhat.com>
      Cc: Rahul Kumar <rahul1.kumar@intel.com>
      Signed-off-by: default avatarJiaxin Wu <jiaxin.wu@intel.com>
      Acked-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Reviewed-by: default avatarRay Ni <ray.ni@Intel.com>
      cb4820b6
    • Nickle Wang's avatar
      RedfishPkg/RedfishDebugLib: provide Redfish debug · 5a0932b7
      Nickle Wang authored
      
      
      Introduce RedfishDebugLib to RedfishPkg. This library provides several
      debugging functions for Redfish application. Redfish drivers rely on
      Rest Ex protocol to communicate with BMC and the communication data
      may be big and complicated. Use RedfishDebugLib in RedfishRestExDxe to
      simplify debugging process.
      
      Signed-off-by: default avatarNickle Wang <nicklew@nvidia.com>
      Cc: Abner Chang <abner.chang@amd.com>
      Cc: Igor Kulchytskyy <igork@ami.com>
      Cc: Nick Ramirez <nramirez@nvidia.com>
      Reviewed-by: default avatarAbner Chang <abner.chang@amd.com>
      5a0932b7
    • Rebecca Cran's avatar
      ShellPkg: Improve "ping" output by adding equals sign after time · fc14c809
      Rebecca Cran authored
      
      
      The output of the "ping" command shows the time without a space between
      the label and the value. e.g.:
      
      20 bytes from 192.168.0.1 : icmp_seq=1 ttl=1 time1~2ms
      
      Improve the readability and consistency by adding an equals sign for the
      time value:
      
      20 bytes from 192.168.0.1 : icmp_seq=1 ttl=1 time=1~2ms
      
      Signed-off-by: default avatarRebecca Cran <rebecca@quicinc.com>
      Reviewed-by: default avatarZhichao Gao <zhichao.gao@intel.com>
      fc14c809
  3. Mar 01, 2023
  4. Feb 23, 2023
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