- Mar 07, 2023
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Pierre Gondois authored
On Arm platforms, the number of available RNG algorithms is dynamically detected and can be 0 in the absence of FEAT_RNG and firmware TRNG. In this case, the EFI_RNG_PROTOCOL should not be installed to prevent from installing an empty protocol. Signed-off-by:
Pierre Gondois <Pierre.Gondois@arm.com> [ardb: return EFI_REQUEST_UNLOAD_IMAGE instead of an error] Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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Pierre Gondois authored
mAvailableAlgoArrayCount holds the count of available RNG algorithms. In a following patch, its value will be used to prevent the EFI_RNG_PROTOCOL to be installed if no RNG algorithm is available. Correctly set/reset the value for all implementations. Signed-off-by:
Pierre Gondois <pierre.gondois@arm.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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Zhiguang Liu authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4348 Per SDM: DisplayFamily = Extended_Family_ID + Family_ID. DisplayModelID = (Extended_Model_ID << 4) + Family_ID. Correct the related code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Star Zeng <star.zeng@intel.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Signed-off-by:
Zhiguang Liu <zhiguang.liu@intel.com>
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Gerd Hoffmann authored
In openssl 3.0 SHA512() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Jiewen Yao <jiewen.yao@intel.com>
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Gerd Hoffmann authored
In openssl 3.0 SHA384() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Jiewen Yao <jiewen.yao@intel.com>
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Gerd Hoffmann authored
In openssl 3.0 SHA256() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Jiewen Yao <jiewen.yao@intel.com>
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Gerd Hoffmann authored
In openssl 3.0 SHA1() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Jiewen Yao <jiewen.yao@intel.com>
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Xie, Yuanhao authored
Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Yuanhao Xie authored
Rename AsmRelocateApLoopStart to AsmRelocateApLoopStartAmdSev Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Xie, Yuanhao authored
Add the 'AsmRelocateApLoopStartGeneric' for X64 processors except 64-bit AMD processors with SEV-ES. Remove the unused arguments of AsmRelocateApLoopStartGeneric, updated the stack offset. Create PageTable for the allocated reserved memory. Only keep 4GB limitation of memory allocation for the case APs still need to be transferred to 32-bit mode before OS. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Xie, Yuanhao authored
Add CpuPageTableLib required by MpInitLib in UefiPayloadPkg. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Yuanhao Xie authored
Add CpuPageTableLib required by MpInitLib in OvmfPkg. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Xie, Yuanhao authored
Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Xie, Yuanhao authored
Add the union RELOCATE_AP_LOOP_ENTRY, split the path in RelocateApLoop into two: 1. 64-bit AMD processors with SEV-ES 2. Intel processors (32-bit or 64-bit), 32-bit AMD processors, or 64-bit AMD processors without SEV-ES. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Xie, Yuanhao authored
Check if AP_SAFE_STACK_SIZE is aligned with CPU_STACK_ALIGNMENT during build time. No functional or structural changes. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by:
Yuanhao Xie <yuanhao.xie@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Rebecca Cran authored
Improve the formatting of DEBUG messages in UsbBusDxe by adding a hyphen to separate the EFI_STATUS code. Signed-off-by:
Rebecca Cran <rebecca@bsdio.com> Reviewed-by:
Hao A Wu <hao.a.wu@intel.com>
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- Mar 06, 2023
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Wu, Jiaxin authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 This patch is to check SmBase relocation supported or not. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. ASSERT it's not supported in OVMF. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by:
Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Wu, Jiaxin authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by:
Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Wu, Jiaxin authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 Existing SMBASE Relocation is in the PiSmmCpuDxeSmm driver, which will relocate the SMBASE of each processor by setting the SMBASE field in the saved state map (at offset 7EF8h) to a new value. The RSM instruction reloads the internal SMBASE register with the value in SMBASE field when each time it exits SMM. All subsequent SMI requests will use the new SMBASE to find the starting address for the SMI handler (at SMBASE + 8000h). Due to the default SMBASE for all x86 processors is 0x30000, the APs' 1st SMI for rebase has to be executed one by one to avoid the processors over-writing each other's SMM Save State Area (see existing SmmRelocateBases() function), which means the next AP has to wait for the previous AP to finish its 1st SMI, then it can call into its 1st SMI for rebase via Smi Ipi command, thus leading the existing SMBASE Relocation has to be running in series. Besides, it needs very complex code to handle the AP exit semaphore (mRebased[Index]), which will hook return address of SMM Save State so that semaphore code can be executed immediately after AP exits SMM for SMBASE relocation (see existing SemaphoreHook() function). With SMM Base Hob support, PiSmmCpuDxeSmm does not need the RSM instruction to do the SMBASE Relocation. SMBASE Register for each processors have already been programmed and all SMBASE address have recorded in SMM Base Hob. So the same default SMBASE Address (0x30000) will not be used, thus the processors over-writing each other's SMM Save State Area will not happen in PiSmmCpuDxeSmm driver. This way makes the first SMI init can be executed in parallel and save boot time on multi-core system. Besides, Semaphore Hook code logic is also not required, which will greatly simplify the SMBASE Relocation flow. Mainly changes as below: * Assume the biggest possibility of tile size is 8k. * Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. * Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for first SMI init before normal SMI sources happen. * Call SmmCpuFeaturesInitializeProcessor() in parallel. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by:
Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Wu, Jiaxin authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 The default SMBASE for the x86 processor is 0x30000. When SMI happens, processor runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from processor perspective is to relocate and program the new SMBASE (in TSEG range) for each processor. When the SMBASE relocation happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE for each processor. PiSmmCpuDxeSmm driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program the new SMBASE itself. This patch adds the SMM Base HOB for any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for each processor. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by:
Jiaxin Wu <jiaxin.wu@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@Intel.com>
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Wu, Jiaxin authored
This patch is to replace mIsBsp by mBspApicId check. mIsBsp becomes the local variable (IsBsp), then it can be checked dynamically in the function. Instead, we define the mBspApicId, which is to record the BSP ApicId used for compare in SmmInitHandler. With this change, SmmInitHandler can be run in parallel during SMM init. Note: This patch is the per-prepared work by refining the SmmInitHandler, then, we can do the next step to combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler will call the SmmInitHandler in parallel to do the init. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by:
Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com> Reviewed-by:
Gerd Hoffmann <kraxel@redhat.com>
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Wu, Jiaxin authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4338 No need call InitializeMpSyncData during normal boot SMI init, because mSmmMpSyncData is NULL at that time. mSmmMpSyncData is allocated in InitializeMpServiceData, which is invoked after normal boot SMI init (SmmRelocateBases). Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by:
Jiaxin Wu <jiaxin.wu@intel.com> Acked-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Ray Ni <ray.ni@Intel.com>
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Nickle Wang authored
Introduce RedfishDebugLib to RedfishPkg. This library provides several debugging functions for Redfish application. Redfish drivers rely on Rest Ex protocol to communicate with BMC and the communication data may be big and complicated. Use RedfishDebugLib in RedfishRestExDxe to simplify debugging process. Signed-off-by:
Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by:
Abner Chang <abner.chang@amd.com>
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Rebecca Cran authored
The output of the "ping" command shows the time without a space between the label and the value. e.g.: 20 bytes from 192.168.0.1 : icmp_seq=1 ttl=1 time1~2ms Improve the readability and consistency by adding an equals sign for the time value: 20 bytes from 192.168.0.1 : icmp_seq=1 ttl=1 time=1~2ms Signed-off-by:
Rebecca Cran <rebecca@quicinc.com> Reviewed-by:
Zhichao Gao <zhichao.gao@intel.com>
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- Mar 01, 2023
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Sunil V L authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4350 Currently, stack HOB is not created for the stack memory. This causes stack memory to be treated as free memory and any memory allocation which happens at this address causes random memory corruption. Fix this by creating the stack HOB which marks the memory as BS data. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Reported-by:
Andrei Warkentin <andrei.warkentin@intel.com> Tested-by:
Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com>
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- Feb 23, 2023
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MarsX Lin authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4241 Since UefiPayloadPkg had supported multiple firmware volume, remove the platform specific logic via protocol Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by:
James Lu <james.lu@intel.com> Reviewed-by:
Guo Dong <guo.dong@intel.com> Signed-off-by:
MarsX Lin <marsx.lin@intel.com>
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Sunil V L authored
Fix the UEFI memory range calculation by including the correct stack memory range. Without this fix, SCT hangs in MemoryAllocation test cases which call AllocateAddress(). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Reported-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com>
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Sunil V L authored
Replace rv64imafdc with rv64gc so that it works for gcc 12. "g" means imafd in gcc < 12 and imafd_zifencei_zicsr in gcc >= 12. So, replacing rv64imafdc with rv64gc will work for both gcc <12 and gcc >=12. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Tested-by:
Gerd Hoffmann <kraxel@redhat.com> Tested-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Liming Gao <gaoliming@byosoft.com.cn>
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- Feb 16, 2023
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Joey Vagedes authored
This patch updates edk2-pytool-library dependency to v0.14.0, which has an interface change to FindWithVsWhere. The BaseTools plugin uses this function, so it is being updated to account for the interface change. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by:
Joey Vagedes <joeyvagedes@microsoft.com> Acked-by:
Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by:
Liming Gao <gaoliming@byosoft.com.cn>
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Sunil V L authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RiscVVirt is created to support EDK2 for RISC-V qemu virt machine platform. Add maintainer entries. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by:
Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by:
Michael D Kinney <michael.d.kinney@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org>
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Sunil V L authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - It follows PEI less design. - EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW - Leveraged from ArmVirtQemu Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org> Acked-by:
Jiewen Yao <Jiewen.yao@intel.com>
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Sunil V L authored
Add the SEC module for RISC-V Qemu virt machine support. It uses the PEI less design. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Jiewen Yao <Jiewen.yao@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org>
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Sunil V L authored
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL to add the translation for IO access. This is copied from ArmPciCpuIo2Dxe driver. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org> Acked-by:
Jiewen Yao <Jiewen.yao@intel.com>
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Sunil V L authored
Qemu NOR flash driver needs this library. Add this library for RISC-V leveraged from SbsaQemu. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Jiewen Yao <Jiewen.yao@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org>
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Sunil V L authored
RISC-V Qemu virt uses SBI calls to implement the reset. Add the base class library. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org> Acked-by:
Jiewen Yao <Jiewen.yao@intel.com>
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Sunil V L authored
Add the PrePiHobListPointerLib required for RISC-V Qemu Virt machine since it follows PEIless design. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Jiewen Yao <Jiewen.yao@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org>
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Sunil V L authored
RISC-V Qemu Virt platfform needs the PlatformBootManagerLib similar to the one in ArmVirtPlatform. Add the library in OvmfPkg/RiscVVirt leveraging the one from Arm. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org> Acked-by:
Jiewen Yao <Jiewen.yao@intel.com>
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Sunil V L authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 PlatformHasAcpiDtDxe is required by other architectures also. Hence, it is moved to OvmfPkg. So, update the consumers of this module with the new location. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org>
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Sunil V L authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This module is required by other architectures like RISC-V. Hence, move this to OvmfPkg. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com>
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Sunil V L authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Acked-by:
Abner Chang <abner.chang@amd.com> Reviewed-by:
Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by:
Michael D Kinney <michael.d.kinney@intel.com> Acked-by:
Ray Ni <ray.ni@intel.com>
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