- Apr 09, 2019
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Michael D Kinney authored
Add text file that contains the history of license and contributor agreement changes. https://bugzilla.tianocore.org/show_bug.cgi?id=1373 This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by:
Laszlo Ersek <lersek@redhat.com>
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Ray Ni authored
Reserved6 is changed to Reserved7 because the bit width is changed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Ray Ni <ray.ni@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com>
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- Apr 08, 2019
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Ray Ni authored
GetProcessorLocation2ByApicId() extracts the package/die/tile/module/core/thread ID from the initial APIC ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Ray Ni <ray.ni@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
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- Apr 04, 2019
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Ray Ni authored
Leaf 1FH is very similar to leaf 0BH. Both return the CPU topology information. Leaf 0BH returns 3-level (Package/Core/Thread) CPU topology info. Leaf 1FH returns 6-level (Package/Die/Tile/Module/Core/Thread) CPU topology info. The logic to enumerate the topology info is the same. But today's logic to handle 1FH is completely wrong. The patch combines them together to fix the 1FH issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Ray Ni <ray.ni@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
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Ray Ni authored
Per SDM CPUID.0BH and CPUID.1FH outputs the same format of data in EAX/EBX/ECX/EDX except CPUID.1FH reports more level types such as module, tile, die. The patch removes the unnecessary duplicated structure definitions for CPUID.1FH because when the structure definitions for CPUID.0BH can be used for CPUID.1FH. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Ray Ni <ray.ni@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
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Eric Dong authored
Cc: Ray Ni <Ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Eric Dong authored
PcdCpuFeaturesSupport used to specify the platform policy about what CPU features this platform supports. This PCD will be used in IsCpuFeatureSupported only. Now RegisterCpuFeaturesLib use this PCD as an template to Get the pcd size. Update the code logic to replace it with PcdCpuFeaturesSetting. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Eric Dong authored
PcdCpuFeaturesUserConfiguration. Merge PcdCpuFeaturesUserConfiguration into PcdCpuFeaturesSetting. Use PcdCpuFeaturesSetting as input for the user input feature setting Use PcdCpuFeaturesSetting as output for the final CPU feature setting BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Eric Dong authored
Remove useless APIs, simplify the code logic. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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Vanguput, Narendra K authored
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1593 For every SMI occurrence, save and restore CR2 register only when SMM on-demand paging support is enabled in 64 bit operation mode. This is not a bug but to have better improvement of code. Patch5 is updated with separate functions for Save and Restore of CR2 based on review feedback. Patch6 - Removed Global Cr2 instead used function parameter. Patch7 - Removed checking Cr2 with 0 as per feedback. Patch8 and 9 - Aligned with EDK2 Coding style. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Vanguput Narendra K <narendra.k.vanguput@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Star Zeng <star.zeng@intel.com> Reviewed-by:
Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com> Regression-tested-by:
Laszlo Ersek <lersek@redhat.com>
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Eric Dong authored
V2 changes: Update the commit message and comments in the code. When waking vector buffer allocated by CpuDxe is tested by MemTest86 in MP mode, an error is reported because the same range of memory is modified by both CpuDxe driver and MemTest86. The waking vector buffer is not expected to be tested by MemTest86 if it is allocated out because MemTest86 only tests free memory. But current CpuDxe driver "borrows" buffer instead of allocate buffer for waking vector buffer (through allocate & free to get the buffer pointer, backup the buffer data before using it and restore it after using). With this implementation, if the buffer borrowed is not used by any other drivers, MemTest86 tool will treat it as free memory and test it. In order to fix the above issue, CpuDxe changes to allocate the buffer below 1M instead of borrowing it. But directly allocating memory below 1MB causes LegacyBios driver fails to start. LegacyBios driver allocates memory range from "0xA0000 - PcdEbdaReservedMemorySize" to 0xA0000 as Ebda Reserved Memory. The minimum value for "0xA0000 - PcdEbdaReservedMemorySize" is 0x88000. If LegacyBios driver allocate this range failed, it asserts. LegacyBios also reserves range from 0x60000 to "0x60000 + PcdOpromReservedMemorySize", it will be used as Oprom Reserve Memory. The maximum value for "0x60000 + PcdOpromReservedMemorySize" is 0x88000. LegacyBios driver tries to allocate these range page(4K size) by page. It just reports warning message if some pages are already allocated by others. Base on above investigation, one page in range 0x60000 ~ 0x88000 can be used as the waking vector buffer. LegacyBios driver only reports warning when page allocation in range [0x60000, 0x88000) fails. This library is consumed by CpuDxe driver to produce CPU Arch protocol. LagacyBios driver depends on CPU Arch protocol which guarantees below allocation runs earlier than LegacyBios driver. Cc: Ray Ni <ray.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com>
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- Apr 03, 2019
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Shenglei Zhang authored
AsmFuncs.S is removed at c7d22535. And also it should be removed in SecPeiDebugAgentLib.inf and SmmDebugAgentLib.inf. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Hao Wu <hao.a.wu@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Maurice Ma <maurice.ma@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Hao Wu <hao.a.wu@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Ting Ye <ting.ye@intel.com> Cc: Jian Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Jian J Wang <jian.j.wang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 v2: Remove CpuSleep.nasm| GCC and CpuFlushTlb.nasm| GCC in X64 arch in BaseCpuLib.inf. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Shenglei Zhang authored
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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- Apr 02, 2019
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Zhichao Gao authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1549 Add the new PEIM DebugServicePei and library instance PeiDebugLibDebugPpi to dsc file to verify it can build correctly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Hao Wu <hao.a.wu@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Liming Gao authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1549 Add a PEI debug library instance PeiDebugLibDebugPpi base on DebugPpi. Using the combination of the DebugServicePei and this lib instance can reduce the image size of PEI drivers. Notes: this library instance can be used only the PEIM DebugSerivicePei is runed and install the gEdkiiDebugPpiGuid. And this library contian the depx of gEfiPeiPcdPpiGuid, that means the PcdPei.inf cannot use this library instance. The PcdPei.inf should use the same library instance that the PEIM DebugServicePei consumes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Hao Wu <hao.a.wu@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Zhichao Gao authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1549 Add a PEIM to install Debug PPI so that PEI debug library instance can locate gEdkiiDebugPpiGuid to implement the debug functions. Using this PPI can reduce the size of PEIMs which consume the debug library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Hao Wu <hao.a.wu@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Zhichao Gao authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1549 Add a debug PPI for PEI phase. This PPI will provide basic services of debug. PEI debug lib instance can use these services to implement debug function to reduce the PEIMs which consume the debug lib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Hao Wu <hao.a.wu@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Hao Wu <hao.a.wu@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Chasel Chiu <chasel.chiu@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Chasel Chiu <chasel.chiu@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Acked-by:
Laszlo Ersek <lersek@redhat.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Leif Lindholm <leif.lindholm@linaro.org>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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Bret Barkelew authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:
Zhichao Gao <zhichao.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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