Initial U5SeriesPkg for U5 series platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Initial version of SiFive U500 VC707 platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

This is OpenSBI platform code implementation of U500 platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

PEI module for U500 platform initialization.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Add SiFive U540 platform build metafiles.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

This is OpenSBI platform code implementation of U540 platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Platform PEI module for U540 platform initialization.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Serial Port library for U5 series platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Timer library used to access to machine mode timer Control Status Registers
for U5 series platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

This will ensure that it is dispatched properly by the DXE dispatcher,
which means it doesn't have to go in the APRIORI section.

Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>

RAM based Firmware Volume Block service runtime driver for U5 series
platforms. The firmware binary image is stored in SD card and
loaded by Zero Stage Boot Loader (ZSBL) then mapped to RAM space.
This driver provides EFI Firmware Volume Block protocol to access
to firmware volume at RAM space.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Timer DXE implementation for U5 series platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

This is the library to create U5MC Coreplex specific information for
U5 series platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

SiFive U54 core library for building core information hob data.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

This is the initial version of SiFive silicon package. Provides PCD
tokens.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Add RISC-V platform package.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

SecMain module for RISC-V platform.
This was cloned from OpenSBI fw_base.S
(RiscVPkg/Library/RiscVOpensbiLib/opensbi/firmware/) and revised to
edk2 framework.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Common Platform Boot Manager library for RISC-V platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

PlatformUpdateProgressLib

NULL instance of PlatformUpdateProgressLib.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

PlatformMemoryTestLib

NULL instance of PlatformMemoryTestLib.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

NULL instance of RiscVOpensbiPlatformLib.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Add OpenSBI firmware context processor specific library which
provides interface to create processor specific firmware
context hob data.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

RISC-V Platform Temporary Memory library

NULL instance of RISC-V Platform Temporary Memory library.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

- Add RISC-V ProcessorPkg package which provides RISC-V processor related
  drivers and libraries.
- Support RISC-V OpenSBI and RISC-V platforms

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

NULL instance of RISC-V platform timer library.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

for RISC-V platforms.

RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
and type 44 records.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V
platform level timer library.

Due to RISC-V timer Control Status Register (CSR) is platform
implementation specific, RISC-V CPU DXE driver invokes platform level
timer library to access to timer CSRs.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

RISC-V PEI Service Table Pointer library

Implementation of RISC-V PEI Service Table Pointer library using
RISC-V OpenSbi.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Library provides interfaces to invoke SBI ecalls.

Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>

EDK2 RISC-V OpenSBI library which pull in external source files under
RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi to the build process.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>

Add submodule opensbi under
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbLlib.
The current supported opensbi version for RISC-V edk2 port is tags/v0.6.

Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Timer library for RISC-V.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Initial RISC-V Supervisor Mode trap handler.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

This library provides CSR assembly functions to read/write RISC-V
specific Control and Status registers.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

RISC-V processor package library definitions.

IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.

RiscVImpl.h
-Definition of EDK2 RISC-V implementation.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Fix input param error checking for the BcmGenetDxe ComponentName2
protocol.

This fixes https://github.com/pftf/RPi4/issues/85



Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Fix input param error checking for the DwUsbHostDxe ComponentName2
protocol.

This fixes https://github.com/pftf/RPi4/issues/86



Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Fix input param error checking for the DisplayDxe ComponentName2
protocol.

This fixes https://github.com/pftf/RPi4/issues/84



Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Any DSC file that uses the UefiCpuPkg MpInitLib or CpuExeptionHandlerLib
libraries, now requires the VmgExitLib library. Update the DSC files to
include the VmgExitLib NULL library implementation.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

The UART namespace reference in DBG2 is incorrect. Fix to point to the
correct name.

This fixes the certification failure reported by FWTS tests at:
https://github.com/pftf/RPi4/issues/69



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>