REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4242



Define a macro for SmbiosFeaturePkg usage which named
INTEL_FVI_SMBIOS_TYPE and initialized to 0xDD in
IndustryStandard/FirmwareVersionInfo.h

Signed-off-by: Hunter Chang <hunter.chang@intel.com>

Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Reviewed-by: S, Ashraf Ali <ashraf.ali.s@intel.com>

Add reference of IpmiBaseLib

Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Nickle Wang <nicklew@nvidia.com>
Cc: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Add functions to get system UUID and LAN
configuration parameter.

Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Nickle Wang <nicklew@nvidia.com>
Cc: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Add functions to get system UUID and LAN
configuration parameter.

Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Nickle Wang <nicklew@nvidia.com>
Cc: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

The serial number of Edk2OpensbiPlatformWrapperLib Library
and RiscVSpecialPlatformLib Library in the figure is opposite to
the text description. Fix it and adjust the text order.

Signed-off-by: Dongdong Zhang <zhangdongdong@eswincomputing.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

PCIE Base Address is 64bit PCD and the Mem Limit UINT64.
so typecasting to 32bit is not needed.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4068



Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Include the FdtLib path to fix a build issue coming on Arm/SgiPkg with
PlatformStandaloneMm2.

Fixes the build breakage introduced by 9ad168c9e0:
StandaloneMmPkg: Include libfdt in the StMM

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4198



After commit 1e1e35bb,
FIT Type 2 ACM entry is not generated as expected with given -I arguments.
FMS/FMS value is overridden by GetAcmFms().

This patch detects whether FMS/FMS Mask is already assigned
with -I argument. If it's not zero, skip invoking GetAcmFms().

Signed-off-by: Dakota Chiang <dakota.chiang@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jason1 Lin <jason1.lin@intel.com>
Cc: Rahul R Kumar <rahul.r.kumar@intel.com>

Add CpuPageTableLib required by MpInitLib.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

Building the RdV1 platform fails when only providing the
'-D SECURE_BOOT_ENABLE' flag due to MmUnblockMemoryLib missing.
There is only one MmUnblockMemoryLib implementation used,
so unconditionally use this implementation.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>

Rebecca Cran authored Oct 25, 2022 and Sami Mujawar committed Dec 13, 2022

Modern platforms that use TF-A should use PrePeiCoreUniCore, since
any secondary cores will be put in the TF-A holding pen and won't
reach EDK2.

Update the Morello and N1Sdp files to use PrePeiCoreUniCore instead of
PrePeiCoreMPCore.

Signed-off-by: Rebecca Cran <rebecca@quicinc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Sahil authored Dec 08, 2022 and Sami Mujawar committed Dec 13, 2022

The PNP ID 0x0A09 used for CCIX host bridge in the current code
is not defined in any specification and is therefore incorrect.

Also, there is no need for a separate ID for CCIX host bridge,
for the following reasons:

1. CCIX doesn't have any host specific requirements/ingredients
   as such.
2. CCIX protocol messages flow over regular PCIe.
3. CCIX devices and root ports are natively discovered using the
   CCIX DVSEC.

Therefore, reuse PCIe PNP ID for CCIX.

Signed-off-by: sahil <sahil@arm.com>
Acked-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

256-bit invaildation queue descriptor could be used for both
abort DMA mode and legacy mode.

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Reviewed-by: Jenny Huang <jenny.huang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Robert Kowalewski <robert.kowalewski@intel.com>

Add Maintainers for LoogArch in edk2-platforms.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Signed-off-by: xianglai li <lixianglai@loongson.cn>

Add Readme for LoogArch and Modify the Readme in the root directory.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Support Dxe for LoogArch.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides interfaces related to Dxe Hob.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides interfaces related to restart and shutdown.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

The Library provides Boot Manager interfaces.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides interfaces such as
real-time clock initialization
to get time and setting time.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This driver produces Timer Architectural Protocol,
Registers a timer interrupt and initializes the timer.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Add PCI CpuIo protocol.there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Platform PEI module for LoongArch platform initialization.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides a delay interface and a timing interface.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Read the memory map information through the QemuFwCfg interface,
then build the page table through the memory map information,
and finally enable Mmu.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

QemuFwCfgLib for PEI phase.
This library obtains the QemuFWCfg base address by
directly parsing the fdt, and reads and writes the data
in the QemuFWCfg by operating on the QemuFWCfg base address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Use a register to save PeiServicesTable pointer,
This lib Provides PeiServicesTable pointer saving
and retrieval services.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Add SEC Code And Readme.md for LoongArchQemu

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Serial Port library for LoongarchQemuPkg

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in WhitleyOpenBoardPkg as well.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in Vlv2TbltDevicePkg as well.

Cc: Zailiang Sun <zailiang.sun@intel.com>
Cc: Yi Qian <yi.qian@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in SimcOpenBoardPlatformPkg as well.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in QuarkPlatformPkg as well.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Kelly Steele <kelly.steele@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in MinPlatformPkg as well.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4155



With new implementation, FITGEN will populate info needed
for the PROT assisted BootGuard solution and TXT on servers
using FIT 4 Entry. FitGen based on the CPU FMS FITGEN will
decide to call one of the two Type 2 FIT entry.

Signed-off-by: Rahul R Kumar <rahul.r.kumar@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>

CreateSecondLevelPagingEntryTable() has a return type of
VTD_SECOND_LEVEL_PAGING_ENTRY * and an error condition
returns a value of NULL.

Change return value of EFI_SUCCESS (value 0) to NULL to
address CLANG compiler detection of incorrect return type.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

CreateSecondLevelPagingEntryTable() has a return type of
VTD_SECOND_LEVEL_PAGING_ENTRY * and an error condition
returns a value of NULL.

Change return value of EFI_SUCCESS (value 0) to NULL to
address CLANG compiler detection of incorrect return type.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Graeme Gregory <graeme@nuviainc.com>
Cc: Graeme Gregory <quic_ggregory@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Graeme Gregory <quic_ggregory@quicinc.com>

Pierre Gondois authored Sep 08, 2022 and Sami Mujawar committed Nov 01, 2022

From ACPI 5.1, s19.5.28 DefinitionBlock (Declare Definition Block):
  Note: For compatibility with ACPI versions before
  ACPI 2.0, the bit width of Integer objects is
  dependent on the ComplianceRevision of the DSDT.
  If the ComplianceRevision is less than 2, all
  integers are restricted to 32 bits. Otherwise,
  full 64-bit integers are used. The version of the DSDT
  sets the global integer width for all integers,
  including integers in SSDTs.

To be up-to-date with the latest table revision, bump the version
of all dsdt/ssdt tables that are relying on an ACPI specification
version above 2.0.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>