Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64

The current revision of SC2A11 contains PCIe bus issue.
In MRd transaction, 1st/Last DW BE fields are not correctly set
by hardware.

As a workaround, set TH bit and specify MSG_CODE in iATU.
With this setup, the value specified as MSG_CODE is set to the
1st/Last DW BE fields and PCIe controller can emit the correct
MRd TLP header.
Same workaround was already included for MMIO32 region,
MMIO64 region also requires this workaround.
Some deivices, such as Samsong SSD 970 EVO, do not work
without this modification.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Masahisa KOJIMA <masahisa.kojima@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>