Silicon/AMD/StyxDtbLoaderLib: add description of the cache topology

Emit the cache topology into the device tree too when generating the
CPU nodes and the cpu-map. Note that the cache geometries are all
fixed and thus hardcoded - the only runtime variable aspect is how
many L2 nodes to generate (one per detected cluster)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>