rdfremont: configure system counter implementation defined registers

On RD-Fremont and variant platforms, the system counter should increment
at 1GHz as per SBSA requirement. With the refclk at 125Mhz, these
platforms require a per-tick system counter increment of 8. This
increment value has to be programmed in the implementation defined
registers of system counter control register frame. So provide the table
of impdef register offsets and its corresponding values in the gtimer
module config data.

It is SCP firmware that configures the system counter register frame and
so the table is supplied as config data to only the SCP firmware. For
the MCP firmware, update the system counter increment frequency as 1GHz.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Ibda329735f9ac9df61434b2b5aafabd69da956da