MLECO-5966: Update for Sram_Only memory mode

For `Sram_Only` memory mode the "weights" RO traffic was previously
wired through the second set of AXI ports and the timing adapter
settings were kept the same as the first set so this traffic also
sees the same bandwidth and lateny envelope. However, it is quite
possible to see slightly better performance if we only use one set
of AXI ports. For Sram_Only memory mode, the Vela compiler schedules
the R/W expecting to use only one set so this change also aligns
with how Vela intends such a model to be deployed on the NPU.

Change-Id: I7b37c3548e2ab00dda55ac1e13a7883f8e588f9f
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>