MLBEDSW-8926 Port LSTM to Regor
- Ported lowering of TFLite::UnidirectionalSequenceLstm to Regor.
- Added reading of TFLite intermediate tensors. Added a new TensorUsage::Intermediate for these tensors.
- Added logic to allocate tensors which point to the same buffer to the same address, enabling this to be controlled in GraphIR.
- Added an optional Tag to the Buffer hash function in order to differentiate between multiple empty buffers which stem from different TFLite variable tensors.
- Added missing rescaling for Sigmoid and Tanh when fused with Elementwise Add, Sub or Mul.
- Added some limitations to persistent tensors:
- They are now required to be in linear format.
- They can not share memory with non-persistent tensors.
- Made a small modification to graph traversal so that partial writes are processed in the order they are added to the graph.
- Added supported operator checks for UnidirectionalSequenceLstm.
Change-Id: I6bd08822a41dca48b3aa8091b07747327b37d68f Signed-off-by: Jacob Bohlin jacob.bohlin@arm.com