add Kconfig support for this driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Martyn Welch <martyn.welch@collabora.co.uk>

This function sets the polarity of the PWR signal which is not used on
the opos6uldev board. Remove it.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>

This commit updates the doc/README.falcon regarding Falcon boot on
NOR flash memories.

This code is used by MCCMON6 board - so for more details please refer to
configs/mccmon6_nor_defconfig.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

This option will provide the offset in the parallel NOR flash memory to,
which the falcon boot data is stored.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

The CMD_SPL_NAND_OFS description was a bit misleading, has
been updated.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

This commit makes the CMD_SPL_NAND_OFS only visible when we use NAND
memory.
Before this change it was present when only CMD_SPL was enabled (and
would stay when board with other falcon boot medium is used).

Signed-off-by: Lukasz Majewski <lukma@denx.de>

mccmon6 works in 10/100 MiB Ethernet environment, so disabling 1GiB support
improves robustness of the network after power up (as one don't need to
wait for autoneg).

Signed-off-by: Lukasz Majewski <lukma@denx.de>

The IMX6Q based MCCMON6 is not using USB for any purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

This comment is a leftover from the Kconfig CONFIG_*MTD* move.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR
clock to 352.8Mhz (25.2Mhz * 14) by using the clock path:

	APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock

To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
	14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)

	NIC0_DIV:      1
	NIC1_DIV:      0
	LCDIF_PCC_DIV: 6

APLL and APLL PFD0 settings:

	PFD0 FRAC:  27
	APLL MULT:  22
	APLL NUM:   1
	APLL DENOM: 20

This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>

To support HDMI display on EVK board, the LCDIF pix clock must be
25.2Mhz. Since the its PCC divider range is from 1-8, the max rate
of LCDIF PCC source clock is 201.6Mhz. This limits the source clock
must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs
are higher than this max rate.

The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source
is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK,
NIC1 and NIC1 bus.

Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz
(25.2 * 12), with settings:

PFD0 FRAC:  32
APLL MULT:  22
APLL NUM:   2
APLL DENOM: 5

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Update LPDDR3 script with the changes below:
  -Update the precharge command to CMD=01 at the DDR initialization phase
  -remove unimplemented registers
   Write data bit delay --refer to the DDR_TRIM bits in
   IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn

Test:
  One EVK board passes overnight stress test.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement.
We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM,
the NUM should always be less than the DENOM. So our setting violates the rule.

Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock
is 318.9888Mhz, which also meet the DDR requirement.
To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

If no CONFIG_OPTEE_LOAD_ADDR is provided i.e. you are not loading OPTEE
into memory in u-boot, then just set the non-existent CONFIG option to
zero, elsewise stringify(CONFIG_OPTEE_LOAD_ADDR) will return
"CONFIG_OPTEE_LOAD_ADDR" - which looks weird in the u-boot environment.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

In the Mbed Linux OS bootflow OP-TEE runs before u-boot and provides a DTB
overlay at 0x83100000.

This overlay should subsequently be merged into the main DTB before handing
over to the kernel.

This patch defines fdtovaddr at 0x83100000.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This commit enables CONFIG_OF_LIBFDT_OVERLAY a requirement to perform a
merge of an OPTEE provided DTB overlay into our main kernel DTB image.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

In order to switch on DTB overlay support in WaRP7 BL33 we first need to
switch on LIBFDT support. Do that now.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Reusing the loadaddr to load the boot script breaks some of the logic we
want to have around the bootscript/FIT load addresses. Making a dedicated
bootscript address allows us to differentiate the bootscript load address
from the Linux Kernel or OPTEE load address, thus ensuring that no matter
what the load sequence the bootscript and Kernel/OPTEE binary load
addresses do not conflict.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

When obtaining the bootscript from a FIT image we need to specify the name
of the bootscript as defined inside of the FIT.

This patch makes a define that appends a "bootscr" parameter to the source
command when compiling up in FIT mode on warp7.

An environment variable is supplied to enable others to use a different
name than "bootscr" as the image name of the boot script in their FIT.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch switches on FIT verification of boot.scr. After this commit your
boot.scr must be in the FIT format.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

BD71837 and BD71847 is PMIC intended for powering single-core,
dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847
is used for example on NXP imx8mm EVK.

Add regulator driver for ROHM BD71837 and BD71847 PMICs.
BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced
version containing 6 bucks and 6 LDOs. Voltages for DVS
bucks (1-4 on BD71837, 1 and 2 on BD71847) can be adjusted
when regulators are enabled. For other bucks and LDOs we may
have over- or undershooting if voltage is adjusted when
regulator is enabled. Thus this is prevented by default.

BD718x7 has a quirk which may leave power output disabled
after reset if enable/disable state was controlled by SW.
Thus the SW control is only allowed for BD71837  bucks
3 and 4 by default. The impact of this limitation must be
evaluated board-by board and restrictions may need to be
modified. (Linux driver get's these limitations from DT and we
may want to implement same on u-Boot driver).

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add thermal dts node
Enable thermal in defconfig

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add i.MX8 thermal driver to support get temperature from SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add sc_misc_get_temp to support get temperature

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Commit 32ce6179 ("optee: Add lib entries for sharing OPTEE code across
ports") adds code into lib/optee but neglects to update MAINTAINERS to make
me buggable for questions and maintenance.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>

When booting in BL33 mode i.e. with u-boot loaded by OP-TEE we get the
following print-out.

Board: WARP7 in secure mode OPTEE DRAM 0xa0000000-0xa0000000

This is incorrect the right range is 0x9e000000-0xa0000000. This patch
fixes the defines on the warp7_bl33_defconfig file to tidy up the output.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>

Commit c7b3a7ee ("optee: adjust dependencies and default values for
dram") makes the TZDRAM defines for OPTEE show up for all configs as a
side-effect. While not harmful its not what we really want.

This patch makes the following defines contingent on CONFIG_OPTEE=y

CONFIG_OPTEE_TZDRAM_BASE
CONFIG_OPTEE_TZDRAM_SIZE

Rightly, if you don't have CONFIG_OPTEE=y you don't care about the above
two defines.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Rui Miguel Silva <rui.silva@linaro.org>
Acked-by: Rui Miguel Silva <rui.silva@linaro.org>

This patch converts mxs_spi driver to support DM/DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>

The code responsible for setting proper values in the MUX registers
(in the mxs_pinctrl_set_state()) has been ported from Linux kernel
- SHA1: 17bb763e7eaf tag v5.1.11 from linux-stable.

As the pinctrl node in the imx28.dtsi file has gpio pins nodes as subnodes,
it was necessary to use 'dm_scan_fdt_dev()' (as a .bind method) to also
make them 'visible' by the DM's "gpio_mxs" driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>

This patch adds support for DM/DTS in the mxs_gpio.c driver.
Information regarding per gpio controller pin number is passed via DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>

Those properties are U-Boot specific as the mxs gpio Linux driver (up to
version v5.1.11) is not supporting them.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

The fec_mxc.c driver can be reused by i.MX28 when DM_ETH is enabled.
One only needs to add proper compatible and dependency on FEC_MXC in the
Kconfig.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>

This patch copies from the Linux kernel stable (tag v5.1.11)
SHA1: 17bb763e7eaf i.MX28 related device tree files.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>

Since the board uses SPL_OF_CONTROL now, we don't need to
explicitly initialize the MMC driver, but we still need to
pinmux the corresponding pins.  This patch removes the
initialization code and leave just the muxing behind.

Signed-off-by: Adam Ford <aford173@gmail.com>

With the spl code correctly returning either MMC1 or MMC2,
this board can not boot either from internal eMMC (MMC1) or
the uSD card on the baseboard (MMC2) using the device tree.

Signed-off-by: Adam Ford <aford173@gmail.com>

Currently, when the spl_boot_device checks the boot device, it
will only return MMC1 when it's either sd or eMMC regardless
of whether or not it's MMC1 or MMC2.  This is a problem when
booting from MMC2 if MMC isn't being manually configured like in
the DM_SPL case with SPL_OF_CONTROL.

This patch will check the register and return either MMC1 or MMC2.

Signed-off-by: Adam Ford <aford173@gmail.com>

Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>

Writing/updating boot image in nand device is not
straight forward in i.MX6 platform and it requires
boot control block(BCB) to be configured.

It becomes difficult to use uboot 'nand' command to
write BCB since it requires platform specific attributes
need to be taken care of.

It is even difficult to use existing msx-nand.c driver by
incorporating BCB attributes like mxs_dma_desc does
because it requires change in mtd and nand command.

So, cmd_nandbcb implemented in arch/arm/mach-imx

BCB contains two data structures, Firmware Configuration Block(FCB)
and Discovered Bad Block Table(DBBT). FCB has nand timings,
DBBT search area, page address of firmware.

On summary, nandbcb update will
- erase the entire partition
- create BCB by creating 2 FCB/DBBT block followed by
  1 FW block based on partition size and erasesize.
- fill FCB/DBBT structures
- write FW/SPL on FW1
- write FCB/DBBT in first 2 blocks

for nand boot, up on reset bootrom look for FCB structure in
first block's if FCB found the nand timings are loaded for
further reads. once FCB read done, DTTB will load and finally
firmware will be loaded which is boot image.

Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
information.

Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>

The clock subsystem needs active maintenance as it steadily grows.
I do offer my help for this task.

Signed-off-by: Lukasz Majewski <lukma@denx.de>