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  1. Nov 02, 2012
    • Tom Rini's avatar
      README: Document CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG · 7e27f89f
      Tom Rini authored
      
      
      This option is intended to be set by boards which will set the
      board_name and board_rev environment variables.  These are to be used
      when the U-Boot binary can support more than one board type at run-time
      and the user needs an easy way (for example for scripting to determine
      what device tree to load) to determine what board they are on.
      
      Signed-off-by: default avatarTom Rini <trini@ti.com>
      7e27f89f
  2. Oct 29, 2012
    • Stephen Warren's avatar
      fs: separate CONFIG_FS_{FAT, EXT4} from CONFIG_CMD_{FAT, EXT*} · 03e2ecf6
      Stephen Warren authored
      
      
      This makes the FAT and ext4 filesystem implementations build if
      CONFIG_FS_{FAT,EXT4} are defined, rather than basing the build on
      whether CONFIG_CMD_{FAT,EXT*} are defined. This will allow the
      filesystems to be built separately from the filesystem-specific commands
      that use them. This paves the way for the creation of filesystem-generic
      commands that used the filesystems, without requiring the filesystem-
      specific commands.
      
      Minor documentation changes are made for this change.
      
      The new config options are automatically selected by the old config
      options to retain backwards-compatibility.
      
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Reviewed-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
      03e2ecf6
  3. Oct 28, 2012
  4. Oct 22, 2012
    • York Sun's avatar
      powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 · ffd06e02
      York Sun authored
      
      
      Move spin table to cached memory to comply with ePAPR v1.1.
      Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
      
      'M' bit is set for DDR TLB to maintain cache coherence.
      
      See details in doc/README.mpc85xx-spin-table.
      
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      ffd06e02
    • Ashok's avatar
      README : Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111,... · 3bb46d23
      Ashok authored
      
      README : Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111, CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96
      
      Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111,
      CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96
      
      Signed-off-by: default avatarAshok Kumar Reddy <ashokkourla2000@gmail.com>
      Reviewed-by: default avatarTom Rini <trini@ti.com>
      3bb46d23
    • Gabe Black's avatar
      fs: Add a Coreboot Filesystem (CBFS) driver and commands · 84cd9327
      Gabe Black authored
      
      
      This change adds CBFS support and some commands to use it to u-boot. These
      commands are:
      
      cbfsinit - Initialize CBFS support and pull all metadata into RAM. The end of
      the ROM is an optional parameter which defaults to the standard 0xffffffff and
      can be used to support multiple CBFSes in a system. The last one set up with
      cbfsinit is the one that will be used.
      
      cbfsinfo - Print information from the CBFS header.
      
      cbfsls - Print out the size, type, and name of all the files in the current
      CBFS. Recognized types are translated into symbolic names.
      
      cbfsload - Load a file from CBFS into memory. Like the similar command for fat
      filesystems, you can optionally provide a maximum size.
      
      Support for CBFS is compiled in when the CONFIG_CMD_CBFS option is specified.
      
      The CBFS driver can also be used programmatically from within u-boot.
      
      If u-boot needs something out of CBFS very early before the heap is
      configured, it won't be able to use the normal CBFS support which caches some
      information in memory it allocates from the heap. The
      cbfs_file_find_uncached function searches a CBFS instance without touching
      the heap.
      
      Signed-off-by: default avatarGabe Black <gabeblack@google.com>
      Signed-off-by: default avatarStefan Reinauer <reinauer@chromium.org>
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      84cd9327
  5. Oct 15, 2012
  6. Oct 03, 2012
  7. Oct 02, 2012
  8. Sep 29, 2012
  9. Sep 27, 2012
  10. Sep 02, 2012
  11. Sep 01, 2012
  12. Aug 23, 2012
    • Scott Wood's avatar
      powerpc/fsl-corenet: work around erratum A004510 · 33eee330
      Scott Wood authored
      
      
      Erratum A004510 says that under certain load conditions, modified
      cache lines can be discarded, causing data corruption.
      
      To work around this, several CCSR and DCSR register updates need to be
      made in a careful manner, so that there is no other transaction in
      corenet when the update is made.
      
      The update is made from a locked cacheline, with a delay before to flush
      any previous activity, and a delay after to flush the CCSR/DCSR update.
      We can't use a readback because that would be another corenet
      transaction, which is not allowed.
      
      We lock the subsequent cacheline to prevent it from being fetched while
      we're executing the previous cacheline.  It is filled with nops so that a
      branch doesn't cause us to fetch another cacheline.
      
      Ordinarily we are running in a cache-inhibited mapping at this point, so
      we temporarily change that.  We make it guarded so that we should never
      see a speculative load, and we never do an explicit load.  Thus, only the
      I-cache should ever fill from this mapping, and we flush/unlock it
      afterward.  Thus we should avoid problems from any potential cache
      aliasing between inhibited and non-inhibited mappings.
      
      NOTE that if PAMU is used with this patch, it will need to use a
      dedicated LAW as described in the erratum.  This is the responsibility
      of the OS that sets up PAMU.
      
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      33eee330
    • Liu Gang's avatar
      powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet · fc54c7fa
      Liu Gang authored
      
      
      Added descriptions about boot from PCIE in the files README and
      doc/README.srio-pcie-boot-corenet, and changed the name of the
      doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      fc54c7fa
  13. Jul 12, 2012
  14. Jul 09, 2012
  15. Jul 06, 2012
  16. May 23, 2012
  17. May 15, 2012
  18. Apr 25, 2012
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO · 0a85a9e7
      Liu Gang authored
      
      
      When boot from SRIO, slave's ENV can be stored in master's memory space,
      then slave can fetch the ENV through SRIO interface.
      
      NOTE: Because the slave can not erase, write master's NOR flash by SRIO
      	  interface, so it can not modify the ENV parameters stored in
      	  master's NOR flash using "saveenv" or other commands.
      
      Master needs to:
      	1. Put the slave's ENV into it's own memory space.
      	2. Set an inbound SRIO window covered slave's ENV stored in master's
      	   memory space.
      Slave needs to:
      	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
      	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      0a85a9e7
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave module for boot from SRIO · 292dc6c5
      Liu Gang authored
      
      
      For the powerpc processors with SRIO interface, boot location can be configured
      from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
      for u-boot image. The image can be fetched from another processor's memory
      space by SRIO link connected between them.
      
      The processor boots from SRIO is slave, the processor boots from normal flash
      memory space and can help slave to boot from its memory space is master.
      They are different environments and requirements:
      
      master:
      	1. NOR flash for its own u-boot image, ucode and ENV space.
      	2. Slave's u-boot image in master NOR flash.
      	3. Normally boot from local NOR flash.
      	4. Configure SRIO switch system if needed.
      slave:
      	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
      	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
      	3. RCW should configure the SerDes, SRIO interfaces correctly.
      	4. Slave must be powered on after master's boot.
      	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
      	   locally.
      
      For the slave module, need to finish these processes:
      	1. Set the boot location to SRIO1 or SRIO2 by RCW.
          2. Set a specific TLB entry for the boot process.
      	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
      	4. Slave's u-boot image should be generated specifically by
      	   make xxxx_SRIOBOOT_SLAVE_config.
      	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      292dc6c5
  19. Apr 19, 2012
  20. Apr 11, 2012
  21. Apr 02, 2012
    • Daniel Schwierzeck's avatar
      MIPS: fix endianess handling · 6cb461b4
      Daniel Schwierzeck authored
      
      
      Make endianess of target CPU configurable. Use the new config
      option for dbau1550_el and pb1000 boards.
      
      Adapt linking of standalone applications to pass through
      endianess options to LD.
      
      Build tested with:
       - ELDK 4 mips_4KC- and mips4KCle
       - Sourcery CodeBench Lite 2011.03-93
      
      With this patch all 26 MIPS boards can be compiled now in one step by
      running "MAKEALL -a mips".
      
      Signed-off-by: default avatarDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
      6cb461b4
  22. Mar 30, 2012
    • Marek Vasut's avatar
      BOOT: Add RAW ramdisk support to bootz · 017e1f3f
      Marek Vasut authored
      
      
      This patch allows loading RAW ramdisk via bootz command. The raw ramdisk is
      loaded only in case it's size is specified:
      
        bootz <kernel addr> <ramdisk addr>:<ramdisk size> <fdt addr>
      
      For example:
      
        bootz 0x42000000 0x43000000:0x12345 0x44000000
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
      Cc: Tom Warren <TWarren@nvidia.com>
      Cc: albert.u.boot@aribaud.net
      Cc: afleming@gmail.com
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Stephen Warren <swarren@nvidia.com>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Detlev Zundel <dzu@denx.de>
      017e1f3f
    • Marek Vasut's avatar
      BOOT: Add "bootz" command to boot Linux zImage on ARM · 44f074c7
      Marek Vasut authored
      
      
      This command boots Linux zImage from where the zImage is loaded to. Passing
      initrd and fdt is supported.
      
      Tested on i.MX28 based DENX M28EVK
      Tested on PXA270 based Voipac PXA270.
      
      NOTE: This currently only supports ARM, but other architectures can be easily
      added by defining bootz_setup().
      
      Signed-off-by: default avatarMarek Vasut <marek.vasut@gmail.com>
      Cc: Tom Warren <TWarren@nvidia.com>
      Cc: albert.u.boot@aribaud.net
      Cc: afleming@gmail.com,
      Cc: Simon Glass <sjg@chromium.org>,
      Cc: Stephen Warren <swarren@nvidia.com>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Detlev Zundel <dzu@denx.de>
      44f074c7
  23. Mar 29, 2012
  24. Mar 28, 2012
    • Vipin KUMAR's avatar
      Enable high speed support for USB device framework and usbtty · f9da0f89
      Vipin KUMAR authored
      
      
      This patch adds the support for high speed in usb device framework and usbtty
      driver. This feature has been kept within a macro CONFIG_USBD_HS, so the board
      configuration files have to define this macro to enable high speed support.
      
      Along with that specific peripheral drivers also need to define a function to
      let the framework know that the enumeration has happened at high speed.
      This function prototype is "int is_usbd_high_speed(void)"
      
      Signed-off-by: default avatarVipin Kumar <vipin.kumar@st.com>
      Signed-off-by: default avatarAmit Virdi <amit.virdi@st.com>
      f9da0f89
  25. Mar 26, 2012
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