Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

This driver only supports Driver Model, not legacy model.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.

The SPL framework is supported.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Email address is not longer valid that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Since commit 326a6823 (malloc_f: enable SYS_MALLOC_F by default
if DM is on), Zynq MMC boot hangs up after printing the following:

    U-Boot SPL 2015.04-rc5-00053-gadcc570 (Apr 08 2015 - 12:59:11)
    mmc boot
    reading system.dtb

Prior to commit 326a6823, Zynq boards enabled CONFIG_DM, but
not CONFIG_SYS_MALLOC_F.  That commit forcibly turned on
CONFIG_SYS_MALLOC_F.  I have not figured out the root cause, but
anyway it looks like CONFIG_SYS_MALLOC_F gave a bad impact on the
Zynq MMC boot.

We are planning to have the v2015.04 release in a few days.
I know this is a defensive fixup, but what I can do now is to add
   # CONFIG_SYS_MALLOC_F is not set
to every Zynq defconfig file to get back the original behavior.

Tested on:
  - Zedboard
  - ZC706 board

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>

With e37f1eb4 we now use strict_strtoul() in do_mem_mtest() and this
gives us a warning:
../include/vsprintf.h:38:5: note: expected 'long unsigned int *' but
argument is of type 'int *'

Signed-off-by: Tom Rini <trini@konsulko.com>

Top-level Makefile has option to select dtc binary, but it is ignored
due to bug in Makefile.lib. Fix it.

Signed-off-by: Pavel Machek <pavel@denx.de>

Since the Kconfig conversion, boards.cfg scanned by MAKEALL is
generated by tools/genboardscfg.py.  Every board is supposed to have
its own MAINTAINERS that contains maintainer and status information,
but, in fact, MAINTAINERS is missing from some boards.

For such boards, the first field, Status, is filled with '-'.
It causes a problem for "set" command, which ignores '-' in its
arguments.  Consequently, get_target_arch() returns a wrong field
and MAKEALL fails to get a correct toolchain.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Since the Kconfig conversion, config.mk has been included only when
include/config/auto.conf is newer than the .config file.

It causes build error if both files have the same time-stamps.
It is actually possible because EXT* file systems have a 1s time-stamp
resolution.

The config.mk should be included when include/config/auto.conf is
*not older* than the .config file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Tom Rini <trini@konsulko.com>
Reported-by: York Sun <yorksun@freescale.com>
Reported-by: Stephen Warren <swarren@nvidia.com>
Reported-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>

Back in fc46bae2 a "clean up" was introduced that intended to reconcile
some of the AM335x codepaths based on how AM43xx operates.
Unfortunately this introduced a regression on the DDR2 platforms.  This
was un-noticed on DDR3 (everything except for Beaglebone White) as we
had already populated sdram_config correctly in sequence.  This change
brings us back to the older behavior and is fine on all platforms.

Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM

Reported-by: Matt Ranostay <mranostay@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

Currently, memtest will silently accept bad data. Perform error
checking on user intput.

Signed-off-by: Pavel Machek <pavel@denx.de>

In stead of user_buffer_size, transfer_size should be used to pass to
ahci_device_data_io(). transfer_size is the length that we want the
low level function to transfer each time.
If we use user_buffer_size which is the totally data length as parameter,
low level function will actually create many SGs to transfer as many data
as possible each time. That will produce many redundant data transfer.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

The u-boot environment is redundantly stored in a NOR flash on our boards.
Redundant means that there are two places to store the environment. But only
one of the two is active. I discovered that on one board the u-boot (env_sf)
uses the environment from the second place and the Kernel (fw_printenv) uses
the environment from the first place.
To decide which is the active environment there is a byte inside the
environment. 1 means active and 0 means obsolete. But on that board both
environments had have a 1. This can happen if a power loss or reset occurs
during writing the environment. In this situation the u-boot (env_sf)
implementation uses the second environment as default. But the Kernel
(fw_printenv) implementation uses the first environment as default.

This commit corrects the default in the u-boot env_sf implementation when a
problem was detected. Now the recovery default is the same like in all other
environment implementations. E.g. fw_printenv and env_flash. This ensures that
u-boot and Kernel use the same environment.

Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>

After this change it is possible to boot trats2 device with Image.itb,
which facilitates automated testing, since only one file is necessary.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

After this change it is possible to boot trats device with Image.itb,
which facilitates automated testing, since only one file is necessary.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

This change allows using Image.itb image format with Exynos4 devices
(especially trats and trats2).
Such change facilitates automated testing since only one binary needs
to be prepared.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Remove GPIOs from smdk5420 board file and because the same
is already specified via DT.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Add backlight enable GPIO, and delay needed for panel powerup
via FIMD DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Now that parade driver supports reading SLP and RST GPIO
from DT, specify the same in parade DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Now that the exynos_fb driver supports handling backlight GPIO
via DT, specify pwm output property via FIMD DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Add support to configure EDP_RST GPIO and EDP_SLP GPIO,
if provided in parade DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Add support to configure PWM_OUT(PWM output) GPIO and
BL_EN(backlight enable) GPIO, if provided in FIMD DT node.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.

This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.

This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

The peach boards have their SDRAM start address at 0x20000000 instead of
0x40000000 which seems common for all other exynos5 based boards. This
means the layout set in exynos5-common.h causes the kernel be loaded
more then 128MB (at 0x42000000) away from memory start which breaks
booting kernels with CONFIG_AUTO_ZRELADDR

Define a custom MEM_LAYOUT_ENV_SETTINGS for both peach boards which uses
the same offsets from start of memory as the common exynos5 settings.

This fixes booting via bootz and PXE

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

We can enable / disable trace feature from the FTRACE config options.
To enable, compile U-Boot with FTRACE=1.

This patch add #ifdef FTRACE in exynos5-common.h for enable/disable
to use FTRACE configs instead of having to change board config files.

Signed-off-by: Inha Song <ideal.song@samsung.com>
Acked-by: Simon Glass <sjg@chroimum.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Commit 2e82e925 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook (snow).

Changes in V2: reorder lines as requested by Joonyoung Shim.

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Joonyoung Shim <jy0922.shim@samsung.com>
Reviewed-by: Simon Glass <sjg@chroimum.org>
Tested-by: Simon Glass <sjg@chroimum.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

The Orangepi_mini is different enough from the regular Orangepi that it needs
its own dtb, but when it got added a copy and paste error was made and it
got the same dtb filename, fix this.

While at it also add a short description of both Orangepi boards to the
defconfig files for them.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

Conflicts:
	board/armltd/vexpress64/vexpress64.c

Signed-off-by: Tom Rini <trini@konsulko.com>

With the most recent board firmware correct SDIO clock is 50MHz as
opposed to 25 MHz before.

Also set max frequency of MMC data exchange equal to SDIO clock -
because there's no way to transfer data faster than interface clock.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
 * slc_enable/disable
 * slc_flush/invalidate

For now we just disable SLC to escape DMA coherency issues until either:
 * SLC flush/invalidate is supported in DMA APIin U-Boot
 * hardware DMA coherency is implemented (that might be board specific
   so probably we'll need to have a separate Kconfig option for
   controlling SLC explicitly)

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>

Now when all infrastructure in ARC is ready for it let's switch ARC UART
to driver model.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>