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Commit ec4b73f0 authored by Jagan Teki's avatar Jagan Teki Committed by Michal Simek
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fpga: zynqpl: Add dcache flush support 



Buffers must be cache and dma aligned.

Signed-off-by: default avatarJagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent e5a9a407
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