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Commit 334e442e authored by Grzegorz Bernacki's avatar Grzegorz Bernacki Committed by Wolfgang Denk
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Set ips dividor to 1/4 of csb clock. 



Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.

Signed-off-by: default avatarGrzegorz Bernacki <gjb@semihalf.com>
parent 4c9e98ac
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