pcie_hierarchies: add example pcie hierarchy json files

RD-N2 and RD-N2-Cfg1 FVPs has multiple IO Macros and each IO Macro have
four PCIe root buses (x16, x8, x4_1, x4_0). These FVPs accepts custom
PCIe topology file and instantiates the PCIe topology as represented in
the topology file. Add example PCIe hierarchy files to be instantiated
under root buses. Each topology is configured to have 32 MiB ECAM space
(thus 32 possible buses), 64 MiB MMIOL and 32 GiB MMIOH space.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ied6eb01f7b598dffb36d6397ac408685f4039bab