Optimize performance of SNOW3G NEON implementation.

See merge request !11

Change-Id: I8f3996e0d33a3db3c28f9e46435f8336eda89b59

Change-Id: I271d57ee5edad53a196b48583aed0c647267e1d3

    Following changes have be done in this patch.
    1. implement 4-buffer snow3g uea2 by assembley code.

    Compared with 4-buffer NEON intrinsic implementation, the
    throughput improvement on different micro-archetecutre is listed below.
      Neoverse V1 : x1.13 @ 1024 buffer-sz

    We use DPDK command to calculate performance improvement.
      sudo ./build/app/dpdk-test-crypto-perf -c 0x3 --no-huge
          --vdev crypto_snow3g -- --devtype crypto_snow3g
          --ptest throughput --pool-sz 16384 --total-ops 1000000
          --burst-sz 8 --optype cipher-only --cipher-algo snow3g-uea2
          --cipher-iv-sz 16 --auth-op generate --cipher-key-sz 16
          --buffer-sz 64,128,256,512,1024 --cipher-op encrypt

Change-Id: I9146fb17fdc8ef717301fa2c51df413c16a14399

Implement SVE 8-buffer SNOW3G UEA2

See merge request !10

    Following changes have be done in this patch.
    1. Add job manager of snow3g uea2, this manager can schedule
       8-buffer with un-uniform length and different keys.
    2. Add 8-buffer implementation of underlying algorithm of snow3g,
       such as s1 box, s2 box, multiply alpha and divide alpha.

    Compared with 4-buffer NEON implementation, the throughput
    improvement on different micro-archetecutre is listed below.
      Neoverse V1 : x1.44 @ 1024 buffer-sz

    We use DPDK command to calculate performance improvement.
      sudo ./build/app/dpdk-test-crypto-perf -c 0x3 --no-huge
          --vdev crypto_snow3g -- --devtype crypto_snow3g
          --ptest throughput --pool-sz 16384 --total-ops 1000000
          --burst-sz 8 --optype cipher-only --cipher-algo snow3g-uea2
          --cipher-iv-sz 16 --auth-op generate --cipher-key-sz 16
          --buffer-sz 64,128,256,512,1024 --cipher-op encrypt

Signed-off-by:  <fisher.yu&lt;fisher.yu@arm.com>
Change-Id: Ic3c62ba6936eff904f3767386e97edf00a795843

Fix performance dip issue on multicore

See merge request !9

Signed-off-by:  <fisher.yu&lt;fisher.yu@arm.com>
Change-Id: I1186ebd84acc5a9c0604bb14082ca02548c1cf76

Fix cross-compile bug on installing shared library

See merge request !8

Signed-off-by:  <fisher.yu&lt;fisher.yu@arm.com>
Change-Id: I3466aa56aaf265a327f2ab55e2324668fbb4f93c

Add imb_get_errno to indicate the param error for SNOW3G APIs.

See merge request !7

Signed-off-by:  <fisher.yu&lt;fisher.yu@arm.com>
Change-Id: I0181d2f6f0fff2dfcd91328eaa69f8ae6565b39b

Implement Neon multi-buffer SNOW3G UEA2 & UIA2

See merge request !6

    Following changes have be done in this patch.
    1. Add job manager of snow3g uia2.
    2. During the keystream generating stage, implement 4-buffer.

    Compared with 1buf-4blk implementation (1-buffer during keystream
    generating stage, 4-block during polynomial mutiply stage), the
    performance improvement of 4buf-4blk implementation (4-buffer
    during keystream generating stage, 4-block during polynomial
    mutiply stage) on different micro-archetecutre is listed below.
      Cortex-A57  : x1.48 @ 2048byte
      Cortex-A72  : x1.48 @ 2048byte
      Neoverse N1 : x1.36 @ 2048byte

    We use the result "./perf/ipsec_perf --hash-algo snow3g-uia2" to
    calculate performance improvement.

Signed-off-by:  <fisher.yu&lt;fisher.yu@arm.com>
Change-Id: Id93be206bbd6aabf17e47b15df7ecd36d958d128

    Following changes have be done in this patch.
    1. Add job manager of snow3g uea2, this manager can schedule
       4-buffer with un-uniform length and different keys.
    2. Add 4-buffer implementation of underlying algorithm of snow3g,
       such as s1 box, s2 box, multiply alpha and divide alpha.

    Compared with single buffer implementation, the performance
    improvement on different micro-archetecutre is listed below.
      Cortex-A57  : x2.20 @ 2048byte
      Cortex-A72  : x2.19 @ 2048byte
      Neoverse N1 : x2.32 @ 2048byte
      Neoverse V1 : x2.92 @ 2048byte

    We use the result "./perf/ipsec_perf --cipher-algo snow3g-uea2" to
    calculate performance improvement.

Signed-off-by:  <fisher.yu&lt;fisher.yu@arm.com>
Change-Id: I37abe20f697c41a7c67e0c8231fa855d93d9e475

Add imb_get_errno to indicate the param error

See merge request !5

APIs.

Change-Id: I63414102157cc032933880c623a43c6eb0e0e01f

sync parent repo intel-ipsec-mb

See merge request !4

This is to sync ipsec-mb with its parent repo intel-ipsec-mb, it focuses
on the function as before after this sync. Some following changes should
be done in another patches. In this sync, below changes were made
1, remove all files but index.html under docs directory
2, remove test/wycheproof which is test for aes-gcm, aes-ccm,
   chach20-poly1305, aes-cmac, gmac, hmac-sha1, hmac-sha224,
   hmac-sha256, hmac-sha384 and hmac-sha512, these algorithms are not
   implemented on arm arch at the moment.
3, is_job_invalid and is_submit_burst_invalid function are changed,
   we don't follow those changes up, it's related to the implementation
   of burst mode API that will be addressed in another patch.
4, the most important change is burst mode API that was added to unify
   the use of DPDK PMDs' APIs. It will be added into arm arch in
   another patch.
5, replace intel-ipsec-mb.h with ipsec-mb.h
6, fix the bug for zuc256-eia3 with tag size being 4, it was introduced
   in multi-vector test.
7, remove .github that is dedicated to github action.

Jira: SECLIB-818
Change-Id: If95c47e109bd168f3ef7f941a34f2f79ecdc551d
CustomizedGitHooks: yes

Co-authored-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

Compile option added that removes self-test feature and ignores status of the self-test
- only to be used for development or debug
- enabled with 'make -j EXTRA_CFLAGS=-DNO_SELF_TEST_DEV'

Fix for issues reported by Coverity.

- up to 16 bytes can be read outside the buffer on flush operation
- number of conditions must be met to make it happen (similar to issue #107)
- SSE, AVX implementations affected
- all architecture interfaces affected except avx512 type-2

For UIA2, on non-AVX512 architectures if SAFE_LOOKUP is disabled then
fallback to the default implementation as it is bit faster.

avx2: [sha256/224] use SHANI extensions in avx2 type-2 for SHA224, HMAC-SHA224, SHA256 and HMAC-SHA256

It exercises test vectors from https://github.com/google/wycheproof project.

Tested algorithms are: aes-gcm, aes-ccm, chacha20-poly1305, aes-cmac, gmac,
hmac-sha1, hmac-sha224, hmac-sha256, hmac-sha384 and hmac-sha512.