- Dec 22, 2022
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RdN2Cfg3 configuration is a new variant of RD platform. To enable dynamic generation of PCIe SSDT, MCFG and IORT ACPI tables, add the configuration PCDs required by the library in the platform description file. Signed-off-by:Nishant Sharma <nishant.sharma@arm.com> Change-Id: I12430705e7b9599e802010004ed6386557e78d62
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With the dynamic configuration of PCIe controller ECAM and MMIO regions. MCFG cannot be compiled statically. To resolve this issue the MCFG table should be generated and installed dynamically from the data provided by the previous boot components. This patch add the support to parse the dynamically generated PCIe region and bus info and add entries to the MCFG table for each segment available on the platform. Signed-off-by: -
FFA use DT to pass secure partition manifest info. Signed-off-by:
Achin Gupta <achin.gupta@arm.com> Change-Id: I4ce9116e554c92790bc261f9e198969f8d000ba3 Signed-off-by:
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Enable PcdFfaEnable flag for StandaloneMm on rdn2 platform. Add fdtlib, needed for StandaloneMm DTS parsing. Signed-off-by:
Sayanta Pattanayak <sayanta.pattanayak@arm.com> Change-Id: I7553645e35a06225a2d712ed9312095b32524bad Signed-off-by:
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- Dec 21, 2022
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The UART0 controller connected in the AXI expansion space is used as the debug UART controller. Add platform memory map descriptor for this UART controller. Signed-off-by:Tony K Nadackal <tony.nadackal@arm.com> Change-Id: I8341533e6389a4ef311b84cfb2e9e05c6b5b1035
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The Neoverse RD-N2-Cfg3 platform is a variant of RD-N2 platform with a different mesh size and GIC ITS count. As part of the initial platform support, add the corresponding platform and flash description files. A new PCD named PcdGicItsCount is introduced to specify the number of GIC ITS blocks supported by the platform. The default value of this PCD is set to 6 which is number of ITS blocks supported by the existing RD-N2 variant platforms. For RD-N2-Cfg3, this PCD is set to a value of 12. Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Signed-off-by:
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PcieAcpiTableGenerator, creates SSDT table for PCIe, based on data at runtime. For CXL enabled platform, there has to be presence of CXL specific ACPI objects. ACPI0017 is a SW entity under System Bus of ACPI tree, that indicates the presence of CEDT table. ACPI0016 is a SW entity under System Bus of ACPI tree, that represents a CXL Host Bridge. The _UID object under a CXL Host Bridge object, when evaluated, must match the UID field in the associated CHBS entry. In this patch, the UID across the objects, is Zero. Signed-off-by: -
CxlDxe discovers CXL capable device with memory expander capability and reads out memory range details. Platform drivers fetch the remote memory details and include as part of system memory through ACPI tables. Signed-off-by: -
This patch introduces CXL Dxe, which primarily discovers a PCIe device with CXL capability and configures the same. This patch creates and registers event notifier based on gEfiPciEnumerationCompleteProtocolGuid. Once PCIe enumeration is completed then CXL Dxe triggers function to discover CXL capable device with memory expander capability and reads out memory range details. In addition to find out a PCIe device with CXL Mem extended capability, the module also looks for CXL device with DOE capability. Once DOE capability is found, then execute DOE operation to fetch CDAT structures(DSMAS), which carry information about CXL Device Memory range, type of memory etc. It stores the remote CXL memory details in local data structure. Later it installs CXL Protocol interface, which will trigger AcpiTableGenerator module to fetch CXL memory details using CXL protocol interfaces for preparation of ACPI tables. Signed-off-by: -
CEDT structure type, CXL Host Bridge(CHBS) describes the location of CXL Host Bridge, allowing OS to configure CXL Host Bridge. CEDT structure type, CXL Fixed Memory Window(CFMWS) describes Host Physical Address(HPA) window that is associated with a CXL Host bridge. This patch demonstrates, the addition of CEDT structures, that allows OS drivers to detect the presence of CXL Host bridge and CEDT structures and then perform necessary configuration of CXL Host bridge registers according to ACPI information. ACPI0017 is a SW entity under System Bus of ACPI tree, that indicates the presence of CEDT table. ACPI0016 is a SW entity under System Bus of ACPI tree, that represents a CXL Host Bridge. Above two objects are added in subsequent patch, where PCIe SSDT table is generated based on runtime data. In this patch, Interleave target number is considered 1 for demonstrating a reference solution with CEDT structures. There is no real interleaving address windows across multiple ports with this configuraiton. It is same as single port CXL Host bridge. Signed-off-by: -
The primary objective of this patch is to create SRAT, HMAT table at runtime based on configuration data found by discovering remote CXL Mem device. In SRAT table, the Localmemory, GICC structure information remain Static, but only configuration data about Remote memory node is updated at runtime. In HMAT the latency numbers are not tuned to actual performance values in current solution. After consolidating all structure data, SRAT and HMAT tables are installed. This patch creates and registers notifier event in AcpiTableGenerator DXE, and the event depends on CXL protocol interface, so that remote memory node population in SRAT, HMAT tables can be performed after CXL device discovery and necessary configuration. While preparing SRAT table, CXL memory information (number of memory nodes, remote memory size) is fetched from CXL Dxe using CXLprotocol interfaces. If remote CXL memory is present then from the reserved Host address space an area equal to remote CXL memory size will be added to EFI System Memory space. The memory is EfiGcdMemoryTypeSystemMemory and has Normal memory attributes. In Single-Chip scenario, one of the primary use case, of having extended remote memory area and SRAT,HMAT table, is to avail CXL.Memory device as memory expander. Signed-off-by: -
8GB address region starting at 0x3FE00000000 is reserved for extended Remote Memory use. One of the use case, for extended remote memory region, is using it as CXL.Mem region. Remote memory region, with Normal memory attributes, is included into the Translation table entries based on the PcdRemoteCxlMemory flag status. Resource descriptor for Remote CXL device memory is not created in PlatformLibMem, it will be added at later execution phase after the discovery of CXL Mem device. This patch adds a Pcd, PcdRemoteCxlMemory for identifying a platform with CXL enabled configuration. Also marked Local memory block count, for creating SRAT tables in subsequent patch. Signed-off-by: -
Introduce compile time flags to switch between firmware and kernel first error handling. Firmware first support is enabled by default by the build system. Signed-off-by:Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I7bca83550a6c512a85322244e7cc3cb120c97a26
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AEST ACPI table describes the hardware error nodes supported by the platform. The table also describes the interfaces and interrupts used by each error node. This information helps OSPM to initialize itself and perform kernel first error handling. New INF file is introduced to support both kernel and firmware first error handling by the platform. Both features are mutually exclusive and firmware first support is enabled by default. User can enable kernel first support selecting the new INF file form build system. Signed-off-by: -
Support added for handling 1-bit CE detected by Base Element RAM ECC. The driver implements the HEST error source descriptor protocol in order to publish the GHESv2 type error source descriptor for 1-bit Base Element RAM errors. The GHESv2 error source descriptor that is published is of type 'Memory Error'. The driver registers a MMI handler for handling 1-bit CE errors. On error event, the TF-A invokes Mmi handler with error info like whether the error was generated by Secure or Non-Secure Base Element RAM. The MMI handler populates the Memory Error Section structure and returns. Defines flag EDK2_ENABLE_SRAM_MM to selectively enable SRAM MM driver. Signed-off-by: -
EINJ ACPI table mandates at least one entry of trigger error action table be present. To suffice this add one instruction entry to trigger error action table. Also initialze the EINJ buffer memory region to 0. Signed-off-by: -
Define PCD values for EINJ buffer. Add memory map entry for the EINJ buffer to allow OSPM to access the EINJ memory region. Signed-off-by: -
Enable initial support for EINJ ACPI table for RdN2Cfg1 platform. EINJ table uses Gic Spi interrupt as a error injection trigger event. Signed-off-by: -
Support added for handling 1-bit CE and DE that occur on CPU's L1 & L2 caches, TLB and MMU. MMI handler is implemented that collects all the error information and notifies OS. The driver implements the HEST error source descriptor protocol in order to publish the GHESv2 type error source descriptor for single-bit DRAM errors. The GHESv2 error source descriptor that is published is of type 'ARM Processor Error'. The driver registers a MMI handler for handling 1-bit CE and DE errors. On error event, the TF-a collates all the error information including the error record registers, the context registers and invokes the MMI handler. Depending on the security state of the error, the handler populates ARM Processor Error Section information structure and returns. Defines flag EDK2_ENABLE_CPU_MM to selectively enable CPU MM driver. Signed-off-by: -
Driver to install the ACPI tables required to enable platform error handling on RD platforms. ACPI table helper functions are also implemented by the driver. Signed-off-by: -
For ACPI tables that are generated dynamically, define the ACPI table header values that have to be used to build the table header. Co-authored-by:
Thomas Abraham <thomas.abraham@arm.com> Signed-off-by:
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Enable the use of HEST table generation protocol, GHES error source descriptor protocol on ARM Neoverse Reference Design platforms. This enables the framework to support firmware first error handling on ARM Neoverse Reference Design platforms. Co-authored-by:
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Thomas Abraham authored
Enable the SSDT acpi tables for SoC expansion blocks on RD-N2 platform variants and add necessary PCDs needed by various ACPI tables. Also enable the SoC expansion uarts. Signed-off-by:Vivek Gautam <vivek.gautam@arm.com> Change-Id: Id44b87b3db5b0083fb898cb8dbfe9244ecab7e32
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Add support to the IORT table generator to generate the IORT nodes for SoC expansion block that is connected to the IO virtualization block on RD platforms. Each instance of the SoC expansion block contains 1 each of SMMUv3 and GIC-ITS, and two PL330 DMA devices. Signed-off-by:
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Add the support to generate IORT table from the PCIe topology information passed from the previous boot stage. Add the support to populate IORT table header and then populate DMA and SMMU instancs for each HostBridge then populate the info for each RootComplex. Signed-off-by:
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- Dec 19, 2022
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Add preprocessor macros for DMA named component nodes of IORT table that can be used to describe the IO topology connected to the IO Virtualization block. An IO virtualization block could be used to connect PCIe root bus or non-PCIe SoC expansion peripherals. The SoC expansion block that connects to the IO Virtualization block includes PL330 DMA controllers that connect with SMMUv3 present in the IO virtualization block in the following manner: 0x0 ------------- 0x30000 ------------ | DMA device |---------->| SMMU | | (ID) | | (StreamID) | 0x9 ------------- 0x30009 ------------ The DMA controller consists of 8 data channels and 1 instruction channel. The device IDs emitted by the DMA go to the SMMUv3 as StreamID and the SMMUv3 programs the corresponding translation contexts. The peripherals in the SoC expansion block are connected to one of the x16/x8/x4_1/x4_0 ports of IO virtualization block. Each of these ports have a base DeviceID that is added to the StreamID of devices to create the IDs sent to the SMMUv3 and ITS. Stream ID coming at SMMUv3 is calculated as below: Stream ID = DMA Channel Index + Base PCI port index, e.g. For example, for channel 1 of DMA0 device (connected to x16 port whose baseID is 0x30000, the streamID that SMMUv3 sees is: (1 + 0x30000) = 0x30001. Change-Id: Id10d0d402621bfde0b5ac74ab93a095601897bf3 Signed-off-by: -
Rd-N2-Cfg2 platform has two IO virtualization blocks present on each chip. Each of this block has one ITS and in addition one system ITS is also present on the platform. Update the Madt table entries to account for all the ITS present on the platform. Signed-off-by: -
Arm reference design platforms have multiple IO virtualization blocks that allow connecting PCIe root bus or non-PCIe SoC peripherals to the system. Each of these IO blocks (also referred as IO-macro) consists of an instance of SMMUv3, a GIC-ITS and a NCI (network chip interconnect) to support traffic flow and address mapping, if required. The SoC expansion blocks that connect to the IO virtualization block incluce devices such as UARTs, DMAs and few additional memory nodes. SoC expansion block. For platforms have SoC expansion block connected to the IO virtualization block add a SSDT table to describe devices included in SoC expansion block. This change adds preprocessor macros to define the device nodes of SSDT and use absolute memory addresses and interrupt IDs. This allows scaling for platforms that deploy multiple instances of IO virtualization SoC expansion blocks. RD-N2-Cfg2 platform has one SoC expansion block per chip. This change adds a RD-N2-Cfg2 platform specific SSDT table that has entries for all DMA and UART devices present on the platform. This SSDT table can be built for the platform rather than the common SSDT table. Change-Id: I5c8fc9f105106534585b290a415395c4d766cf97 Signed-off-by:
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The IO virtualization block on reference design platforms allow connecting SoC expansion devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by:
Shriram K <shriram.k@arm.com>
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Add the support to auto generate and install PCIE SSDT table from the data passed from earlier boot components. Signed-off-by: -
Add support to generate RootBridge layout dynamically from the topology information passed to UEFI. Use a template to generate the basic layout of the topology and then use the topology information to update PcieHostBridgeLib specific datastructure. This file is share by all the platforms on Sgi platforms, add a Pcd flag to enable or disable this feature for the plarforms which does not use this feature. Signed-off-by: -
RD-N2-Cfg2 platform contains PCIe Root Bridge with SMMU in the path as part of the IO virtualization block. To allow the OSPM to discover and enumerate PCIe topology, add the Mcfg table. Signed-off-by: -
RD-N2-Cfg1 platform contains PCIe Root Bridge with SMMU in the path as part of the IO virtualization block. To allow the OSPM to discover and enumerate PCIe topology, add the Mcfg table. Signed-off-by:
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RD-N2 platform contains PCIe Root Bridge with SMMU in the path as part of the IO virtualization block. To allow the OSPM to discover and enumerate PCIe topology, add the Mcfg table. Signed-off-by:
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Add helper macros to generate MCFG acpi table that adds the Memory-mapped Configuration Address Space description for the correspoding PCIe host bridge. Signed-off-by:
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In preparation of adding multiple SMMU, IORT and PCIe root complex nodes into the IORT ACPI table, parameterize the existing IORT table. The SMMU interrupt numbers, device ID and base addresses are all parameterized using helper macros. PCDs for these parameters are defined and the platforms can define the value of these PCDs. While we are at it fix the Coherency flags and Number of Ids fields of various nodes. Signed-off-by:
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Add MPAM ACPI table based on MPAM ACPI 1.0 specification for RD-N2-Cfg1 reference design platform. OS would query this table to understand about the type and details of the MSCs supported by the platform. RD-N2-Cfg1 platform supports 8 SLC slices. Each of these slices have individual MPAM MSC controls and register set. PPTT defines this group of cache slices as one single cache, tagged with a unique cache ID. All the MSCs would in-turn refer to this unique cache ID given in the PPTT ACPI description. As the macro SGI_REMOTE_CHIP_MEM_OFFSET is used by RD_MPAM_MSC_NODE_INIT macro, add a reference to PcdMaxAddressBitsPerChip PCD. Signed-off-by:Rohit Mathew <rohit.mathew@arm.com> Change-Id: I8e5111b51225abae4ee8a896c3817c8bb88667a7
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Define a helper macro which deals with MPAM ACPI table population. The ACPI table population macro internally calls into the MPAM MSC node population macro, MSC resource population macro, CPU cache locator macro and interrupt flag population macro. Add all the above said macros to the common header file for Neoverse reference design platforms to use. Signed-off-by: -
For RD-N2-Cfg1 (platform with CMN-700 mesh), use PPTT container with SLC included. The SLC for this platform is 8MB in size, 16 way set associative and has a cache line size of 64 bytes. This SLC also houses 8192 sets (number of cache lines / associativity). Signed-off-by: -
For computing cache ID, the package ID, clusted ID and cpu IDs are used. For a private cache, cluster and cpu ID could be zero or non-zero. cluster or cpu ID being zero indicates the first (as cluster or cpu numbering starts from 0 to n-1, where n is the count of clusters or cpus) block of cluster or cpu respectively. Fix the comments stating that cpu and cluster ID being zero indicates a shared cache. Instead, '-1' is to be passed for cluster and cpu ID for shared caches. Additionally, update the macro's CoreId parameter to CpuId to match the description in the comments. Signed-off-by:
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