- Sep 28, 2022
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Allow RD-N2-Cfg1 platform to choose linuxboot fdf file and use LinuxBootBootManager instance of the PlatformBootManager library. The LinuxBootBootManager library uses the PcdLinuxBootFileGuid to boot the stage-1 linuxboot kernel. This is an initial approach to support linuxboot for Neoverse RD-N2-Cfg1 reference design platform. Signed-off-by:
Shriram K <shriram.k@arm.com>
Change-Id: I9b4fa007f37ee2e603b6ecf92172c6982eb605f1 -
Allow RD-N2 platform to choose linuxboot fdf file and use LinuxBootBootManager instance of the PlatformBootManager library. The LinuxBootBootManager library uses the PcdLinuxBootFileGuid to boot the stage-1 linuxboot kernel. This is an initial approach to support linuxboot for Neoverse RD-N2 reference design platform. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: Ib02cf7c63125e16475a3a10424bb8d92c26a1fca
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- Sep 27, 2022
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Omkar Kulkarni authored
Introduce compile time flags to switch between firmware and kernel first error handling. Firmware first support is enabled by default by the build system. Signed-off-by:Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I7bca83550a6c512a85322244e7cc3cb120c97a26
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Omkar Kulkarni authored
AEST ACPI table describes the hardware error nodes supported by the platform. The table also describes the interfaces and interrupts used by each error node. This information helps OSPM to initialize itself and perform kernel first error handling. New INF file is introduced to support both kernel and firmware first error handling by the platform. Both features are mutually exclusive and firmware first support is enabled by default. User can enable kernel first support selecting the new INF file form build system. Signed-off-by: -
Omkar Kulkarni authored
Support added for handling 1-bit CE detected by Base Element RAM ECC. The driver implements the HEST error source descriptor protocol in order to publish the GHESv2 type error source descriptor for 1-bit Base Element RAM errors. The GHESv2 error source descriptor that is published is of type 'Memory Error'. The driver registers a MMI handler for handling 1-bit CE errors. On error event, the TF-A invokes Mmi handler with error info like whether the error was generated by Secure or Non-Secure Base Element RAM. The MMI handler populates the Memory Error Section structure and returns. Defines flag EDK2_ENABLE_SRAM_MM to selectively enable SRAM MM driver. Signed-off-by: -
Omkar Kulkarni authored
EINJ ACPI table mandates at least one entry of trigger error action table be present. To suffice this add one instruction entry to trigger error action table. Also initialze the EINJ buffer memory region to 0. Signed-off-by: -
Omkar Kulkarni authored
Define PCD values for EINJ buffer. Add memory map entry for the EINJ buffer to allow OSPM to access the EINJ memory region. Signed-off-by: -
Omkar Kulkarni authored
Enable initial support for EINJ ACPI table for RdN2Cfg1 platform. EINJ table uses Gic Spi interrupt as a error injection trigger event. Signed-off-by: -
Omkar Kulkarni authored
Support added for handling 1-bit CE and DE that occur on CPU's L1 & L2 caches, TLB and MMU. MMI handler is implemented that collects all the error information and notifies OS. The driver implements the HEST error source descriptor protocol in order to publish the GHESv2 type error source descriptor for single-bit DRAM errors. The GHESv2 error source descriptor that is published is of type 'ARM Processor Error'. The driver registers a MMI handler for handling 1-bit CE and DE errors. On error event, the TF-a collates all the error information including the error record registers, the context registers and invokes the MMI handler. Depending on the security state of the error, the handler populates ARM Processor Error Section information structure and returns. Defines flag EDK2_ENABLE_CPU_MM to selectively enable CPU MM driver. Signed-off-by: -
Omkar Kulkarni authored
Driver to install the ACPI tables required to enable platform error handling on RD platforms. ACPI table helper functions are also implemented by the driver. Signed-off-by: -
Omkar Kulkarni authored
For ACPI tables that are generated dynamically, define the ACPI table header values that have to be used to build the table header. Co-authored-by:
Thomas Abraham <thomas.abraham@arm.com> Signed-off-by:
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Omkar Kulkarni authored
Enable the use of HEST table generation protocol, GHES error source descriptor protocol on ARM Neoverse Reference Design platforms. This enables the framework to support firmware first error handling on ARM Neoverse Reference Design platforms. Co-authored-by:
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Add MPAM ACPI table based on MPAM ACPI 1.0 specification for RD-N2-Cfg1 reference design platform. OS would query this table to understand about the type and details of the MSCs supported by the platform. RD-N2-Cfg1 platform supports 8 SLC slices. Each of these slices have individual MPAM MSC controls and register set. PPTT defines this group of cache slices as one single cache, tagged with a unique cache ID. All the MSCs would in-turn refer to this unique cache ID given in the PPTT ACPI description. As the macro SGI_REMOTE_CHIP_MEM_OFFSET is used by RD_MPAM_MSC_NODE_INIT macro, add a reference to PcdMaxAddressBitsPerChip PCD. Signed-off-by:Rohit Mathew <rohit.mathew@arm.com> Change-Id: I8e5111b51225abae4ee8a896c3817c8bb88667a7
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Define a helper macro which deals with MPAM ACPI table population. The ACPI table population macro internally calls into the MPAM MSC node population macro, MSC resource population macro, CPU cache locator macro and interrupt flag population macro. Add all the above said macros to the common header file for Neoverse reference design platforms to use. Signed-off-by: -
For RD-N2-Cfg1 (platform with CMN-700 mesh), use PPTT container with SLC included. The SLC for this platform is 8MB in size, 16 way set associative and has a cache line size of 64 bytes. This SLC also houses 8192 sets (number of cache lines / associativity). Signed-off-by: -
For computing cache ID, the package ID, clusted ID and cpu IDs are used. For a private cache, cluster and cpu ID could be zero or non-zero. cluster or cpu ID being zero indicates the first (as cluster or cpu numbering starts from 0 to n-1, where n is the count of clusters or cpus) block of cluster or cpu respectively. Fix the comments stating that cpu and cluster ID being zero indicates a shared cache. Instead, '-1' is to be passed for cluster and cpu ID for shared caches. Additionally, update the macro's CoreId parameter to CpuId to match the description in the comments. Signed-off-by: -
For Neoverse reference design platforms with CMN-700 mesh, System Level Cache (SLC) of CMN-700 is treated as a PPTT cache and not a memory-side cache. Define a PPTT container type supporting SLC for these platforms. Signed-off-by: -
The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level cache. Extend the SMBIOS support for RD-V2 platform with this configuration. Change-Id: I70197ef6a1c94b6bb2f18c12c0c6c594816f5d87 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com> -
Add the RD-V2 platform identification values including the part number and configuration number. This information will be used in populating the SMBIOS tables. Change-Id: Ib8f8f95c2f04a1f4f5572d8e20893a258bdb0b9b Signed-off-by:Pranav Madhu <pranav.madhu@arm.com> -
Enable the virtio-p9 device that is present as part of the RoS peripherals on RD-N2 platform variants. This will allow filesystem sharing between the Host PC and target platform. Signed-off-by:Vivek Gautam <vivek.gautam@arm.com> Change-Id: Id195e446f40b604d5e3120947e929d8c168c0b73
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Some of the Arm reference design FVP platforms support the Virtio-p9 device as part of the RoS subsystem. Add an entry for this device in the SSDT acpi table. The device entry is listed in a new SSDT file as only some of the reference design FVP platforms support it and so this file is included in the build for only the supported platforms. Signed-off-by: -
Allow RD-V1 platform to choose linuxboot fdf file and use LinuxBootBootManager instance of the PlatformBootManager library. The LinuxBootBootManager library uses the PcdLinuxBootFileGuid to boot the stage-1 linuxboot kernel. This is an initial approach to support linuxboot for Neoverse RD-V1 reference design platform. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I4091053ee4d3a216619556bf28fe20f2e070029f -
LinuxBoot is a firmware that replaces specific firmware functionality like the UEFI DXE phase with a Linux kernel and runtime. This patch adds LinuxBootPkg and SgiPlatformLinuxBoot.fdf which includes the stage-1 linuxboot kernel as a UEFI application. The build flag $LINUXBOOT_BUILD_ENABLED is used to used to enable this feature. This is an initial approach to support linuxboot for Neoverse reference design platforms. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I952bd76487c9a643e39cd82ddcb222417a883847 -
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3479 A recent change in MdeModulePkg [1] introduced VariableFlashInfoLib as a dependency to support dynamic variable flash information. Add an instance for the library class VariableFlashInfoLib in SgiPlatformMm.dsc.inc to resolve this dependency. [1]: https://github.com/tianocore/edk2/commit/8db39c60cdf35e0a53ccdbccf7e152ab41f54f4c Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I38f14cd88ce923aeda5681b34b476cf6a7056f4a
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OpenSSL requires floating point support. So remove nofp compiler flag from SgiPlatformMm dsc file. Signed-off-by: -
RD-N2-Cfg2 platform contains a PCIe Root Bridge with SMMU in the path. To allow the OSPM to discover and enumerate, add Iort, Mcfg and Ssdt tables. Signed-off-by: -
RD-N2-Cfg2 platform contains one PCIe Root Bridge that support up to 128 buses. To enable support for PCI in RD-N2-Cfg2 platform, add PCDs related to PCI in its platform description file. Signed-off-by: -
Add the no-stack-protector complier flag for both AArch64 and x86 host build of StandaloneMM. Signed-off-by:Tony K Nadackal <tony.nadackal@arm.com> Change-Id: I2c546bf01d4b5bbdf4854c05e413c7c595c19e71
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- Sep 17, 2022
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Vivek Kumar Gautam authored
The RD-N2-Cfg1 platform uses one instance of the IO Virtualization block to connect PL011 UART controllers and PL330 DMA controllers. Describe these devices by including the SsdtIoVirtBlk.asl ACPI table. In addition to this, add named-component IORT nodes for DMA PL330 DMA controllers that is interfaced with the SMMUv3 present in the IO virtualization block that is used to connect non-discoverable devices. This node maps to the DMA PL330 device node present in Ssdt table for the platform. Signed-off-by:
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Vivek Kumar Gautam authored
The RD-N2 platform uses one instance of the IO Virtualization block to connect PL011 UART controllers and PL330 DMA controllers. Describe these devices by including the SsdtIoVirtBlk.asl ACPI table. In addition to this, add named-component IORT nodes for DMA PL330 DMA controllers that is interfaced with the SMMUv3 present in the IO virtualization block that is used to connect non-discoverable devices. This node maps to the DMA PL330 device node present in Ssdt table for the platform. Signed-off-by:
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Vivek Kumar Gautam authored
For platform that connect non-discoverable devices to IO virtualization block, add a SSDT table to describe those devices. PL011 UART controller and PL330 DMA controller are connected to the non-discoverable IO virtualization block. Signed-off-by:
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Shriram authored
The IO virtualization block on reference design platforms allow connecting non-discoverable devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I70bd3f790f51fa86707b0d300b3a70168731a4ff -
Vivek Kumar Gautam authored
The IO topology on the RD-N2-Cfg1 platform is built using the IO Virtualization block. There are two instances of the IO Virtualization block on the RD-N2 platform and one of these instances is used to connect to a PCIe root bridge. Add RD-N2-Cfg1 platform specific IORT, MCFG and SSDT ACPI tables to represent this IO topology. Signed-off-by:
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Vivek Kumar Gautam authored
The IO topology on the RD-N2 platform is built using the IO Virtualization block. There are five instances of the IO Virtualization block on the RD-N2 platform and four of these instances are used to connect to PCIe root bridge. Add RD-N2 platform specific IORT, MCFG and SSDT ACPI tables to represent this IO topology. Signed-off-by:
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Vivek Kumar Gautam authored
Add helper macros for generation of the MCFG, SSDT and IORT ACPI table. The macro EFI_ACPI_SMMUv3_ID_TABLE_INIT simplifies the addition of the SMMUv3 ID remapping table in the IORT table. The macro EFI_ACPI_PCI_RC_ECAM_INIT describes the location of the PCI Express configuration space in the MCFG ACPI table. The macro EFI_ACPI_PCI_RC_INIT simplifies the addition of the root complex entry in the SSDT ACPI table. Signed-off-by:
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Vijayenthiran Subramaniam authored
In preparation of adding multiple SMMU, IORT and PCIe root complex nodes into the IORT ACPI table, parameterize the existing IORT table. The SMMU interrupt numbers, device ID and base addresses are all parameterized using helper macros. PCDs for these parameters are defined and the platforms can define the value of these PCDs. Signed-off-by:
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Vijayenthiran Subramaniam authored
For reference design platforms that support more than one PCIe host bridge, update the PCIe host bridge library implementation to allow support for upto four PCIe host bridges. PCDs are introduced to allow platforms to specify the values for bus count and the various MMIO base address and sizes. The available PCIe resources are split equally between the various host bridge instances in the system and macros have been introduced that makes it easier to implment this split. Signed-off-by:
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Nishant Sharma authored
Isolated CPUs are those that are not to be used on the platform for various reasons. The isolated CPU list is an array of MPID values of the CPUs that have to be isolated. This list is supplied via the NT_FW_CONFIG dtb. Add support to search for isolated CPUs MPID list and, if present, update the MADT table to disable the corresponding CPUs. Signed-off-by:Nishant Sharma <nishant.sharma@arm.com> Change-Id: I9f7af896c1bcf0e0845b8b4f9f2bc199f15e6cc2
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- Sep 16, 2022
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Pedro Falcato authored
As reported by Rebecca Cran, there was some build breakage when compiling with stack-protector-on-by-default toolchains. Adding the proper library to the DSC should fix it. Cc: Rebecca Cran <rebecca@quicinc.com> Cc: Marvin Häuser <mhaeuser@posteo.de> Signed-off-by:
Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by:
Rebecca Cran <rebecca@quicinc.com> Reviewed-by:
Marvin Häuser <mhaeuser@posteo.de>
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S, Ashraf Ali authored
Add Ashraf Ali S as IntelSiliconPkg reviewers Signed-off-by:
Ashraf Ali S <ashraf.ali.s@intel.com> Reviewed-by:
Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Isaac Oram <isaac.w.oram@intel.com>
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