- Feb 20, 2021
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EINJ table is statically installed. If RAS is disabled EINJ table is not required. This change checks if RAS is enabled, if not then uninstalls the EINJ table from the platform. Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: Ib4babfcf06072522436674280bd1a6618d4c3b0c
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- Feb 19, 2021
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The error injection intructions that is pointed to by the EINJ table are placed in a region of memory reserved for it. Clear this memory region before it is used. Change-Id: I1aac512045372ac93cf1a5e2a8d670c5df7a523c Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
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Keep the HDLCD controller disabled until the keyboard/mouse inputs are also supported by the model. Change-Id: I8c5e1a923640139b1f9b32d157ed3740f36535e4 Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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Add ACPI Generic Event Device (GED) support for RD platform. Also added SP804 dual-timer irq as event source for GED. Change-Id: Id14975b2b7377e030b1d9b45a2a0440a8a9b447f Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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The HW-Reduced ACPI model has specific requirements for GPIO controllers. RD Platforms has PrimeCell GPIO (PL061) integrated to RoS, enabling GPIO support. Also adding GPIO signalled ACPI event template for reference. Change-Id: Ic6839543288baeaeb4f5f148c7292174b1d57d21 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Enable ACPI CPPC mechanism for RD-N2. The implementation uses AMU registers accessible as Fixed-feature Hardware (FFixedHW) for monitoring the performance. Non-secure SCMI fastchannels are used to communicate with SCP to set the desired performance. Change-Id: I6ab4f4e67511b7c2b3e800bd28ceb5559a78f816 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add ACPI Operating System Capabilities (_OSC) control method for reporting platform-wide capabilities on RD-N2 platform. Change-Id: Icb4afaf9bbc6d8f41dfa76a93e5448e96eaba45a Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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RD-V1 platform in multi chip mode supports 2 LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). Add idle support for RD-V1 multi chip platform. Signed-off-by:
Pranav Madhu <Pranav.Madhu@arm.com> Change-Id: Ibb9195654e767928a063625cfdd956a8f40b87f6
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RD-V1 platform in single chip mode supports 2 LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). Add idle support for RD-V1 single chip platform. Signed-off-by:
Pranav Madhu <Pranav.Madhu@arm.com> Change-Id: I4ecceeea0e3f92cfcb2602a9f947880f6427ce99
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Enable ACPI CPPC mechanism for RD-V1. The implementation uses AMU registers accessible as Fixed-feature Hardware (FFixedHW) for monitoring the performance. Non-secure SCMI fastchannels are used to communicate with SCP to set the desired performance. Change-Id: I96dcdf71c1e73b9f576250c1280a07621680caeb Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add helper macros required for use with ACPI collaborative processor performance control (CPPC). Change-Id: Iefd72ca34820b063f980efbfab55f3038841c31d Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add ACPI Operating System Capabilities (_OSC) control method for reporting platform-wide capabilities on RD-V1 platform both in single chip and in multi chip mode. Signed-off-by:
Pranav Madhu <Pranav.Madhu@arm.com> Change-Id: I62d6d00234c44cc5e717a5071200e9bec4649740
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RD-N1-Edge platform in multi chip configuration supports 2 LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). And the cluster supports LPI2 (Power-down) state. The LPI implementation also supports combined power state for core and cluster. Change-Id: I8aa625545f0066a4802c7d3bbb6d5c9e754d71c0 Signed-off-by:
Pranav Madhu <Pranav.Madhu@arm.com>
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Add ACPI Operating System Capabilities (_OSC) control method for reporting platform-wide capabilities on SGI-575 platform. Change-Id: I8e93e63a501601d497fec26a3c4c674971faee9e Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Adding Differentiated System Description Table (DSDT) for RD-N1-Edge dual chip platform Change-Id: I08cfb2b6bfb2275053634440b3b945ef14577b31 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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RD-N1-Edge platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). And the cluster supports LPI2 (Power-down) state. The LPI implementation also supports combined power state for core and cluster. Change-Id: I82b1a297f6559bead2292af4e07bc1106b727ec7 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add ACPI Operating System Capabilities (_OSC) control method for reporting platform-wide capabilities on RD-N1-Edge platform. Change-Id: I0099bb173eb924df6be7793752130eac5e7e2284 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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SGI-575 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). And the cluster supports LPI2 (Power-down) state. The LPI implementation also supports combined power state for core and cluster. Change-Id: I869254cb3a4e0ae6bc12b12938291d853210a6fb Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add ACPI Operating System Capabilities (_OSC) control method for reporting platform-wide capabilities on SGI-575 platform. Change-Id: I3bf690ff587744654602c2cecedbbcaeba6ad16d Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add helper macros required for use with ACPI Operating System Capabilities (_OSC) control method. Change-Id: I193def4d0547226a03be7594703c75fe7208bf92 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Processor Properties Topology Table (PPTT) to describe the topological structure of Processors as a hierarchical tree. PPTT also describes the Cache private to each node in the hierarchy, and the vendor specific information regarding the SoC package. Change-Id: Idf70a583b1df9100a3f06112d3cf1b6a5370aa76 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Processor Properties Topology Table (PPTT) to describe the topological structure of Processors as a hierarchical tree. PPTT also describes the Cache private to each node in the hierarchy, and the vendor specific information regarding the SoC package. Change-Id: I4e072290cac5b2c4253e8c44795823e1a139c61c Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Processor Properties Topology Table (PPTT) to describe the topological structure of Processors as a hierarchical tree. PPTT also describes the Cache private to each node in the hierarchy, and the vendor specific information regarding the SoC package. Change-Id: I1cd690e27d6460abe7506711d958e4dd802681a9 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Processor Properties Topology Table (PPTT) to describe the topological structure of Processors as a hierarchical tree. PPTT also describes the Cache private to each node in the hierarchy, and the vendor specific information regarding the SoC package. Change-Id: I781629c1359bf438a4f3656d17e1d6527e77561f Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Processor Properties Topology Table (PPTT) to describe the topological structure of Processors as a hierarchical tree. PPTT also describes the Cache private to each node in the hierarchy, and the vendor specific information regarding the SoC package. Change-Id: Iac7db22b6f824c4bec1e3a908c142cca68a2cdfc Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Processor Properties Topology Table (PPTT) to describe the topological structure of Processors as a hierarchical tree. PPTT also describes the Cache private to each node in the hierarchy, and the vendor specific information regarding the SoC package. Change-Id: I89e653a8f1adc98f435b689aeeefd32a1b2693ab Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Processor Properties Topology Table (PPTT) to describe the topological structure of Processors as a hierarchical tree. PPTT also describes the Cache private to each node in the hierarchy, and the vendor specific information regarding the SoC package. Change-Id: Id0f4a94247f6e228103785f09d8d7b264d399a98 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add helper macros for the creation for PPTT table. These macros help with initializing processor hierarchy node structure, cache type structure and ID structure. Change-Id: I9271c77fb0ead2c843b64d27e35576234587891d Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Adding SMMU and Timer entries to platform memory description table. This entries are required as per SBSA specification. Change-Id: I5268d4d69b2e55ffe27f13ebe1a1db5ccf6d9195 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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The generic timer and watchdog timer interrupt numbers on the RD-N2 platform is different than those on the other SGI/RD platforms. So in order to reuse the existing GTDT ACPI table for all the supported platforms including RD-N2, use the interrupt values as defined by PCD in the GTDT ACPI table. Change-Id: Ibf7fb31fc60424cb6500f7a7d0babf43b6807bfa Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 32 table (System Boot Information) that includes information about the System Boot Status. Change-Id: I83ca0b491682b7337cadc027e55e29ed7455aac6 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 19 table (Memory Array Mapped Addr) that includes information about the address mapping for a Physical Memory Array. Change-Id: I80b1c39735cf793aeeb95a06cae50a7aae01b802 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 17 table (Memory Device) that includes the specification of each installed memory device such as size of each device, bank locator, memory device type, and other related information. Change-Id: Id926f75a6633da60166665ff7e783755e9328c2d Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 16 table (Physical Memory Array) describes a collection of memory devices that operate together to form a memory address. It includes information about number of devices, total memory installed, error correction mechanism used and other related information. Change-Id: I427202ffd145cb2f04a72770d9e5199012cfa28b Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 7 table (Cache Information) that includes information about cache levels implemented, cache configuration, ways of associativity and other information related to cache memory installed. Change-Id: I3ec446de36af99fafde1dd6fbfe8d58bb7a21944 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 4 table (Processor Information) that includes information about manufacture, family, processor id, maximum operating frequency, and other information related to the processor. Change-Id: I4bb5ab90919faaa81573171e43c3770ca40d6ed2 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 3 table (System Enclosure) that includes information about manufacturer, type, serial number and other information related to system enclosure. Change-Id: I3fdd8edca8a505d4e8c3d232e62c50f229cc9421 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add the SMBIOS type 1 table (System Information) that includes information about manufacturer, product name, version, serial number and other information related to the system identification. Change-Id: I8b2be3429a16da2bd6f760f3b595aea9587c4c52 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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SMBIOS provides basic hardware and firmware configuration information through table-driven data structure. This patch adds SMBIOS driver support that allows for installation of multiple SMBIOS types. Also add SMBIOS Type0 (BIOS Information) table, that include information about BIOS vendor name, version, SMBIOS version and other information related to BIOS. Change-Id: Iac9c196dd4f0b7dd76f48d9d2cede0f524c8b9f3 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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Add GetProductId API for SGI/RD Platform. The API returns a product id in integer format based on the platform description data. The product id is required for other drivers such as SMBIOS. Change-Id: I5f9c7af836b8a497c30308adba8645d07abb53f9 Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com>
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