Silicon/AMD/StyxDtbLoaderLib: add interrupt-affinity property to PMU node

AMD Seattle uses a range of SPIs to signal PMU events, and this requires
a description in the DT which SPI maps to which CPU. This requires us to
defer the generation of the PMU node to a point where the CPU phandles
have been allocated.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>