Marvell/Library: UtmiLib: Fix pll initialization for the second port

According to Design Reference Specification the PHY PLL and Calibration
register from PHY0 are shared for multi-port PHY. PLL control registers
inside other PHY channels are not used.

This fixes issues in scenarios when only UTMI port1 was in use, which
resulted with lack of correct PLL initialization. On the occasion
add relevant comments, describing the register groups in the header
file.

Based on original change from Grzegorz Jaszczyk <jaz@semihalf.com>

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>