Platform/ARM: Add CPU RAS error handling driver

Support added for handling 1-bit CE and DE that occur on CPU's L1 & L2
caches, TLB and MMU. MMI handler is implemented that collects all the
error information and notifies OS.

The driver implements the HEST error source descriptor protocol in order
to publish the GHESv2 type error source descriptor for single-bit DRAM
errors. The GHESv2 error source descriptor that is published is of type
'ARM Processor Error'.

The driver registers a MMI handler for handling 1-bit CE and DE errors. On
error event, the TF-a collates all the error information including the
error record registers, the context registers and invokes the MMI handler.
Depending on the security state of the error, the handler populates ARM
Processor Error Section information structure and returns.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Id273b8bfa64ad107c7f08a4fdb9e9dc83a861b5d