SimicsOpenBoard: Use default 10ms as delay between INIT and SIPI

Today the delay is 10us but the QSP simulates the multiprocessor
by dividing time into segments and serializing processors within a
segment.
The length of the segment is configurable and Simics open board
is configured using 100us.

But the firmware configures the delay between INIT and SIPI is 10us.
That results a possible senarino that BSP sends a INIT and SIPI in one
segment (100us) while APs are still in SMM environment. The INIT is
queued but SIPI is ignored by Simics, resulting all APs being put in
wait-for-SIPI state when they receive INIT.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>