infra/common: document Base RAM ECC error handling test
Add a document guide to perform 1-bit CE error injection and handling
test on Base Secure RAM present in Neoverse N2 Reference Design platforms.
Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ie4637fb2e10a21082980e9c3bfe99d6dbb0edb11
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