diff --git a/.clang-format b/.clang-format index 0a7e60c7568c97705180c9f723d92848a507b124..31e0b6eae68fb23a2963c1fd2d33abfd0c3a3bb8 100644 --- a/.clang-format +++ b/.clang-format @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 0000000000000000000000000000000000000000..257ec9d32bcce39605a7b00b97e8e5c80284af37 --- /dev/null +++ b/AUTHORS @@ -0,0 +1,8 @@ +# Below is a list of people and organisations that have contributed to the VIXL +# project. Entries should be added to the list as: +# +# Name/Organization + +ARM Ltd. <*@arm.com> +Google Inc. <*@google.com> +Linaro <*@linaro.org> diff --git a/LICENCE b/LICENCE index 6f85a3791f5a8bae3003084e8bafcaf8b6c4dd9c..0acd8ebd638214f18442d55972cb046756ecc7cc 100644 --- a/LICENCE +++ b/LICENCE @@ -3,7 +3,7 @@ LICENCE The software in this repository is covered by the following licence. -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/SConstruct b/SConstruct index ccde2e564df2efbaab0389fbb6af66c79c75df69..074970fc30eb42eb37f11af4bb0e70b15de9fd2b 100644 --- a/SConstruct +++ b/SConstruct @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch-link-masm.cc b/benchmarks/a64/bench-branch-link-masm.cc index 11608f9eddb815a3f66b38d2c38c39bedd81daaa..9495b5c0707086e178c192d742be8598f0593b4a 100644 --- a/benchmarks/a64/bench-branch-link-masm.cc +++ b/benchmarks/a64/bench-branch-link-masm.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch-link.cc b/benchmarks/a64/bench-branch-link.cc index 4dc0495439485e42d4152ed3ee8b5dd2daa5690a..76684f6336ed668d727c93e96ca8cb433f6c464c 100644 --- a/benchmarks/a64/bench-branch-link.cc +++ b/benchmarks/a64/bench-branch-link.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch-masm.cc b/benchmarks/a64/bench-branch-masm.cc index 7fd1d105870fd148ba7fbe723cf7ab10fdce9700..22a5405537d84274da7868aeb6de8a3a2f56be5c 100644 --- a/benchmarks/a64/bench-branch-masm.cc +++ b/benchmarks/a64/bench-branch-masm.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch.cc b/benchmarks/a64/bench-branch.cc index 8976e7b227db7ad01effa0d76e8e8ec743f3c996..43121db01283e1975a7a61fe544b2907deeae6ee 100644 --- a/benchmarks/a64/bench-branch.cc +++ b/benchmarks/a64/bench-branch.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-dataop.cc b/benchmarks/a64/bench-dataop.cc index b5c6faa329d10fcee631c9350a6faa6858d7e700..a0d5dfe7c2a973e54e4861f3ee80cc20ca27ff64 100644 --- a/benchmarks/a64/bench-dataop.cc +++ b/benchmarks/a64/bench-dataop.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/abs.cc b/examples/a32/abs.cc index f819ef38d3a97be2017091a7810e66adab4c264e..50bf995e62bdba36bab559dfe64da24c1560c689 100644 --- a/examples/a32/abs.cc +++ b/examples/a32/abs.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/disasm-a32.cc b/examples/a32/disasm-a32.cc index 28280c113a0840294edb573896e4e43cff2dff9e..8a664ac4ee402db928558d5bdd1641d7c0d4466b 100644 --- a/examples/a32/disasm-a32.cc +++ b/examples/a32/disasm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/examples.h b/examples/a32/examples.h index 0e75cd59301c414f0c019bc9d229ed10fdecd350..e2af019426d2418d5bc45480f495c7fc8fa73609 100644 --- a/examples/a32/examples.h +++ b/examples/a32/examples.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/getting-started.cc b/examples/a32/getting-started.cc index 3b167d34294223f2560690b70313846dc35c4038..e7c78232eeb9f7f223d16b37f0cfc2a0080b3ced 100644 --- a/examples/a32/getting-started.cc +++ b/examples/a32/getting-started.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/pi.cc b/examples/a32/pi.cc index ebea62604173e678f52e554ebff9b63fb7f780a6..b8f4bc920239edacb6f55188b960ecb00ae4f1de 100644 --- a/examples/a32/pi.cc +++ b/examples/a32/pi.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/switch.cc b/examples/a32/switch.cc index a7a00eae5d2568e882360aadbd8a2459aad80a15..689a9b27381a115fb39c57c2aba8b731a04b769c 100644 --- a/examples/a32/switch.cc +++ b/examples/a32/switch.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/abs.cc b/examples/a64/abs.cc index f9f746c9e9f7c13655c90caddfb806a55d30ecfa..5014d36c9bc39f2156f43e086e5e30a35a6d421a 100644 --- a/examples/a64/abs.cc +++ b/examples/a64/abs.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/add2-vectors.cc b/examples/a64/add2-vectors.cc index 3ec2b995842a2d10c067919698d4081285c5bcdc..919606a85c9482cb6800d522c6ad68d3ad60ea69 100644 --- a/examples/a64/add2-vectors.cc +++ b/examples/a64/add2-vectors.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/add3-double.cc b/examples/a64/add3-double.cc index ded48f516110ea32d1e0a33ee20263f4b8785266..8590d4818f400f873f9b123c27d8473d70e4c6d8 100644 --- a/examples/a64/add3-double.cc +++ b/examples/a64/add3-double.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/add4-double.cc b/examples/a64/add4-double.cc index 897ee098ff610ba7ed98cb278a29cdb1862e5d3b..3a861d66bd5b0e2724abd70cfc978e32d83ce70f 100644 --- a/examples/a64/add4-double.cc +++ b/examples/a64/add4-double.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/check-bounds.cc b/examples/a64/check-bounds.cc index 51149c03f196fb827983b05ac842509b7f3888ac..9d2bcbadec265a04262def26b478a3619804f900 100644 --- a/examples/a64/check-bounds.cc +++ b/examples/a64/check-bounds.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/crc-checksums.cc b/examples/a64/crc-checksums.cc index 1e664549a3f6b88d501d06c9da666cd48e2ca8db..1e22245abce7ac5d3c6391bea3bf3ec123cc1cd2 100644 --- a/examples/a64/crc-checksums.cc +++ b/examples/a64/crc-checksums.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/custom-disassembler.cc b/examples/a64/custom-disassembler.cc index a75e6d7af9362de62b20af1996e0a77b62bf1058..1bf184bbd91ed2971d5ad6c98038f7eb4ff2dcd6 100644 --- a/examples/a64/custom-disassembler.cc +++ b/examples/a64/custom-disassembler.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/custom-disassembler.h b/examples/a64/custom-disassembler.h index adac833ddaf553099b4733376de595cbbffcbc80..af310c12f078af3d44949e98a588f1d5d6eb2542 100644 --- a/examples/a64/custom-disassembler.h +++ b/examples/a64/custom-disassembler.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/debugger.cc b/examples/a64/debugger.cc index 0b2bf7a0d3cfe5e28a4fd79fc1e1231bbee2b6a5..1bff8a4bab007171d27ad3bbb0f44d9d125d2d84 100644 --- a/examples/a64/debugger.cc +++ b/examples/a64/debugger.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/examples.h b/examples/a64/examples.h index 4a18a76091bd4d437b3b58ae133746416407a0d4..4a49d1c4852446ab28596b67f0d7ddf58c3fa857 100644 --- a/examples/a64/examples.h +++ b/examples/a64/examples.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/factorial-rec.cc b/examples/a64/factorial-rec.cc index 2a3c7c8190601bc7c23ee94e01ab19adee5408b7..0dcec2099a4042356e21db466ca3e7e2e7b0a069 100644 --- a/examples/a64/factorial-rec.cc +++ b/examples/a64/factorial-rec.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/factorial.cc b/examples/a64/factorial.cc index ca87ddda07b925b7e7e44b271437c3256c80a4a4..e7430060be725d3ff471e5b973ed5c9c2363a9ee 100644 --- a/examples/a64/factorial.cc +++ b/examples/a64/factorial.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/getting-started.cc b/examples/a64/getting-started.cc index 4572ea63553b7af5fc8c34656028c21a5f3dea19..465b276f151b5758d78c59c4abb6c3b4784c4fb6 100644 --- a/examples/a64/getting-started.cc +++ b/examples/a64/getting-started.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/literal.cc b/examples/a64/literal.cc index 2c8782afa6dfe18dee62b974bdb520f8a7661348..2b338763be7f23d4066b5f62d94c6f08615f3007 100644 --- a/examples/a64/literal.cc +++ b/examples/a64/literal.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/neon-matrix-multiply.cc b/examples/a64/neon-matrix-multiply.cc index 9e0db3964536627959b483c605692411fd4f92a8..0e25cfea92893bdf0bf876d44aa57add9e723399 100644 --- a/examples/a64/neon-matrix-multiply.cc +++ b/examples/a64/neon-matrix-multiply.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/non-const-visitor.cc b/examples/a64/non-const-visitor.cc index e4422650c8fb60f15b2f703ee48886591f7ad2ab..843b46257246f20684d62c99e8bfa5dce1e8f027 100644 --- a/examples/a64/non-const-visitor.cc +++ b/examples/a64/non-const-visitor.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/non-const-visitor.h b/examples/a64/non-const-visitor.h index 1df30c9bab626a34fd8250737f8cb9910dc873fb..138a990e36feac9090bc7780dbded2a8e38d7a88 100644 --- a/examples/a64/non-const-visitor.h +++ b/examples/a64/non-const-visitor.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/sum-array.cc b/examples/a64/sum-array.cc index 99e3f98ea35717dfa38d15a432e33dcaecb6bcac..2f64c3fe4e6547ff5b31cc0281027b0f70897cff 100644 --- a/examples/a64/sum-array.cc +++ b/examples/a64/sum-array.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/swap-int32.cc b/examples/a64/swap-int32.cc index e23718644cb494863dcd0873d1cddc1637ad6d48..861422db3f187bcdab13839e300cf24a964a020d 100644 --- a/examples/a64/swap-int32.cc +++ b/examples/a64/swap-int32.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/swap4.cc b/examples/a64/swap4.cc index 7a933a6aee4859db76a0fde5d96f68b94f565f34..91e9d4cf3ce01ddc81ff6767fa5cc0cbafd01948 100644 --- a/examples/a64/swap4.cc +++ b/examples/a64/swap4.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/assembler-a32.cc b/src/a32/assembler-a32.cc index 6da161cba06d8a996d5cd1235fda96ad1edb5b3b..a0b8722dae9fe38f398867a01f329b35ab4b821e 100644 --- a/src/a32/assembler-a32.cc +++ b/src/a32/assembler-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/assembler-a32.h b/src/a32/assembler-a32.h index 84a3d9f38e38ea4544cbdd57d0b7b0a9b212f708..cd40ad40c5012702d6362200c568e23b3a86de3f 100644 --- a/src/a32/assembler-a32.h +++ b/src/a32/assembler-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/constants-a32.h b/src/a32/constants-a32.h index 75cb54744c61f3381362eb4837f524a8ac319211..4f5ef74b96e53875d8cc6b09864cc4a0cdb19ca9 100644 --- a/src/a32/constants-a32.h +++ b/src/a32/constants-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/disasm-a32.cc b/src/a32/disasm-a32.cc index 4a0cedf8fb564056fb1cb4a460762d97f95d1b85..1673f6c1ab12b02470d3817026c8437fdbe2656b 100644 --- a/src/a32/disasm-a32.cc +++ b/src/a32/disasm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/disasm-a32.h b/src/a32/disasm-a32.h index c9e5749ade3b63a1d8ba22832ef8b3876c3904cb..91f62c5a61b66a243776122290b244a3e7f63a2a 100644 --- a/src/a32/disasm-a32.h +++ b/src/a32/disasm-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/instructions-a32.cc b/src/a32/instructions-a32.cc index a35ffc3e7908bb055dfbd7b58bfd251af656b974..9fff4b04f34655866bb5d6558034cf9be2a493ec 100644 --- a/src/a32/instructions-a32.cc +++ b/src/a32/instructions-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/instructions-a32.h b/src/a32/instructions-a32.h index c95f92db02bac182021e8c13375c127c0321bfdd..ff2a9066847fe181859ff2aae6e5ac9f0ed7213a 100644 --- a/src/a32/instructions-a32.h +++ b/src/a32/instructions-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/label-a32.h b/src/a32/label-a32.h index 8d0fb91b94e7b4974960f8bffd19b75af6bc302d..57197dfb276430a0581b0e655ac0848a102cbc6e 100644 --- a/src/a32/label-a32.h +++ b/src/a32/label-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/macro-assembler-a32.cc b/src/a32/macro-assembler-a32.cc index eb1d1964d9c8932f7f7508fba2c2985648f51130..cec06c7a9bb3817cc29d458dce20d2c875fde117 100644 --- a/src/a32/macro-assembler-a32.cc +++ b/src/a32/macro-assembler-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/macro-assembler-a32.h b/src/a32/macro-assembler-a32.h index 0860860c94a3a3644fbc87d7c9181737eb501152..f1c76045dcd716375700ce77262e75c2b209c496 100644 --- a/src/a32/macro-assembler-a32.h +++ b/src/a32/macro-assembler-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/operand-a32.cc b/src/a32/operand-a32.cc index 7968992ea69544fd0e31cc68c8454a8745637168..5d7b93fc74e4822da9d970406f07fd95bc4d7ac5 100644 --- a/src/a32/operand-a32.cc +++ b/src/a32/operand-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/operand-a32.h b/src/a32/operand-a32.h index a0521dbebbebe67e802e8b128443561de266ccc9..45b53340d875b649cecd586cb83d7577c9a0378b 100644 --- a/src/a32/operand-a32.h +++ b/src/a32/operand-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/assembler-a64.cc b/src/a64/assembler-a64.cc index 9ec4cd2c17edc0f852d8c2efc03703e4329f303c..702b1183daf56e5419e3753ebfa1899520590f8a 100644 --- a/src/a64/assembler-a64.cc +++ b/src/a64/assembler-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/assembler-a64.h b/src/a64/assembler-a64.h index 3d94053af4421d1beae59e15db6e77c67f4468d1..f77fe0d0d06285588f2c323e7e83dbec59850013 100644 --- a/src/a64/assembler-a64.h +++ b/src/a64/assembler-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/constants-a64.h b/src/a64/constants-a64.h index 2ad581d1dfe3e69edfad7ca4e1f6790403208cfd..911732a940ee30e2510d9f04159842a9d8d11c87 100644 --- a/src/a64/constants-a64.h +++ b/src/a64/constants-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/cpu-a64.cc b/src/a64/cpu-a64.cc index 895a1042bad33ee020bb64f7c599962b0ac4a1fe..891c51240334136c973c1411f284f657aff0ab28 100644 --- a/src/a64/cpu-a64.cc +++ b/src/a64/cpu-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/cpu-a64.h b/src/a64/cpu-a64.h index 986ac2f2192e4a3bfb21a40a45d426e37e472743..c253ddcd6106bf946e32f6652cdc7a4e22b68909 100644 --- a/src/a64/cpu-a64.h +++ b/src/a64/cpu-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/debugger-a64.cc b/src/a64/debugger-a64.cc index 48f63e0421b0a3563bf94f2dc3bd6866bd069a8a..cf3170ab4d8694872a22655fcec559976d12a017 100644 --- a/src/a64/debugger-a64.cc +++ b/src/a64/debugger-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/debugger-a64.h b/src/a64/debugger-a64.h index 9f3f2e7619b0e0ea369d627d75f8a42719dc8f2b..cb58266bf5649e1265d0691deaa1477c1307ebb3 100644 --- a/src/a64/debugger-a64.h +++ b/src/a64/debugger-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/decoder-a64.cc b/src/a64/decoder-a64.cc index 6d79b34857495d30838be1286269072a896188e5..cd2c9a70895f56aa783203220ac6f1bf64412bdc 100644 --- a/src/a64/decoder-a64.cc +++ b/src/a64/decoder-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/decoder-a64.h b/src/a64/decoder-a64.h index 35f47ecbf4bac77466ba797fa1c71b3253639275..de2f3e07fd235f69af7a258785e11cc88c856dee 100644 --- a/src/a64/decoder-a64.h +++ b/src/a64/decoder-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/disasm-a64.cc b/src/a64/disasm-a64.cc index 3ebbbea02b3afc5ec9a1f3fbc3bc5f0dbe43d866..d0fcf1c45cde65bbd8498d2d1691d5ec26dcd55d 100644 --- a/src/a64/disasm-a64.cc +++ b/src/a64/disasm-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/disasm-a64.h b/src/a64/disasm-a64.h index a8f8a0995e5b85bc826098850e45e6942e25209c..f2ebb11eeba0bfc1994332e3feb3d59a5a19a69c 100644 --- a/src/a64/disasm-a64.h +++ b/src/a64/disasm-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instructions-a64.cc b/src/a64/instructions-a64.cc index 2ed79a765b02d3972601aa02e3e706982c3f516f..202fb282fef6c780dc4465473434e91336187204 100644 --- a/src/a64/instructions-a64.cc +++ b/src/a64/instructions-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instructions-a64.h b/src/a64/instructions-a64.h index fd4a24c484d987a8febc4ac1d1b8fb1ed27388d4..b6523eb5c4f6a77835abe13a4b0a5fe4410ee6c0 100644 --- a/src/a64/instructions-a64.h +++ b/src/a64/instructions-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instrument-a64.cc b/src/a64/instrument-a64.cc index 4a77ee9560bf16e33d6345f3b79bef7770b06348..edddf43eba88f5778671242862ba079db1572a33 100644 --- a/src/a64/instrument-a64.cc +++ b/src/a64/instrument-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instrument-a64.h b/src/a64/instrument-a64.h index 7d888e0cd2d7659a6f3f8685592a7e76920c5336..f90ff23a20cfc836713db1ab43f61e5d8fcd3522 100644 --- a/src/a64/instrument-a64.h +++ b/src/a64/instrument-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/logic-a64.cc b/src/a64/logic-a64.cc index 674f3cadd7865abe8e35013ce271cd201b646c52..4a912350da00af38ad186cf3c4d17b5854c774d8 100644 --- a/src/a64/logic-a64.cc +++ b/src/a64/logic-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/macro-assembler-a64.cc b/src/a64/macro-assembler-a64.cc index ea365e80a77a850f71d754ee3c698e855fbd72ea..401d93ec931a2752eb829360cb8c6978b80d3a8d 100644 --- a/src/a64/macro-assembler-a64.cc +++ b/src/a64/macro-assembler-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/macro-assembler-a64.h b/src/a64/macro-assembler-a64.h index fcf5ec61c667e202e5d42b569b164e0507e8ecdd..483718355c75270f396d8d5e9e2836ef93741955 100644 --- a/src/a64/macro-assembler-a64.h +++ b/src/a64/macro-assembler-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/simulator-a64.cc b/src/a64/simulator-a64.cc index 7044ebb31a78ef7bc8cf85056372619fc4f8179e..05c4d9b889bbe48640b635998cfcfc3b5e9ef9af 100644 --- a/src/a64/simulator-a64.cc +++ b/src/a64/simulator-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/simulator-a64.h b/src/a64/simulator-a64.h index a9a1a1fc43586ccad929e796c79a21ad30cd831c..64a33c6ebf72abe257ed10993879bca8b7f91771 100644 --- a/src/a64/simulator-a64.h +++ b/src/a64/simulator-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/simulator-constants-a64.h b/src/a64/simulator-constants-a64.h index 8400ae052162aa021f9486030e01dd4e5731c8c2..416cb317cb2ae159068fc2b5a22ab786745900f2 100644 --- a/src/a64/simulator-constants-a64.h +++ b/src/a64/simulator-constants-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/code-buffer-vixl.cc b/src/code-buffer-vixl.cc index 522f9399aadad4bd5740ceacab8cd4e24cb55403..d2f14f542d120112691f362cca1c0288fd6a2879 100644 --- a/src/code-buffer-vixl.cc +++ b/src/code-buffer-vixl.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/code-buffer-vixl.h b/src/code-buffer-vixl.h index b9fc1ce4e36e64879ecf1e06dc65b80be6b810bd..4230dff3072660745bf17ed5bc1c4a52fc2237dc 100644 --- a/src/code-buffer-vixl.h +++ b/src/code-buffer-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/compiler-intrinsics-vixl.cc b/src/compiler-intrinsics-vixl.cc index 04735b570492ff97cd7d94f2e31ac0fbc121e0c9..ae182c7d8c2f779ea56dbc3666766a96bab43bf7 100644 --- a/src/compiler-intrinsics-vixl.cc +++ b/src/compiler-intrinsics-vixl.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/compiler-intrinsics-vixl.h b/src/compiler-intrinsics-vixl.h index 960937f0300b533a7b2ede0d1626529bd1fad54b..b27f94ebf30f6ba5c8946c2be1b61509045c5f80 100644 --- a/src/compiler-intrinsics-vixl.h +++ b/src/compiler-intrinsics-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/globals-vixl.h b/src/globals-vixl.h index 60668f47b9c2e1b563eb72a3aa92da8237007cea..e3e4a8654af4579f3a7d27b8b8f40f4112c02088 100644 --- a/src/globals-vixl.h +++ b/src/globals-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/invalset-vixl.h b/src/invalset-vixl.h index 6ca72edc916155b1348ea9760e9dbe6effd54403..8d74fdd6786f61af1916680441656ea9d86d59e6 100644 --- a/src/invalset-vixl.h +++ b/src/invalset-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/platform-vixl.h b/src/platform-vixl.h index ab588f07f549aa387ee07aecaa00869bf3fc781e..f47ebb606a063a462012fb77f9d3b194f738bf72 100644 --- a/src/platform-vixl.h +++ b/src/platform-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/utils-vixl.cc b/src/utils-vixl.cc index ad9f213b19494701a723ea0ba1601d3f8b4d1504..0f754d8548f351a8c12687f46c38c7f03265aaff 100644 --- a/src/utils-vixl.cc +++ b/src/utils-vixl.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/utils-vixl.h b/src/utils-vixl.h index d19cbac60082820b9700d82ad0f9c338c9b4ed0c..06c7551e6539a58ce86984c34ed92bc985034353 100644 --- a/src/utils-vixl.h +++ b/src/utils-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-immediate-512-a32.json b/test/a32/config/cond-rd-memop-immediate-512-a32.json index 8ca5b8b6c1830d96c849a7d3379c6f57c5053a32..780b1d9b090dc80e44ff100d37f72fe132cf3045 100644 --- a/test/a32/config/cond-rd-memop-immediate-512-a32.json +++ b/test/a32/config/cond-rd-memop-immediate-512-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-immediate-8192-a32.json b/test/a32/config/cond-rd-memop-immediate-8192-a32.json index 857c15dd4e90e16327627800c86e6c593b3256e9..7f8ce86af8c0bb524d877524583a0f775b7a83df 100644 --- a/test/a32/config/cond-rd-memop-immediate-8192-a32.json +++ b/test/a32/config/cond-rd-memop-immediate-8192-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-rs-a32.json b/test/a32/config/cond-rd-memop-rs-a32.json index 74b89d84fc170409105d1c024118f4ccef635b89..4c7cb24a08358004090d80e67739484b17ce95d2 100644 --- a/test/a32/config/cond-rd-memop-rs-a32.json +++ b/test/a32/config/cond-rd-memop-rs-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json b/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json index 7a38b8cc889e58629851cb3681a15c99021ed558..3ce98deebf77be6191d095829d8df29dd34d6aac 100644 --- a/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json +++ b/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json b/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json index da76f6d006767db01310f5aea5ff00d52edf7d87..4aaf7e340856e86d78eef008cf5274687b78d195 100644 --- a/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json +++ b/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-const-a32.json b/test/a32/config/cond-rd-operand-const-a32.json index c9d25bd931b66f6cf3e9875e558fe01a3400b447..9ec2d3ac41ab4f81b434e999c2995d7a9fb51366 100644 --- a/test/a32/config/cond-rd-operand-const-a32.json +++ b/test/a32/config/cond-rd-operand-const-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-const-t32.json b/test/a32/config/cond-rd-operand-const-t32.json index 0cb4adf5ebfcbc7ee7cb4cac1c3fd2e5f163a7d9..95d00338a2d52ef3e3ae18348735998aa456465f 100644 --- a/test/a32/config/cond-rd-operand-const-t32.json +++ b/test/a32/config/cond-rd-operand-const-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-imm16-t32.json b/test/a32/config/cond-rd-operand-imm16-t32.json index bc18660c56cb8d7920a52e68f800757416232244..21e7ee112f79067fa093614cbe4974b5addcccc2 100644 --- a/test/a32/config/cond-rd-operand-imm16-t32.json +++ b/test/a32/config/cond-rd-operand-imm16-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-a32.json b/test/a32/config/cond-rd-operand-rn-a32.json index 6d39bbd6d3f0d5b9795a80684b1f8bf3211a10e0..e7c3b13d6037645abe1c78edfaffaec32accd5cc 100644 --- a/test/a32/config/cond-rd-operand-rn-a32.json +++ b/test/a32/config/cond-rd-operand-rn-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json b/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json index 4ab52c612bb5fd4d5ba62d014725efa941969b55..3d56a5195c9b5e99bc91ad1414f957695c689697 100644 --- a/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json +++ b/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json b/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json index c2c5ff6ac5d377363a978a3bd1d7e4ac2c6fda26..e60be68ef89b18b159972b16e8caf3a3e74503b9 100644 --- a/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json +++ b/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json index 3992c68ea33416ae8830a39f099cc9777ee238a1..a7aa610ace988d0965348a74308b51203394a62f 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json index 24b662c6f63d72dd09109f2ac9bc6c7744a355a0..d20113737ccfe16b52c68870ea197cf7a5691ca1 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json index 13580fcff0306011882875edac5aeb0f9efd9ed0..815db1964bd317d44040b82ecf245ffdafdeea21 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json index 2f19d8bd6b5bdf62993bae103127546f067f91a1..2855883aca4a0344c3dbcfb09600f2feb5d4d390 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json b/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json index 338ac4f30d044fffe7e2dff9542c252edf9d87a6..882d37da7644dde989ecf806359eb06eb2292540 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json b/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json index fc2958bceb6713c35a77bc21351ab5f2c8ecdc79..e52520e6b882f058ce4a97ff9d78e41a541997b3 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-t32.json b/test/a32/config/cond-rd-operand-rn-t32.json index 37e358bbcc27da342e38b20383080982536102d8..0729be420b65d88d444441a8e87c77ff32da5d94 100644 --- a/test/a32/config/cond-rd-operand-rn-t32.json +++ b/test/a32/config/cond-rd-operand-rn-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-pc-operand-imm12-t32.json b/test/a32/config/cond-rd-pc-operand-imm12-t32.json index 9800bcbf82e7fed8c0edcc619193b9c612f8bf8c..09b4f4f3c249fcc88cf2c97fdc0e0f815bd3b28f 100644 --- a/test/a32/config/cond-rd-pc-operand-imm12-t32.json +++ b/test/a32/config/cond-rd-pc-operand-imm12-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-pc-operand-imm8-t32.json b/test/a32/config/cond-rd-pc-operand-imm8-t32.json index 05a5d7a033a9b7312c9bf34cc35fba9ae795ab05..6ad449806df9adfb1f38c733c2c0f81f9e57e1d2 100644 --- a/test/a32/config/cond-rd-pc-operand-imm8-t32.json +++ b/test/a32/config/cond-rd-pc-operand-imm8-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-a32.json b/test/a32/config/cond-rd-rn-a32.json index 0b70e4bea407dcc183ec1af2fd878882427cd5a2..6ea3d759fff7059c44aaa71d3a24d7b2ee943b03 100644 --- a/test/a32/config/cond-rd-rn-a32.json +++ b/test/a32/config/cond-rd-rn-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-const-a32.json b/test/a32/config/cond-rd-rn-operand-const-a32.json index 866bcfca3a3c6b6d8b1ebb720f68c605d19466b9..582871a43577a95664e7deea47e63ba50a2ea378 100644 --- a/test/a32/config/cond-rd-rn-operand-const-a32.json +++ b/test/a32/config/cond-rd-rn-operand-const-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-const-t32.json b/test/a32/config/cond-rd-rn-operand-const-t32.json index 4d739c776fbdced677d98ba0dbdcf80688c6ee97..4d72b5e7ac3cf08ed2a90980b07d66bc9ef34d4c 100644 --- a/test/a32/config/cond-rd-rn-operand-const-t32.json +++ b/test/a32/config/cond-rd-rn-operand-const-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-imm12-t32.json b/test/a32/config/cond-rd-rn-operand-imm12-t32.json index 32efca9349489c6c231a296489606dd1fdda820d..c4ac2f5b7b46bba2a982bd819bc1fe53cf15b4f3 100644 --- a/test/a32/config/cond-rd-rn-operand-imm12-t32.json +++ b/test/a32/config/cond-rd-rn-operand-imm12-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-a32.json b/test/a32/config/cond-rd-rn-operand-rm-a32.json index 8a0789916e43f7ce831b0f35841e2d24165f0682..2b7419471edc8c25239246787ebfa956127c3120 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json index 8e3b77da2cc14e2d6610eb7f7cffa6ab419d0640..8092c11cf0d0c4576b69506a5790709dbe5e81e5 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json index e834306ac7ce6da9238683a2269aaef701e28c76..bb74af07025540b30ae766e629e84d666508c940 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json index 9c4511727a029205ac2a929e49b6e59e6dbb12ac..5a62acef197c9ecc26d1065161caad4543092222 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json index 826c5113376fbe2da7d222efe67e850bea8cbc6e..9419e095381826ee995fce56034975021baf0893 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json index 04e176636232e56a1b912a1773a3b9860eb6145c..e173d30738a907ea391beeb5fda85cb3c9cef52a 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json index 4bbeb3cd8d8f4f0966de889e7ffa8f8c348b69da..5749bdd635e53def92696142f3e259f70498be61 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json index 6827ba1f6e4b09b1eaa5c6fb539e87a35ebe04a8..8a01da4ea3e5723485c7ed8846fb92f8670b7856 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-t32.json b/test/a32/config/cond-rd-rn-operand-rm-t32.json index 2430ea2e4ccfb7520fec36f5c410414e3ddba433..041988aeec0f8449ff450dc486b2654b93d9e7d5 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-rm-a32.json b/test/a32/config/cond-rd-rn-rm-a32.json index 186992bc11aa59844873fbe452a1016610bdeb9c..33b236fb07329eaa467eac80cf390350191b7fcd 100644 --- a/test/a32/config/cond-rd-rn-rm-a32.json +++ b/test/a32/config/cond-rd-rn-rm-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-rm-t32.json b/test/a32/config/cond-rd-rn-rm-t32.json index 8f93e16af79e099e9dcbccb8aba23c407b49b8a2..e73f8b658ae0ce3bfbb7425cc239ca61e19d32c3 100644 --- a/test/a32/config/cond-rd-rn-rm-t32.json +++ b/test/a32/config/cond-rd-rn-rm-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-t32.json b/test/a32/config/cond-rd-rn-t32.json index ee8237875a5d3fdf43544f63f1aab7e525e56cc3..c0fa0b9b0d5292087405f29eace568a12c3924ad 100644 --- a/test/a32/config/cond-rd-rn-t32.json +++ b/test/a32/config/cond-rd-rn-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-sp-operand-imm8-t32.json b/test/a32/config/cond-rd-sp-operand-imm8-t32.json index c82503d46bc6e6ff255570062becfe30b0bae366..44a6da439cc80c5b4291a2c804cfd9ddc95db21f 100644 --- a/test/a32/config/cond-rd-sp-operand-imm8-t32.json +++ b/test/a32/config/cond-rd-sp-operand-imm8-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rdlow-operand-imm8-t32.json b/test/a32/config/cond-rdlow-operand-imm8-t32.json index 875ac39c878ba4bdfca5aa312fac71359305b5bc..240831fee52d4c7413c0e68106c647e77741e01b 100644 --- a/test/a32/config/cond-rdlow-operand-imm8-t32.json +++ b/test/a32/config/cond-rdlow-operand-imm8-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json b/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json index 73e687671cef8c5324aa5948b8ff4bd7b305ae6b..9c53053e6d05eef2b396013731b45257d5c1aa4a 100644 --- a/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json +++ b/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json b/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json index 084a1cc4e1618a0dde9cdc89e50b8152f6b0cfb5..0c056c44f72f9c63fb17367d79b69ac200ac1945 100644 --- a/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json +++ b/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-sp-sp-operand-imm7-t32.json b/test/a32/config/cond-sp-sp-operand-imm7-t32.json index a7ad7315a156ba2af5292e4ce444d930b0e05fbc..6d9b042900bc252e768101621d0f6f65c52c0902 100644 --- a/test/a32/config/cond-sp-sp-operand-imm7-t32.json +++ b/test/a32/config/cond-sp-sp-operand-imm7-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/data-types.json b/test/a32/config/data-types.json index e8f8c3737704da77d1953b23f095d6a8451b9d2e..717cae697682a6e010bc312bd81a17f05fc7bedf 100644 --- a/test/a32/config/data-types.json +++ b/test/a32/config/data-types.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/rd-rn-rm-a32.json b/test/a32/config/rd-rn-rm-a32.json index 9044c9d785013e86cabac9c1036d6c3784f8f8be..8465a008a9bdd9385665e427568f9f7d08fd267d 100644 --- a/test/a32/config/rd-rn-rm-a32.json +++ b/test/a32/config/rd-rn-rm-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/rd-rn-rm-t32.json b/test/a32/config/rd-rn-rm-t32.json index 393717b6ee019f603617e224fe0cb892192b9004..832e3a8f71560a5ebc9aba629ff0d378da35cd70 100644 --- a/test/a32/config/rd-rn-rm-t32.json +++ b/test/a32/config/rd-rn-rm-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/template-assembler-a32.cc.in b/test/a32/config/template-assembler-a32.cc.in index 51b91d2674cc14f97d4b451406cdd62f890388f1..7f608fee4005db4fd759031c10ddb349cda5d2de 100644 --- a/test/a32/config/template-assembler-a32.cc.in +++ b/test/a32/config/template-assembler-a32.cc.in @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/template-simulator-a32.cc.in b/test/a32/config/template-simulator-a32.cc.in index 945c799b473056ef551611e09e07d1ecf91c8350..48c8f81414e08216955bb80f16666d36fa508f37 100644 --- a/test/a32/config/template-simulator-a32.cc.in +++ b/test/a32/config/template-simulator-a32.cc.in @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-a32.cc b/test/a32/test-assembler-a32.cc index 2eff5ce6b54fde43e1708b12b7758302d2077d25..525873a6454e11ba97789aa845240c84e4777694 100644 --- a/test/a32/test-assembler-a32.cc +++ b/test/a32/test-assembler-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc b/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc index 219db4e90603bfa2409165feaf48cfd0308c9248..26ce6e1c5d29cfb057e67c7f6ad1b5f3e284a0ff 100644 --- a/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc b/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc index 370575ee0c62c2878d5c2288fca308b9d8b1a89f..360081fa9b794998fc39e382e0ccffaf62513c97 100644 --- a/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-rs-a32.cc b/test/a32/test-assembler-cond-rd-memop-rs-a32.cc index 9aac9528d6935acb8776c4bd4df500e10a25008f..19d44bf8b5b4696ca80c235009c8e2a2be76ca56 100644 --- a/test/a32/test-assembler-cond-rd-memop-rs-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc index 20257555f8039b1637ac53c9c2274577c3af259b..1c46cba0e7d09203b1f98ea8c744e9195d52f079 100644 --- a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc index 554f1669f35cff165ebe7c688e2965b55d156ba2..e6b77d14245f61ff29383501a7fa846bb2e56842 100644 --- a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-const-a32.cc b/test/a32/test-assembler-cond-rd-operand-const-a32.cc index 190079dd4c1b2eda225742b62bcf330df63d1411..f39f57ed3518efbf5fda262bf8c448322c705790 100644 --- a/test/a32/test-assembler-cond-rd-operand-const-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-const-t32.cc b/test/a32/test-assembler-cond-rd-operand-const-t32.cc index 4c2707c29ed64b93769ce39732418b60c4371137..4d703bfd54f3bd4eba1571e0b1cace40b2eb3a07 100644 --- a/test/a32/test-assembler-cond-rd-operand-const-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc b/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc index 2af27b3d647c9d630a8e6b22be86ab74c07dc9bf..8ac6c19dc9965c3d33d4630db417f58dbd4eb00a 100644 --- a/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-a32.cc index e1521785e79f89412587ec9ae4f90bc48214dcb7..539a3117889e611179bebee834c100e0d9bb6329 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc index 1d7ddb17a07b7b1576d3d4aabf81411c6916ab1e..563a4f64969ad85f20481af6b414636dd9774789 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc index 8e3a9f11d87e756b33b5e7dda8b6b0e3ea0acc3f..6da504e324af5833a3f75fa0a9c2e6ef8de09f59 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc index ff8523889dd2d21ceedd98226ce8f8609e6a8f97..bd3d920b373bed6767f42633e69b5bc14a2a0ed7 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc index 0f7a74796f918d504e286031955a6ce44a5ee8f9..6aa8c0704622b5c41cb2c8933d5a9549192e540a 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc index 18aefb1928f748a284f0b56da61003680ecf1d85..71e55d8c0eac27b0b8a698cb16e7f40980d37458 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc index b9110ff7cdefe52b48d3bce24dc084bacbed7081..30d39f4073c0ef351baa0b6e3d88e7b9f61cdec3 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc index b7968dcdfff657ab7be33f0f1b60063df719041c..ae7b003bb7ab97a85aeab9af1112b97d95633c7c 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc index e13992e6d9513aeec41cb7e0974196076b9d96c1..672ef1784e5b05c98c54136117e82451976440b7 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc index 292de9cc152694d02004c7507852f297975f6596..c9f4df77b0b7f1ed3b3607f35425fe57ca855784 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc index 7664aa1bc72e6e7cc20c498882705750c44222e5..e8a9cf341a621ae1e576acc6530e78f7bad4c8ab 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc index b4d6e8531c2f37bb6fc57b533a64e29031c40970..46072c872480d4e7fa91467017af5bf4995224d5 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc index 705bf4ee74a3578562b3d99fb2c74691d796b38b..3a621cd0faaf4088427fce92925bd3bd1edd4c12 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc index 014263c6f4f04408c99239ac2811423e501c5ff0..de1a1789240d88615399cbedd66f184134daddf9 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc index 0bbefdf9b80d0cd9a4b4a3ff8d9cc00d78e61ded..71aee3aba2f58a8adaff6ffa7dc2c223d8317f83 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc index a5927d37ed9c56018b7b89d1d5c6eb7bb269f2ba..e02ab2e72b868b975349de0b72dccdc5a3c3b91a 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32.cc index 2e014936cee86e9d5557d4a7e78b066baf409a35..7964d5a82252bb0c75f5c0e42a977dfff7865913 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc b/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc index 2b3b2e3849cd39ece0eab933af9e91a13501cfbd..cfdb0e4aa39b631f2cba231724f1d5bacb22d7d7 100644 --- a/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc +++ b/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc b/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc index 60b0afe2c61360299e83d19503ad35af3f9ae8b1..e00080998e6a9a6556731826221c9cc3e8f7928b 100644 --- a/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc +++ b/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-a32.cc b/test/a32/test-assembler-cond-rd-rn-a32.cc index 477ea7b99491afff92aa8ec4d68cfbd52558c961..d30ba55576809d0cd2848334f138b876902de35c 100644 --- a/test/a32/test-assembler-cond-rd-rn-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc index 86cbff838047d50db32a5fdc9eb365f3a907f45a..2572bfad30a22b583efa765b4f43857a778d1c4d 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc index 727fb091f36c75d91a315a49eceb9f57a3d6e0c1..a0a5d0f19a10a8a69d3a7cbbbff87eb785e4ddf1 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc index 2dc502dad971b82da415445d1b5aa4a4f87f5e37..beea28dc709849a47e04fa4041cde57639d2ac45 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc index 120c30f6efe11ab8d176c19211845650d95b2b12..3c63fbf475b0c9272b6c447eb3bda8db24eb316c 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc index 6ee0939731c0b6431985e7677f10a5e047bbd293..c65a3fd4a11dd8ca55eded31853dec2a09937476 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc index 5477ea9e1905fdd72b5eea87cfbf6d523d06baae..36220ebfb665cb76cfb8e4d5ea069d3bbea86307 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc index 57244520e5abb4509ded108a78d40cdd127c7860..89ef78380732010ba32859fc9abaefe27adbe1fb 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc index 44b5299d5fdbf5e1c5103b4ad8a776cf6e2162ca..d5b4dde972948938966233c0251a11193d45e841 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc index 5efd10cb25dfda66f877194b676457409ef23c4f..dfc23a18849756e22e0e3cf74225b1939315ae33 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc index 8a399ca346f78fc1e5dae2aed8e68f219fa0fa08..7977c40c1290dee64dc336cde0a8c8cdea5b9f42 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc index f02b8b93f606ee3c70f63b4335ba70da030d3b67..8ac47a48f0706e2afcb3a3fb173f7ca81f3a7ffb 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc index 1487fde77f150e5580b4629d5c82fc76c1e559b1..d711f99d42b035cc9a55dd43faea5bf386018a7d 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc index b80f5525b18adace802c08ea77581a7627156192..1cb335cba0ab42f069994f9aa84d3005e93e7af1 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc index 0f710f62f76baf575e0a3a67eecfd593d970f101..61cc58edaf29358adba1c628914fe4d90cfb5954 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc index 8eb851d8f8aca6c535ed9fed8416af9fa8a49ad6..4095143feb9d93df1f3bf56aebf036ce0e033b80 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc index f4bccbaf62e888872344645169b7347bec9f043d..2b61f100da095beb13febb4bfa126e39e75d9f7a 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc index c313ed27166f351fe02087748bce876b9ce16cd4..75321814b237e2c531a37f13e456cc2bea9bdee6 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-rm-a32.cc b/test/a32/test-assembler-cond-rd-rn-rm-a32.cc index 77b637db68c306133fe0e883c67f61d61ebeecf5..3bf6a2699c2df8020a0075d720a8eb66dd918718 100644 --- a/test/a32/test-assembler-cond-rd-rn-rm-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-rm-t32.cc b/test/a32/test-assembler-cond-rd-rn-rm-t32.cc index d6927a1175a72daba9db78671805f5227e400f91..02e2a6aa639855b4ca433ad0dce86195f8ba7c6c 100644 --- a/test/a32/test-assembler-cond-rd-rn-rm-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-t32.cc b/test/a32/test-assembler-cond-rd-rn-t32.cc index 2143ecc831db9fc5f3d93cba1c826e50e32503a1..367f986388c9f36e807729971db04954838a4ddd 100644 --- a/test/a32/test-assembler-cond-rd-rn-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc b/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc index c1a9a9aa4fe4918ecc0b58ba3bab2fffe323a3c5..8d3090e75e16e2934802cbadf14e047b4bef6ff8 100644 --- a/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc +++ b/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc index 19340a1f4bb66f6d8f2ffb64c189798e2c1e9505..4b5bcaf120d755b0626f46272ca272ff7bb9c1ae 100644 --- a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc index f745581d1149f6ae6df2cb5af21ffd81246b5add..0ecab756b79b9d1cc8a78517c1eba8a0f28ec459 100644 --- a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc +++ b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc index 57c998219dfc0bdb448f07ad9f6884d5e1040729..7b6021748fe235fbff6982337f304b9662dc8de0 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc index 244d826fcd784a1874565deb816deb2cd609a950..8f336894ba0382af928411445af7ffc74ed047be 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc index b2de652da02018a2aa2b883c1de1c66c298ecb69..a017855be74e4870754767dba0f19470fc6080d0 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc index aaf59397b0f765d730a51a4c26d33d9db1e7d39c..79ca6f721a793ef4d034fa5829ec13b33d33638a 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc index 09c4b2977f75e8a699f9fe7dd949cfbae98fe6fe..09a2cdfb3910aeb108bee493268706da86d98588 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc index 1acb35934ebbcb5b03aea62e4ea33fc9e129762e..649ba25ee59d4444c7737bc619b1b04fa4b036ef 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc index 310e92bfca1b44b0ec3dd6d21acb88d615b99a27..5e2a4db1d5e9975829907729683935976b1a07d0 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc index 2ff468326de2f37e042597b13e6bcb74706623c9..31128720f77230066008d34553946ccf6222a302 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc b/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc index efa2b1b577781dc1977e0a0be212d54297d1f8a2..2d73076f846e613cc639531d0a8186c8573b77e9 100644 --- a/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc +++ b/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-rd-rn-rm-a32.cc b/test/a32/test-assembler-rd-rn-rm-a32.cc index 75c39a896c1e74779b1eb56ad9ff8ff15e6b30c7..58b69cd41a1ff84542b39d15ffb19ef21d48f11e 100644 --- a/test/a32/test-assembler-rd-rn-rm-a32.cc +++ b/test/a32/test-assembler-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-rd-rn-rm-t32.cc b/test/a32/test-assembler-rd-rn-rm-t32.cc index d4a5b438415ad604c431c74a7dc9e7f4d91cc59e..6e71708f2eab87e016ae7ba77bc30001a1e8568d 100644 --- a/test/a32/test-assembler-rd-rn-rm-t32.cc +++ b/test/a32/test-assembler-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-disasm-a32.cc b/test/a32/test-disasm-a32.cc index 38e3ef8024c0dce86774bd2d97e9b792b9780fc3..7679b8fad9e8dfb6fea657706282670587c37143 100644 --- a/test/a32/test-disasm-a32.cc +++ b/test/a32/test-disasm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc b/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc index 3bafd82beea2c6ec46a9c9c5688e66e64b019560..eebc757deebe79a4ac91698412baea1d60b4d426 100644 --- a/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc b/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc index 1875c3e2c251264075f073754ad23eb6e37fcb08..2ab6bc00c6f5d7d7f9ea79a60c38a6201321378a 100644 --- a/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-rs-a32.cc b/test/a32/test-simulator-cond-rd-memop-rs-a32.cc index b13911bbf437850cb699bbec4970afcc02134d99..6ddc2e4a860ecc68cdbdbe97772df0bcc654178a 100644 --- a/test/a32/test-simulator-cond-rd-memop-rs-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc index 05ca3a3dd7b6c613c84ca8a974557a31c06cb675..2b362ca30f8163e594fbbdd13098923bce4b5be4 100644 --- a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc index 3ca7a2a4b9f34a55383d1534c7f38786e311269e..3550f41d694684959b4838251d2ddacbdc50d65a 100644 --- a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-const-a32.cc b/test/a32/test-simulator-cond-rd-operand-const-a32.cc index e7feedeefd0507b35bd58a3a60400b8f229ee838..dce994a47fa75789e88081318a2cb0c1b69cd88e 100644 --- a/test/a32/test-simulator-cond-rd-operand-const-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-const-t32.cc b/test/a32/test-simulator-cond-rd-operand-const-t32.cc index 685e61df8c1adb798f1a03946dd1c6531d325660..4d1eb5dba563b41ef335f1a6ded739c8927684aa 100644 --- a/test/a32/test-simulator-cond-rd-operand-const-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc b/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc index ee206135ba76be64b70a4c7ebd65f956cc9a346f..273d67c4a06b2b80da290e9ccdf1f2e91ac59313 100644 --- a/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-a32.cc index 44a68f6cddf148d36bff2e432697c8d6b5c86d45..8c68aa5b8c8d13987037b4bc2cbbe8cda298e9cf 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc index 5c2c1353b89fb9c95136fe0b60feb23e20d20df0..d066af05833de3f4f170364c7014f33740d3eafa 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc index 652bc19c62f04520cab825a58afa83aca8cc0658..7e365040e1d8d11d0bf31c6b2c6dccaf199fb448 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc index 372097e0b4ff943296bd2b11eda36459bb054bc0..a426cfec537728e3ea6c19a997c5c694cb6e19f6 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc index 244ca013f67ac4b0b6bcad3f95abecf18d611613..98cebe8366b88ff22d8c96a1a166fbc06b537e16 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc index 58898e4db90a32124ff47c2d7dccd7ae273f4fd5..048a4d6e454a1f7ea978a470ac5cce0115669c0e 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc index 64069a640a675c5e4297ffba1f4a848283fb83bd..33a46d26360446779cb6c74b680080202ec5da06 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc index 9eb9ab1546490f4635af9fc7055d6856ba4445e1..c2c1010bdab37597804114e8e93ea203a4d71faa 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc index ce47fd79f80590ace627e5239497fb330528abc1..49a5af619524c34e1a15b82ba24bb0deec698d81 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-t32.cc index 1dd23768379b34b850f98b8b1a7c597e54c7bf75..799e90ef3a501f86c2d914637811c05266cc3c4b 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-a32.cc b/test/a32/test-simulator-cond-rd-rn-a32.cc index 0ebb165c6cf213c88a6309cafc02fe91b0e2192a..b3612a32b6e34a7c8ca38ef66e44f13d8e7e26f6 100644 --- a/test/a32/test-simulator-cond-rd-rn-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc index e4b9e8eb9d9adf250ff798b0bcc6f417cd2dac3a..b95a0538d85a91ae3a39e4e166a122838616dc6a 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc index c5be86e92e2b02b2097967e25c6c63d25734457c..e21bdc1683b280b4d1abcf1ce204d5d559bb6b68 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc index 1033c37474b9448c8e1f0e058192b65d392eef11..3c9b7cef11de4c32d37b658e090fb9d8098fdc5e 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc index b0a0d514baa9000bc80978ebf0297339076f7f11..2d12bfa2e26d0591f2e150a93ba3330abaabc588 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc index eeb53e0d66b1d2e39771041ce667fa23afb2d59a..e8fb0f3d3d7ce7dafe3f4ec31c0f8dcfe2077ae9 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc index 61a7501da4dd9036edd5e2787900525d53dd4723..8e00e2eba48e8fabecc896531621759ca335a351 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc index 273a2c788707c1282e9dc47f2034daa75cc1bb24..ae5c97593ca49e9c86542b664aa857efac1bae8e 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc index 99577328edcb8b21b2bf606bd34f2a65a716c54c..889edb42e3019d5fb482f780a7cc0981c5cfb06d 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc index 2ce9a4424c92df14065bcece52b594b2227ec87e..60194fa2696df2ecace64893425c7ccb315d609b 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc index 825e3bcc5ce826b04b50c41d347112203ddd9070..3943cfda62a344efabe6ca470554ed051f596b1b 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc index 257993139d9ed3016caf9d7bce02f757f7354328..06db8a08ebe0750c6838785616b0618beeda84cd 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc index 2db1a9713507f1b3e8107cbd866428566b869d4e..b1c972b26dd52461331844408a7d34982f3242db 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc index 9def547e6a071b48613787b17b216aaacbd9e9e3..d7ff20dffd5cd85adcc86e33ff30f42d7c0361e3 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc index 6c0d4d813f763a443a8aa553ddab020f04477b8a..a08979c34cde576420ef4e306580819b296f6e47 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc index 7dcc8f59c33ea6a222a6d1c962bd42377423dbaa..486fd808d33138118af2990704525ba113ba8b1f 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32.cc index c902d0f757d41ee164ff22bd2e0f9893ad2c6b3a..b97d3cc6cc54e8c61f97055650b876160e7cecca 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc index 6ab46934d6b2f49a52e7f64e0e800c6b355a4282..7a07133cf71d2c19fa86cefcdc5226a2ed21e361 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc index 036be0cfc24dd112e909a27f052f50f55726c768..992ca561fd86fe3a9f0e65a4d84db4172eeceff5 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc index 9bec2908b4f3e44792484971faeb1b62c59aa0ca..50467c419b47c3f15b4cc2d7a62b973434f7bba2 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32.cc index 89a9e8aa30bb65480fe8a79ff41c5413d5390dbb..fab30bc98bf38bb63f6066cb85e67843a988654b 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-t32.cc b/test/a32/test-simulator-cond-rd-rn-t32.cc index 5c910deb5b16707f7484e03b0780895378a0fb68..d441af4b7c24fd83814ff5aaa8c8624eea1da398 100644 --- a/test/a32/test-simulator-cond-rd-rn-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc b/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc index d65018405f4bde847b2f0118ae0892385d8fe689..24f4f4af38e0013cd1b8c1fcadf173fb96c1a356 100644 --- a/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc +++ b/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc b/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc index d1686a31b776a95250c8db0213c2a67c9909fc72..4d75e27b0694b832dad5fdbf7639c48b7a920a2c 100644 --- a/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc +++ b/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc b/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc index deadca49a2bddcaad2b43da353619c3c51520d3b..5cf1244026f2c6796d5f39bbe311f24b2a1f718e 100644 --- a/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc +++ b/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-rd-rn-rm-a32.cc b/test/a32/test-simulator-rd-rn-rm-a32.cc index b3b1075ede7f4e0f3b7e68e6cc91d94e39c64d8d..afc8a58e9b0068f3a331acb1bd131f74da279c79 100644 --- a/test/a32/test-simulator-rd-rn-rm-a32.cc +++ b/test/a32/test-simulator-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-rd-rn-rm-t32.cc b/test/a32/test-simulator-rd-rn-rm-t32.cc index 098752f645c42e412f1a5e7f9345b1fef9cc579e..a55380bcbebfd100c32045f4b553f6edad0580b9 100644 --- a/test/a32/test-simulator-rd-rn-rm-t32.cc +++ b/test/a32/test-simulator-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-utils-a32.cc b/test/a32/test-utils-a32.cc index 13ff9241536222bf11bdba45541d315137de747f..0837baa571799b7913ecd6bebb36bbe697ab0b00 100644 --- a/test/a32/test-utils-a32.cc +++ b/test/a32/test-utils-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-utils-a32.h b/test/a32/test-utils-a32.h index 7d238b7544af6212a019edb7c429b5cf7369fd26..d4e78876cfa75cdfba8ed787fa984134745a56d9 100644 --- a/test/a32/test-utils-a32.h +++ b/test/a32/test-utils-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h index 774371d70f7f46f2e47967778c6c9adfa4f1511f..0e3c4d94b014ae0905f9f0d83291643e9e8fba82 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h index a5d0a530868e9d4c0154b9983d22d6cca4990cfb..ea09d7f4bf40df8b52cd5272aaf00ddc01dc8599 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h index a941c15605f7a56ab6910b4ebb93fd19fd1ce329..6c803f3043a514e54b6c8beb3bb25da140027901 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h index d57a37b66ba93f893c5114fbcd010cb5978ed3b1..f2162b053958eae6e957e92846fa85cdea9d92c9 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h index 4b1e89dab2246bd0f239528591ae3b762fa84c0c..a0551acce7d0c895e79ee358a2d0d178fe2ee1b2 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h index 98f8b04d9a4d8aeb52df944d3b544850664839a4..e892fd84c3db8f875eae668e284b0eb820018c88 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h index a5fe23ac1eb338670cb64445a0717cf23920d4d9..48420a695cd9c3beb8e342b4fa35f9a5de051368 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h index bd924413d7eeacc382c11f43c67a1780890b9b97..28907f351dafb53b5d7e5a112f311a31bfee4599 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h index 0e89be3a9788a93598b50b9e6de016a37fdfd2cc..f7acdec647603d87df4b631474ee3532dda94c6b 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h index 2bb5d0108f5112b6c770aef16629cc9f30e7cf72..deb0d774daa989913ced7ea62b663982436d3abb 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h index 50b241dd43d7ebf77eb2023497c59fedc6b7e5ee..af38f446f87bcdc62ce907a9bda17d9eef8604d5 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h index a1ac6b3b93a40f700ae2c8f92cb9d20aea781255..fa11b093eb5bd438da981f4fc4d0700f34cffdfa 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h index 83f04941ff0be36c9f37e91481d65b88b52745b1..b65dbdb76d3fff1e9fbc2be97de785cfb97016f3 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h index ff1793c2578376342d1cefedb6648d2c63617710..3aa10f6b1a3f45375bd8e1764345ca1eff1163c1 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h index c4639852c7bd9b144cf4977ba328a4ea6d49bab3..0af6f63ae58098f7bce146c0a3fdc0cf99b17433 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h index 591a1b18952e45539e958e5edbc5ea3fe78102b5..bb58d50f803f9e6dd5aa12cd4c18be3d679dff0e 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h index c27875ff6cf75b0b0874dfa4e7b4eafd66486835..f966626dc99d71e59433e3383917110daf64b115 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h index 832d31187fbc837ab7e069e5a6a1b9e68f1ea6dc..a795078118a4fd53d904ded2a8821ca90d126d3d 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h index 4ae30c99be6691fb1c7136eb9bd6e356ae04911f..9fd7e505a62af7ae6db18f5b0426f81766c45931 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h index 966e66e864c47bfeed5b5c1b98eb11339e246c3c..57cc690b38e0564507c4f50e6438fef88f9d0d44 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h index acf146b19c05181e35b47f7385ba310edf9032b1..d9b620b55b2be46fa41119a2a6e6b415ae29da1d 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h index 16387b2a348da082afca7c3f6b1b2420a1db4853..03ad46388713b2e827d0f88e3210b6efd2fe8767 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h index e70d9a216f925c8325879356c005b01a99fab0b7..189c4921ea90ec39e7d3c6dca75c3826bee82d47 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h index 463370661e8f28e62096dae3e2b12a3ff2d8aa7b..e19adca4683e72458ae0de03cc570f9103c719f5 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h index 6b95d71ee5d958489d6500f19211028ca22c39e9..391faf7e1a9fa70de1efcfe4daddf4d612c10d4c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h index 28247d5d80d35976a476fe6b812c647957904458..33785a7b8db75009f608451648177eb0c69e003a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h index 4c181722ae4a7d56d393f4f7958fcdd4de9d9f20..31c221c05c6712b85f47e8cbdeb51671f7b39f63 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h index 9df01fd7e01a89a824c4ff831580fe9804c04435..52baa580357691143a53154ec0d07268719d9921 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h index 4fd1bcd07ac92c6eac983a975c29d5c0e8687222..fd8d73def118df25d4629d3e997f5d076379220e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h index 62d50511745625ddab7ef7ea10c9a1aa2c8f4ab5..533e5e9c4ef6658734aab78128fedec497baef0a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h index 3711ca2ad445013af98186480da030c4304c797c..e8cebe7f85a879373c39eb564a51193544cef6e4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h index c114ffd7372badc5b7d380305b7b459efac5b192..1097c42686136b2f016351a4acc6f6b3181fa9ab 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h index 6a59e834f0b3c55ca1fd9ec0751a01d0d67dbea1..3ff558d3152f54a18035da55e5a8f6d526a23a8a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h index 1bd80fcbdc1a07de112494f0b34f423c088a078d..d835ad8888cda38b3c41eb73cb4382fe40f1dfd0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h index 0da56c141192c192336aa5334f6386be7348cdd6..27ea59c6164e9d067aacdad23352e8d6d14961bc 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h index cc74dabbbe6d411ad75f610151852a6857a04215..263336a17e14fdeac582ff55b1ba32af415db059 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h index d7cf20e2efb091baf1dddfa473b8b9f070e2fc14..2264151c94935d64ccbfef15affce5b327645e3b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h index 3e4da4f028621acab94234911ebacb45e88c5538..42db2f0b3f16982e87d656d25d4594c5e7358bc0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h index 5a4b983bae874c64a36fe2061ce73c9abb85c670..7cbc9411079c36755ca708f04c9761e252856459 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h index 36e5003ceaa5f961eab9a66be24e2c07cf75011b..c17e23a0269d4553d0f720f514f0dd4f5d6e3188 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h index 64ed5030de53c71662baf8c6bc6f55938e4836d4..d4562307b0a1093015f32a1b6f5dd55e2202f5ab 100644 --- a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h index be5ebb697e148db8f25861450004cd694357d584..28e14f73ca2eb84e25804f10fc10b9548ba48428 100644 --- a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h +++ b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h index c3e0332b50fab3958092c398d8c66273bb885f38..5ea149b1412f7e64b42bce512017e3c7e7f264fb 100644 --- a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h +++ b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h index 584cb6986c7b5cd0587c7e4919ae4cf5b5be93c9..48152c97dec87d2b572a0da49f35f2ec0a31ef24 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h index cf10bd3b9679b390bf1d0f54fd3c6b49f4dab098..d9610d4e322e3cff66a1fc5e5fb7c815a4aa1964 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h index 875d7818ef171f83ea19bb2c1f340ca1248912b1..9ec88e29e635c44023e4239e80f1a42e419660f4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h index 153f4a3f1749911fb57c9e5bc9abb12b23702bfc..4cd302f89443d844beab1e26ae779ef6c51f42b4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h index b9482e809a6ad5731f2ae1200173e8a84cf190e2..81cf7f1aa52c8f56bce890968dd3aceddfcc7080 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h index dc434e6d9f6bdb01db0ca5fcec45544a571214b6..d32c391bfe55e83534c3dddf3ed1f91411490bfd 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h index 0dae920e86fbe28da55d73ddb358fccb09974dfc..c294795b632871326ffd098a0ed61c95c9b16062 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h index 0e030612837653957ab17b248a6c8d5c06cb43b4..49637a025312b621300ed108be76350462d394b4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h index 98d7124c10acfe537f0b25c643362ed587959143..f5697250ad204331f309fbb52493428467253a36 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h index bc0933a3614885a02d6d2abaa965fd23cec7e16d..0cc016cc6fe8f2fa608b7967f4e0343a2ca8681c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h index f73efbba6c739e1c792fa2ca85a6bc2ff13a2ee2..137fb8541a7541f19796ebf30b2ad1f61ec9f84f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h index 0a66c330fe7d8210fe335551d01e365f4a93259f..83c2bdc4cb6618eed1abd50c9c114a5359eaec89 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h index 4694ec5b87367bbbf65c6200f14c2a72556fedf8..858424f8b10f20eb44807fbeffae833367354794 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h index d916f6ba084ad1da342bb44f747932c19d868eb1..89d72ff2bb073d0bc4c1bd0b2d9f2b8f85305c8d 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h index 9abe5b18e57ad812bbab6152d1075755bbf87762..bc8ea43916e1d5cf58a131409ccd933b59e400e7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h index 6cf2682e3488e7927ea871fd9bcc670979d22c4a..ddf0266ad7d8d38ae740df2a380c3cddc66e5fcc 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h index 2527554057a9e7ee8c6fa0e73bba1c0b12e13e4c..976bf6195753f861b2e8f55a95e20136b5f09989 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h index 76650b517f09e2485d82d7c3ff58c8a803623c2d..0b6e3a78bd3c11761343cd1d96b10c123a8b1c39 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h index 2761b1db36a34ce239b5a65c1bbd721fb0a3d095..432aa75a7f712e7d0ed2b0e4d8d827c422cbbd81 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h index c84767784ba39db5c625298883750623322f9bba..719a497185b35479cf7193d9f2669df1eca63229 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h index fc72ece527b0ec7b9c2446b8a25ab935ebba58fe..5a4fcaa70b401cf8671a75398954a5dc1f8416ad 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h index 1ec3689711db058ad1b68551e2e4058837049516..d8b0ec05bf670f69d0ab9ea0db1fae194e635c02 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h index 21aca6eb96e33212b27eb1652ff1d72ed13ada92..c355a996e853522567d5188012eceea225892808 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h index c42be764f86ac94ded471e579f2581824b05fed9..6d91ab8c79875b05d75b8e378eb01831d07abe01 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h index 23bc4ca9e8ca3bbdec297952c7a45dd3cb4577e0..18345a02e9022fefadb55e8fcb18f7aeff4c0864 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h index be594ca682e6f79d10f008680aea1422d6491b72..19195e25926493c4c261e6d0395a958e34f2a372 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h index 1a1dad2db59d2fba1ead51260ead68949b59552d..0e82822b828612e358352f9b9efae46b376d8380 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h index 1825f92b67826166d7a58c17ccf3117d32418fb9..bc50a5f4a7ab38236530ceaa5df4a7646c963013 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h index 6ecd30fcf1dc18f744b7d69dfc565898590ed397..e69ac7c2e360f04fbcbec99186b89f0628eb69f8 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h index 201fa984accd2a35c78b617e4933de5b94818114..bd9c3e77e8b3faf8dd399ce62f530ae56b96ba7d 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h index 5b9824e0514e8ad7c30c67e83aa56b7e861c381f..457d6c42d6fadb686b92a6b8c4653c0ca05397b0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h index 3eb3983b9a35b9958c7b34412f12b24724127348..939b52beb4cfd2eb262643422917cc4a0eec084a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h index d7dcb7a7492bfd708e49f309efe212cda4323883..d799585b1329644b05ae6a977ceb546e45a6a2e5 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h index b1283a3a0d9f803ea2bb3e9bf15ace56b831f1c6..e72bb54df4bc73f2ca0acbb775f94c3c65d307a1 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h index 0a2ff44d2ff0fcb597ac1fa0167a23ca7da58504..44babec7da0408bf1147ce40fe7cc1e18576ec18 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h index 8c927217c385237a934f7ec647f191bf7ea8971f..a0a12be7521a31402462ca454c4a507446ab4b47 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h index 81c9728e3860fddda143b31c925549be701fb20f..7a19b8c5708016d26dbbdfd1bdb99449ffbd6ef0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h index 4778f56d955648b68e698d3180f5020302272fca..3e7c9da4a0c62c28d819c00e1595b92b3e0f970c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h index f90115463d2244cbe18f68cf9ab1d1e0701e3b9e..6ddee1a5646d9e589e76a8e54767f8a8ce38ce31 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h index 28d96627c785f05773fb8edcd8ac7bd2f89f9eca..12c81301c8299510b2dcd420277aed3ce511057f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h index 5e536c9a8b82cf1f2fa5af4c50c922e30adeb1d2..37d2ff7dc9fdaae21acffcbb752f6f0c596eacb1 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h index 2abb975db9cdf5d37f9f54b981252e4db6a019b9..a0a73e387e5bfd94b9ece6d73fd069ff90353ed0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h index 95cb43ba4e6e85cdbc38d8d5300b04057aeba097..1b7cb258dc9a0654230d44360c8c663a7192fb5d 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h index 66cfa7802accc3b0b0745a180836ec8c7b40ba0f..9ab93dd179ba6ccc2efe787a85f57450aeee2e42 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h index f76b9a5512fc4feb46456dc0a33b624211b8dcd3..eb91f993591160cd0105c4a542d41e81a880f05b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h index a81caa200cea013821968e4c6fdf3278b4b5c05a..e3e4d6a25bcc4f148af653ed2b94737bb1ceae86 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h index 33dfbce624e7328e5dc391ba7fafe2e1ebcbcddf..3433aec624823d265de590d276bb4603c857e048 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h index 88f5357bda4bc9ce1f262ec099cd57c29f3807d8..f796e59fbc0b0cd119a1f4dd27ffeb164e6289e2 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h index d4a007843beeaa5edbd2f9cc623b3d3598fc97d5..612cf4a0b634011d48414c84fadbba24608df5ee 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h index 71f4d990f7c97aa0058cfc642babcd2fd6433a2f..fb183faaaeca3a518d9729308cdc4d12d26ecf2f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h index 098edbeccd3836549d6057fad3e56973a108fdfa..85d234cbad6d269e7acb80cf192fdbd710fe0027 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h index cbca445e4927e844865fee0158e778550539b555..2d66248e2fecce46516347739d1f9d55daa88cd6 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h index 55343411553d6a0a9a8ebd470c16571f5e7d9eb1..dfdcf544e9d15f70062a0f66705058906e7f4342 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h index e4cf7ecf9f93528a90609b37cb3049bff93541d2..a71897a37b996221bffcc588626e62393a5e7ee4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h index c3452f2979435a7297b076a1442b2bcb1344f1b2..27b63bd61efbed62c3e6eba8459487f8c3f216f3 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h index 31e1c6bc5eb2245b48297aa84251ce658520ac7f..98987a8415e2af3ce1a71853e06eac39e0939ac7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h index 920e85c311a49b5f1ccbb7750a06c4bb00619512..07d870cd44c9a2b6d15c743ab5302d0075c2ac97 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h index 6028a472de26328c4e3003722f4960a83f93e9c3..6859a52b8dddbc08df0908b9859a63d4fb04812c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h index 36c86a0477f42274fd091a3436f50077e949ee6f..7d9ff435b9b4852ab14d95561d36f8ebc802a882 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h index 2fc53fc40da789c983b18a38fc7c86d81c6b60d8..3769d7ff859a3b7d1ef29e8556db6a7d114f1c92 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h index d462d196b9643522447ba1700678e2edd6c659ac..3591a5b2643bba8235f6fd205ef581bf6761bc52 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h index d926b4c766255b2e8943e869f0167b002136a666..9531d8edd5f331dbdf023b5280192588f6a07d9e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h index e9d43b919c99bb9e8afbf94118c44cb93bd9ad37..1329e3022c3b77c87222422501063c078a6b61d8 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h index 8d02be83e2a540ba8e079a54ca9e6162be42d073..731065e3fa81f79b498048e349add9ac57f546a7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h index f4f3ace9bfc33750d261eee45fd4ac16992a342f..517b79a4f425b825c4b263a8b43eb8e5fc5f45a9 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h index 523459cbedd85c9a3f751fcff28a810c56877a40..d8f2dd9c8bae45aecf669fa691ffaea076d14957 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h index 7de00bdd9ec2f245b094867a144da6678f6af1ff..f3e061f7ea27b24cc45228bcfd488c4c3e4c0365 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h index 8a74887cff5fe1513122b1912794c0d1a395da60..2520be2e7ad60dd0980fc9abb2c5b11251d0cb21 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h index a1d5086732533ceab5e57c797c0dfd081206fa6b..da907edd952de0a490103a3377b42f1a88d07fb3 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h index b22ade14eeb213e982242a3c9d9a54658313d07f..2c58d3250c43e0b48dbcbd1029116f3d41618feb 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h index 11ac516f85f677b9ab64f1b16c9663e9dc022970..d047737beaabcfcaa7c9d21925dcd260589b98d7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h index 1af03422a27aa14d85dd98c5d5d1131342a78940..104ac25271801718f57d772f8b58c56d38803186 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h index a087de4eaa0cdaa70f4b7a2f4e06c2ca2787bc49..34bfdb11a546dbf92890778d476f3c65ca3d1f17 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h index 7e2c48402d02dbd876cb9d3d4c0af2184cb9e344..d3c32f79f7f2f177f3e7e2d47915fc8bfc236801 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h index f8493589c4c6bae583360cc35124483f8c98d091..dd9e66cfa11abbde86fb501522e1f03dc7d36341 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h index abdf330cef32fe4735f243269bf2815f5bf3da40..0fda62d28627e2629bb8cea0c9ddb4357b5a1804 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h index cf280ddd1db6934b2b757173c6dad02ae4193a1f..25889a3a196dcfb702599419b7dcc0a435d7f377 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h index f8516b69b315bd37ddb0daf8e26f151d95af0839..5d8d426e4111add064c86c0bc3db73e2fb86b835 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h index 5632d8fc8f5ef1d33c4c261791957ec08db3dac3..35e8ff60a9751977424f2b80e00460b3bc356d03 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h index 33e05897be19fccfe097a2bfec29381023036504..99e2c04ea06b48aca26f2f99834851e77e5b036f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h index 9214fe84bd103bdf2769e4ade1bbc120640048d8..d7f8ce028981c519e57bac3377a1c3cd70246550 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h index 116f63ffc7f01a117fc2bb207eeeffe09647eab2..85f1afd7254e5cc1e97b0e2c05e1646691758aaa 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h index a214e7efb43eb7d9118bb3abc6071cb8238b1527..3003069a24f9d41c1f8f08e07776ed4192d7fd7f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h index 79909f96fbd825953b4c82f82f907911ea3abc46..6597ea0114edc528576d370bfff355e0b6953963 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h index a41bee441eff71bfeb2cac426f873a1ee6499f13..a35b88d3cf68dafc6dde286efcf25e9dd653f576 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h index a050350b5b0b90ec0ff44014009a18a5b2f4b10a..ab383f84290bec84f84c336c14df23f0fbda13ae 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h index 23bf007229e33d16593ebca2ce3fae03d1c497ff..2e68a09f653e9b345bd89ecc75d4ebe178cde2f4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h index 83298e0f5b8da9b990bd2907dffdd49c980516ac..e95add8c0fba9aa7f14d6b45dbf4c58b5b4dd34a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h index c5c6af35b82f4a5e0f7af4a7b2c4047c1182a2e6..fdaa88550078a93f3b2e025b868902a8317e050b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h index 14de22ccb5c720b46d3153a329aceb91c7589de3..bb3693383a9d69ee292cc9bc839dd09e691ee72e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h index b4107bfbd0b32b4eaa254928ce81fd9ee8c25fac..417776f46ac411f8f7bdea9409bbb3718dc1ac34 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h index 2f45b818a06f926315793ec709d18a51747df09a..a942174a09882fe2ec71bd74df75a8f01ab0fc7d 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h index ca270fcacbe6916e3754a51ffd9af712747e772d..6d347606f225140515bbe9430bdc74afb64d07e3 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h index 6a12b430ffcf87c534dbcb3872b3fd9e65315cf8..472aff5a7fcccddbee050bf45273fbbf954fba5d 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h index 1272dbce720f0eb2205f8d29222a97823ab61c98..5dd7a17eb3339c1ced6e89504436a1900385ac81 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-clz.h b/test/a32/traces/assembler-cond-rd-rn-a32-clz.h index 02101b8a126553fa4bde8a543649e831d9fcce17..eb2b70da185d6bea4d39d8ee1a373b55e8cb6d85 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-clz.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h b/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h index e20e383cd7d63dd8e264cd8f07fd660455ced9f2..9f885855ac901de6184b6a829c4c05120fbb2c05 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rev.h b/test/a32/traces/assembler-cond-rd-rn-a32-rev.h index d3ec573b9b41b04826f762c05b43a1424d6fa557..70ee1458ace1a67dd841dfcbc041042c18a5f4b1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rev.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h b/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h index a038f632504e7455fa4cf6b05db98ecbbac6f33e..4d6f79fa7a69faf2b90a5057eedeabc537d2b918 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h b/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h index f99035f7977dc4a33ad04e18e7ffb779ec043cc0..ca6c5e456d51a39320d757e74fc1ea772286347e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h b/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h index ee48ca35fed81d070ddef336fe6f8fa61049691e..4116c2aca3a05455c13e09c4f6cd7d31144510db 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h b/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h index b4d820e8bddc1fd3e5b95354a5359828e239a01b..70e7be3c14db4e861df89b8529fce26bf1dd91af 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h index 9dec5c4696aa44116e13f2e4d57abe61d24632ad..0395b0355564e67b4df28a2cc2c9cd907969021e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h index 2bc3ce282a2c107822a2a7bb317264c4f18f323a..cd78ca4d20a429bac5d9ca776978897076223206 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h index 32c66435253140f0c6afb0171c5afc37abf2ebed..5386c099b9379cafb8aa287f3116a731e9892dda 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h index b7403c2fbc3fbb1f1be2ef92a954111fb725149f..2ee21b65dac45f4ab11f21c613cd21e12e3b1429 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h index 98714b3ef9d4e201ab1207253a42e448128f5b1b..c979ffabb38686d0a0b03583c53c6aba1a7dd7c0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h index 2722a0d78f08681d261fd9165b43c012503dabcb..24733e1c644b061d74d3a7daab31eb37c3e7447b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h index 2ceee0622c6c1136fa2dcc6c4a736a9facb7fe3b..ea481b0f31c96f7ef869cec47904721d0f9d4495 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h index 8c97602b5496538b9531c09d5dd1bc74daf115ac..c005f47dbc641217db9bbe692b41b1a3eb54c331 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h index baf5d76b98aaee50b6258ed97fc8398c7df3fcca..8ab502bf9d55a6a131075b99c3dd789a4839f37b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h index b6365b3e849b0921467ddb997933338542bb6854..1c68eefc24c26532c591552a6797faf8e94fb556 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h index c2af11bc9a1cb3697a1b9d051db9ccc9ada9492d..3a57fd8401d1ff5b6f8ceb24ab3ad096e0d1e816 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h index 7421c33b202859399007b8cfd23084e853a28416..bb7d9bc2e6391223b44ba33cc7a9c107e7ed358f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h index 328d591255f92b5f2cd27c383a8091911d000bd1..121ffd8a442cc0c74dec8f4bc1c6c4e9c5ad1e48 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h index 00436ae4f9b4c8d6ee5d287a9b7ea95918c6bac0..189996142693c76815f45584b0a730e323f7eb2f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h index f308a898ede6dca740d14344cd220dd88d0158b7..04280d95eee5a8653f324e417c1d28fe0aee9a4b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h index 1e61341fa9ac8c3ea2f7ca9b796b188b3613f91a..d2c769ed5aab0630b857911e4b2a1697832e3d93 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h index a61af2124185f476c5c123113fdaa7e01b16a38f..8298290575b891a2b6acb81f21bab6d3767c5406 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h index 029d004653d85d67943eb1844973f0082a4c618f..9c09bfff62728015f3c6670b37d9575fe91b0dc6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h index 1dd2ea2c908cf73c1a0d612a0421b825eddf7ced..09cdc80fb939187fcbe5709fea8a392e0ba799d7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h index ffdf6529b90e15fdfba6e4ff8e563ce757c13864..8be38ecbcc2d61a8b61bada165d70dd74268a511 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h index 387b92be5a1c062a7ffb5fec7ffa0563e3d5d42b..b41f5296c161c6542ba024a4e4f4561a79ae0e57 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h index 83f2c8f06550033ca377201e4b076075d02f7f57..2b71565533301d45657fa6a6a2f5e47c4b73bf0b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h index 4c8a79c4072c4efcf6265dd00739f67d72161fd9..7690f8d0cff4ee2f67da8401ac94eb816dc3f17c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h index 5068907f331a920c394b4e79f451d9922dde4530..7d3bb6716e447c78146e777ab6fddec1f8ebfd23 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h index 83369e3e089387ef66b583b3b4ab9618e0ddddb8..a9a7ef85fcffe811db5180d926b94a960abd5646 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h index 75fa6e5b2dbae6b6464b8e7af6d0e01951ba3eed..238fd96e33ebedfe58700d2859efb4c728bf0bbb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h index a3b932e7e9e42cd9099c92b302868e38e4c42467..b95b896f0fe075ee5897c1607fa0697d48f35738 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h index 9aa877f3710bd1ea6e13c1ef03091026179afabd..853b4293c5b71803bc3b466242a891dd83fc4f31 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h index 51d6781d9b8affc27a3a879c39c3f799cb8cc573..8839c8990edeafc1bfb2fb33d44b458be3bd2e84 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h index 0359e3a36ce43f97077d7723c9368af9d9f3b1e1..e301510a1133d924c25273f8fe8991fd53acd5c3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h index 860cb50313bef570f0ff1aeae34b9c29b9d580a2..be9526c1b27d8e18e0a999f3b801e15f2f1bd8f7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h index 3655db0b78af16fab329ec29f8be415682a6d0c9..b4caa32f55656241bcbda6d6d2a85dc98eacbc84 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h index ca1ec1f196c38e192eb499287e4668d853f399c7..382085455f012d92c0a371db5d2b5d786c39dfba 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h index 9056c90b90f735e86536165e7651a19789eefaae..fbebbb0ec915f026e6ad69c859f9d6e22273a5b6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h index 80cfea81f8c8f65258db6912f81d845a4c1d0f5d..6146d3b613b9446f664462684772f30533ade35d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h index 61f1c11d522c706e2ada9aa164c5138de962eadd..a0bf583bf99b89749ca86d809e05034fd37539e6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h index dd731bc1dbafbeee675918637ffdda469d429c35..51c791a05fdd03f5b8cbcf5a240333e22b47b297 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h index 6295b63cb576d703b2fc501b48c36e9a607c6453..9c6d4a9caf0c12dbfc0b842f6eebb81d005965b7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h index 61292f7c90e4fb82cbd2b28d0eaa5d1bded6b7a5..390ac3a4290939acfdb47e26a82d948ade1c3453 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h index 47aa4c290894429d9def5b4ec6eb27ddffc54510..facd3171711833e7ba8b53798f077d01be61b628 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h index 6ed6bd84b04c1e7071435ee2fdef9d14b6b17ae1..091ec1ab9b5f6341db40ff4dbb8e3d79d6fc291c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h index 73948859b2679d7384558cd8c4ece04e85f1e6b8..64f0f217887ad1eb953de2470cd5a3e6241e39a2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h index cd9853eb40981ef2eae551219f3c8417f94684a6..dec54647fe9fcfd7731049629b7140d41d013d78 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h index 43a5ae673f13aa2e2a872d7ffc13776203d68425..99a68a8456cf8f140ca9566b2342963bb05b4245 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h index d8f8a8af14a50de5120138e1b6a26b7254b87379..74a6ccff832f3c7b886ccb1b940405af9256248d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h index 245d190be15134370ac5254ac087ad0adbc69432..ed6e5306f9fe0863ddbe18c0b49baf54fcbaa721 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h index 9aa15e40f62afae6de6bf458d163646596979a90..25614b38d4852621b55bd9855c5bb006d9fc168f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h index 4431ac664177f9ebc672f7c4d5f938f95a396a39..0fc2d090941723b0bedf4b2a18f877eb8c308814 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h index becf032cbd0593a42e9bd85e0eeb669918f26e7b..b6e91b4d90920ff17e9f164e9dcca51aee82296f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h index d19ba2e006dc5e8024fc1b16858aaae6adb93e1d..b1b9a164c271ee163faf6b3af9e482453812739d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h index 82721488205737d905680e9be35426cd348000b1..c293fd513b26fa94adbdf2931779fcc9857b6ae0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h index e57d3d67725c26f9910d8662f9cc684a5da42b6c..5bd6bbfb25a2f67dddd8a2d3facccca1747f74f2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h index d2501ad3587c1a10a0e97a3cd913efe2404f99ab..70004f1aedc6b9b719dd0afc215635cd2615ce27 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h index 6b98b3104181db67a4e788e934ba4ef7d73d27c8..d75dfcbf4d33ae093d89f8824d24c6d7e743b406 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h index 52232dd33c6a8f236d8f4cdfa85043d8a3279dc8..f769b816edd235ae21d047d8bc62810eb13a78d3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h index 70786f69f36e3ddcb1abd62d7085f597511dfd3f..03d2892cb699e2c9e688f193878be5c8491c1b1d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h index d22866c0738378c4094ebd4c85cd46ba00721430..94890edf3736a12a633353ff40b3b47bdadfab4d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h index 22bc127ef3019a615b1bdc05cdbee26a870f693d..65f631886311ace9d7fcdd69c7b3939c5a40ac84 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h index 022fc465fd3e997b974012d0d5c6d234a81cfb54..c78e9ce94f7f593d6adb63c2697e6a8701fe0327 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h index a0725bc2ab7ec2113ef804bc36e399dd47ecf2e8..912e1f76ccc35738fb381a1b6fc886331e569097 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h index 42f4c07a19d3d5ea1780b36c85bd8e4f29397f34..29559890b4dca749c9a4430fa440a620844c03c7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h index 1170c31be741bebbface7697e43d32a11a69c140..2161670d5aa536b69fee271e73b408ae13cf1401 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h index 3176ff88960be99a62a83ea90250271774fd5897..f2410698d11af274576b9b4c42fbee05cf2c8304 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h index ed6028768f1855d8fd95fffeaa902f4e66bac995..b1fc222fa789e906e8d3021d4f408ef01d9dc675 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h index 362041c4b2ddb06aac4584e3f68ec6d134092ff9..65d816deb2f8742b4baf748c22bb30eef80f64a5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h index 6318c80edad57a34c19bfb9bc60e1a915e4c0a53..7be11d458b76a6e11176c9f8487de4fafbd8d366 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h index be1968682b568d61710feee81b32c246ca6c6042..ba9f6c0b8617697de9d61ce5669a734016e75482 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h index b5371c5dc08a1e0e379d276da7805f65823220e6..be1010d19dcb57c375fe9551a0cc683ac2923c4c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h index baa6ca43152fa9ab0faeb755ab45f9f4913ad143..23dec971cb33d8eb4cb5e0f389603b52be4a3474 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h index 30e1b97bf952a9146d1b7e7385b78eebcbfa202a..77ba121c871cb8ba3f8c1c82003135f72c889a02 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h index 075b9aa415e4fbef2864f319f0923df724c203a6..324b6ec679b4fb9b3abc20a66075369ef930ac1d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h index 204b9e17f937712d7defd3379420af031139b321..476aa7e963694b1b10d29693c40020df3471489a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h index 6d16f46f27924acc7b463f2afca0ce57ef2dfaf1..f9a58b5d2b42d45942fdaa74812866eddee29389 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h index d69fbcbcb83d7b9944987dd8e67ac93342e743ef..848a6916a6b2c8023ed98654633576bed169b627 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h index 69cb6d0d117b40e97642798fe610b6acf8ce1c70..31a6b18ff0715648ccc3f06cc6b26842478ae718 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h index 0ad0efa0b479e94d7dbe01c3d708a60b0fc97cb8..97abba7405779aeaad95c0f92709f0e833eac603 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h index 42f9c8f590e9254753d2a20aecde76885c6e72e0..4682d6d0a84583c94d1346a20589f1e9df3860db 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h index 496fd3fdd8ec926df4c37f2cf05e09b818a9276a..7a6000b98571dc1f93faf4b1984a236e12280579 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h index d9b09975976dc5ceac909751c95c093148c47d49..8620faf7dd6754d6d2b8fb61c4c709123b1d8896 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h index d80aa4e9e0aeb151b8ed3779a5562b516dc4980e..dfdc3d729d7fb13284debfa8f75f144e426fd370 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h index fdc40968219c8ba3eef96cdc2ccd9926f59aa6b1..c18ff1f2b60c24150aec98b9b10608f4ba242a79 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h index 856abafea483bea52f8253d40d783f1b43869813..1834b859bb900ab369df9c1a4dbfd171f4628abb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h index 0c1fd1ec16b9ead1a1b8da543a912affaca81b4c..2bdab2132a00ce5a2fbff860c15d6dd62cb3c31d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h index e35cf7408b010f4b3f3f170ab57fc40b453512fa..059ba54c22b1aa4d3fd85041fbaf76117f551785 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h index bb36ee97e312668c043b6b325507833894af9b3d..c713e1e529d7f884d51b65c15d906816ab5637b4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h index 02d954f84af0727817ef191eb6b0eb03cd234ba8..276b4c9f8cbaafb3868d6d186b534effa0fdbf5c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h index 6b3420af259a0e95ea9797ea42cf1805cd56cd6f..0e05637f7dbc7ac1db4c1e4ed3de6264ad365b8f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h index c83d1c5ca9ad54cb133159e8147bcfe9717f0615..88e218b57300af13aeca425aeea4b6fa327f8b3d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h index 10167a2114efd0e864422dccec86c9ca102683ba..489630f8285ab9c41bf5831af69e2335044f640b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h index 16935694b2b982bcea48abfc6dab9903b721ccd0..75c0cf259919a41f53b30ca83bf9fba66d65db99 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h index 698c25327b65a33f0e74b85bbb1c62e249d95c25..e0e984bc298d75f095d93ca699cdfa09ab8d8361 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h index ce82ed0d11fed370065f7cffdb3496039585e9f1..5cfce16eb2dafa37d18d51bf8a4ec5a7bb59e373 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h index a0ed70d867426e6a98c128443a9a1333ff57b01d..0c2978f74715c025ee4d9a3160b18eb0231914eb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h index e51d8fb3ab4867921b13cc15608855437e9348bc..fe943e348e2f35c717fd558256642fd0a9eabab7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h index df7c028071c2310609d5371fac436ba205497934..950ae91bcbbf4ee0480f24d40a18f0b8128a3ced 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h index bfa5e3f6d9c08a5e96f1cd97fead3f7e4255f304..d40f7d8c76b2fa3f21c7afc51970d4d9caca44f5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h index 81e99d5841c3f023cd3d6a024c25646d98f80cd9..2301b10f5363e148551212fcbc96060384f6c5aa 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h index ab791cc3805cc47c4e728ef3fdc276f01b5e9ad0..8dc24e2bdbd79956f4c0530793a8683b8eb684e7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h index 34f7090b00c70b34783b3d4901acff53db4825ed..7d0c3d3ca78062e460d43368b5ca4f60d1336c49 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h index f137e62f4081d56c6322381dd5958298cf9fa688..136c51776f2c26ebca90ef3ff7dcc624890b4fbf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h index fb6292ad212e343ab9ac9d62f3d20860fb30afa1..f6f60683c4d5fb5fa178b9f71d4c3d9481a8c2f6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h index 480e37dbfabd8d5b53a72dfe7133317ea157ec0a..03c6663a06d7d6d7ba1d645768609779263c8a21 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h index 5bbd14c31d7722df3e04fb836766077c51f2bc9b..b064d02729b1d603e0d16f0855596bf46c220e1b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h index cbe13323e0c222fddab783e72ee6542588055e93..04dc99f4450a9579060da1d61ac8c172b5a6402a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h index 54bfe53ac6e84fcc8035f9e6241ddb9d163e086e..7f2ee91025d6c757a074016b7f45923cffbedbed 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h index a42d073230dada5d7bb048fea442099c8af5d1ae..67884b9532a53c84977defd2cb222967b0944245 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h index 85500c3b207d245f231213119adc0778b8f2be1f..d71c46d1fda700270bd737b2f7a339453959b313 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h index 213ef8d0e608cd515edb03d48762f05c40ee1344..74b5feec288ffa2e2efbd3ee9c412a8cf3b632c0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h index d2b4483c201baf592bc9ea249f97e3d34036139f..1bf1da945e99c7cb10ba5d37e8fb4984eaf03b0e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h index c0c5fb22d78defbcd0287ba709643eb00ab0f3a7..a2e7568d971ba6cd206573f23d71876bf66132e2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h index 85557cff8bc51db7a05522ad7046ba5ae3fbec30..cbc4deb0d77489b5974db4758af6ddaf7cbfb518 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h index bc0b203b93d5ec85bb511741a2906600bfbee3da..aefc8d1b095d6710a98a00333bfe7e63a670e2a2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h index f8276125bbab6c7af8148ee40c1223a04bfbf1af..b321e7f7baeee22d836e7700acef66af164fd2ed 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h index 3a0e0cf23582485a95492f27ab1824656c791ffd..8f1a0f51e1848d6f5849e949a17745d188b6538d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h index 2f83b0ecc00ec06f96e9b43a6fd89d154415caf2..f517d54fd77a4320d32e8e21a089bd8d3b943132 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h index beddd6cbd0b8297415719fa30e3bc689dcaaff6c..8dfb1a9d4ad36f47fea2d653d395ebe6c6795361 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h index aa692f92664697d35977ce807c065d499c55ff50..bffb06ee6653749e7e97f86a061ad3f01a9766dd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h index 5a71e1c76cfe5fa677a8255880a58f88c7f5a946..4f6a6dd1c32094cc1e5cc2637aa500d2dd98b9a6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h index 3f3c86981d7b31ede8bcc02cd7d64fcf1c8571ee..e02e499e3b025e30115ed72958a4764bcb904603 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h index 1dae9f9d295a5ae943abecc7a40b528e072add9a..0223c53a3a93916040427c2b654eb3dbfe48d911 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h index 2d66b7b615fb0afe7b7ba263dd59630715246b70..100a8caad41e60a780dd14b5eceb6c29d97297d0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h index 0dcad93979b4adc89315c8fd17feb3a0ad4d2b59..23679474bc1e09bd32e81931bb5d2ab1699a6f4c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h index dde6b596d2221d2d3af7f613eb2ab9af956bbea6..7e1a5e51229c9e1f7752f9f22aee2f8aaf62d38e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h index c7ac0a166b582b77f1a6d9d9c215b328f0e6c11d..53f9e343b24fd4c42bd20b7db4d60f071a0ebffc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h index c31fc089f1c5626e691290472ff743ad36557be7..bb1ff815d10281634634690bb0f5a944acb90f87 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h index 172b4df7259418178950a0569367fa8ed05d0e35..cba716be94a5d66acba04a25e17aed6c46603f90 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h index 8bf9cb4166744b9491d876de1b3a8f0d9eac80c4..081f763d53f82e3daebd0db46e57ff69523f4205 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h index f92b1077518666633b7c401677bf5336294aae2e..e5190788756a7ea750bfbf727f2c7d0fb68d7576 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h index 6560bfd851008dccd16f1bbb1b17c155e2b042a7..d9032d147b42f76c2ff1e0704850ef805078bf4c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h index ba19bae7df23ed8af7e48b449219f0fbd4f2ff92..436ad35d8cd97a0c0be03073147408fb4cffd51f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h index ae41188ad785b81aab21e265dc50eeda2d794a3d..1b1408ee79b01193a5aaca015072cda5a0b8054b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h index 5c2a27e810ab626593f636e07575d8281b4680be..bcd38874fe419bbc54a77c4dc7457b20938aa734 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h index 944653f2fd3cbb82fdf7f3ce24e929b5fd573e2d..709e6820cb08313ddb7185bc64a2e9ae0f92f062 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h index fd6342f369f92fe8d1d07ce8330964b8b44150f3..8ee7578f1c6bd89e0013a3d1be508fb466ab859c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h index 46f79dab26b370da3650ed6a092192d760508f07..e3e6aa4bc2058f4fd67f8edc1b09667c173fce38 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h index 639370bd7dfb2c39cf40a20047a79c05bf6f80ce..794a4b9b65fe22dde15e749297845915e4e88906 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h index 21ef02ca51ef792da8bd4e9ccbf15080af8d14a9..7cb824f43aaadb5e12e4da5cd3ba847443c80ea3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h index 1e8a8a5da723c79227d81bf3683a20e3175f6c2c..bb1095002090c7b5c4b24bbd5463eeb9ac6ac04a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h index b409ed9b244011d3b81801b32eb9a1d607d1dd47..87e5c5c226b677e99ae3d5c9ac429785bd3ef7cc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h index 58bf5ecca8992ac8becc7ab648b62b397c5d43af..229ea236c301a9144e1514607cefb5f6ce020741 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h index 4283172309988b96b44a9743a4451751979b3235..63039857106f15188096732dbe5f5981150dda0b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h index 93750d5b11e796b9fe2e86e7d8081e0621a77a7d..7246f567e132084666ea05a92949d4def75ccd76 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h index 5460ab94368fbc41adaa691dbc43eb4c17e805f3..b2f629ab3bd7b3db1bd11942f2adb1bf4650d00a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h index 4cb526a4919de2205dc9690f0a8451e45af553cd..49ca1bef5482c67a7d8cbc1c476226968cbdc887 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h index d9d8b6a861f09304b634b8945a74878f527f5f1e..724239cf907076215c9ac3cf32e3fcfa8073a2b8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h index e5279273f4dea9a06f1ff28537696e84c4ee8b26..3d89f8419593b8403b91573cb7551d6ddaf09587 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h index bd267b8ea67a3bac4e066ef62c0b11ebd6b73920..4cf9bbfe41d11e19dee6ae1d35ba7040683e7e3d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h index 7e1ae527ffa112e7daef8c490b754148b3336b97..f89bfdca479d83476091f4fe3942e0310e7d7f82 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h index fc09993e1ed086a23f25f6e96a91b27c84833bd3..5ab189ab4b06aec1f77d73c9d35bfd54996ae3cd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h index 93623dcdbc3a6681c8d697f98e14838ad469afd7..83db97533df5b89284acbbcbee6b2552dd7d641c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h index a38de423762c16298c2d03fce723338266651092..7fe20faa4c69bedd6853c9289584951bce56e6a0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h index 9191d14fa64e2f907c4bbc683da6102201216ed3..8c6946f62f676aee82fdaba3617f97bfec78e472 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h index 71828af225afa213aa17dacbef5f9b934ab47ba9..940c899652cff904343d5675853e13a809313893 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h index a9d2ce2e1f06f18bca80b2daa7fdc2bd1b302a7e..d911a63b355c8a14239a5c9be0bd6ab8c2f6c53d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h index f80087080867c979ec452872e6581cb5a09234dd..21a3513d1fa2fb473060b35f11c6ee42fc6c1b15 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h index 190722c6db814f2712c4309f85def95f2ac08aa0..967ac3504a1bcf7d05bac241a426c631155c0a34 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h index 4adff4d78a70565fb05fe1e4cbade03919816880..fb908ab5ba6b2b90852508952f0ba6a676266e4f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h index 331568e7882d370a88971a65f18e17d6b055b925..b29bac3ac0bdcb01d01abb92da373ee23ae0b538 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h index ca2ae6dff4c112c96be8d41e31ff94b4b5ebd4c2..31e770f2a75e070663be52cb5fb8a97fa6cc6ffc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h index a9324381959279bd53290cd9d25c142231846051..5e33737fa38c085dae9d10866fd6677ac9f19670 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h index b1eae84833963fb2a8cb24c14c8add91d9936a96..f1fe595c848f638c85163b9864926e43df4cef71 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h index f520e1197acddc91f9b23b82c408cc2768286e6b..ad4798785f2193966617d15e285460ac0a57fdef 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h index 6ebf66db704e137e835359743f757ec195452cea..0003183dab590db7c13b191ccbd2f548c8894bc7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h index c3be8d7ea1eed63e8db0f2bded0f9924876128a0..10934534c0197703fd799c043a702c495bd6f3be 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h index 772987b1f1b6146b214156cebe3fcea79b4b60cb..8a3b96ca521e39c4c55a08a8474dbcae2e150556 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h index 3286f66d3d9e8ccf1f8f16558772914e3d2960e9..d16211a859b25dc3d1a715509556af10c5d6ff8f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h index 2ee4759e03fb83c58c834f12929ec224fbef203a..1614f421762118c2cf2744fded02ef5578a69996 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h index b9bf2f7aece4e388942d03885596f67f9335a6cd..f9c0a809dd1c2113d127b49c2abe55629b59859e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h index e8cfb06939b6c3565e6ee6ce023a30970008332b..e236b59e1faada690842a1a6688eb02f597efb99 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h index 8743dc8ba8dbc919ab800e7ccda28995ddb284a0..04c68122a66c13b5b158a932b3081616ff9771cb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h index 30b26c16d2248440bb07670e944b4e3e51977845..d21904bc23af7272759cbd21b69c18ce8facae1a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h index 3c2445db2b9e7a30bab7e194b578a17fd1ba3cec..22c711fd77cabb7c5bb80a3695d9682d4ba8d416 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h index 8b1efda366c967c4fd320e2589a28f124c34e5ad..5c64fe36a4cb98758517cc5c1ac2380d367dd69c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h index 22ba7c53320def8f14037be38461b163a1610939..5f875157cf250a552ec197ed2331e9e17e7cff9e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h index 9b6b4641b35d6ae133ae80718b56287491b1d79c..20b49e23098337d2c2dcaa1fec4d2460c68db1d1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h index 045ec56d510d76024586e67878f20a8e4a550704..92e1f693b82e483a803f2077b88e33b6bb0ff6d8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h index ace8064f46adab8b6e566a08c2b2a047cfdfc4d2..8d2b6f746c969f58d6a8262b9c35f5d8c1a81647 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h index 5fbdd62f0d039021328bc640c5c0cea19e4329d7..ac84fd256fdd2d5f8bdd871ba52ddeec3fe39cba 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h index 86e8d6c6c9614e44eeb1e0d18d089350fcf9eed5..801729b15e9a915a5ae04a0497effeffa81b88b8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h index 4ef0419fc0e2815360641758f58a59a90500abf9..7f19a3d29cf982e11ffc24cda4830d6a4d2d5538 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h index 9e3b544d32b0230ccd6a4242e7cba866c10d6228..2ebefaffbfc9eec22930e7e9d19a63a80293f59b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h index bf7a2a804994887308ac7b49cb38007bd3f2adc8..6d570a5c7112fe5dceec25fc11147a42b8ae51ba 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h index e8d89e4e61c878fda76168d356a25a47ac102eac..ca73dc8f69f0ea91a182ef29af1415bae8c7f719 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h index 6d0d2212c26c9bf901d12e96e81a9dd5ee1ec636..73e635c54d55d82526cd9c712ccd3c0b062fc25a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h index a897f304885e80e2055e8e93e29fba70b75d590c..55a8808e58b1e5ab751fcf8567d650ee653f2631 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h index 7131aef55ded23f114cce67dd5d90cd65b3a504f..839dd383b085ebb3d9e6d32915b96c89926234fd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h index 664472f97d34e325282e2ef45537804e3a571a00..db9a82bf3db45449056649db1b30c88ef5717431 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h index f03cbd5af6a1e4eda80c9a138e590d1dc2a8e9a0..12783a6891a9ada133f3d2064ca97ae7cd1e8fc6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h index 280ab069ba761d00fcdb0d60c29c4d36e024e4a1..d220c9f751856afae2109f7ae17e230a5e2e4432 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h index 05f044ded55d29a23432c1317cc98025752d3a1c..cb021e372cd7e084f584a2765630223e440a9e0d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h index 60b19db98f228eadc1b4f62cfa3e781ef2d3155a..0d3b4dbacee85a177ca3507f8e49ba058dfb5497 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h index 679ff151800a73cf7fa8e178777ec52f4db5e33f..8fb00ae3450e7843a026926b778d60ec5ac13930 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h index 7e1c148d96a1d48697bdfed736e969bbfec35a57..4eb5e9dcbe7afcdaafb64997c7dd9cdcc05de3b0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h index b75d9631fc84d03e0c7a55ef6034e119b09e5548..f3958498af7cba511890f84f7ffcb5c98966b72c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h index ab9186460d0be2ec06c2160e538351735c894a30..bc774080139dca861e970c52941b7780707dc184 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h index 8b19fa94c84349ad7a1d6fcca628a6bd3c5f7e3b..6e714210abb038cb526f798d01adadc5e0dbc3f0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h index c9ef8cf6d1a233cc03bd8e5502231ca763abf807..17d6dd081dc7e56e5ccae91c02d47338c83cf4d5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h index 6ab9dab7c7c3b2b92a96d4fadeae300fb249b270..61fe1adade0c18dc493aad1c8194ee5574859487 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h index 14937009a96783924486068b100e2e5a77b8721b..9103c8862ceec0b94d53b7f05a01ce53c0c3c46c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h index f253d29c9f2fead827559f3010c252b206546a92..fdd6b5dd05b70ffb54960f85949132201240538c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h index 0eaddbbea1af6a8b0eab821e8a41a67f28c069c0..9608b86fc0c299fbd2098d7b06a0b9bd3482d9e6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h index 9934dfc062a23b1d15cfc1b2ef5d8acd72657205..0daadfe10390373425b1f4fbb3839d0a21d35ac5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h index 3005d80bdac71bf359f14ef369d63c5199041d6f..4df122e5d19c0150096cf07e2cfef0891bcfe9a3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h index c104f6619f5074b5e39523101df286653980913a..3637fd3df7e90dadf8318474b2686e006f0b6235 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h index d2b8a6d943392c21f3c0aaef78ad1f5ec1473b4d..edb06c725fd394f906251446c40f26dffc20e153 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h index b70efe78dd2934d746e64c8bc2f694b235cd65e9..90cf8389ec53fb652619e218bd72bc92c8cb1b23 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h index 2e14d4d8fe2422aeec3db8629eb2fbcd71e518eb..982aeeda8c62fb8ce1feaced9dac15241d576df8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h index b8b30bf27bade57688aca1b031696384c2cd5a61..c222c10eafe7e0ab128a8726608a2e0f03894415 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h index 38483e96118462fb2ef90a5c9a81cf2a801ad29d..337df3899ffdc86dfdb7b1124ca455337528a348 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h index e85180460c11899f3fbfda5021986ab627b43eab..f3ead3bc69f35eff76e2f9c47a70a494274054ce 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h index c973d236b93f1ad54a42d2e200050420e32be045..6a4bb0de136964e381deb9c4486686e2e24a418c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h index ee214ad5119a858194f38fe822120e9eed684d9e..826917f8efca27234bf158737b94a0ddbd4429ed 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h index b0d05474c80e163032a13b2b40404c92cc1a729f..dcec4be8e264906965b28e2e44fb9d5f831fd363 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h index 17a0c78df7f22cad80ae0397ebc2460889bd4809..363aa7c16bacfef05352da90fcdddacf3f3c87ad 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h index 45dcef3915559c4fed8a3d54b4461911fd4eb16c..1cc90e45045b7edcecbc5f2371d72e5952e672cf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h index 6926066ff4f23e261356ded7fdabfc75395cdccc..6ee3bf7ddfc9223c7974738c1a5210135ce09602 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h index 70e2126f076ca7ca79342e2c648d8fcec53fe514..f8c6bce824f1266d5b0a228b79a9781f5ea0fd76 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h index 1119893b1a9883c5e72fad19954b2636e9255b13..bc654c9cad4a91fae2f908536dcb702ca76dc5f1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h index 5e556e1eb0eb1a6c1ca0ee479c28d20d0d89e649..4657faa53124cc568ab75291fc9715f28cb1cfef 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h index d3371de6c3a60af7f5328bc5f1de6c05c1647066..c45d06312b1239299bea07b23ee9c63099052cea 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h index dd428ec370250355758a236b5bcd46371122bcd3..f8baba56fb36b9de4cdb1c035101afb4f16f7390 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h index 268232e88f8495a12e94d7316adf61af8defde51..1a30c903c6ff42b41c105db06977107315186414 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h index 43a194a7ce0bd86cb2537baa0345561f09ecbd3a..95e830551f91ff73b1f2444b0ca0b84eeea7c751 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h index 4bc8899f9bbef67075adfb7b25f718f7da10059c..11d2eafa9e44fd3af2bd8f40e53babe8e688af5e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h index 5c78b490a93fd18a2009077c2bdb6f2cfc30eb36..89cfd482ff7971927d549231a88f273d7e47db42 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h index dc82b96ab3201d717b07ce926d1da02e302b2284..03e2d98b27a301f89b6791d7d08dbab6264ca475 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h index 89cc13832bd01ec04338a5e6fd5b701daec976ac..f4464d93594eb63fe0a5fa9fc5eac1b1db5f8c2f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h index 1b682269f2ce41d00a7b6551ad29c25d75da645e..05dda63bef689f5abf06cd58676b5ed6c862f60e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h index 6f3766c1bd137847540d9bccbea63670ad5c491b..95fc9b64740a8d75fd9b5985286140581eb044c6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h index 101aa327664964e120d8b56ad7c93399d7bf19db..1ae20bae3210d869feb7dfa861e9f1fc04f4c492 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h index 9a944702eb9910149262ae38da9867f376648ecd..4b4084e02d472b361b50653435981ef0c8e3dc93 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h index 407154f9086348fb212784025625dd579ec6453e..cc6df5ef8da4f966005913623b4e5a399427cbf4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h index 0449cb7c0a69714619a8ffa4cde9adda6f152f49..112f9c3e292461425cd3b6724cccfbefb14582a5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h index cbd88aaab84f28e6b30ffd7611f808fd69363f9e..b0cc5fc8ac5863d9f0a21c764de0e5b325827bcc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h index 70151a3253fd92a2fbe2611b5cafd43b97eec261..653134372d375a6415ed6e17869ef0be3e40b27c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h index 6a113b59838c6eb04c4c0b70760ebdb4155861c4..643c99c9ca27069c3fd627cec6f9d75c7d259672 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h index 26f96ea5d4162da4c827e895746352b44e4dca69..8ebfd51dbe74bd2dee637f97f9daf1d76bf89e8e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h index 479ccf1d6c2cb3a4eca593e2d3813a56f026a8ae..835956777bbc0b72318a6c9f2133bd4a1e425298 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h index f8f74eb1cdeb30607d541a9efbaafd0beb8bcca8..0a46e04cdfcd4e29904ffdbed2da9a4ce9ca3284 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h index 7950d918b19a590ae05386afd2899c1dd0174891..a4359590e5e88efc5e7ce9ed02275d422c2f3e06 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h index d45d27dfd6c71787576456413e88f70eded78276..dba67420343939faffbed685b466e54122e2975e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h index ebdaee80242cc6598c5b8adff226679951efa66c..e05e3cdae6c74f5028851cac2275daef6114985b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h index 324adaa085d34e92635e2d9e477b741e510b4065..5c13b104d4df6819fd8abe8db2312dc6ba5aa708 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h index 9186f8878ebd381d8c7ef6adab253f26edb11393..e7b3c868d2728c91b64909c6acf646392f3255ac 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h index 67661fef5fda0da948d6acda937555f3bdfc2f5f..51842c5f41e0387ab85425660f77e6f6dc5f4edd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h index 476aa507fd5ef268adc34bfa4706c8f60712478b..ba82771f436b0d89731b27a1fed570ce77dba1fc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h index 20010c3a4e914f562f1006fff3f40ba52cc1faf9..b1bbff4693c58255b35bde2f91db638e7f87d1d7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h index 333e1783b355cc05b216651e27089010fe51e031..ca164236c3d1e413c229501fdcceb314e4ad22b8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h index 73c1ecbed6b4bbc626bf6663d32ad9030161bf31..241d99cdcc7fff75810589350a68a72f235ed328 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h index 330623446d07d2fd4f50a3fb309a86045b0b3dd2..862bc3eb59c73e32641d667d84d2b8d9499bbcc0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h index fbad24461ffcf6ee8739fb2382e575342c7dd668..2f75679cba030b7b60299ceda6a9a826254eb956 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h index ecffeaec29fc1a35614baba67d07070ae6e440e2..757d6b177f4e37e278a7a2aeb466a6ec40fcb007 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h index dc33751272b8a7c2571332ebf549091a7c2a64d8..f6af34f8426e09ad420cfc34d4b50b21fbb82cdd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h index bc6e652ccfc90712591d0c4f3087e2d069124dbf..2fedea234df41e6c4b58985f24502137a844fd71 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h index 47cf6c04bb69070b69487555f9891c4743522af3..776975965cca81b053bc8688e9f31a7c4bfab7cc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h index 78b1ad79d4e9bf8a2c1ed56511b994a23bb446f4..59bfc3b16f9cf8d3515aec182abf47b3bb14630a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h index fff22cc91d97ef174649d9c8fc63a1df469aaa0d..4ff8f1b3d2e87baef72bb8d344355a5992f8d46e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h index eaa57fd58cf0cbe14ed18bc0a4901bdea06cd249..a1a4866261e6f9820aec5cea7dc353b9377a975e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h index d0ddd25d1850e51d4fa52a6c4068a8859fe76c94..692e5511692c963cef053daa2191665ba39db3c8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h index 093f0c41286429f4d74898b70f17fe8bef201ae5..0b98da0bafc98557f17a64419a5f19035d4be286 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h index e58a95bc92182305230b5c1c38a5c5259a14c9ca..cf3cf3851c37ebde3877b50844543f71aed8736e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h index b62809ded2886544ec93a77aff5d923a499b604a..96ffb553c0b0026937ad4ee1fa172f01c2ce710c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h index eeb66c8d166a30a7534263148fcc4737c12cacca..e6806994591f8e91c1737ef9385a97b2bdcc4158 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h index 52b94426b7760a894df7a16f0fe543fc4dbabd84..e5f26f6f26e489f4b48bf46aef589d274dbe131d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h index d2ec3b5223bc2788d991aeaec4e22e74d88198e2..6e9ddec53cde3fe5d10db9bdfaf0f9ef51426bb4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h index 46470f7be6db180a3d59fab47628d9ab620100e8..91a68d530e86a6721653e3ec2d0f088bc9f560ce 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h index 914621fd1296557165d0b2ae750a08ac372030d8..14ab3e77f5611ce32498a39a649b15b26331dbed 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h index ad307592440ecea783f069f754b7cc3b7fe0d96e..b7b12f330c6d0755cf97bb46614cd6ce18a5636f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h index d5dcbd69f4b19078f7d2e6cf5bb7e9536bafe9db..57fbb2a06f33aca7edc5ca84faed3fcc8b2b6766 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h index 1f3e16ef40b72e7a242a182717b61872128896e1..b9857c3f1d99663a66baeb9efd631cfc87662454 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h index b5e7c6441c73045a12400f833596f8292497d46e..bb83919a6a59067d3f6ea87c98da452f16eae264 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h index 6b013959184c40b976b80bc939ec2a80081b2c97..334ede54ec51522f03da17f23d72fb245d6543ab 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h index 5984b1809602fc555f9515b0e60b4db6f9b96cb6..8a86cc60c6db295365aae5d2dc2ab3e694255a40 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h index dd93978713a088d6185594497bc2178fad385bfa..25c17f036b83b6ab31fa41d56bf9db949e35fd69 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h index d745c7b949e47554697922e1d0e23086033238cf..8e474400277d20edd1fb62f9d74b5a4c870c8461 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h index c681c32103789c4adf76e72caf1a183b678cc2ae..887b04ac6ac4603772b2edc270cfc641d42f07b9 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h index 5011d5218e0b20158503afa715c9d2c645c1b608..2f34d09d80f7c2ee95b57b9be57f23b76ffcb49f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h index 33f9c37ceca555e2f73e5e5756d0434e125d8ed4..07d1b222563f5c2c2750e2527074574c57453324 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h index ee4e94d5e9ac87d7ad1f14229b4c0b3e8ac790fb..f1d4612db44da7ba15c3c41b21e01c1341c33d50 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h index 91150c1b1efd3879c6e7fdbb9df9d505064b5378..0fa32ddfa9ad006a870a32d41c27285d7fc9fd34 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h index bb8f62421c28f230f4ac320753d2cbf3c7fc01da..6fb0c1dfceb356372a4866772a847500a55fd9c4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h index f59a096931076a8bd64cdf2a724d2a27016649d6..964225feb68ad0b9648ec24411e82e6da7d0f3cc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h index d6674f921a117ce482c41bbefcd872435971b86a..659140ba0af866de9cf13ebcc9a57bdeb578ea18 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h index 65b96c88aa57c853054a33edfa9a788b76f28181..a94763a4ea53e69cff29a6ba07140dd9dccec775 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h index 948504a1145d4e2fe02de2774229ad84c1686876..25e93203c321db0e56585a49fd9f5cf442dd2f68 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h index f9c12dd6b8a3c866d85ae2af4014901698687bdd..3516e6341ce50ae8081d35f1116fcd312c02d515 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h index 31c1517ed64cef3b3781c2407f093b8230237b1c..e751d897082d18e4c79060519797f6ba86e228d4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h index 4286fc4456fa44291db01f8392a065fdfe0fd30c..8faec293f0d5f6aab5417621a58d3b4d6b62b97c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h index bd359d5b2a1a243456a1dfc1105904bd9bb5aca6..a7da6b7ffbcbfe057d3b3f487c23f4496469947b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h index 305ce43a6a2c53eda26a4b937c905f77fccffba8..bae647764641096fb4e405fc6e232a6bfc00fd22 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h index cc4abe2a5d4c08e40fb735f2e1f09d37d6e46814..abe81366f22ae64f8df9a8107771a2f223c0bd61 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h index a8ae6ceddf215e78ea66b17a961c186288564774..43d2c5268bc95b12d1f6b47caf800813522716f5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h index 7c589adce9d97ffdb9f61a4c2a180199a0ecf8a6..7955679e71dd74585c8ee8170a3150ebe1e4107d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h index ba64f95c5ada58da71d9e94227fb3d2a37e0255e..8efd222340a92c993479e5f2b85bc7f3a6224bd2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h index 9bf41ad03148135fc8905278556445811fe99bd5..f6f91d3bd24fd4b873ddb0fc96bd585ebd8da230 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h index 17ad79a07bf7443ef9a392134192a748fd3e21ee..b129d0d79e864b1ec948bb89d66c6e7c4e7382f7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h index 6133c9ed6d91c0b86d6df9a57b4a641ac20dea5e..c00f7d22f52277a860eeee2434c2accd57e3ea98 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h index 85f012ddad0d915a8c07c2f727ac29ee54a5150c..28fe7d451296e739a056206af5f6306d983b50c9 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h index 005b9f0600a934594da1ed505596adbc1363ac11..f3ec878ca00d455979d5f55df9ae941b6d44ea9e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h index d3ec8e81145a58e0f5407e8dbc0316596099f5f3..a551d38e2e5c13bf71f81add193dfe447a9d9ed4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h index 700ad62b611099494da852d069160e8a22c2b92e..527ef1e4f8ad1a1677cd019cdcb25a8a73943958 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h index 79c2cc49f08bbeee38258a631a9ef453d9ff56d0..8d1c27e0f6aa12158d9a61eb6da2856ca046d35b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h index 9579f60e7492af83d461d3145474ed540f6ece66..fac2f83dc29ad32ea838f6def64eeafa83bd607e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h index 34cae2ac42f376cb695de5161f60ffaa37821700..ccfbe4b0e20e98446273cd3b367b66666e855f77 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h index 141d8228356c4ae9e9705abba6fe26542344f1b8..b3ec21ed30f39587aeadf9245312e01826ebd006 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h index 6d1f30ccf9e3b345a24da31e5b88f29b7466ec6c..63b6cc7144ce3ebc450c20f7a71da243750eedd6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h index 026d843f720dbfea31a80abf72c96222a0f667a0..cac44ccf91cfef75f60ab3562f8b03254334aea6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h index d5e8fcf5ffdced057b7ae02423d943159b35de6d..3251bc2f3731586e55c11f6c4685e2c912fb81b3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h index 5ff9026125d7f8dc20e506c1900428556278767b..09abd6ff8e16f7c1fc51f3e4828a52793d5990c5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h index 4d828c2a5c049d68b9f9d07617f37873ca37ae4f..e293db70c64f1cea437003bb223a6969f98bbe0c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h index 3f50fb5bc27df23776ec4e168fc9e14263230021..3ba5f458e0d1380bbdf8998e7f427970d3918ff0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h index 6d987d84dbba4563ab635b93436100651ced0976..f427af14a9cf3c4fce1dcde083c7e218cb409099 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h index 957dc2b26bcad49c22a9122fc24481b489c4cc09..609a4cb0de4a15c76fc734beca4aaea589d9bb57 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h index ee1cc9d1b113d516886a383af4a9bd83fca3f7c5..9502b305725233e14875ba6e349ce2a44873f665 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h index b499ef0d6a25702d6c1ca2140cabf8d02cab0f31..8def748d500a067e349d370a934977d60e359705 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h index 8d11bc202b5ffb168e351b2620b2d242b913e5c3..bc887dc4c3e2eb4df9987a49d0faa81b722469c4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h index 5553863ed930e776141db5926ec7e2c1be7c9ef6..3c04b8b1e3a8d589e0591d07efe315bf339b8f5d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h index f87cf1a6aaa716b112ff2802b1726922129ff0ab..95b485173c27fc10cf07ef657f1e22b7ed5adc65 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h index 149b2399ad32ee9219055977ec5772236b2843d3..e5bd0ca310d605170fc7b09e49862ebb4b399a46 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h index 2dd3f0389c042369b07ac63e48562b7f50b65c78..edf3e2005deadd6d9dc8ac53561a1e1e3e57294b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h index 27df603ccf67086905f8289227db07403dcb7d61..164c2ae0d0f610ff0f0f50d74afb8ab65e42d65a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h index 479a1b2b1767e7eebe66500d894df0a8fec5a389..736b1ec1de7dc00c6faf1d6947dd37ca0c0a45be 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h index 1d701a479b19766700035212fd9f1b297c171bc7..7d830bfdaec094e7b1044a0c7006b2454840df25 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h index 004c868249b15076703978c00b5b5d4e38020deb..9f2e6126ff937f50982f03cd2b95310e797e9dd3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h index f81588a1718fbb759193fd14bb4f43cf5e8e408c..95c9dbe151bef73d54b3d264a38e7efcc2d54e34 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h index cddfddde1d2eefc6807ee7e0fa4bc73b1498d11f..5b9742231e7b2c97ee0888254620ef317a035f55 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h index 8984686181caf3a41a85fc076c33e606483c54b6..f0f4715461272f2679e389196e65d93a1829873e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h index df05c4902ab72413546be6e54579c63ea6763f52..9cba570371c98803fd5f915d4bd6a7759af9e361 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h index dbdc02ee9d96bf26cd0cc8cf55f87fa5dd67b164..9287fe4ed992a3a63282d75715e35cfbe3a3cac8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h index 2addbd91b4ab8144be04acfeaa49713575ae4ef0..a85b2478302134ec69fa82d20fb0e4812eb896cc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h index 99be8c1c6a0f8c0821a9a9f79e425dded78de4ef..e7eb92ea015bffd1d9ef32784b954003100fb883 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h index 08b5caf397ecaafe2c49c2f52b72f922d55ae084..81f8d437d5325e5a4fabc1123b31bb99ba88a834 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h index 59a5a841d693822d9d76743acdf4da05fcb4fdec..10bf2bfee8ad3a5258dea0e5d5446c0deef7224a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h index e4291693d378203b9c7ad16500e30bebb2bfcaf9..236a9179d670818b5da33fb045cc1dd9fa31fef8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h index 874a2e169703dd19cfce6b66f3fd091cf3715e17..9eef63fb4644801b8114593a74edfa493cd5e38d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h index b49dc7bcc87f34725076c1aab0f2d029b309ffaf..d7de9d41b0b71d9fa93f564000cbde29fb19677d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h index 581a02afcfe5d34cb3a624e5088a899d4e0d9b6a..f28cef546877496a13f57722482f9ad928a75237 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h index e252b48bd45a35d5d817d14f4fc80bd2fd10a071..aa49b5a60584e1d79caf1a35d5e67db47c5aa511 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h index 101522f473302143ba3ae583e178d0fe28961017..e7f284ee350b03322bb809eb60eca5165d18b950 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h index f068fd931bd0a30097180cf7f866ead6eb39d1b6..fa778bc6d36be600e4ce038b0359b75d3e0ff2d0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h index 26f822c5b696bb2c73e138b818e47e0375d034d5..dfb783df0af44a8d12b6a5c8cc028e969fa581b1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h index ef17c0e2cb5dbe0a2f956621308c947fba89ac77..caf8b62791823850e93922ab7a46294697cbdd8b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h index b7bcfb3695fea05a2dcbd31c5c38edb194251de9..561e4084f08cffc1125179d5aa61271a512e4e0c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h index e5bfc24ec9bd9b1331eb0478592692a8f63fc53c..81ba0db04c6b7b8bf3af67b482b6334783e153c6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h index c491c5735991a8e1d783b9523e34ef9bd82158af..5a2a97348e2f86d9edc1e3357551de1cd5f36455 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h index 8b8ee51f378f40aab16cb5663db7bca78b984f14..0c020867fa56d4fbfe0a79aedd94762acf78ef0c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h index cf8f1304d4e711374b153b478f0bb63ffaa0be74..3192bb3506088b2a73dfda72188dc6e382520fbc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h index f914067d0dd17a3d82940b751709f8a9d867dd1b..1da611822403c911f90b2e3963a235a1fb622227 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h index fc35046f1161516229d30ee804591f56077069c4..4cb5c4de887de394e3c19819625830695410d4f3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h index 01f3f5e7754723a44320b076dfc05f86cb7db431..e555ec8af79f20cb9d48189f552a219f1d427be6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h index a275e6e9ca155002b431c0f09455835b445419a1..5eabbb1b0ec3b5601e1b6f2f08d9a99c3eb87db5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h index b315795b1c5740016be296481be610d63c78600f..2426db731828bf4d3a7bb9e994782f16c0807deb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h index fba54b81b9202e2b164d0f8a8dcb485652fc63f9..33297e8052a638eb1c3478ccab60eb81784e567e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h index 9dac8d9ceee3fecb7a1af7e8098dab7f58cf3957..807ef7f0bcf61a539e5b12278303f1b75b7c2b8e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-clz.h b/test/a32/traces/assembler-cond-rd-rn-t32-clz.h index d65ed2b227f5835f7e51d5eb0446f1658a2506dd..0658d7d4732c508f7faf0224fda165132779fcbf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-clz.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h b/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h index 78674175073e4c8a31a24df10e905f0eac4dcdf1..fc6efbf328a1bcd9db1f6c40d5d211e2e21fbbfe 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rev.h b/test/a32/traces/assembler-cond-rd-rn-t32-rev.h index 9bc93cc2a60eb35fc616ea73ebade8f90bc4e439..ee932f266ace378af0a238305bda35e1e19c511f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rev.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h b/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h index 966834a609df2e3176d9cbc5ef9ec87d7b8437ab..a04102267a26fce0411dd7f1defd64714fc1a45d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h b/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h index a0d4ba720994f20e9f4215d6b81e3ec7cba52ce7..545f3d0ff19444b5b288f7be66ba372ad847da9a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h b/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h index 42dc0b499f778036a0a3cf687786d6198cab74b5..025a141b4788de7248e42e4e27f4736cb74d69b0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h b/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h index bb7744ff1fa538e51bc75c4ea6d0e6518f8e2e37..fd6d45b360377d432195f9ae6a17bb508c070ea7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h b/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h index 212327d45818efc521c14f719c2eac5199a17f9c..9bcac96be5376304e61af57f1009063fa3b735ea 100644 --- a/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h index 5d0c5713fe7f6f8947ad6e337942349df75a96c5..f05c712c8dea0553aeb42a68ef9f067aefd17191 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h index 2cf5c2440748c8160fd7b780764a9472ea11e004..6c28249d44c287b7249705657b98be01ca01d40d 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h index aa13a88aabe3679729651e9e311540659dafdbd2..d50e03b84b3a36dba21972281912db6373002d0d 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h index 7b0ba803553f1b01cd7744a3fa707eba854644aa..fb859afe075979ed23365bcd196931d6ef332679 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h index 472455fae712a05f32290f5da5cd9af1575489c6..0d55a3b40fd6e020369757bc5dba0f8268716210 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h index f9de6f49d5318703a0f55575ee0ca35bf452b61e..eef6744b131c066f76620ec0fbc9a1f271696176 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h index 136b6f9abe683687c8c463e6558d39ce688e8c5a..76fca09c5c4f222855280ca5b78ddb61fdea359a 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h index 9e779c295f2a877f4383b3e8a94026f0c6d67d10..cefa239f812080769e7af04ee6fc6a547a3c5c6f 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h index fb5b17f48301683a8ef698a84b2077dfb67ebc87..06dfa6e6180deb0a425fe63cda90f96d0a867630 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h index 7229de63e39d170eca77184049c87edcda5cbb92..c0aa75b10fce3ad98e506d3640d6b747ee073535 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h index a6339f7fb8804f521cd61268611bd6e88bac0423..b09ad48b8c8b0ef68782c762cd413cc4a555dcb1 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h index 59767bd4c5a30b8e2ac966b73e680c36050228ab..093aef4cbd71505e2beab734f79f3616c6f83a2e 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h index 40ff206d7d269e9659ee7256026910dd2e348d00..42ab0dee96d332f12eeb26b6e8db057b81bae36e 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h index a4eda89f32813061dd316a77efc6d76b90a74ef3..c245714c60a210691862aca7e00cd06c3ec4eda7 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h index cadc411f41f6d509ef14ebf3d18ef68a32779d60..a3a1d10aa2540afbe426b65e12f7c4157148461f 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h index daa497de830b8ee75d6d9b73af6eb02b9a2b1966..f8020ba19d40e171b5c43134ab871da05737b9f5 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h index 2f27a3becc2c1a3b857904c70c61596d55cb28e1..29c0a203c2f1d0cfd73d549ff8326e6fdd0257d3 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h index 48faeebc5b7ed0ade3a08af3a7283b088c8bc2d3..27118b81cf30d00e746f181c95e575422ffb32b7 100644 --- a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h +++ b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h index e7e0eb889ac046cb9fe6167c32121a7b46a0e72a..adf26a47410b1123194f7dee550c807546faebc2 100644 --- a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h +++ b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h index 8aec6f3d8f5cb96831f9115821c28a1fb9682b69..4e8b3117524317e9e7910c153fc7c5b02cef127a 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h index 4d15396b3dfbd810fb45b65e8af92a4f939a30c4..6b7bc4538ac5dcf4efd47f58658a4f3a6ed5c3d9 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h index 5fb2377b13a1fcc1057ed9d0affae8d171462c42..5d40af5b489b34dac0ceadc5d415c5316432d7b6 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h index 38a4a656f71830cc1b5bab1e5e305baa3b9cdfcc..c031a2d4919121ffb27f80501f14be61a169d01b 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h index ea66ed920f7d482a0b9e9e10bc93300dc49ecaed..cc2067a4995ae7337b9e5ef0301cb906143e7995 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h index c52512da46afc4c28bef223ccdbccb447feae812..2d60b1dda6229824ce4371b2119d474c7d50418d 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h index 5095a30760e42b5a2c12ac20c1262e907c05a399..8cf0a8637ea59c20bb884fb5365e63bffdbace5f 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h index 7f5c110a5e27b1fb7aacd0cefa83640b28baac15..f4c136d5bbe423d686b4812222f6945b82f6c2a8 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h index 89eb75fc7eab4934ba34c9f0586acd6b2e14888e..2764d7cde87d0b29ee023efceb08e1f563a29fac 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h index 1d4825d70e5edff98a826e6bcc8b6dc045d4f9d3..fbcc6a7ae479c7880ecc86a7196f4c51e767359b 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h index b8c25ce5374dcc06e96c6c153d9b0697b0a905b2..68bcda7ce4c532531807ed0af30da5093cde6ccd 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h index 870d883461005430c52219142a74a13331d230b4..9dfa61917eca8ed9383a5f135fb79f12ba0de8c1 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h index c999c9e44b795595632a56fbdb8fc2d8d7045416..f2b028ce6f6b5b5b199f43e82c90384a83cb2146 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h index 7db75c1d89da8f80d58d89dece0becc66e9547fb..68a5e05a17c9544a95e0a0a844f1728ceb94869c 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h index 2025e2d21ac05749573b030ca3ad74c50ca5af71..2ced3bb2c0e8b2fc3b1f0eaddf9c6d5e1022bc32 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h index e46ba84d255103c51ba96d594f856eeb6b26cd83..816c3739cfc2d9abab5dec0bdb852a14265bf612 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h index 38311195a98c53742883ea7ef37327d3d70050b4..62ffe5bd465685933877feea9ae2c2270d2a13bd 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h index b8f177a68d03551e990a5668b947e17d966b266b..a892db61b83f6c648f68b013f1d9ac728f6cf3fd 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h index 608b90d414e4348466acef411b44108021af951e..d52bd1f3e77cf5d7db168defb917770937d4cabd 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h index 6743c04c6d73b2304d1f80531a3788c34d664e70..5b63cf7726dfc1cab1f6776f856c1ecb1ae174d3 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h index 051bdcea40f3ce04557bbfa2f77c54029740828a..ec2fb68e922d9b4950ca65aab3b7684457798505 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h index 35d69156b87e6fd643bd41fcb5d89036c1431fbb..c86918eb040a25520e55bd790fc4907cc87946fc 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h index 3cb038d61933c914c921a9942276290d37352fe7..9d14899ba1c239531cb11dfc218c13398531db42 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h index a33650e893f838845d818bd2ef49de6e5555c025..5502f5a46ef3414ec53623bdf8fb686e12967539 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h index e0c55fce97ef3f1617041410e9f2902f2ca8c657..840a58438d949a59a885ee1a043758d7c1b77d1e 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h index dad8f166063c8602e1ee71af5df8685e66b47ce5..1ebb8f629983052f77ee7f0e351e1686a4dea183 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h index 97e82ae946d912e193174b863fde83797846ec16..ddefd4684342a3e0588a2d4e50d41c01998ff7f7 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h index ed640dd6e4e613fceb0b3699145a7c803a20089a..eb990ff04802dbb7117cc3e610013ab787ccb3ec 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h index 31789523e08aaed2bc5a4f1cf6480315d8c59f49..507ee22373a03c0ebf7a70c2fe777e6ece81a8cf 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h index bd0f8804310804760a39f2d08ad728b1d3e4ab2e..a7d43a33b2ba42494c60ec3eca219fe278f97fdd 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h index f7d4ca77baedc6cd4250a354afc32e1691934432..b6726bdb6d70ea129ca0850d73746f1af6d6c8dc 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h index f6d4c354223da711e81706921782903abdeecd16..68c110ff33821d2b6ac310bcff7d8babad024ced 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h index b0ce0ab10f8e66a16ad9fc06a1b9bd76fcad4c8b..c0ef071eb8e353c324a17443e13949fafcbfaf7d 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h index 154ecf0ffb6ba5542c0ef2402ca1bbbcd1151a26..fd84eacaae8d47b2a1ce673ce645557236664553 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h index 0209b858a1c26547847d17057453a1e5d4baaac0..482e83dd522566685ec23a6c6b44299ed1bbaed0 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h index 6634ed4db78834bde0bd2ec5174100037302bcd8..3b77afbd8b67637e85375d2e83879195990943f1 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h index 773b925870a44839956608eb99ac744baa226d27..46b5aeb5db7a4bf2278c98f0e78e0e7fcb46cade 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h index dda511ab726084c98eded3900d4fcdcc15d5b47c..61b08a50732e5de736b22250ca001f043b4ebef9 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h index a57915c0f187cf7ed39b56f71fdfcc3f80437986..84c341f991ab7a7db732a965933dcf0fe6bb741b 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h index c75856e8167f700019e611a22426e9e4da2d24da..b78cdbea65e5b8797421036a8dc4ec7b7da9d7e3 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h index 8ddaf3ac823cb60a42bf7e6970ebeeea699bcd06..a22fbd864995b1717a67335f15923b33f3097aa6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h index fb1005332b7054f0d071e660cd8b7d32127e78ff..ef85fadb21e037d924004a504d1576c0806670d0 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h index 4519040167a2ebd3ac7b624a028cdeb0831e9edf..320f528035113d82172c616e4119cb1e8e1c1141 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h index c9ca5d642df031892638995249c955828871a699..cdd945aa3ebe3a8f9dad75e553765989528fe7d9 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h index 1b872a40ad6a3e6db709beffce2681604d7f27f5..ff83eb3735ff207c3c7cc7a378f377906672c189 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h index 62626f8824a20c3739111e9f385c335d3910fa0a..14aad86d1b3bd4891d25dd5817dda27715f09399 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h index 6f81aec76a0910f744e2a258a98dd68b4d14f32d..6022cbfc49399ae94e69fde1bdc97a7b6c4cf800 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h index a38073a4906249b8f263d67c33385de1eda918cc..6502b9c4fca18d65c8122c035157b77d661beed4 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h index 8964d365c0f2dd24d1b15b866e0e1be08a986523..f8d9a7ac03da6ce17292627e0b5730154f18a15d 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h index d2413456a3bbbf47b08d488e142a4985e96d9887..fead00b9a629aad4ad82625dd03d51e56a5f35d0 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h index 101107814fa186a07e3d0c14102be629e11955fa..1cb54b856f38c7590f74493bdc1e7e2b7fcc38ce 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h index 605948af30934111276bad90c839f300cd6260d7..2c33e7653fb822d03c16e8636466eeaaf46c99f4 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h index 7c3860519515fd1ed44161a475e2ff0c266c864c..f229d5e28594cd6201c5b3bf4d8e5220890003d5 100644 --- a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h index 1ddacf35a8e499b80aa0e6985980d57ba5f6fab6..f9ff9af6eef60bae122b302049aa3fc15612d567 100644 --- a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h +++ b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h index 5eed6060db38c7ce5224ad5997b29c4ec2aef306..cdde9fc890e6d1a8540767c26ea332cf6b0e8e78 100644 --- a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h +++ b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h index b1e8d3051124ad606fb378a75655b39aea824a12..f3aa3eeea70a6b44cf5776cda1ed53e50e551981 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h index 05f804e2c99fff2ddac1625cf354fd487d60fb5d..34cad6125c4b292ab36b69e90eabd466b754308c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h index 3fc8bbd3a741b1c66c6e3efab9600d52eb15fb91..8ba62c0e84320cf2e9e536da90f4d9a81b704b93 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h index 2b16be90d684ce2ea24b7e15093a375f8949b274..d92b2b76c91e517fafadd0d36aafdc825c8acf3d 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h index ee4e45c706f3aea5a08098314266f7855a579bd1..47631b01d91e237a49677095afecd048de275c45 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h index 8fade2cd9334e39edce503ae6db86b8e28ff5057..36f8fb40bbb763308b579e644ef5d251b070d2eb 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h index 8af186bc9e5fd275ccf592618f43d9e5e9f4a3c7..a8f63bd66d8444836177a37a11ac8c4144c803d4 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h index 2912bc86a590046efb2047b8ebbd6bb803a1a0ec..57e3ab744fb7c229f39670b7e7067949c830858a 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h index e60a698efeeb3718375f1c0ea6997d75b76759c5..afa112ba71f59db690ab3a108dccb44786e51a63 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h index 8f3bf349e6f99162825ed69391b60b59793abce4..1d49edad8f0aff62d2a3fcec6d2e7cde6cbb85bb 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h index a799e8eddac00f0a4bc7b548671d1accbc3bdccf..939caba12c2c844507858ef05f1a2926b8b92deb 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h index 25a3ac5c111d815a29c667ec514d7f3ec8e2ec0e..090cc6bae6773979ed4dd3884acc734763f1e2c2 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h index ab9cc1cf3fde68506e6ffce5a8aae60fb85b5e3d..5d8615daa76f1950e739e115e4ed9bb7bd154a77 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h index 29c89585d4c9748c4725ae6337f623e38268d32c..242ffab987d79f2358e26cfdff3bfcd2cad3907a 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h index e9361007826a746c1356c7f18d929094a0f6987b..ac5752ca4ecbb3230286e53ca139dc1bbd4ba95b 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h index 303cc11bfd3630b38ff3b5d95d06409ea6a0eeb9..36c627fe9828b327e48a42196263379dffc48291 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h index 64249d10e15bb5ee28cbf7e685a55a029acb2d7d..e716fc2fb60881ba7cfaf2429f8b658bd578f331 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h index af6e3a622e9f2ea174e6e1e7fa3066523ca61d38..ed94a3dab1c496639db2b905cc7623f86e6368c6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h index 28e430a3f6a5848f2611e73c6e7af09cfc751ece..9b01b9bc2c6771cbad88375020a684391186487c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h index 8598bb75184c615f5f948081e0b30140386f4b67..b5590a26d2eba674b1d06471bb78458d5d6dab92 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h index 882393823102e693ac4cb55ba43b70d240c0ffb2..f6c315daec31d9cdafeec09b1db4d13bf97bd007 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h index 96ef8c267a305b73da22a4b177192ee8a4dd1438..1ddc21bd2aa8f7ad57fdc92f2287e86ade532f96 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h index 95ddba402c19824af57347c1692da0d4a7c6f929..0b7ed7554b57250105d9748f4ccc29de2cb1e145 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h index c3358ff4e71ddfae2505d0f270008505eeb8159c..a6d6210c58f44a73c864f7b667d835079a5d46aa 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h index d920dc7de466fb85c33b461790991f73c308489c..6d549bce88b0bca57e329e0061a83d35e6a87feb 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h index b0549c3b57216fcca42b5aafbf4941b8609850d1..c4e22bb17a6af5527b2b6b04b12da812566999fa 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h index 0b708bc08a0284b468e33e82228a17bfedaa2fdd..c61b491e981abfcaa8812b54a9bda8668126e4c1 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h index 32006eebb20e8e8a1fe2759f13fa996e0c7dda33..815bc6010a17af767763f35627812f12acfb92df 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h index cc81204ae9274a75077bff8440a4a706652c2440..7e3b1da691b09188b2974f81680b2237f75536c0 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h index d170e47dc28e4623cba9b25a6b005ab371a5b756..5e1f0e20f292079a9c03761b4f40b260fdc306df 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h index 0686119d66d8b809eb68bf77343bce4e15b097d8..7546c541a412eaa34483b48fb4e7258c9b88a48b 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h index 5c7afe894d2102025bf49ae3ca0aa9c924faab92..1912a29e11a61a26e88b727f12da4ca101a09eb2 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h index dbbfb6311ad9af3d5b0a009e8257cec5a0fc6fae..de8ef29c9cfecd5664d013bcfd7b69fbfe4ddb2f 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h index bb283d1048d32dbb3194171e3eb3d81808382c9e..40a96484600e7da7fc192c9e09cdd4b23a7bc470 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h index 5557d45d19e2877363a4e37595c92ea5ae236900..426c08c3b4ccb59b822ea65b226922d4fe13f07c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h index b1da5a0eb8f471313f8e4ef2a789db9271e506e8..f4e9f64c19640d6b016912abe9ba96a17b9b5abf 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h index 859431f47e04834967405e2bd4b09c3ef2f53e1e..71081310a5599dc8bc1e78e607190a157c5d7d30 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h index 6ad692ce40deb922c7831ab547fdf14a00a9e74c..13306f97259b25cbd293dedfa8b4c7ba1fefa1cc 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h index ca3f5c4f57968d08a7c122649bbae176318c5fd5..c71f41de684fd36c2a178d1817cea9fe2c335c20 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h index 758a37e43c07c2bb3029fad2da492ee6bb1fd5d6..5d7ba5c815beda5f7e036b98694d7093b8189b1e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h index b871ecb4eda6cedc40e3a8909b1b6a0aa3e41fd8..720b7af4cc1547699a4cd64923603c950efaed93 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h index a13c599f6e812acb3b2c8a1ea8c653fb47b2ddc1..970e01854a1b7d3cf919a5ee05b83ced9f3ec6da 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h index f57a5e5566046fe2e490cc1e010cfd4464a730a0..b4eee5f6b1b1db00386791654d5d92f672d3834f 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h index 817d4d2568d6d644373fbc9ba95365b452c395f7..2a1f4638d3f7a274c0ad933a5ccc910b9712586f 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h index 1fd9db2bd71dabc04a08f3d571d2ba19144e07bc..4ed8cc1d9f6e3ae768e3faace4c977573baea47b 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h index 4120414ad53acdc22f93f4a35e326d4a71a1560a..f13f2c6526416bcbfb63ed6a9375b66415b6f81c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h index ac7f56ac6cc96980a39604a7ad3043b798061370..7bb9ea9e7481657d3cc680d146e449289a7dc3dc 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h index 1a7d9a5946278e46e2131e7559f509b281b676d8..fd4dc852c99d71753e09e0641336cd5af943c811 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h index 746aa395e53fe924696e8475f0c0a7240ef63da5..6913f921693fce501cc21c24711eecdb5c1cf95f 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h index 845f2d651e7be01a96de12e1aeaa4d0720005dbb..2a1566be9d4e748b688dfe267534301f69a7ecab 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h index 93f91fa18a778bf6252470ed6cf2ba71a586941d..78f953205af8d64d0b512a55c971812c330c45fc 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h index 9182c040c206745d2c38c3095163d373e6d8b73c..83beb4cfd52968063c40845cc46db8a6a080e723 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h index eb79603f28ebd3e310e3823960fccc49277897fa..5f5cb440a2a0137badc938a0e81ef9f9c8b6cad6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h index fc5c15d8097eba896b6a82b5b4ebf4dcd63b48f4..059a503801b09827d7fc76092f8ec12c63abd74e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h index 4b81a3178a826791aa82d4acd2412b576c6d548f..bea52899a7027d76937b8619361fa1078f7b4e4b 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h index cb04a6e8c1168d26482164a4fd5ec76a8758a6f2..229bea7a824cc39af4d851992ee428255560a638 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h index eb2f369648b8b219a80f45ed8c9ef5060a1e488d..a2cc63ad2dc716209c48469f8b365236c7b53357 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h index 5301c759112828b322de1b549cf7f3a27abf3169..7539409a3370f29e56eaf83cd9ca60c85dae0eda 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h index fa9eebd36fc1d531910a4c92d85afaf32488480c..670188e1aadbde73bb81714c26b7a9a88c0ce21a 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h index ff44d9f8484efbe3c3beda6b3a1f0ad144102fc7..786e7673ba21077a6945aefc1c68353deb5d87b6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h index 6f8c7af6c7861a344ec131f2e593d7e6c30ed5c1..71788e4ac79aa8e6f5900d81c07ff80da0755a00 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h index f639c17fa3dafa5715fb90c1cf55a7d8be7bddd3..5355a4f888bfb5a58931180c0a1cd89d67b34d4e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h index 9cf061de07f1d3836e881c2eaf0dab0e7852cf86..1ebcea70acc7fe9c57bd72fe40c81f818f4e8423 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h index a1f91daccd09e9367a6394115529c72b43e0c141..339ad400ab3e4f901ea150594f6cc4869346a739 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h index f77d4f67388a360658c0e6d1a4f744952affec04..81d38c9ccf9c5befaf5fc9df7a12c3871d97a7d5 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h index f67bb220c14bd54cbbc7bae4d8b749ae422ba89f..250d369097ead46882a058790f5d511668974f78 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h index a6adbdd7e2ea38720fb1320ec2df8983c0992449..c6d0a012b6124e0bfda581685b2dbec78044c9d0 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h index 20f3eec71913298bff6b92e1f890e3d46b14af0a..1d6b6d406aa28173f9e04cf6d0c2eb1b879c0156 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h index 8f320bb55db914607d5b1006da57ff326e99bf94..8605890dc362559b42567a4c105a9c12f28df41f 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h index 8b457675307c16b1de08057c663d72399ba23744..c8072e5f5dea32b4831202adc2b9aed3e646ddd8 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h index a278840cd154076a4de129ecf5b84478848fe3c2..fe1945b222c48fa5c299c21b11924e8728e72474 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h index 98faa239a582579fc9d6659acd4ae0dd9bacbb85..f56e8842f5f69798a5de3b734f60a11228a1dacb 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h index 3b102d6a1016d258b5deb764f11dfd4835f57ac7..6a0806e83d73bc92eca22fcce0f5fc3bd8698403 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h index 832d96023c036ec02bb2e05e2dbf396713c2237e..5de82847243a08a665cbca7942bca40a8834e3af 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h index f8f5ee0d9079568ee7f46ed6b0c8fecf15eb3943..553f386d9a5ccc56ce533772ff9462a70e090453 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h index a9733ff4a71ac70817a5028ee28e9129691a9109..9e7418a0e3e0d365c21a939b71632ae37503049e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h index 568bdf9033415e1abaf34ccd2e092573bb835894..a6ade4d6ca67f10e9769cc326a3c84ea767e79f8 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h index 6b7ef1320720814aa35ac7a0542d48d59f709112..6b986b61d864601550906f34a1616129db3d777a 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h index 12fad7ce7734a5691b01c26a6da6798a50d942fc..c56020277110d28d7b4cded2ab3d372e0d055217 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h index c0ec74e46b88a7af36e4233debefb58f3309f313..c1639607e4e73a37545c249047a206227e511733 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h index fc821a9b71ba57b786659e170b6b71fe760e6a38..6bd8ae0237674616b1242900f92f092ad1717fba 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h index 83231f93ec65c2fca593445d0831601d563290a8..7cbfda4911cc1aabb82bde226a2d3d75036f4517 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-clz.h b/test/a32/traces/simulator-cond-rd-rn-a32-clz.h index e77eb7fe30eded06c73aff1a34872f041e86dc1c..dfdd3335297b2ca0437b73081057aacd07a80d0c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-clz.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h b/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h index 6b7ba0b9a81d6b464bc371c372714a4d9b7da5b4..54ce0a5da23d1cb2252f9bd21866d537c183e599 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rev.h b/test/a32/traces/simulator-cond-rd-rn-a32-rev.h index 7a362c10ccebd2040e838074139b8a7592bab108..ace283ce2a489efe6cca9da806be1985d2783c7b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rev.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h b/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h index 6d7165933a220359b9618a866512735ee17dea3e..fcd3488ab3d5e29e802b050ec5f1eb1f8f0f7885 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h b/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h index e54c8999717b456ad95c07a5fe231e4fd16be9b7..4ef51687d4fb00be3bd6690074a24c4746f63a2f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h b/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h index 1f6d23aa5596672d11c2cc9d9841292a22c5da27..4d8318681e469c9f053675e01554251e9a80fdfb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h b/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h index b938eb2cb2ceec35bb4e8380944939ef6aa118be..3f7be61f0f0346784928602a44de7459794a517f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h index 6b581e129d3105a88fdd4262bff6694451f63f36..775599bebb73ce4bdc7b4ce85bd203a2c57340c8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h index d2e29f952368e4f96cfc991583d953a32040b3be..da65a08af9928041820c96d04b52eecd0aa057fe 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h index 947a04a00ae7fee6e0279852e3d5c961b7ff527a..293aa4439ba5e2378d07cae40642984e34d87f2a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h index ee7e2d9a17cdcbc6a3a4e3089225ef2924f8ec2c..f23898933b194019d967cea44a0050ca60fb003e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h index d7a8ad7ca8c4353c9b2180c3860491b07c2fd177..3358ce99442aa5740885129f82361887bc4b26ee 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h index d206ded9347e68544809bdfe361610db2a96d25d..99417052c361e8347a2d7946f57e0ff2c5632ff7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h index 0b83999d0005a0f0f0210009f558b44d40599004..a6b28de5f7b182aa6d5b6b0f38160609275dfb13 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h index 50adbf7195adcc21b7d3161990595e02c88eb18d..0db9ac200118a5e4955163d6f13d0d736e576249 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h index 2fe6acd828868cb732f0fe2a4819f890f228ff9a..0c667c80f6973130b9837f9ef5577e46f88a3a78 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h index 7c863eb761d37e51a2e4efa2d8f543b81ede5563..3ed354a20661130df26d8671b869f1d3ffe13c8c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h index e29c7246d42c0f2bd855aca03549c87f92bac671..eff44db7c9b211359153e5d5fc9849a83ba9fb5f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h index 7eeeecc0442781e7263eefb887ffeec607d37d11..69230355f65f22a9ccea8a0d8061109a8fb588ba 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h index 1a5a82a7a70e497422411f8a9de47e91dd68c5c2..007fbf07f2b7371bda5bcebd0381a759ae04baff 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h index 5a75838e4297c617a62b2fb70f53b6ed5c51e926..c57a65f365b654035954bf07c63ff7ff9aae3673 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h index 806c5c70be1cd35bfa4b720f7878d30e1c4198f3..82fed3330a14abcb1700b33a1b62d79c3451ef81 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h index 45eb16be8184079d48af30800a629b1abf6b4a31..b37cf4f7a63722e9f5b111d0439c4d1f7a56fc90 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h index 03b38ebcb08e25ddb46a6b9a2100bc90c874147f..b59bce08ee184ee7ba4212232a379c9523b3d344 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h index 48e4a4d64ae89077a66f88b0d21590af3d1c0de4..8a2d84e87c12c76e310af64b119857138a689a8a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h index a1cc2bc6c969b03fe978b721ea87a0f65c54009c..9a74da4cc395b203e56396fbf1795861c6557ebc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h index d9e8d83a3dd6a634cfc1cb524e849f80b1c3afc2..348d7c987fd2b92ad66f43499e21c002c6f844a5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h index effa05a03e718d3a66d000261ff4e92a84bfeec6..96c5ccded09dee13b8916d4b7a1a1563063de8eb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h index 156e77b4eac896b16bfb3bc2903db1f9eff29181..ac8ef3cdd8378d146cf8ff4ba0fee5f0a24a2035 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h index 092a2139690fcf470a7fca6f39968f4022306f1e..d58ecac7f40e59c2fd40008232b90d3759639f8a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h index 9dc4fa10012a5a8f0deed7a219e7ff54b7c95e6f..8cab82f2beeeb6673f257b74d47aa9336d6fd3b5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h index dbc72eca676d742feb5af5d9c7a9c65be430b428..64db0c1641dad7150b9fc3d29b5341b7affa0472 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h index 8af5a00d3a30dc4266ca95e236fd093616f70cd9..7957100791fd7d6adac4c240bf22e1cfd39dd65b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h index 0e0e579668fb87f55e56077488dc549b3eac13c4..d69b9180b00e5a88a308950eeb4d60c483b61881 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h index 5b8e54d2fd29e3377243751bf70b9b91b21ff63e..6246301cbe3fc3d82f70a4981026451ca5ca6bcb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h index c02c637400c52ee7d274f422923a23a91a275b07..c6f1a0dfc13ef32a505e4b54a7945d42d0301781 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h index 24dff9d5a9207ba832448c441bcdfad48a2be87c..26cf5501d838ebcad74e3b087b3eb9cb917338a3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h index 6889a9037e22d876fc11e37844b8178f32c14915..57f8be29f86900a3937f73b0d88ecd5cff8ca8fe 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h index 7568d10f9fd99bc6ae72cab725d20711ed5c48a0..85ac0331f62ccb6c99941b480c343b10b04881b0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h index 4ecce0d23441bdd2fe6c0c29ff704593610c317f..9a4f785928152f287190e60d0e6ab83bcaf31966 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h index f2eeb2021e21d37ac72d39a7d89213bc9498e7bf..0e54057b69733dc2243371a5d1888e35f4b4193f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h index b57fdb518927b1518dcf68bf3b4a17866c1817be..0d6f3f53e23f6d5b1981fc9ebffcbc044e00723c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h index f972b3d00479b0f0304917f9237bb0070deb6791..7b4238821072d15a0f0136e35c8d61bb307bb916 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h index 4ed3729132afc4af590a99b79e44bbf1a01e369a..4f67efbe1f6f425224f9adbeef29c066d17ce132 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h index 8d37e8c518c3945551ceac8f98ad4c7772ea465a..a538c19685cfe5b0426d4cd7ba83b3100be32800 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h index d07440a1fc9e80075bfe4704dc0efd02a3a2a2e7..6c26ab1ec1c2f38ad6fd4e1114ce8c8651eba54f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h index 85f2aa259d6e539fdd84b4434baa99c6b8a8948b..8d82f15de5b51e0192c6a7de09d0ab86b0f44a2f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h index 82d2e63f55534b9c0b759483ad14e250692df33b..cf8b906a2e8324fba717ef031900141918388e42 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h index 9618586e04b4e3a6bc2d438206f92176255002f1..8993dd88e23882a262935e4272564e041d4f5dff 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h index ec83d3174759228729fabb08e69faa3c4ad516fe..376e737bbda4aee88ff6aa36368f7970275a2c01 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h index dc5cf30967e6a14edcb4b4f55028e2da1c761f7c..3dabcc616b1ea61d37446b1f16b6e483b1fb6a1a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h index 9d7ad8e65f206bf4f54d4c1540627a26751b0ab0..1c5871aecfc4b9e5a59c130a2ae0ba40d240590b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h index 3d3c10f94b1fd82d3db1a818b40525db8aa4c17b..1f9deda64abded99c24ad3ece7c287971502b27d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h index da32c2201bfcf79e720aa940266c98b48dc62389..a8fb908bba64758916cfdb29e48eee40e5f5a618 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h index 35f68aea71504938fdc48dcc921303bf588581f7..cc4c35debf90a5451212f3503dfbe39686550a68 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h index 891cc791e9ea96611ac1db98d9ae3b90849b5d6e..a96a6b0ae51c1ec430b03f3e542ef74ed149f33a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h index 881c439157ef81972799a87774a7fc9f3308b358..945c55e41620fbee8b3b9d6a371944d9ce314a5e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h index 35810d3378de9c48752e316fc6bdbedb24ba9d3f..24b3e25e7b145d7e1fcb0d665f22f00af339539d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h index e549f3ca4b3096b8411e208b226b2e3d7a1682fc..95aa4c63eec90fd1734bc8a6c0d480644047db3f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h index 2c2e2f16c7031622ed44674287740ad5afe91440..e346c0706aa9a98e8ec0ee04f1214536dbc14b8f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h index 6bbad20a83c39cf39bea91824f7f93ebfb4cc7b0..57585cf84ce8b44ddc19810bbcd636a1ee2ae4ef 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h index 8d59976897c958a85e06ba2382e453d3ddb12811..6043e4c70f84987c0b607d583c4fd492968e5a47 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h index 295d2cfd9ad13c1f8842c8cf7737d4f15aa7bb26..f9d9dea6d81e3e9d103c355d2cdd64b7c2ba03d5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h index b9f3b541e57840c3ae3f2acc1ba0dfada5c714d8..4fd2736a8fc90d5584654269a95a38beee65e398 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h index 77bed1809bcad2666811553b9d6264a7fafd63db..f1289aefd2429b9e46c24d7f157ad77f459a5e75 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h index b16a300b7561ea9a8075a8404d18f0af45ce059f..7b6badb144a5e41b3c5dbce9bd2b57c85dcc34af 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h index ad50c204b78f56e47d15d28bc91c071631a53c8f..d46cab5be49921c94e9db00e45143aa7e053af51 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h index b2e2dd15a550eb74ab167c10ab1319113adb0f95..1f9d1b1bf40116dd732ed0d4d717f2f8b09c8fbf 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h index a5fd47ade4164558078e4ed2490be13b157acd77..1006b14d8616ffaf3327a23500a8a0b76fde6039 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h index 510259678459eddcbeac729ba6b3ef3f286417d5..971de840939dc37af922a8541ec89d0fd3dec3a6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h index ed9884dcafe18eebb0a9b1b8b81f54fbe1bd5b9f..5eee28428172d0f96cad8d59a5722f5c6eff75d3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h index 400e256202577ec230c56394df9603b3bbda03c1..05f8c914ba0987d91ec36236552dbcc6ec962bb7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h index eb25114c401d6e79d8997652e85b7c35a217a690..3b3dbf0e267989771a4c2d2bda421c96073a3376 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h index 9a5971f94f76e35cf8246b93f20671226aa2e985..70d54648e93af8fe43c38b05e7a1b10413e2376f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h index 405f819b46a6362ac623335f0e894ee13d537f98..f7062632a2d507a0b64604fe88ab0b282ceeec13 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h index 988afe8ae6941eddfa5fac0c58202592adcc1e13..7d274818bd30f007a96ba2ecc81f69f2ec52d540 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h index ea5f1cd0b406e171bddfa96a7c4c9d4a676e2fb3..4095c599435684ffbc11d2ba5a06ff7ca7f9245b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h index 153849d58d8731131364119ac49f7491f2f5e1cb..7a7fff03f71ed6aecfb26aa7175e8f5bdec0d96a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h index 91b5f4b68e108fca0090479fd639b90f89d3435c..8cc73101f09d4df4493217934fa5e94e60912e09 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h index 3e3363dd3310275d14ec1b5490d03d5b567581e6..18d9ad0e7a9c109132639a2ec711c971caa2c623 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h index fec3ba4141fec5a1262c610ef08439fb3b4c2024..6b355e1a9de5e9491a1dc2789a76f8eb7b01aaf8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h index 3ae945d9d028044072add77e06d8fdacf1ba8530..7e36d0c9133484ba579729323082f2640f3fd87f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h index 4b50a71315f2749ddc1cf91d3c9f34c14baf324f..1203418566a96ac87b259ed61a2dc745ea02b723 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h index 66d79d278c5c739743c9ed686bd822f982395f22..f2e2535cb824e2cec0b04ad709ff3bdb061a5f76 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h index 41e4aeffa4a03e4bb8ed52d696160d90849a71a8..0a54621c7491b690999db2a9e87b213b0c36d2af 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h index e3047224aecfd42d554995738fd839805ad17689..b50165636eb074d3706567f6e54d4ac936679d35 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h index 0701e287fa1a470faee7a4dea6fe2a450bb17fcb..830485cd18aec469fdc547782d155f40afa9a6c0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h index 096645a4f0ee0879af55b76b81f734e778af59dd..1ede536cb72ece82ce6e332839f0c33ff14fbdf3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h index 701dc5d31d7f5c1a4d36e15563cf4eb92b12a35f..fc12b0ceb85d36e261c762f71aec45eb265841ce 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h index 6b356da4d4bd103662c1f34850409381523b032d..b8a9f7bd98ed4ba4f5755a0b7941cb4357b70f2c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h index a43c33a7e84ac5887c2aee76681475f7a6852151..aad0e84f069730f1b017d737c9a934a50fc19fc0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h index 94d0544ce72415ee728d8fb1e351cadeb5cd689c..c5e4c977f3ba03719c3b5b9fe04436ac3579fc5f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h index 8a4ce6f210a47ad4e1a3af348b0426e9465e8332..e466f7daf5de91c96b269cfeaf031b622a4c8ab0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h index c553ff66382c0d4a5f49f7d87886604e6458b60b..b9044f7db604317485d453ad3a8d2bd54f996f5f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h index 2a7b97ea3aca7b707e936c4125703cf9a4fec75a..dccde9ba5da5deef7cfe19535dae0880a4e28138 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h index ec60af72870954cd404edea7873e7fe3ea4dcb4d..a3737f0f5851f95ea7dc14ffaac92e34bee1f107 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h index 2c6716bc33765bcb21637cc79ab2cf222728e058..7aa082d5691becfd605838df7a9fd6355d54f08e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h index 328998587681fe1fe87babaa710dd24c5373fee7..dae283ba927e757e347b07d3a06fa54b3c5062fb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h index b9925a3bd4264aa5995838413426351e59beda59..62cfad1582414d380d4a79201739245313edf9e0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h index 3b7f053ad69ff1d9d90924b53ba9b4e74a9b6059..b39ffed82045fbaf5d5a5fa973352a5c524f0ffe 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h index ab35ac352b47b5c984f2406aff4fec95cc421d2a..22315b78ed926d6ea4acebdcbafbcb2a05182246 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h index e0905f06b34cb9111818311f8bbba2dce33a8409..1da64119315f07327c821115df2b9fa0d1cd166f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h index 9e798f4e7c56c1025bb377163e8f4699e20aa9cd..a488c0c159d64b3bdee8c25ff025a1e7ba661ff1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h index e3a155da55ec4b595b76f649d54d58f4408e3869..3a5e5d03898de3074d292fb7b56c8ea32df6679f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h index 5a486b72ff6256ffb842a04ec2ea9b209a084314..5fa2eba4188ef9f745b1a9e64d90c71e13c26a64 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h index 1f95de8b25d957dc3f5b90af7b22d89b77cbfebb..d21348c6011c15383c12d5151ab1df95bed67c47 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h index fca30ea64697af8952a8e16dd6519239bcbfe80a..23608d87906cdf4252b2c5d7a3eea205e4035077 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h index ea16ebfdea7a155e851de3654cb37b5cea4a6a0b..aeddaccb7e3591e59fae5e53ba5b608604ada7e0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h index 76c37d2de1365616ccde24c8970421c1130ecf54..591c765fcf029f4d1bc1d8a60f6f3676a8936a7d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h index 6673ad1c25cebf70bcca6b4fe2a6966a151587e2..ed87db41f62048f8bdede12ef46b18169b28c80d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h index 38186dbdd862ca2f4e01276d8dd345e0f9d8bb8d..0fd35603119ee164370ac208940e923f19839f3f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h index 5e1154cc5f518fa581ffcb62edb03169989d5b32..1f8fe73d346e9550e516a9bda63bca2c3756f968 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h index 95d407eaccc859f739694e005e2a68379cacf473..e12a8f0dfd9ed1c0adfdd6e336b1ad45ba0c31ff 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h index 2dce34799f2330cecfc567debaada28103907ae4..e7fae1290941a265ca07cd974431b1734b7412b2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h index 85ff36927cdce5d0139d20499bcefc71a999662c..3d3fcd8e0780b58a1706fe2c7e4a2002b3a846e8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h index 3cc1a9de7b6ffcb9ba9ea1b1b71e1e20a845758e..c94ba17604c45346df62e48ce63e3d2ccd3c3fe9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h index e4fbec0e4833c134b200a7d40e7d2109f790be1c..496c3bf00a8762f3ee0f7b4483f72e20b3406425 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h index 9248ee74cdbc41eb9704ad93efe72d7e9b7a5386..7328c5386b451ee24c7d0bcb84857bf476e9b0da 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h index cb5d6cf8537f04fb29167e563e33717de2b27e4c..bc5085a9466addb026882626370f5c81d390a943 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h index 4e2f4811b10d0e726a9166d537323ca566f1a7c0..384fb6d54268844483c16d7be2e986561a134b1a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h index 361bf22474e9702c62045ccb5e2777b34c7341b7..6fecaaa2a7576c58467fcc83bb12fadace8ea992 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h index c98f83692c17063154af1eacc71b3c29b976488f..b30a4742bf191b2c463e4f1f9a2edcb892156438 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h index bd765b0d59ffd4f0a7722a51bee22d7515ea2d2e..87e506ddc72eb10d55a5f4c2081ef7f98d7a5b33 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h index d93cd3c7cdbb40f761869ce9c2385e410455bd09..bf5254312ff3a8c8873250c4bb5b20cde2af5f69 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h index ea5c43ccd114e8b76f37b678deeb004292a9f100..638a33f27d2844858df9815f1e3ac0297df29624 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h index f4b96c6af891485414c49db7b8a7c5249f63ab21..54532964c5a7d27cf093a09ef57c7bedb860caad 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h index d6bbbd1a22506ebccf1ca60da6a7525dbf5cc6eb..ef6e81c009bf7c0d476a4e34dcf6966594af907d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h index 0413a571490c96ce0d68932986f2c4be11d17977..58a73281c1205aaf632f2a27a85111188918be67 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h index feab30ffa2ecbe60a89e5f5a5f846a607b6f9e35..003c88304735bdf309b4ecf02ae35c1d0f02d62e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h index 9d9b11b2767062daffdfdf1289e301cb7de4620c..4a8462976f816d5d54658598e859bb847f2bc9e1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h index 78c6379e3ca7888033286fd3995f13ef831351bc..35d8afef4611138e4610b03fc1a95bc0797fbd38 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h index 216db14adcf3ab58180fcce48629e0072bcb605a..be57ffe7bdb174937b92f3508e50d7fc7258961e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h index 563ddb2078ef16ea57493595e34b9d6b4c141a3d..24e997c2a13383dc994c09d11fc4df2f606f3050 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h index ee693430ec645c424e08c0b35abf28352fff174f..83d2b319e49cd51576360cc1cf42fe53b9322a2f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h index 294d582702bafdf748661907404a66956799c4de..874d639176c21e9adeba3bcd3e901d5e341a159c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h index c2c5c17492919f82a43edd71260915a1a9180bd2..5063cd31780fcdad7ad899c0b85fd05d6e9acce1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h index 3a89a26d24b88120b4bcc3ec9f3258b0eb050784..44758011744b371cc917e92d7ba353926e7ce7d6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h index 220499eb22857861ffc53093689f775acf260f65..99b04b3d1341cdbcd0b7c8df25827dfa8acbc3fa 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h index adf40d3cd6c94b9b76715e5881f7c5460bb98723..5d9bc8fcb3b48161c6080cc080e8edc621c7d577 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h index 71037332ae54c575b8b518063ebf345c47972143..ce7d53b5f47d5d0de40589a746a92dbfe2fb12e4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h index f288da82791a36d8c6d0115f6cbdefb85a3b1d37..429589ad8765df0df0b7667936b37c064fb30b70 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h index f22c031edea9f823bc79f17cc263fb36c456bde1..192190e7c84e9db9bc8dc4763937b798d26190e0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h index d0441f1a2f48861a669cb76810c523d89d187666..95a9cacf1f1e2acc634e0f6efc08757ed928775b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h index 5ff951bef372c85dc3a34291b590e99c4af3b78d..f924779354e52a57da37922b2fb9592f0366be43 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h index b641d13570d1e0399f9bbc20ba8b6912b262f030..60ba37857e25a671ba898b6010c8624f1355900a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h index c051b9e086d6c0d7099746e6714c5f0ab53af1da..052e8dc0593f1f7286447e1ead5a27ee7eddda65 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h index 44dcf6173f8008813aef9e485d03d4dcf583d5d5..9a8ff41f6811524436d15a53f91db15d40238416 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h index 5109a25372c63ec5b30760265ac868bbaa241561..a148f2bdd837f4caa05c780fc86104d006a790dd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h index 404791d98204c91f0892c5ee6424c088a03b09a0..03ca8738a17e2a07b642be63e574af0f895090e0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h index 814a4921aa5123b590fbeb6d8226834ee0d0b7b0..8057f1df6b0ad51ce6b837a4a3c1f48881cf8a51 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h index 472b9c6963ea439ca943cb5d3fa3fd6630b298b9..de327b7ce3ca52200ef4616191acea0ab5f1fd57 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h index eb45ebc5f9e373a8b7d32a54b383eac16226655e..661f44c88beb8434f64ae9c4730e431b4da8384c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h index fa5e5b334d115583f6bceeab0cd5352124cf4434..694cde33739f4d24a10135c513f18ded7c70f172 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h index 0d13ecc8913fdd77160af5a7d12595300b96aca1..4b117927c33e72c0198c6a8e8bb525efa3c30335 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h index 8f11526090c077d4ddb56dc4e42f28c97d0427c9..b86abac31d1d5a671f0ecdec55c2a81800636415 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h index ca5c83b48dde4e1c83e6033695c31f437044a2fe..89f3b3b1cd4ea9cce7c893d4a80486331c1db825 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h index 57151f5a3aa01f5ab39ffcd4dce18144614f9d97..61c4fbcf2ec22fe54fe77513bc5cd7fca8ad36de 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h index 1017e958dbff22ea8e86263a979e47a0f412124c..e19686b67365ac0f3a0efca640a9a11f5a4584d4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h index 3c006f5d04bd4b8995f4766dff464eaa3b58e0d2..2ca357e2c4ddb08084eee040a9772a3352d829b0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h index c97fd9cad948ca22b59a0098e29fd82fe25a82b2..0dad5a33143da9fe14a458000f538d375135952f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h index 3719eb30cbb26d7c205d76942048c1b6136e17be..3ce46f8f1aab3ae929308e430918824691847273 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h index 2a0c1df0d1afc4976525dd73a3cf391484a2f2c2..f767a630515f0be3cb99d6c0adf9935e9e1ad7fc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h index cd362aafe24cc60571c6c14489aaea940f67556f..fd54e3ca73693b49a302f3223a60fdae03654f35 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h index 3b9dd28a94c9e4d8523dffc092ec99533b37a16a..496ef03042707758bd575d829a25891dc54e81a2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h index ccac5264df17026e0cde76b838d6fa2fbd18b6ec..a1efcb72cf2dc5cf0ef094ba1947eac2a2b69baf 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h index 047885f9ef9b0134ab47c897da473cf206e77f61..77b8b48eaf337fb11b1d4c73b2da034c7d23f18a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h index a61c31b3f4c9a24ec4b704eeb5bddcc229ab9be8..f45193629dd85dd883fe1d0ba1c00a65775428a4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h index dbf701bb6ae6fea94621c45d957e500d1353a44d..27ec4cbdd8e706d56b167d18d790f180750d4498 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h index 0bbb2f145757eb49d2c8a02295870c41ee74b0fb..b3bf4fa0666c3f530f9b3ba8d5201e8ea9eb96bf 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h index da02658a803fae98ca465a0a9094dfd6c814d1a6..5ab53cbe788350f284a08a1731e3b86877252ff5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h index aa46e84890f904595565628ae569d7f041336d1a..c4a2e79a35ee3042b811d9772945547b947300a2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h index 59478c85b49cf0eb1ac05b6769f31b7e3823485c..cfc7ed69b8dadeb336751801c138fd15d1f6d708 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h index f41429c211a63e73fc4908519ed0d09488c8a96c..37cd20a774c38ab1e8921605b438ce2c0eaae91c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h index e3409ae75b5036647f905d5a0ed498712e3ab553..8b4bf60b5cec4570b90ae9778bad6e46b9f0b54a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h index 0ba213e0e7f7c9e2ae97f6c5fae6a04e4c8c33a3..b256f606771347afc831187ab8657d492ff58eee 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h index 737dd787d0752ef8a3a200c59f42fa3c372f9d54..b94d061c801ba8492d4a30bd6b32a6463e0339a9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h index fb2f48e9754187d32229e903af93761bdeba080a..16f17e63faf244a745673865ada42a7b6560c1d1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h index 19bc5b544b15b5fd87eaab289ae70f6e2908f99e..153893b1c17c787306f645cbbe5994ea8801a7c4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h index eed34684016b48f652cc2dae0f978e983cc5080b..a8d0897a8f81e2533b6c65a508fc14e18dced492 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h index ab40291e5d3b67f38cced1ee3e7c67bc5662bd57..e7a981b8f1ed53937f2dffffb1115b5e287dad66 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h index e7f87219d7313ef60625914fdf7b41a28af79fdc..2ddd637ec8f5195612742ea236999af5e358e5bb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h index 53bda18d89f8737617ef6809542e91f389edf000..6da7f72c0189d1dd62ed1c0ca32c30406dcf4c04 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h index 7dab661ca2b31fba856d4080467d46af1e1645c3..f7563b9bbc8565764d2852f7453ef7347c3fcddd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h index c91853e80a3ede9e0c1b7e8a221a5d2390401261..fa2107f1f964d5edb5e3076a9f47f51c186c373a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h index e41cd9bc3f4fb2180112221df9ae1ca53cdfcbf7..60a350ae3ed550e94fb65c4319c7764b2eb85135 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h index 8b7568c74fa4eb3c50c3f5c14ca69e49bfe86cd4..8bcc93e51b71555e7dcbed89f8b472a7b4b58e78 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h index 7fb99875f750056539112f795c80b8e8649fa5cb..2837496fbdba82c0b4605406636ac64412127db9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h index 8541b0a45aab6ede8038b4a4ac78e807f85b06a0..dd0f947eba0e1ecb6d384831be8f881495019802 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h index adf4ebe1a25f92f3e705edae4f56dfa1512fbef3..4d1b87cceec225d2dedcccd4d5b3ef03d635f60d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h index 8c75e0cebea7ee981579bac04771ce676e4f41f1..65cd0a6e22fe9588ab29478f310d9a60162f5716 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h index 2aec94ab19f5eb71a0a6adb604f568215a183cad..7be5d60a5001424d5a9d864d8a9382ec51728299 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h index 041bbf1c2123b08becc90858a6a99dc3285d23f6..6fc0a9cb5b09842c199bfde785fb8086794b16b2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h index d8fc7ee3f70d121da6efe7a71796da733e24ec90..615ef47ba51f86992b0ccd0eac01cda98c9a1300 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h index ed037549f3ba15603f55e8ace1f6b5c686a19003..eab028462f0de3e729764ae48883c8e0a0746b6e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h index b10e6b36832af403e7f168dc59890b39aa4177ca..d00fa00dfc7ae2b68627045acc6b30b91b8becd6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h index 83628bc0ca734725155cac709c24d7a7ec1219fa..12a9b8b6f7ff285354565ac67b038d97e7476696 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h index 6fdd2441a798d6d6dddf57b623da527e11d95067..62077f131a0005a045f79389840c972af4e2e62b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h index 5843149fa343791e29569125823a2e133efbc0b8..a57d0117ddaff22fd8e2db94b36a104ba8f5d8c9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h index 61fdd282dfbb6d8eec85e15d679d7fe93fd7723b..b354d06495b3ba2ef27f72b43f567766eabdc5d1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h index 887955ae55719e033f85232edcca567a93a86af1..5511bb423442edfa14dace5df752f000cb9f43b0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h index 2958462c4033bba6b011a2a8b40d2802def16a3c..fee9d51803ef638390521f2d3baf61ffa95bcf70 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h index 244fc71012f1a1ff0228c52b5536d5bb339f36fa..ab8de3151411cb3f57d42af65d97ea03ffd95d12 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h index 499ae4caa1e977a693a25511b975d8408957decf..9e50e4c8c179ca913ad02c47e59c6d5bfd4b044c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h index 965775a37c78a0ce9ad799332732cd741efab764..709ece2946b59f5b222d74620ed7dda247dbd733 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h index d1abe402e9f8760ba484b79eb5540f259d28c7de..d5305faf2bd829c3dd18e42508997bdd615dfa7f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h index 1fc5fccdc49003e9714fdb2474c0b3f124ba3a2f..84e85be3c3e9aec744172c5ceea13caa7ac37b36 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h index 91c9f0e929c663ca6b8e9103cc5c84ae8825b542..6cc642f7bf8a2bb680c65696b8f51fe41ae40f17 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h index 589d016b27cbc78e34d40c32929123c90bda33c5..b4bb441a35c3f1918ae65949efd18229d53ae9b3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h index 2450c9f793282523a6b27fd948d0a98fef757c9f..ee4bd681ff416f37a8ff52aca8a06bce2846571a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h index 1beb281e939290f3bdd93a6f34d7b30946463a71..d895031f4fd87144758de501c1d054739edbca6a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h index 0d9ded52331853836070f05b9696c54199408515..7ce64137e8382230a751fedb85926e757808ccd2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h index 11289bfc32a1579da6dc7b185656918f2a91e33f..e234b7e91f4ea44e57e464c3ac4ecda67726b480 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h index b4cc440d5f2d9c7f1f0dbee1ddbe279125a2c909..7d69702e2c89421efaa699ccfe591402062f423c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h index 6f515635d343c463dbdd4bc373843e4df7514e5d..ea92b59551b905b71d6e655ca966b07f5fcdeeb3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h index 7d4168f1ca4f435afafdf791be45be9bbbdda26e..0cdab54e2a1629e3844a49102ee65c6c5d3824ae 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h index ce8ad029bc977aa87424a956a5776d0132058571..b27160cadd2eaf7aea9bf04a99ed4d2f36bc81ad 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h index 10822e73e9a277dc8ef8fc6a5347bda607ad972d..9b1d0045e89cfdfd6a131326db642b89c11c25e8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h index d1dcad7fa2537043c06217a3e069d00aeb2ea37b..d97f06a02efb3d77336d6c38068fe0ab176316cc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h index 294ad4c840f757c6e550d807e297ba307f7bdd5b..b2eb9a39c80b58d67e5ba0843112493fc6346eb4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h index 48cc6b103ba22a11ba8dae3c1f01174184e050bb..5b89e19d860ef2bd957ebcb882328581386688b7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h index 9dcad8cc0b667017857c3da763bddac0273efc2b..53b8ab70ea294a7a5e29f7b2425e809c0c6ae7ee 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h index 825307b9579f56435c3a515b44e359605327067c..fdbf6f655ca98f61f1e5f0c4a23500e8862d09d6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h index c4ca7662240dab7e29fe5e5b17a004788907e9f3..1d414f29c74656e05e67b55e6b8a9b88ca4f8fa3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h index 30a9c8df6465f67ed1618c1987cb84e3a4c0a4e5..1cad52a60e5a479092fd3f83e8d333b407240343 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h index 48bf1967e7ed1d70d68cebafbea7627c223b3fd2..1a16d4e9de1613a2f57c7b6e87f4831aa1acb096 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h index ef46f2e3b166a1c306b35309e540028db9198959..9a385d58091d2f91be20d182cd80fd12c9d1e838 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h index 102aa68702f333604cb0659c3c6a72191d42b3f0..163d8f9b0be0a9cc02bf84830c3d72d94e737e18 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h index 8602d275bfde85af9132331d1a6e58991b2ebc01..fc98b063659b8e53181c95adff84f67ec6db7812 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h index 36094c735914df561e2a1e3468f60320bf388df0..eb635ce1e480697d0d0cc431ca0d06011683536c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h index 702e4a74590d271f773341b7178a130c63a8ac54..ea63b351f9358218c0138613c8c3620654135933 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h index 1027e5962847025dca3b8fbdd6bd6b0351a2b33a..18790a1a2a511a32e5dfe066b459dcfa8bcac555 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h index d049755aff8b2a0cd27aa128b582987bed31e551..01f3773b1a708058cce4e6530f6f547bbbff646c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h index 993cd2210cbdeccfee6a000fbb60eda2baf8ba1e..118900554aa1e325d200956f33d803a75f421f81 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h index 92b5a04040d161a70d711fa49e36886a8e07bc1c..0f27047b1c01bd4735df3b7f913f7ff0ae2720fc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h index b74754f6367cc9d6ba40a79d452bb99d7002b23e..ff80776474b8c1f1ad5650cc2dd2cf797ee78113 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h index baf8d8f3ea9656bcb0e6fdb5c7bf47bb5af7254c..8c10c89e28d5acf8b0a4ce776555c1f71280ca7d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h index c0e6d11ae75ffb96683119a2d926058a5284bea0..d2230c9d65ec52ac4cda1c7b68ff97275b558ca0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h index c08c868c38f59e6c10041158c2c719cb143607f4..a644732fb1faaa3276749757f0b75d09b3b3dafc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h index c9070e3a19c1cf49f9c5684f8bf0a5d77f02eb05..066a5e1b58b8e0e02825499c891547c3406403f7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h index 10deeb9f88abfa2beaaf3d85c41567f76a33ab49..9893fbd4631701df0cc3ffe7c131612a1e0a9d6a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h index e6c625495b34d74641d811b131ffd903bd9aaf78..7cf64e005b3b0ecf6e946ce5d66dd2d0afff4015 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h index 04fb0699154fc6d8c4b44aa2d288af1f0a4329cf..63b43e6d79410e03813576b9158cf9b71e104605 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h index c3bb1fb5e576c7c53ec4eccebab6cdf4a02a4312..31a931ab4d66e0602bd2efff96e153a9e72ab9eb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h index e20ac13232caf88f20758699368f0d01b4e3815d..663424d470519bb3bdcf8cb721cfb7dde5fbd090 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h index af9dbc616fe75b9dc2f5081818fce6c49fb3f9b7..29356c25c4a3058ae7daf3076b0aeafdfda06fd7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h index 908145232f1450d8268134698340cc48b56fd651..8b363d12cbbed20546c1fc311f900fb01579824d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h index daa93b6382e0e7e7d8d57f4d08380485fcb8f66e..2e01bf922d966c7af1f14aaac76452b31cefd899 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h index 0d56d5bbd029fd32b8d0fcc8c95fafab026f241f..efb61dd06324d00541b93dfc70a6ac0bd42b86c1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h index 18e1fe74ac1340bb29c90ae7e2cb046eb8d71f81..757763b9df9c0fb0f3a43190f15c5ae354912aa1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h index 89f6e078bae171fbb3c06ef7530946e8befedf3b..ef2451d75aa6fd3e0510ee567c72399d41402e21 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h index 6a7baf3912794b94a33e887e0faf4aaabb6a2f91..480704d673a08805e93480196c16a412ce51e5fc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h index 1d677c52a9926dbc88f1fe3fa9ccd605e477f2bc..87d403fc59c0436bc3b74fa39766f5bb8c5f166a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h index 05324055344fa7e68f9d177008c59ea2fd270957..5c3695c846771137f955f4eab6f3bdacf4ec2b64 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h index 58df5b2efbd01f39f5a38b0edde66236383c166f..9e227a857e0fbf5f7fbae000df0b6c3fae262f52 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h index eedda3fdc52e15c98fdfb1a5726230b2fb3e4d23..19abad078de92d8c5a5114b9955bf7eeb17fb390 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h index d3687a32023363a105283c3fb0f5db099422dc7f..47f15cece0f81eae7cbb7a0b034d4a76a022e4bb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h index e122392d4d3488826a2df901599518ab94cb2c8c..59c2c665ae77b77204204cd51fa24066e76e40c7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h index 675fee67af46232f23959b6295f7d02a09bbc328..5124ba371b987375518560fb62e7f40d7a65fa33 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h index 36e431a2c525b643677f18610c0813f8206ad8c5..bd048dc8f1164d1ff32e3a89a116181b4d722bc6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h index 4433c87d3f538a683da9242b71123ac931c26fdf..6f4c9771b9c8ccef5b482984c9e06acbdc684f8b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h index 6c7bf47e1bc105a6cc465ff234758f45efcccd78..ec5b170201ae9d1a9fa728b6a94b901d6edc3099 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h index 8c5aad1093ab4ef2dc412a9af33e86e21d6443f4..9e00b6e087fb5fb2deb81d905eb4c80faa503b38 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h index 1abe506f479a425d87e9c8e75104a778ccd7bd7d..0a13ddde98ff3e017adb9bd6ed2c319f41bdd734 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h index 9e8190413a59adee2584fb42d7dc1077754c190a..df20a6aea00f79e27346aba5cde8a855f9f50c40 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h index 90a4350707d244ff6dae984c1b6d7de140b8b6de..a9b829019ad673d4543b13adc5d84f6c238285ad 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h index b28957136a2073f8202e6224d6497fea81a191ea..5fdb4b67a2d2923493a52f23cc896c38322af83c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h index 69df782e52d65cc06939df768baab71a48641e43..9e6d5abe70f0b930960ed77f7ec1dfc18ad7e459 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h index 30c686a0b239048657147661661c2a006bef050c..bb3384e7077e5d0a317f2077c7d2e10b0776619e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h index 4c4ca18f48dcc55448e1f12da0d676ecbb400f54..2cac732c2f489e87fe67ae2fcf037cfd72064a04 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h index 377b563eb0d2abdbd1d57e2137232c849767110f..99a80fe73401b28da7699ebab0f85cef81ac7e86 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h index 99063c5d38f0917bba77ed5e36bcffed54c53c02..253c2c680d4654ac87b00c81697b633410827455 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h index 70aa1a277d5a242a69b03b1dfee8fe183d895bc6..136b2df489ed61b61f14342115b0931285a4e2a4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h index b9c027466780e6a1e581ed807f8030dd8b29aebc..5f6f182c988d9d7ef75195d2dcf426dfdde4a696 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h index 64e6713e83766db588922ffe6ea514a63fe9b0e2..86445b1b374af42071715eb1b1bbefa6e1385b44 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -9,7 +9,7 @@ // * Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. -// * Neither the name of ARM Limited nor the names of its contributors may be +// * Neither the name of VIXL authors // used to endorse or promote products derived from this software without // specific prior written permission. // diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h index 17d3fdcd5667492bc239e7e41a54dbc56ca0bc36..e18b748f6999f23672de0ffb0dfa14e35d72e79b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h index 1527e33f3773fe9548540c2416280894842fb89e..694bdb11ae8bf0633955180d823ad53efb5a9419 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h index 51be51a39e249e69c7bc6c6a8a842fffc549a250..b2a596766fa509f437ca3f53b69338ab58b3d20c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h index 9580101add319f29f0b89023694a106d9e377be6..84ee62ff924e989c53fcc40a1c74bb02f8f7e30c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h index 227e49cb63cab85b12b9e01889bf4d0a6bf51637..8fa1fd9e5fcd8da6a356172099b17736dd292173 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h index 3e7aef6abf2b6aa77da1e24faa18d9f7c9ec66d5..ba65199e0423f853971f9b333ce0ef60cc1e6aed 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h index fbdb910792bd8e4db24782d005ceed1ab9ce0dbf..d6b944c28605684ce735ff5d3d0088bbeeaf0b5d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h index 98c5c706d85e1dde4d6e87570fe7b0bd4a41cb83..75bbeb235635ac7cad5f08045624259366de72c7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h index 468269ccdc7c37514092a72c591851aea820b3fb..32db22953fa5ed64873848c7fb3ed15bedc24354 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h index 901ed99381fb16dccd97deb9ebceb7bffad3ff0b..100005325e7691e3514aee996f026d5c7126b906 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h index 2bbcd8c006b178723ae44df36cb73a52fc9363e4..9475b86013deb7a3d34017e0df123685ec685462 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h index a3f20b17b8e4e6f26b3b1eb1ac24fb1f86b98416..27172ceca555db0976cd936a016dc214421e5e2f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h index cc27f036511013593c4aab040babce38cd4ee393..add8a4c87b4911a4bfb16ec42990006fe7d068aa 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h index 9e033f1f2e9c46bcf36fbb452b09dab5b8c2e3d1..25a1b0eebf48ec6ba39f7c5e717fafa09fdcefaa 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h index 273a9965d5bdc371e783d9885795f90eb52bd9f7..a0d379c0b0b67e6994978c1d4128d137a93b3405 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h index 7a8500c573164c877cda06a082977bbfc9c6c725..1b5588d11073630c73aceda08208af425c77dbfc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h index 1d457b2f57154d3f90e7b99d9464570fb41cfc4e..3603b2b48ce0fa7f5f253adbc6b49368748b0c74 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h index af5b7800cf3967e7b1b3eac89e0c878cd67b368b..299a24863f6c6e9a107349d6ac9e5bbd1a86cfd7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h index 6a138f9dfcfd7b6658df02d62b41b67f6dc720c2..56c71d4414bd0301f285c0e814013097c4457774 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h index 315641735c711ec595dbd281249fd9366149def8..b3c6cbf6c49d691ed9002963abb85a8aeb57f3f8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h index 09b6b370e40f99cd8ecd994b6dec398635ed24cc..b51101c59d45ee7ac51ccc477beaa7930dced128 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h index b762e56338fedd9f7ba88634d47abc2ec2971d56..2679f3ffb5781b442e12eed53bb3f34d3e04b142 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h index 1182c2d3eac21c584f13165a36b31a0ca8dda886..f5cb84345dd9fd2ecf21b450dd5f968c8ecfe3f5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h index 4db7d93414a25cb305382409208af5c7f7954fb0..9c4598f39ce2cc678ccb1edabe01ea85a43ff669 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h index 25a0837a29a43fa7912a040ef36b55f9c734726c..98dd525fa2799b1d21709c364d1e298d5b606a42 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h index edc5ddbdff6d100fb0360dba2f6c8ac245787b23..ba6718b330bd6a76f86cb407ec67f758ad35e7ee 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h index 2d65ca89fa2edd2a4f3f1145b033d7897e2e731c..04d18a9bb1195b258a2dcc81853ebe7c1e236199 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h index 3d47555b625ef8799ec26f84065454f2d8633a2b..7d1b00956c1e10a2bb3eb4fd090c701c31d48c2a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h index 6eb76a064b7cb4a5a0edff84da23d3acf054c54c..98dd1054e6d74e75638d948475bae6cd7c691f82 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h index 86fe3e44adaefb3c0958036afa26eb51b63b6f99..89d67802dc43090d5e9e0a8994653c04fa3ca6e6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h index aed36fb9b95150bfbfdba5878382df36addb84ab..770802c995a636bcfdaf5845b906ab9d40a0720d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h index 5ee2c704c1c637390df9dedbf47dcca2e5587e96..378b883ef5c7fd49f9f8f985d5784d42951dc359 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h index 16814ff01c11aa29595b1f84fb808684f1b87f69..2e594127b3263909b11a74e2c49b163cbeb62e10 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h index de10bddeffcb6cbcb4b86e7aed2c642e800b82f2..5c23587d970d5e3b2c4904f2f51346e9bcb70462 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h index e0f5276e554bd53df96ff7cf8cbf32b5eaf97115..93d49ec224b620db62744ea7dd2c63265dd33b2e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h index 2150b86668e47fdf587bbd89f7e42780322575e5..8943d754377fdfa059f5a866be64013c8f7d8035 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h index 5bed137f194878276acb2796621f41ceb3569736..6d88a15b8729d0a99bd5d6edb403e5e6e82c55a1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h index a8f1d4e17bc8554427238fbe549ae94d3cb75ad5..cc889843f6ad9c8b0a89030e364627bef7b95cd6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h index 840cff09ff6799ef90db47cd470ad14e00d2bdce..39b727cd441bc825a8153a8d77f8ddec28d0e5ec 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h index 10de0d31c5b47d05a5245991ede4c8a79eeffa52..560a5de9c1de3a7fd6344615d7c4f5454606a141 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h index 9a5a8cc72913ee3703160809084114011709952e..dd3c3e01bea8f17be788fa7436386d26aa328436 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h index 84734ee8880393d0ac16f8c52c501cdd73a0356e..dee4573635f70113902e8a7ca82202c4ab21beb0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h index 2d29ac5439a2d9474e1d3276b8d97c3ea95e01c3..b7222fa5721ee28c222283ff997411fb848bde1a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h index 1543f6174682e6d826bb0b011c0b60b48e23c66a..4552f4786ac551b4eb1bd4ade2523cf6dadd1b29 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h index 0910cf5a0f4d6ce8507a39452361b4dedfe5ccc1..17d87897d9b21614ad9f21a5bf9695802f9bd214 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h index bad678e85a075bef63d40db00432af04eaa8733e..c66c9aab0abfdbb06e537a110ae46e00b0654c5f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h index f9230957ec5bd981280b43a60cf8a584c5fb28fb..76d2be20f05d712d9447d223eed3c88ee5869e39 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h index 5bfd9248bf07beed7bba23a2299b36f6d10507fe..58e9d0de0fd9cb3928bace1c399b688bee4ae86b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h index 56152f6b9580ed12d1d917d0cfe7af6322c5b191..8186e0ce83a9ee597044afbfee87ba4df5168344 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h index c4fcfe518a357856a4d1b5f49f8580d78fe0d36d..febd3330621f0a7e8c66f0b962e3b6c8e178ae77 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h index e0132f6a20d7cc91a0578a5b7af6c3ecb020bf0f..c1d8d691e0a9ce5d4a711148b82ff5d84103e4df 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h index 4f6243982545cf348467a3655b2b204756f019a4..86cff070bd9404fef21196e0c28b9cdf21aecd79 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h index 36b07846c4f44f3da251ab704f655d663ccba719..606614230ef4753cccf26d7c6fb19637c4a9f311 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h index dee8f4183201b421d7d3dc69cb04562817abe907..c2c592f529984fd12edddf627b1893001cb8c0e3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h index 875cd26ab568be5610e94ac77f4007c7ed69c077..78f6b6cb158f46823fb2cebe5a2fb31ecb3eabd9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h index f6284fcb418ebba697ef97bff2799d5f05ecfd9a..2f6da6e35147e7f016ef781a492fb3b8a5cd4fc2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h index aa48a20d24facb7cafd4c79addc0a8225cfa3e30..141f346041e96e2ba438ebb06c3f0c2504010aea 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h index eaebc7bdde3ca08019976f7a104c86482472148a..5c7504db98174aa066e4a2660ce3694d0965adb4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h index 4645c1f0b73e7f1f31358fc9b578834177c1c930..d88cf1d3f844f8a976b9753947b5ada045201b1e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h index 412b0eb5df5122fd3af04fdc2a1b5662c8cca933..a59ec5ffcc629d7c7cd76fe1be5469596c034270 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h index cd2b7d33260d8fe1bf528b52624460d0ff6cd240..c4096571474a0e193fe9db8cd544f82ead55e423 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h index ebbdf65df5c1174e5c81351ff1299f4d5ea7fad2..ace3ccc5b6ed11664a6044a496cca363f11413a5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h index a0e8706499f60a0a34f2cac7710d2d9fbaf87efe..b5f2c2619d20bd5c285f0434a58030da12b8d7dd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h index dd636eb85e9ae8f7fd80afae2ed0095f68b12a5b..50022793fd00f02620c95b781604e169e2ff1eb0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h index dc8ffbed94d3be691f94cf2e0162c46ef3b6f653..c5d123a271ff56aa80668ca5ad8cdd13027068bc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h index 9e1d6a003db9930a9f50033d2aa875c1b40d3812..560cfb09d3ac4374e17cdd7ff166ed445ad11fad 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h index 9862dde2848135abb6bccfa8778232b91cc8f11f..8a3a92748e32e8ec5aeeaa43c46d5b04d9dbef60 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h index a863368b7fd901f0e488785b93a45f17ebcd6a0f..a2d0c14c4fba3c3382ef8dffda84390fa0fb3255 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h index 349a4118fcc49197cb21e3cd6e858e9b9148b17f..e88cf802c8e31481913540ea8cdec7f18b576900 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h index 72e31152ff0cff9cc4c32e83f35f93bd52d1edf2..33af5ec430de197073659a0fe590d309be3db0c0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h index 1c2eaf474d2092102483b34f38f29fb26d119464..71d6292e19c4bb634d94e79befc53bd3e04b5075 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h index 13981795c60949aebfe9f8e4bf32f4e980ef4a5c..482d59f846300954417088f61ea8b7aa3edd7b3c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h index 70384afd5525242baad6c41e9fd68f7fa8cb8794..64376c7053709639e60b7ed0a8192ef1faf229f9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h index 480abcc710a9d71df38bde9ee8465763bf385839..26b4d6f8666e8ac1a9893198af8670342d3c9dcc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h index 9f32f5601e007d263c7c5a44676535b535548757..24db2c037c05c36c8715ba7b029efe793a85e180 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h index b450839121b46e6bb82fda3e4ffee37885478b52..a3bc1d0c81d2cf47e1127b6e51add497e5a16232 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h index 1972a222dee8a56e9244360b2b2f261c9280d3a5..b958b659857a25dbfe498b3776f45e7e1c11c0dc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h index bc10c21cbf87e246e977f6a891c2a68714732952..811e5358ec6df5469e20d538924a9f257e7c92b4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h index 6402354cecdfb13d7af91754431f8554bdf61214..3c51879efd465da6d515d73dff34c1b0356582a4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h index 02e1bcefb8c01c52f22631633fa77154100b24fb..115d93d9e7c20bf7b5de44aef3d0fb55f800edac 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h index f89c6151123e308bc7f7cca308e3ed0b4fa872d5..27a72cc937265761b361325f5066a6da810f02f0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h index bda706428ca9d6b506a81c0c4c33d009a06544d4..1e028e546c6555199b7796f5d0236f95f998fed3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h index 746d23b4f502a5c5e470581947a882a46e94ec80..cadf0dbc7f3dd62fbc7039e7f5af6e78f183444f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h index e3949541c4cbdac684c85e0b0103af6b0725222c..03857b553831b7c007cd5b287770ce4c45b641da 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h index f6f36c40378dc46f8a548cbcf9212b638b3e3e44..38178fde1c96dfe9a1f597d72fc37cd133e4deac 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h index cc32cfb9a7c82f11b0c2608228432cf51ec704fe..726c2104cf0ed67420d96918f56ebd9432390e49 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h index c0022be7ae9d10e3389048936c3726f1a42ea34a..11a3d105aa29c14bedf6f4dcd265e22f1bfb5530 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h index 9282653a8aa223e699c5716fb9cc7f4a6b2fe57b..c63b77c8c8a0b780918d34297bf3df5396d88a26 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h index 1f3f307cce94322720fea0ce42d1d6cd46380763..a712edeb92d7f5175f28ed1906719e9aef496835 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h index e109b4ddcc6ff4d2f0218a2b0556ee6140c12c06..61d85aff4f32fc1b9bca57328b92ae4b008d2280 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h index 7feffe47867ead50332b403f0c8b24aab518d8b5..de9792152aa888ecacd78e61d1e0ee5b264b913f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h index 98e89939ac76422b28d4fda862edc45de07fa7bb..f29907fea2f5e5e568f6adbcf80b21d3a6b1a208 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h index 7170dec4aa22c616175151acf51c91d613b3522c..afed7116f8164aef68b30460611e024e36523a98 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h index 630cf5ec201e8ea01fc7ded29932e3aa9e3a5316..e0d693fcee4cc7e7a8373b21db3348aa5ec5040b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h index 1793f5617775fb3f0708d0eca212a5eb9b983d50..ba93b5fda0d5c7774cc7761db133913fd7a32c5d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h index 290e3ac88a190b92e61ae3e41556afe5c58f08b8..dbd19da5e3c20c0d024ebdd2bdd2f53b306a6f30 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h index 7ba1cdd36e5f0dbf25fe9fd352246e13ec9d52df..4f0feb51fd80f48f83352222057f570f4fc57a13 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h index 7559e96201323e84f41c37de40b9f83fd0afe9b0..62c162d5b00cea567de3f2553593295e62d4ab95 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h index 58c7a64b3e18bcd1893f47b821c01191363b1cf6..c38ff0ab701f7bc4f66336b8f972859caaf2bdba 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h index 8e4790942f3633c3dd7d1bc3b449986815330fda..69e6736dc6e1e7da2b3f45e1ffe6cc8de518d216 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h index e72b2eaa44ab12342416d3c974f677da3aa7189c..faa60839a880ad182aff278a41a28629c3143677 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h index 8b85fe6603b9e6301e24759038cea52216f485a4..3491c7bcb22600e7726a08fdf26e0ae407f71f7c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h index c02290c86e5bc39db4467654dbbfd98b5c470f78..fd6f20c7c20731f20380374bcaa9a63baba7cbdd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h index 189440e9130f9e529bcd49dcefdd121cf5ab2396..4dc7ecf0b3e1da969e7e0958d432dd0c0a77595e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h index 5e3f18dcaf89eaa83a0fbeb29508e4ade014a97f..b4fb418b5a89e1ebcb8d0946f533e231879bffac 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h index d180a40529f3d226a7b887a84bbdd02a04bf4906..2406c8abbc824314dfe4a320748917d4492ee452 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-clz.h b/test/a32/traces/simulator-cond-rd-rn-t32-clz.h index 2b63f2ddffb582f0a7c1378495d15f2fa6a3520a..0b22536a605e8606899dd7e6fed81abb43a5e22b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-clz.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h b/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h index 5fa87538890d694acb5478e30f34220e53743009..4d2d81635362336689bb4032535b5704ff08cb43 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rev.h b/test/a32/traces/simulator-cond-rd-rn-t32-rev.h index 1e76f8fa0a58f9660b72d4065164f187f239e525..9d13aee7659ce36181a732e5e727f789bc8dabe8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rev.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h b/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h index bf1e411a4e58eb0f4b228c1a344d4080d078bcd0..225e2ab7e99a771ecdb2b1f8e33f54190314a89a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h b/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h index b0b5bc0c613e2303015211ccb2c56349c1ee9783..79a6050ef2b4cf6a749562d160986be3c79ec1dd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h b/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h index 29f61c1bfc7ade3c4f27e2201ca9d0ac19efa56b..91ab272b4ecb44c8844bed977e98f1a9c4159ba1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h b/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h index 94438b807026ccee2eb21e123a7f063baae23c76..72a1bdf5838ab925e092e722d5db56ee2828cfd8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h index 9a8607d002dc7f2c5ae0968a7cbe466934a3beb0..dbbe47633db75f59a8d456647ea0e51ca9392111 100644 --- a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h index 660d3ece463cb0807fe2569c214fcfc594ea99ee..ab16e2a9947f92d83620d48a8f4f0294df2f0514 100644 --- a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h +++ b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h index b558f329d5ec27122421278ecf0a9b81572f112a..ae320b9444d27ec0a8a0b2ef269511015f72aa7a 100644 --- a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h +++ b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h index 1d3e166e27ac68c672dcabe816e1492e3f4b594c..1d759c609dc9acb1a7453f11fb30da9b67324e59 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h index dadc2b40f6c12bc77600ea666da7a555f181ed4b..5bbc6f79006a2081ee3789625c7fe22f7d9615b8 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h index 35ae6b2fd9d24662df1ec6e95a03eaf58e0cf69f..7e22f8248e455ce638e03b175937d9286bbf51d4 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h index 76948c2b3f04e2e3426dfde68c5f53b9485ab2e6..583f3533e9ba24efc7474c21f6373079fd40dd63 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h index 8addd9af4d5d036e1cb741c114511f400557d36e..60b5c254f0371f26acf994fd2d18f6ea08f2030e 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h index b1e32e3ebb968c4473b60b32632c657dd326d411..067aa5fc8ffef9d0ae4010c55046bc3bd729de3d 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h index 645beb3b4e1cddc852e87ef82fb3bdecb60d057d..fd2bc318ac77c1b39d0779dd15350d3cd3aa6a91 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h index a9054d6e9f332b235156437b4d4ca0f520378811..e7cc07f292fd8ee6d9f26ef2c626f41eb1504c11 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h index 9e91f17a5193b6fefadb4d6030991f7f8cc6a483..218833786b08159f30f7930bde7a88b1a0f83989 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h index c215a544440d5007b6599313fcef3a16f77e86df..bcca24a19a9ceb6b2d5a0306c39658600e139a6b 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h index 2e5f520f7da74fed1e7253d6a0031a2f7f667a33..e97e9d8e4dd209a3af12b073bd3e3a72da220b16 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h index 565a99ff7e8db3d1d2f4f38e207c963c50cdc487..da87ca097e934cf8875dc59181a2e1ca04445fae 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h index aa1fbc3f3c7f7bef0009430594c1ca12a164583e..c0c74f5602933b6e67b6c811583f56eaf6ba20ff 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h index 947e2887cc73cd2599a1432a3afb7a3d764f70ee..6f8f5f8e0fccf63cf0e97e2602d5b85e72ece8ad 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h index 7f9d69bff17af90e47f00a79dd3343b470429772..c7e49e89dffc728f861048063718d32c3bb3e9d6 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h index 53b5c0f5fb5d2f9785c4024d75beceefa377fbb8..a873f0303cdf9c202ed49d90d80d798b0bd580fa 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h index f7fe6e3bbd7c2a074b076c0c9b58b130ea261a70..690301857bd075a78af606467f52cf9b69a4605e 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h index b7482f1aa6331c3403928f3366f497b14478663d..ddff36af5bcf0eb0f7b355c76c3d94e36efc8891 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h index 2f7ebbaf6cf09f467de4d4e1c46317d4e64df09c..88311021df81b37c3d24fd4131e086b97fc7f8f4 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h index ea64a1dff4faaf58762dd37c22b74e7837af94a0..f843553185bb828c83c7b7369846d3c2cf1bd436 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/examples/test-examples.cc b/test/a64/examples/test-examples.cc index 69b067819957271eacaf339896d7e758458470aa..0be103143030eaab045abf907fe252893b501652 100644 --- a/test/a64/examples/test-examples.cc +++ b/test/a64/examples/test-examples.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-assembler-a64.cc b/test/a64/test-assembler-a64.cc index 2925c6dac8f709ad0bbffd65e8218e27b14b99c7..0ea99d9e3c27eab2b6cf7152a4c3de8b4f057c2f 100644 --- a/test/a64/test-assembler-a64.cc +++ b/test/a64/test-assembler-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-disasm-a64.cc b/test/a64/test-disasm-a64.cc index 87905405fc2ba20283657ae317ffad4db9c44903..5eae18f7f627141bf37095e8f9125acb7e1cf894 100644 --- a/test/a64/test-disasm-a64.cc +++ b/test/a64/test-disasm-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-fuzz-a64.cc b/test/a64/test-fuzz-a64.cc index f876fa80766ac786c9e57a6ff437a6f2fb838c46..2008314c119677118b901f9d8b67aa344d2b0f39 100644 --- a/test/a64/test-fuzz-a64.cc +++ b/test/a64/test-fuzz-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-simulator-a64.cc b/test/a64/test-simulator-a64.cc index 718228870d8dc83294135e74d59761042ec528d4..2167a882776894df328adae2ee12be18808158f7 100644 --- a/test/a64/test-simulator-a64.cc +++ b/test/a64/test-simulator-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-simulator-inputs-a64.h b/test/a64/test-simulator-inputs-a64.h index fd169994b5378786765028ae64141cc96d9f669f..50d37a51e0eb7a2b96b14d61341d6324dfe18f16 100644 --- a/test/a64/test-simulator-inputs-a64.h +++ b/test/a64/test-simulator-inputs-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-simulator-traces-a64.h b/test/a64/test-simulator-traces-a64.h index 61c472ba154ab673ba4971c4fbbedd52229952d5..f46ded9528acc5db185e2dbd60231e0495392eb3 100644 --- a/test/a64/test-simulator-traces-a64.h +++ b/test/a64/test-simulator-traces-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-trace-a64.cc b/test/a64/test-trace-a64.cc index 8932fcb1de1446a4535ad7c9e3f8e87af6869ed8..a0599a72a43525ed57de21fb08e2cb6a128ed2b1 100644 --- a/test/a64/test-trace-a64.cc +++ b/test/a64/test-trace-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-utils-a64.cc b/test/a64/test-utils-a64.cc index ae3220d925346e6b43b34248388d00e0b038446d..289530239f96b4957634bbf94e7766c19684e382 100644 --- a/test/a64/test-utils-a64.cc +++ b/test/a64/test-utils-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-utils-a64.h b/test/a64/test-utils-a64.h index 7151e34c289b3a15a42e6e3759198fdb301b5fd6..8c691c5d3480d39ae4da16d8e81e9e8971b5ade6 100644 --- a/test/a64/test-utils-a64.h +++ b/test/a64/test-utils-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-16b-trace-a64.h b/test/a64/traces/sim-abs-16b-trace-a64.h index 13f1e53fb2f8f30231becf7de19dbb00ed3b5cc6..2fd2e99897ff8c47d10f94bb1a476fd13c0654da 100644 --- a/test/a64/traces/sim-abs-16b-trace-a64.h +++ b/test/a64/traces/sim-abs-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-2d-trace-a64.h b/test/a64/traces/sim-abs-2d-trace-a64.h index d57992f196c6f43562a00449af3705e96157bc81..566aec59b06183258b9729d3a938cad4045efdb2 100644 --- a/test/a64/traces/sim-abs-2d-trace-a64.h +++ b/test/a64/traces/sim-abs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-2s-trace-a64.h b/test/a64/traces/sim-abs-2s-trace-a64.h index 7fdc95e087666665fdc789794fa0f7655886cbc0..f679cf765d2b5914e9ff432898157fee1db6449c 100644 --- a/test/a64/traces/sim-abs-2s-trace-a64.h +++ b/test/a64/traces/sim-abs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-4h-trace-a64.h b/test/a64/traces/sim-abs-4h-trace-a64.h index d556a111021b09d3186d3a86fae399533a31c89d..3a2686629086a85561b1ce5c1fdd9c5c4c1afd0d 100644 --- a/test/a64/traces/sim-abs-4h-trace-a64.h +++ b/test/a64/traces/sim-abs-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-4s-trace-a64.h b/test/a64/traces/sim-abs-4s-trace-a64.h index 78048f83bb54c8c9d8df2eca03594041ad17f5ac..84b237a1943494135f8055d998aec6468d10ef7d 100644 --- a/test/a64/traces/sim-abs-4s-trace-a64.h +++ b/test/a64/traces/sim-abs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-8b-trace-a64.h b/test/a64/traces/sim-abs-8b-trace-a64.h index 4418df681af81bd76794516485c52ffdcc535b2b..16e5640527cb5cbe3b124ef5d7eb5dbfd9e08892 100644 --- a/test/a64/traces/sim-abs-8b-trace-a64.h +++ b/test/a64/traces/sim-abs-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-8h-trace-a64.h b/test/a64/traces/sim-abs-8h-trace-a64.h index 25b35c4ce6f2fc21b839f80312b0615084b1aa49..4671940537d27a99bad9d2ced1c0e9ff55713e63 100644 --- a/test/a64/traces/sim-abs-8h-trace-a64.h +++ b/test/a64/traces/sim-abs-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-d-trace-a64.h b/test/a64/traces/sim-abs-d-trace-a64.h index 28568922d648d5476dcbf5aa1f61f7cd834cf776..fea73c10de31127ac925137fcc00c1c1761a114e 100644 --- a/test/a64/traces/sim-abs-d-trace-a64.h +++ b/test/a64/traces/sim-abs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-16b-trace-a64.h b/test/a64/traces/sim-add-16b-trace-a64.h index 6fb0fff7c14590ca8ffe5b389dcd16e4c5fa649d..03fadc77e9cfd7652b7708b3a14a24ee7770e9c8 100644 --- a/test/a64/traces/sim-add-16b-trace-a64.h +++ b/test/a64/traces/sim-add-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-2d-trace-a64.h b/test/a64/traces/sim-add-2d-trace-a64.h index f1e9cdcb08ad753916c4d78cfdd60fd1b763129b..1d7962e09a8f6eb0b1cc5777dcdfda1facfabb09 100644 --- a/test/a64/traces/sim-add-2d-trace-a64.h +++ b/test/a64/traces/sim-add-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-2s-trace-a64.h b/test/a64/traces/sim-add-2s-trace-a64.h index d69a4686494cbefab689d0fcf3fc7d240f5d492c..64234fb740d5154e89b8f8ba411f488baecc3f77 100644 --- a/test/a64/traces/sim-add-2s-trace-a64.h +++ b/test/a64/traces/sim-add-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-4h-trace-a64.h b/test/a64/traces/sim-add-4h-trace-a64.h index ce69d680bee499b3a4473608dd2cb7c8f29f983e..76c2d299cf518c1f10880bb9f63d10f1314c2d4a 100644 --- a/test/a64/traces/sim-add-4h-trace-a64.h +++ b/test/a64/traces/sim-add-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-4s-trace-a64.h b/test/a64/traces/sim-add-4s-trace-a64.h index 693aa412363b0591f77e9a0766300e5367992cad..702243f6ef9b4ad7ecd24e048f741bd3aee55372 100644 --- a/test/a64/traces/sim-add-4s-trace-a64.h +++ b/test/a64/traces/sim-add-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-8b-trace-a64.h b/test/a64/traces/sim-add-8b-trace-a64.h index b356c88663b6c873979be5772603e9bfcab9e3c0..2bf45ea6d91b0cacaded4ec374780e209b2e014d 100644 --- a/test/a64/traces/sim-add-8b-trace-a64.h +++ b/test/a64/traces/sim-add-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-8h-trace-a64.h b/test/a64/traces/sim-add-8h-trace-a64.h index 423008beafecec59a944c3d9dd526d3dbf138b4a..21e2d063ebe778286cb27e8be197382a638596f3 100644 --- a/test/a64/traces/sim-add-8h-trace-a64.h +++ b/test/a64/traces/sim-add-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-d-trace-a64.h b/test/a64/traces/sim-add-d-trace-a64.h index 33dd37cf886dacaf2e5f99f0dc90c568104e809c..5374424c59123a1f4bf58982828d572fcd769d97 100644 --- a/test/a64/traces/sim-add-d-trace-a64.h +++ b/test/a64/traces/sim-add-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn-2s-trace-a64.h b/test/a64/traces/sim-addhn-2s-trace-a64.h index 670a8abd558f76d9fcc5084fdc9b4e28a222aa8e..a265a020475240e0a4f0ff41d8902f195818f764 100644 --- a/test/a64/traces/sim-addhn-2s-trace-a64.h +++ b/test/a64/traces/sim-addhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn-4h-trace-a64.h b/test/a64/traces/sim-addhn-4h-trace-a64.h index 11ca8eb653eaa89be9cc25aada20611aec2ea637..8960d1599478c9a53cb48789fa55b92b21442cbf 100644 --- a/test/a64/traces/sim-addhn-4h-trace-a64.h +++ b/test/a64/traces/sim-addhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn-8b-trace-a64.h b/test/a64/traces/sim-addhn-8b-trace-a64.h index b151c2cf8234a6332d746f7e92765d20a66e5e21..da6dadbd7d45948ccf8db72f10bfe7bded43bcab 100644 --- a/test/a64/traces/sim-addhn-8b-trace-a64.h +++ b/test/a64/traces/sim-addhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn2-16b-trace-a64.h b/test/a64/traces/sim-addhn2-16b-trace-a64.h index bd48236a8ed2dac1e1410eb08729d199faf83144..336c99ec195c7dedc7643467870837dd9dcf64e2 100644 --- a/test/a64/traces/sim-addhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-addhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn2-4s-trace-a64.h b/test/a64/traces/sim-addhn2-4s-trace-a64.h index 255dfb91a7341afbd5fdacbe768b169325a773f6..03f17b6f29e63806132904e9f5aec97808038a90 100644 --- a/test/a64/traces/sim-addhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-addhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn2-8h-trace-a64.h b/test/a64/traces/sim-addhn2-8h-trace-a64.h index 4888d3b2cc89638b481acac4deaf0104bf8179e3..baabc1b9efa2b85276d40d7e559c1526eb36c42e 100644 --- a/test/a64/traces/sim-addhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-addhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-16b-trace-a64.h b/test/a64/traces/sim-addp-16b-trace-a64.h index d03015079bec43cb994a0a5ed15d9c19ee6b673d..5667c632f93b466d0a3a9ddcc3c0df69c55844dd 100644 --- a/test/a64/traces/sim-addp-16b-trace-a64.h +++ b/test/a64/traces/sim-addp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-2d-trace-a64.h b/test/a64/traces/sim-addp-2d-trace-a64.h index 663117d36362b72229134a85b6b9beb0c085f92b..d829ffa3768760f16eb79170d690d3678e2aad3e 100644 --- a/test/a64/traces/sim-addp-2d-trace-a64.h +++ b/test/a64/traces/sim-addp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-2s-trace-a64.h b/test/a64/traces/sim-addp-2s-trace-a64.h index 16dc9974dd096fc1fafe9574ff07d47852845e6a..ca1a5bbc5268b2f82f6a48e9c4e4c8932efe587a 100644 --- a/test/a64/traces/sim-addp-2s-trace-a64.h +++ b/test/a64/traces/sim-addp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-4h-trace-a64.h b/test/a64/traces/sim-addp-4h-trace-a64.h index 7ed86535e9221d3ca93c7ff95501e7e87c2fa5eb..ce86cbe06bb896a5441c12e47ae40bc8b5d76dd1 100644 --- a/test/a64/traces/sim-addp-4h-trace-a64.h +++ b/test/a64/traces/sim-addp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-4s-trace-a64.h b/test/a64/traces/sim-addp-4s-trace-a64.h index e4b1a21fedc9b523af8da276383c74f997893f0b..1d964f8e306cfd9195be73f33e7a2812a69f55e2 100644 --- a/test/a64/traces/sim-addp-4s-trace-a64.h +++ b/test/a64/traces/sim-addp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-8b-trace-a64.h b/test/a64/traces/sim-addp-8b-trace-a64.h index 23f7d2d8f6e9139afbcf6fe9940405dc7845a1dd..6100308879a94845da0a8e94a844a3b9ebc6f9ab 100644 --- a/test/a64/traces/sim-addp-8b-trace-a64.h +++ b/test/a64/traces/sim-addp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-8h-trace-a64.h b/test/a64/traces/sim-addp-8h-trace-a64.h index cd26d6ab1e0724d12270cbbf188bc1ee3d2c8713..2542f5cb4333117c8dc5764e2ca98fb59d5f78c2 100644 --- a/test/a64/traces/sim-addp-8h-trace-a64.h +++ b/test/a64/traces/sim-addp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-scalar-trace-a64.h b/test/a64/traces/sim-addp-scalar-trace-a64.h index 1c46724779491cd2b0cc93399a06eeed6e9c50f0..1e603ebfe9dd3fe64e0fe665e87ac2dfc5334d7a 100644 --- a/test/a64/traces/sim-addp-scalar-trace-a64.h +++ b/test/a64/traces/sim-addp-scalar-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-b-16b-trace-a64.h b/test/a64/traces/sim-addv-b-16b-trace-a64.h index ccba92b98e2b3f06b18f2b1ba00155e5f0531bb2..04a5bd54d80f4ceb1b7e1f4807424ffe0c779bb7 100644 --- a/test/a64/traces/sim-addv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-addv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-b-8b-trace-a64.h b/test/a64/traces/sim-addv-b-8b-trace-a64.h index 7de4d049101b495157cea5a50bc554a8db854b0b..663640064abfe6f1267b4a361b88230469499e34 100644 --- a/test/a64/traces/sim-addv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-addv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-h-4h-trace-a64.h b/test/a64/traces/sim-addv-h-4h-trace-a64.h index da917200c54ad50ad54e21a898754645115543e6..a7f3ecbaa361636cb4faca4bbff06669b96dfe75 100644 --- a/test/a64/traces/sim-addv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-addv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-h-8h-trace-a64.h b/test/a64/traces/sim-addv-h-8h-trace-a64.h index 212aeb7ebaabedb706ecc1b606bb4f801f07d1a5..0f1974474d4031bbd8d147e395211fc604f4f775 100644 --- a/test/a64/traces/sim-addv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-addv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-s-4s-trace-a64.h b/test/a64/traces/sim-addv-s-4s-trace-a64.h index 7ec6d9e549fe4b11446e991f73e4d0e64f99f5d5..48821a77f0d0e63ac603f37fc910a5e345085eff 100644 --- a/test/a64/traces/sim-addv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-addv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-and--16b-trace-a64.h b/test/a64/traces/sim-and--16b-trace-a64.h index 7ba8f98b5faa82fd39e55eb7bd2b5d5a77fde18d..39fedd291ed5f960dfa73fdbbe85b9a5d2fc8ff5 100644 --- a/test/a64/traces/sim-and--16b-trace-a64.h +++ b/test/a64/traces/sim-and--16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-and--8b-trace-a64.h b/test/a64/traces/sim-and--8b-trace-a64.h index 33a6fd41e9f9bf84e7b00e838b7b9680290cc6a1..4618ea64938ea745ac1ebaef84eca44280739bcf 100644 --- a/test/a64/traces/sim-and--8b-trace-a64.h +++ b/test/a64/traces/sim-and--8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bic-16b-trace-a64.h b/test/a64/traces/sim-bic-16b-trace-a64.h index 9812bdce8293b95d4ea2bdc500d289e890056485..e0c7707e68b224ec6fcd02b555adc1bd4a8ce339 100644 --- a/test/a64/traces/sim-bic-16b-trace-a64.h +++ b/test/a64/traces/sim-bic-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bic-8b-trace-a64.h b/test/a64/traces/sim-bic-8b-trace-a64.h index fbb4532d53f4956dd7dd8405a4b94293a06418f6..47296e17a1c4c15aa18f048c54031f689a3c0a52 100644 --- a/test/a64/traces/sim-bic-8b-trace-a64.h +++ b/test/a64/traces/sim-bic-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bif-16b-trace-a64.h b/test/a64/traces/sim-bif-16b-trace-a64.h index a7f29339cd7abdca926f34d57048e1ddd7cde087..126b0b977e422523e35d098ca35ddfea840ed9e7 100644 --- a/test/a64/traces/sim-bif-16b-trace-a64.h +++ b/test/a64/traces/sim-bif-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bif-8b-trace-a64.h b/test/a64/traces/sim-bif-8b-trace-a64.h index fca8039f900bc28e97175baa00268b3b116a200e..6968abbe559501fca4c8ae176291d16907332824 100644 --- a/test/a64/traces/sim-bif-8b-trace-a64.h +++ b/test/a64/traces/sim-bif-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bit-16b-trace-a64.h b/test/a64/traces/sim-bit-16b-trace-a64.h index 866a30336ff51509d5c3f83d7f27d1d8671c6509..48ed73f37b54b2b713feb2a6274bbd26b2e0dfd7 100644 --- a/test/a64/traces/sim-bit-16b-trace-a64.h +++ b/test/a64/traces/sim-bit-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bit-8b-trace-a64.h b/test/a64/traces/sim-bit-8b-trace-a64.h index ed0786f69453417dc41b93f47f826297fa10b699..613c29e5f3c58d899c9227cd481cc785c4188b22 100644 --- a/test/a64/traces/sim-bit-8b-trace-a64.h +++ b/test/a64/traces/sim-bit-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bsl-16b-trace-a64.h b/test/a64/traces/sim-bsl-16b-trace-a64.h index e84b41924d435927427f14bd24f7146e4c2a50db..ee3d21c21374990e76ec89eb21959c6ea4903500 100644 --- a/test/a64/traces/sim-bsl-16b-trace-a64.h +++ b/test/a64/traces/sim-bsl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bsl-8b-trace-a64.h b/test/a64/traces/sim-bsl-8b-trace-a64.h index 5a48051266975d7c59d248db11d711d9aba00f1a..dc629553ec3fbd7efac745517003a254ce076e03 100644 --- a/test/a64/traces/sim-bsl-8b-trace-a64.h +++ b/test/a64/traces/sim-bsl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-16b-trace-a64.h b/test/a64/traces/sim-cls-16b-trace-a64.h index cab71ef109eea83f341d8546d1eaac4d49f587d2..3299d5744b875f2d49d3cc873b153a761e8f3bb1 100644 --- a/test/a64/traces/sim-cls-16b-trace-a64.h +++ b/test/a64/traces/sim-cls-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-2s-trace-a64.h b/test/a64/traces/sim-cls-2s-trace-a64.h index f4d211ebad4c1fef7420aa72ad30cd0946be5708..24420147e0b42690024030e142a73dc6f43cef3a 100644 --- a/test/a64/traces/sim-cls-2s-trace-a64.h +++ b/test/a64/traces/sim-cls-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-4h-trace-a64.h b/test/a64/traces/sim-cls-4h-trace-a64.h index f5f24bbf4ea92a017e605474d03557fce6e793c2..843c07ad119c42d5fc8486a483b10cb87f6e73a4 100644 --- a/test/a64/traces/sim-cls-4h-trace-a64.h +++ b/test/a64/traces/sim-cls-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-4s-trace-a64.h b/test/a64/traces/sim-cls-4s-trace-a64.h index 28b9b053d6d0362fc4ed6fe7fea69d95a2444e90..c2a5c2ae179a14cd7da5450377c9234a74a7c8c9 100644 --- a/test/a64/traces/sim-cls-4s-trace-a64.h +++ b/test/a64/traces/sim-cls-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-8b-trace-a64.h b/test/a64/traces/sim-cls-8b-trace-a64.h index 0ff967e955565abdd4366c214fae6f17a888c2fd..edec1c071fbf7dc05701050a779d3c61fbc8b96c 100644 --- a/test/a64/traces/sim-cls-8b-trace-a64.h +++ b/test/a64/traces/sim-cls-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-8h-trace-a64.h b/test/a64/traces/sim-cls-8h-trace-a64.h index c7166f761aa800e1395e7932df5a1d8e5bd26a03..ee6cb5d6a23dc9d37752e3b925944f6b6e1e002b 100644 --- a/test/a64/traces/sim-cls-8h-trace-a64.h +++ b/test/a64/traces/sim-cls-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-16b-trace-a64.h b/test/a64/traces/sim-clz-16b-trace-a64.h index 340a7006a7c3e06b5c17e850d3fbc7ce63883fd9..5da1c4ec7e09c1fe6edc082e19ccc19da442ae18 100644 --- a/test/a64/traces/sim-clz-16b-trace-a64.h +++ b/test/a64/traces/sim-clz-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-2s-trace-a64.h b/test/a64/traces/sim-clz-2s-trace-a64.h index 0b0e579b8c4332fd860de31977643849fb1835db..14ac3620e2719e17679fe4afd52a61beddb48076 100644 --- a/test/a64/traces/sim-clz-2s-trace-a64.h +++ b/test/a64/traces/sim-clz-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-4h-trace-a64.h b/test/a64/traces/sim-clz-4h-trace-a64.h index 1dcd82416811d71b680fbcf45ff458812120c52a..a822a5cf06fd8da41d314009bbc4e818267932a4 100644 --- a/test/a64/traces/sim-clz-4h-trace-a64.h +++ b/test/a64/traces/sim-clz-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-4s-trace-a64.h b/test/a64/traces/sim-clz-4s-trace-a64.h index 657578f6378f04071f22e166398940e4cfd446c4..b093216cd965ab5c8a6d6e9022015bdacf8f8b11 100644 --- a/test/a64/traces/sim-clz-4s-trace-a64.h +++ b/test/a64/traces/sim-clz-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-8b-trace-a64.h b/test/a64/traces/sim-clz-8b-trace-a64.h index 49a588cef495ada66e05a47bcdc33638572e3bf8..173453434548f817e31e9a317f22596b3f23a233 100644 --- a/test/a64/traces/sim-clz-8b-trace-a64.h +++ b/test/a64/traces/sim-clz-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-8h-trace-a64.h b/test/a64/traces/sim-clz-8h-trace-a64.h index 0e0a3bc5275b04ce1d3ef235b6a887b2eda58a17..1c6b06923652b41c38915384cddab38615f298df 100644 --- a/test/a64/traces/sim-clz-8h-trace-a64.h +++ b/test/a64/traces/sim-clz-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h index 2afe556da7028f2c6cb68b70a9600477d9e04d8d..ad845e3c16b938e8d72e711c90611fe5d7c0af35 100644 --- a/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-16b-trace-a64.h b/test/a64/traces/sim-cmeq-16b-trace-a64.h index dd467d2c162e5b39716d1bb2acad4d76d457eeac..8d6f248b1b1b14045417f3aa1556e4a2976d3676 100644 --- a/test/a64/traces/sim-cmeq-16b-trace-a64.h +++ b/test/a64/traces/sim-cmeq-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h index 32d1e2231352e08fc0d4468c3c6a10efb49c46b7..55dd38b5721cb0604499a147df9fdb38848fcff3 100644 --- a/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2d-trace-a64.h b/test/a64/traces/sim-cmeq-2d-trace-a64.h index 5547377439a15dfb2a5e8f27d92f7f6bb0a309be..821d7c846628afe2ef370d1ecfa5514ead4d2d0f 100644 --- a/test/a64/traces/sim-cmeq-2d-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h index a8028c078930e191a3fe5d745e157a7dcc305158..61a9c3217bd1fe011a81060acf25fb23b5b3d734 100644 --- a/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2s-trace-a64.h b/test/a64/traces/sim-cmeq-2s-trace-a64.h index 592da285b64373351c23054aad4801575b79fb38..b2723aa77831b3c2ee18f81d27ef5ae2448d79b1 100644 --- a/test/a64/traces/sim-cmeq-2s-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h index cc7916a3b1bcfa98bb8d9fe353282106fbae0129..0f84924ed0419c0048af44e14718d4b823808d44 100644 --- a/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4h-trace-a64.h b/test/a64/traces/sim-cmeq-4h-trace-a64.h index af6deac71b9d24fca1d1a1c2173a09a4decf1dfb..1f2c4e230c6d86280ecd753bdc7e975fb550aa0e 100644 --- a/test/a64/traces/sim-cmeq-4h-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h index f887459bacd5bef37067e7e83b078580da462b58..153651a9a7ad9e72f213f9a52b43dca9dd55c1fe 100644 --- a/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4s-trace-a64.h b/test/a64/traces/sim-cmeq-4s-trace-a64.h index d51f22466bc4ef969cb31f55b19050d8c5f788f1..85b231c4eb67fbaf7e7cfe18141b9e6f61f2c7c8 100644 --- a/test/a64/traces/sim-cmeq-4s-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h index d5951a6c9cd793a44ca53aae5e4d9cc0a2172db5..44830280b44466891dc726e29bdadace8c77d9f2 100644 --- a/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8b-trace-a64.h b/test/a64/traces/sim-cmeq-8b-trace-a64.h index 5538541d06dc3f29630b9c6f2f09135db12c3da9..bc45fb723af0cd89deea388e1a4fff993f7d9410 100644 --- a/test/a64/traces/sim-cmeq-8b-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h index 19842c7a5b913d3e5f9bea39dbb483a9c0dfbd63..cf0557404c788df70cf46cee4ebee01c4ffdce68 100644 --- a/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8h-trace-a64.h b/test/a64/traces/sim-cmeq-8h-trace-a64.h index e4fa36f92db5473a627807febc74b868279c3fdb..fe623e1b17fc40a93d12c28eba6bd09c13266050 100644 --- a/test/a64/traces/sim-cmeq-8h-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h index 9fafe5ac18fda30f4bf58dbf7f165757361ce132..e97fab4416237d78688b96503bbffdfe8aa91ffe 100644 --- a/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-d-trace-a64.h b/test/a64/traces/sim-cmeq-d-trace-a64.h index 6eeb629debee93cb8bd9b3fdb6383007626d894f..f53b4c3986d3053f9eeabb7fef696ed42b340388 100644 --- a/test/a64/traces/sim-cmeq-d-trace-a64.h +++ b/test/a64/traces/sim-cmeq-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h index 9b43f03c602f373fc28baede9a0a08d6bea70174..3d216fd0fe9ccf8f73c3af918c31dbc464538901 100644 --- a/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-16b-trace-a64.h b/test/a64/traces/sim-cmge-16b-trace-a64.h index 6840b01e785d33f79f0c2e860894657b612578ad..63ebb3c9491e8329cc854ee17b3201b6c9d96342 100644 --- a/test/a64/traces/sim-cmge-16b-trace-a64.h +++ b/test/a64/traces/sim-cmge-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h index d6696da4b2e9d73111253a04807cf61cc5557829..892fce517427ebb15a52d40f28be9c0fb7c6047f 100644 --- a/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2d-trace-a64.h b/test/a64/traces/sim-cmge-2d-trace-a64.h index abe8bd59106656983838310d15d5a9c9e26ae6cb..55f145d480a7b258239151f0fe5d35d2e01297da 100644 --- a/test/a64/traces/sim-cmge-2d-trace-a64.h +++ b/test/a64/traces/sim-cmge-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h index f83256a5a8a3a1500b0e461f0841cebb6a99d58a..0371660d1e20d5a97c76a13c03edc2f9720d38e3 100644 --- a/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2s-trace-a64.h b/test/a64/traces/sim-cmge-2s-trace-a64.h index af7a90c4443a9b9756b18ace5d78f5982efb3e5e..71f377c9fc37fe40e1d02b4c1a37df916934bc91 100644 --- a/test/a64/traces/sim-cmge-2s-trace-a64.h +++ b/test/a64/traces/sim-cmge-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h index 00b0d1039c8e70a31ff4675e70604c6b9ba2d84d..7b4c5e37852c2ee702224e106b66d3b437ef17ab 100644 --- a/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4h-trace-a64.h b/test/a64/traces/sim-cmge-4h-trace-a64.h index bc9052083a32a64bf525f1705fb30be4e71ffb51..fa1bf52dbbf4e5436bea97d00c7ba272777e927a 100644 --- a/test/a64/traces/sim-cmge-4h-trace-a64.h +++ b/test/a64/traces/sim-cmge-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h index 2386f228441da5831e275431bc58bb0a2afe1077..0e82125ddc055802e6208b39b4d7c1f562226034 100644 --- a/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4s-trace-a64.h b/test/a64/traces/sim-cmge-4s-trace-a64.h index 58b99cc29fe6e8e6ab836ee8f334882d2a468dc5..fe0020abae76871c8ad5b577e2e4eac5054a7db9 100644 --- a/test/a64/traces/sim-cmge-4s-trace-a64.h +++ b/test/a64/traces/sim-cmge-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h index a20157ae4d3a6b4f8f2f8d13b191a515c3bcd479..881cb6cdc620e2d26c36b7c1c6f6019cb9f4603b 100644 --- a/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8b-trace-a64.h b/test/a64/traces/sim-cmge-8b-trace-a64.h index b80c26afbcfcc5505f4d676de6934448edc07479..65167f773346adf961fae8ab427011b8fe0d8d3c 100644 --- a/test/a64/traces/sim-cmge-8b-trace-a64.h +++ b/test/a64/traces/sim-cmge-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h index 68361b925141c977cae2023e9d04e27f93c8c736..8c3b8b24c1651bd7440c0ab7fb30e5c69f0bf3c9 100644 --- a/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8h-trace-a64.h b/test/a64/traces/sim-cmge-8h-trace-a64.h index 05f82a034fdf3795f597d9e11e138d9bd03833af..1ee4e1646511b8c51e58bd1f0eb35b775e836b2c 100644 --- a/test/a64/traces/sim-cmge-8h-trace-a64.h +++ b/test/a64/traces/sim-cmge-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h index b6b421df6fcbd5f4a0d0022aa0ae80f4da547906..7f666fe4030b1bb82f30771d4b0bebe8f4d84066 100644 --- a/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-d-trace-a64.h b/test/a64/traces/sim-cmge-d-trace-a64.h index 86eb68011d2c28f5b2ccec7729571f697b4e100c..8be6c2f051c90fb877d54fcdb597ed9b591ffcfb 100644 --- a/test/a64/traces/sim-cmge-d-trace-a64.h +++ b/test/a64/traces/sim-cmge-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h index 3ab1107f61ab79043664695df0d7b0b453cd00b1..f51c056183009668db73b9327dc583d57c084d84 100644 --- a/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-16b-trace-a64.h b/test/a64/traces/sim-cmgt-16b-trace-a64.h index c9bcf78d3c314e3837d02daa884a5bf454f38e39..143c3ffb86b5fc1b1fa75f6ad134b2abde67732f 100644 --- a/test/a64/traces/sim-cmgt-16b-trace-a64.h +++ b/test/a64/traces/sim-cmgt-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h index d4030397d2de7cd38d5f54f5a752acfc228b29c3..59e035af1a0be1678ae27378207e45e38b00ef37 100644 --- a/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2d-trace-a64.h b/test/a64/traces/sim-cmgt-2d-trace-a64.h index a33924b5afa259c7d63dfeb223b5ea951cb426f6..babe4a5f01710d5c212aee5eb792f098a0a9d6c6 100644 --- a/test/a64/traces/sim-cmgt-2d-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h index 79219a8a772a3e4e4b1bb4cc7adcdfa67bf6f46f..58d5509ac9315d2aa936a7f9df3d8d6cdcf74d21 100644 --- a/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2s-trace-a64.h b/test/a64/traces/sim-cmgt-2s-trace-a64.h index d6cab32c833d01a4b11bb23e613650472c17a2be..3fa27731a52e7b5aefbe2c7a07238d4a17e0e7f3 100644 --- a/test/a64/traces/sim-cmgt-2s-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h index 6ca0e1e7cbe4fb4af6bc4e420db9461ac08656ce..de1df0ff8e9e39c131b8255257f6d7c0c96c4fb7 100644 --- a/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4h-trace-a64.h b/test/a64/traces/sim-cmgt-4h-trace-a64.h index aaa0c9a3e5777abc4a2f2a296da72a640fcce317..9e6a858d9dc43c2aa9e1ec652a55f902216c2903 100644 --- a/test/a64/traces/sim-cmgt-4h-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h index e0022a12ce0434972e0804eabc9f104333b1a62e..a03688bf69ab6f21f43babac2ed2f2df30d5e5e3 100644 --- a/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4s-trace-a64.h b/test/a64/traces/sim-cmgt-4s-trace-a64.h index 377e66a4dd399b18af3fdee186c4056d287bbcf6..6462671d3f6546bc0acaffdc5c1f83a4fa11236c 100644 --- a/test/a64/traces/sim-cmgt-4s-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h index ea994d8d5aa12204adfe066cedf6c1a910639331..4221114de81c713016143ec18e9b937b24ff8d4e 100644 --- a/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8b-trace-a64.h b/test/a64/traces/sim-cmgt-8b-trace-a64.h index 437e4fe3b893379d8728bee3bacc3bac87ea8326..aef4abcba9ba2a7d717b091c9d48587c929c245a 100644 --- a/test/a64/traces/sim-cmgt-8b-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h index d2685f3e5687195a0e3010a8e9adfc28229d9872..98f886e666ee7403eaee39a8ae15f71ffc8e954b 100644 --- a/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8h-trace-a64.h b/test/a64/traces/sim-cmgt-8h-trace-a64.h index d705b7c1e123875eba8238c0a8390c590ce6ae85..0e9183e52ef63ae7566d5ea1e8c5fb1dd47670eb 100644 --- a/test/a64/traces/sim-cmgt-8h-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h index 6e4a23d4efbb79ca7c8eef275765eda98fa5a119..128244c3b50f4b213c8d997b9dd311af44f5a083 100644 --- a/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-d-trace-a64.h b/test/a64/traces/sim-cmgt-d-trace-a64.h index f40b2b353663b2a69fc733dba7a9471aa74daaf9..614d3ae1ad18674acafd2e28ea684e48049608bd 100644 --- a/test/a64/traces/sim-cmgt-d-trace-a64.h +++ b/test/a64/traces/sim-cmgt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-16b-trace-a64.h b/test/a64/traces/sim-cmhi-16b-trace-a64.h index 0342f5c9d85596deb8dd2f621a26c67f963e2d1a..9080633362739ba692399ee0d1ce315560435f69 100644 --- a/test/a64/traces/sim-cmhi-16b-trace-a64.h +++ b/test/a64/traces/sim-cmhi-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-2d-trace-a64.h b/test/a64/traces/sim-cmhi-2d-trace-a64.h index f5aa4d7e3c1f4738a870ea755fd64d155f90ca57..1f1d2dc771c536ff782261203884bcde4529d81b 100644 --- a/test/a64/traces/sim-cmhi-2d-trace-a64.h +++ b/test/a64/traces/sim-cmhi-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-2s-trace-a64.h b/test/a64/traces/sim-cmhi-2s-trace-a64.h index 3918bef6aafc26b8fed60f8d68f70de38e680aef..802d2803674c8f51f9c3455345da39bb1e223f70 100644 --- a/test/a64/traces/sim-cmhi-2s-trace-a64.h +++ b/test/a64/traces/sim-cmhi-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-4h-trace-a64.h b/test/a64/traces/sim-cmhi-4h-trace-a64.h index 8acbba444a580ac133e8958f0712822b7abb4d85..3b5b2b6a591b3b0cd9c735d56f4e83e21239ca6a 100644 --- a/test/a64/traces/sim-cmhi-4h-trace-a64.h +++ b/test/a64/traces/sim-cmhi-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-4s-trace-a64.h b/test/a64/traces/sim-cmhi-4s-trace-a64.h index 2578aa395e54777af842306301a8a7178c064b11..b689e07667d075731a55e2bcc69fe37a766eb636 100644 --- a/test/a64/traces/sim-cmhi-4s-trace-a64.h +++ b/test/a64/traces/sim-cmhi-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-8b-trace-a64.h b/test/a64/traces/sim-cmhi-8b-trace-a64.h index 3579653a54b633130af97423a3be578f4464c08d..31d823cbac61b8d6a0ea58534f9cfc24066dce3d 100644 --- a/test/a64/traces/sim-cmhi-8b-trace-a64.h +++ b/test/a64/traces/sim-cmhi-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-8h-trace-a64.h b/test/a64/traces/sim-cmhi-8h-trace-a64.h index b24144ef1b1420cd38db090f11e636e892c3a389..8af9f2b707202a09f416641b1f0470a6a31cdd64 100644 --- a/test/a64/traces/sim-cmhi-8h-trace-a64.h +++ b/test/a64/traces/sim-cmhi-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-d-trace-a64.h b/test/a64/traces/sim-cmhi-d-trace-a64.h index 5de94266170ff3855975312d6ba7a3482401a090..3827ef202e11696fffe6573e5632f719b2ba8569 100644 --- a/test/a64/traces/sim-cmhi-d-trace-a64.h +++ b/test/a64/traces/sim-cmhi-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-16b-trace-a64.h b/test/a64/traces/sim-cmhs-16b-trace-a64.h index a12a424f8429042b4572ffe0b540f3e6440ba47f..fe092028b76f155e059e1fec101ad0053c2cf4d8 100644 --- a/test/a64/traces/sim-cmhs-16b-trace-a64.h +++ b/test/a64/traces/sim-cmhs-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-2d-trace-a64.h b/test/a64/traces/sim-cmhs-2d-trace-a64.h index 34e4700791db523d4ad0a9ecfcf250d19c917261..b76f4641fc9e0124d5b64a79e0257d0fc3e36076 100644 --- a/test/a64/traces/sim-cmhs-2d-trace-a64.h +++ b/test/a64/traces/sim-cmhs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-2s-trace-a64.h b/test/a64/traces/sim-cmhs-2s-trace-a64.h index 5d4e8c85ba4be10502df2cd47664773c96d7dade..0ef0d9a980d96483f607bb160659d886faf0c230 100644 --- a/test/a64/traces/sim-cmhs-2s-trace-a64.h +++ b/test/a64/traces/sim-cmhs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-4h-trace-a64.h b/test/a64/traces/sim-cmhs-4h-trace-a64.h index 21f6580dd184d8ac358c995b9a21660cea034202..9008c8ac6ecb2a221f67b3a8066ddf0f62b9ccd7 100644 --- a/test/a64/traces/sim-cmhs-4h-trace-a64.h +++ b/test/a64/traces/sim-cmhs-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-4s-trace-a64.h b/test/a64/traces/sim-cmhs-4s-trace-a64.h index 2ce88cc16f37be8851421569c97f1deed8c1cb3d..1d67f34c90ccc03868d24f55288b31c2b9eddaeb 100644 --- a/test/a64/traces/sim-cmhs-4s-trace-a64.h +++ b/test/a64/traces/sim-cmhs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-8b-trace-a64.h b/test/a64/traces/sim-cmhs-8b-trace-a64.h index da767a30f3c7a6f1c8eaa5595d001344695f8c30..5bcad52cb241f7fd7e532b91927c38fd9cdc3a37 100644 --- a/test/a64/traces/sim-cmhs-8b-trace-a64.h +++ b/test/a64/traces/sim-cmhs-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-8h-trace-a64.h b/test/a64/traces/sim-cmhs-8h-trace-a64.h index a7e677f290b9ed9fbb9b6d07e4274d94ef842efa..5fc28cfa0442cbb63a84da1d75a63b18a9b3a77d 100644 --- a/test/a64/traces/sim-cmhs-8h-trace-a64.h +++ b/test/a64/traces/sim-cmhs-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-d-trace-a64.h b/test/a64/traces/sim-cmhs-d-trace-a64.h index 245ff72a7f75a75fc381e6a4a0cb0a5d558db046..f6fc7730487f6314e8236d8ee0c49608996fb33f 100644 --- a/test/a64/traces/sim-cmhs-d-trace-a64.h +++ b/test/a64/traces/sim-cmhs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h index 26f15a3a7f0d035a3d8103e25076a3b93fcd98ac..1b744d1100d8a021cddf2ca89445455846622122 100644 --- a/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h index 5a57c89b6dab80f00fa39c399518fc05c3ee45b7..bf4a7909d44e90851e00d3e998fe7c8f48678093 100644 --- a/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h index 095fedca6a5d519e469c01ac5f71686caf32f1b9..729c6895c9e88bf85cee9f1b6f0852f9532a5c59 100644 --- a/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h index ac8820b9cfb3273ee80225c3312f516d6185844d..50dca7a1e43d04346005851397a9fc7d05c2f4c4 100644 --- a/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h index db76e7539c72c100778b23710040839ec1c7d35e..eb330e80f08210d2bde7661ab521eb7e29b3ca5c 100644 --- a/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h index c0d21ee83d44e43cc7b83a98082544e39ec0156e..d89cb9567faaa7990a80cc37975bbb04c44ee6e9 100644 --- a/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h index 129b685cf15691716e1bab6920c63fac17440bab..7d97d9084216467a1113144717704bfaa078ae25 100644 --- a/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h index 63b5a29fdf40ca9dedf57a8c7d59c40735d6d2f9..24a51ee687c58f71f0f0324fbc85909cb6ac2803 100644 --- a/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h index d62e7a7a1a92057f50312a1b4d93b6693011fa17..558dda61c13415a9b92819b5d33018c0bf46dbce 100644 --- a/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h index c8de2742bd0fc4a6101cf59d3d808c588348c959..1268718d19340d8d4785174d3821b06739e7fe21 100644 --- a/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h index 1d414597dc00d208ef436a81fa30d2275377370f..7a91b971401dd171e42d1d7e7a50333c96adf134 100644 --- a/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h index d1081e7c60620c414286dd2261d5e6d74d246c1a..ff4632c7d53080cd899224a7e7b0332b228c58ea 100644 --- a/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h index ebac8f2c783fdbd09e26cf8fd5e7902b9941fb44..24ebcc4ae275b87e69203611af746aa1a95fc159 100644 --- a/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h index e18c405170b819e70cfdae936b6956b3d5d1b707..f2d240e7721279b3fb3f2ea26fd34c0d2db821c0 100644 --- a/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h index ff4bde2e7182022548a8fa7e16cae47c55d95c40..c981e23d49d68d361f0ecf4f49b68883adcb9f82 100644 --- a/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h index ad2f4ebb8f1f63be630a9a3a672b5b7ea2592d4a..7c2e0a5ebbfbfd92231839b968a282c2e4ae65f4 100644 --- a/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-16b-trace-a64.h b/test/a64/traces/sim-cmtst-16b-trace-a64.h index a13bf9b807537d07343d15e57fbf777150b6ba7e..f4837f0d2de468dada9790fba94c0ce5143eb579 100644 --- a/test/a64/traces/sim-cmtst-16b-trace-a64.h +++ b/test/a64/traces/sim-cmtst-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-2d-trace-a64.h b/test/a64/traces/sim-cmtst-2d-trace-a64.h index 6b6783cd481565d4754fb6f65e1f0c4063f90433..6b5721c55626456734b6f78920552fbf84db1a46 100644 --- a/test/a64/traces/sim-cmtst-2d-trace-a64.h +++ b/test/a64/traces/sim-cmtst-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-2s-trace-a64.h b/test/a64/traces/sim-cmtst-2s-trace-a64.h index 253c4939320601828f890e744560f833aa89df9b..df1e827b0e8bf2067d1a0c5e8e2edaca9d1e7b8e 100644 --- a/test/a64/traces/sim-cmtst-2s-trace-a64.h +++ b/test/a64/traces/sim-cmtst-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-4h-trace-a64.h b/test/a64/traces/sim-cmtst-4h-trace-a64.h index 8a83c478f70d5370c42652d2835b7e5cfc76694e..3dc8c56ca996f5551d3e2c5146e574c895769ed3 100644 --- a/test/a64/traces/sim-cmtst-4h-trace-a64.h +++ b/test/a64/traces/sim-cmtst-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-4s-trace-a64.h b/test/a64/traces/sim-cmtst-4s-trace-a64.h index 522a7da6ebf8c73d94610e3a4326b4d513f094b1..9dbf872ddce861302d6d4bee8bc6689595a13929 100644 --- a/test/a64/traces/sim-cmtst-4s-trace-a64.h +++ b/test/a64/traces/sim-cmtst-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-8b-trace-a64.h b/test/a64/traces/sim-cmtst-8b-trace-a64.h index 8fe2cb2f8e450558fa6693705c0a3c731f1b5b94..3ef46410dfa43f44b5fe5d70f4f2bd02d34842f8 100644 --- a/test/a64/traces/sim-cmtst-8b-trace-a64.h +++ b/test/a64/traces/sim-cmtst-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-8h-trace-a64.h b/test/a64/traces/sim-cmtst-8h-trace-a64.h index 4595aee331fd47de322399a1952ccf5e0d9718a3..255c8494f097856adb312a5681dfeeff705b20d7 100644 --- a/test/a64/traces/sim-cmtst-8h-trace-a64.h +++ b/test/a64/traces/sim-cmtst-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-d-trace-a64.h b/test/a64/traces/sim-cmtst-d-trace-a64.h index 957c0635efab3e4bd6b2fca618c65b1b066a751f..0bf83b645888cd8fd64faf8f67543d551e230d68 100644 --- a/test/a64/traces/sim-cmtst-d-trace-a64.h +++ b/test/a64/traces/sim-cmtst-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cnt-16b-trace-a64.h b/test/a64/traces/sim-cnt-16b-trace-a64.h index 089fe3fc9a82f2205b64cf69a66d391ff747f4a4..ce167c14f44b5e8358dc6476df6486bf18a4b94d 100644 --- a/test/a64/traces/sim-cnt-16b-trace-a64.h +++ b/test/a64/traces/sim-cnt-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cnt-8b-trace-a64.h b/test/a64/traces/sim-cnt-8b-trace-a64.h index b3bc232fb67c404b0c9756f1d1a6924015d5d3b8..6c4772c7c7f03208605c66a78f872588cf2db180 100644 --- a/test/a64/traces/sim-cnt-8b-trace-a64.h +++ b/test/a64/traces/sim-cnt-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h b/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h index d856778df6c8c7335789949425fb120890c6b494..dfd54c958dfa15f63dcf6a38759d6302b9e27786 100644 --- a/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h b/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h index 30dbcb33bb67d2cfd241302ed3b88e236121c59c..442a6d0c29914927fd8fbfbfdbadc457c5e73257 100644 --- a/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h b/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h index c35d637acaa92b42b855bab826ef9557c9fb037a..8b42a490259c2146b6e924b0f79fcc9126fabeee 100644 --- a/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h b/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h index ba46a4d389fe9979bcfb2a16c4d9fe0f8004a8bb..87b8668ef64262441fbb113a1acefe2521424bf9 100644 --- a/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h b/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h index 15b92e1608f9bfb9c330b5db92eb8cebcfeab235..9cbf3a19178ade0c7f59e47ea60071fe232a2f24 100644 --- a/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h b/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h index 9092928103e487d2f510426d114e9a6e58b6b6e4..5cbbbee64d4d15eee4401762b30ee136aafc6848 100644 --- a/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h b/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h index db1c5287b867c31ffdb69b7764e0dd9fca4be0ea..40994b0a8c840761c854ad879290a3ca16d5d844 100644 --- a/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-b-2opimm-trace-a64.h b/test/a64/traces/sim-dup-b-2opimm-trace-a64.h index 1ae57dedcdc3f222fed30e4e18e54963bd891a37..53d9a724aa6748657d160cf38708dcf98f0660b8 100644 --- a/test/a64/traces/sim-dup-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-d-2opimm-trace-a64.h b/test/a64/traces/sim-dup-d-2opimm-trace-a64.h index cda60dd56a9519231d7271a2bf6920153b01415c..0fbcff197afc82a1ee6190677fcddc5ae6248213 100644 --- a/test/a64/traces/sim-dup-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-h-2opimm-trace-a64.h b/test/a64/traces/sim-dup-h-2opimm-trace-a64.h index 6ad42bef3d440497a9d7cf1ce08720d54ad283f0..74b2c2ad9d2af641896dab91005f926304444cf3 100644 --- a/test/a64/traces/sim-dup-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-s-2opimm-trace-a64.h b/test/a64/traces/sim-dup-s-2opimm-trace-a64.h index 6ecd3d6719f571a95316a1522519352fe4e39671..e4a7ed0d5041ec07e4bc7d308d14344846c47344 100644 --- a/test/a64/traces/sim-dup-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-eor-16b-trace-a64.h b/test/a64/traces/sim-eor-16b-trace-a64.h index b77b72b32e9db4c57e871f7bef68e91290596c60..3860b5d4ffd17a181980099e83513c6cd3c6b2e8 100644 --- a/test/a64/traces/sim-eor-16b-trace-a64.h +++ b/test/a64/traces/sim-eor-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-eor-8b-trace-a64.h b/test/a64/traces/sim-eor-8b-trace-a64.h index c642ea061f6eebf3607f6748170a986075f7dc94..3a9ab24cf79cede0b248d837c38538d5fde63761 100644 --- a/test/a64/traces/sim-eor-8b-trace-a64.h +++ b/test/a64/traces/sim-eor-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-2d-trace-a64.h b/test/a64/traces/sim-fabd-2d-trace-a64.h index 39d2d1a481009c097111f2eee6b621dd9da8510b..c02115a6810e131df17d5618999e35dec37d923c 100644 --- a/test/a64/traces/sim-fabd-2d-trace-a64.h +++ b/test/a64/traces/sim-fabd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-2s-trace-a64.h b/test/a64/traces/sim-fabd-2s-trace-a64.h index 65796575c7eda21347662882ce40a65c49133279..d719faccfb7bad1e79be1fa619f68408dc4a5501 100644 --- a/test/a64/traces/sim-fabd-2s-trace-a64.h +++ b/test/a64/traces/sim-fabd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-4s-trace-a64.h b/test/a64/traces/sim-fabd-4s-trace-a64.h index ce98ac35bd2a24a09ddb2f701c178a8d16d4242d..d202a349ae0101440d015fd454abc7871584e136 100644 --- a/test/a64/traces/sim-fabd-4s-trace-a64.h +++ b/test/a64/traces/sim-fabd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-d-trace-a64.h b/test/a64/traces/sim-fabd-d-trace-a64.h index 27f89fca1fc556818fc5fe731ce7967f25fca110..d757a30dec16fd21ac2f52059755b97d61540a6a 100644 --- a/test/a64/traces/sim-fabd-d-trace-a64.h +++ b/test/a64/traces/sim-fabd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-s-trace-a64.h b/test/a64/traces/sim-fabd-s-trace-a64.h index a9c41504c8a46711301ab9c7ba4ecc282e36e5ec..624ed4dfd450ad4babef41a8fd6b1808d5e57dcd 100644 --- a/test/a64/traces/sim-fabd-s-trace-a64.h +++ b/test/a64/traces/sim-fabd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-2d-trace-a64.h b/test/a64/traces/sim-fabs-2d-trace-a64.h index e7aab7450530588cd2d475cefeba6ee7fa5ebec4..55b96e3834a119fad6e5d9d85262e435301ff40e 100644 --- a/test/a64/traces/sim-fabs-2d-trace-a64.h +++ b/test/a64/traces/sim-fabs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-2s-trace-a64.h b/test/a64/traces/sim-fabs-2s-trace-a64.h index d3b4f57e2239272f82887410da0a491fa8110bde..1f2e2213598581b902b8360403fb96ca022d9bcb 100644 --- a/test/a64/traces/sim-fabs-2s-trace-a64.h +++ b/test/a64/traces/sim-fabs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-4s-trace-a64.h b/test/a64/traces/sim-fabs-4s-trace-a64.h index ae0d7a4b86e9c8b7adc5f4174e979542e933b733..63497a5c8261f351d7efc9e274fd8d1c1ad88fb6 100644 --- a/test/a64/traces/sim-fabs-4s-trace-a64.h +++ b/test/a64/traces/sim-fabs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-d-trace-a64.h b/test/a64/traces/sim-fabs-d-trace-a64.h index 016fc5533fbae6cf017a8df374e6c216d4d0ba03..c1a630780a7edd17d32a3f6af4430d91c23e1750 100644 --- a/test/a64/traces/sim-fabs-d-trace-a64.h +++ b/test/a64/traces/sim-fabs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-s-trace-a64.h b/test/a64/traces/sim-fabs-s-trace-a64.h index 8f64c01c191140296b9ccc91f863e986fd6ded0c..443c271875453f252c0d2fe659cb80331855bdff 100644 --- a/test/a64/traces/sim-fabs-s-trace-a64.h +++ b/test/a64/traces/sim-fabs-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-2d-trace-a64.h b/test/a64/traces/sim-facge-2d-trace-a64.h index e1127ea1af4f9258c956f22834f7b4165d9f4de9..095e948a763aed53b649c77849be83ad872114ee 100644 --- a/test/a64/traces/sim-facge-2d-trace-a64.h +++ b/test/a64/traces/sim-facge-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-2s-trace-a64.h b/test/a64/traces/sim-facge-2s-trace-a64.h index 4b085dffcf9bf39b6b3075a48d3b7328f7c1e53c..049bdd7274e6e6305f341d3dfe742b6fdf518825 100644 --- a/test/a64/traces/sim-facge-2s-trace-a64.h +++ b/test/a64/traces/sim-facge-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-4s-trace-a64.h b/test/a64/traces/sim-facge-4s-trace-a64.h index 016657eb604491670292036e99f566d1630234da..d733ed946e771d1122d762e5a7ec59f34d93c77d 100644 --- a/test/a64/traces/sim-facge-4s-trace-a64.h +++ b/test/a64/traces/sim-facge-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-d-trace-a64.h b/test/a64/traces/sim-facge-d-trace-a64.h index 8e65126d918353306f3918af5a64f50429045cb0..3780454600b1a10a3aacdf796a1aca83211db724 100644 --- a/test/a64/traces/sim-facge-d-trace-a64.h +++ b/test/a64/traces/sim-facge-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-s-trace-a64.h b/test/a64/traces/sim-facge-s-trace-a64.h index ba5f7c0053b5e734a686a848a8d323a75b89bcb0..69df68f89eb81b35966acdfd3498d9a7a47ea3c1 100644 --- a/test/a64/traces/sim-facge-s-trace-a64.h +++ b/test/a64/traces/sim-facge-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-2d-trace-a64.h b/test/a64/traces/sim-facgt-2d-trace-a64.h index f582533cd58aa500c501d2266f5695d5132a8f07..3b7f57b7b9c51c007f90d1ec728bd782d4e0c934 100644 --- a/test/a64/traces/sim-facgt-2d-trace-a64.h +++ b/test/a64/traces/sim-facgt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-2s-trace-a64.h b/test/a64/traces/sim-facgt-2s-trace-a64.h index a64fa9bf3420e88f222eec5b879e4629133972e1..ede45d5b6ed1c5b6921d8aa45a9b91c8d6b655d1 100644 --- a/test/a64/traces/sim-facgt-2s-trace-a64.h +++ b/test/a64/traces/sim-facgt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-4s-trace-a64.h b/test/a64/traces/sim-facgt-4s-trace-a64.h index bad9ca4d059934a111a89050614eb61af546d958..9234a963201da85557d2e9112f6f75545d722f7c 100644 --- a/test/a64/traces/sim-facgt-4s-trace-a64.h +++ b/test/a64/traces/sim-facgt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-d-trace-a64.h b/test/a64/traces/sim-facgt-d-trace-a64.h index 873fda03be027f846998d9eb3b050f1c7de136ff..1dbe7a80c191e93c80d10b53ac82fe5533ac0058 100644 --- a/test/a64/traces/sim-facgt-d-trace-a64.h +++ b/test/a64/traces/sim-facgt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-s-trace-a64.h b/test/a64/traces/sim-facgt-s-trace-a64.h index 65866e339499289d8bca178e86b5e55e76cf662b..98ceb0c2d0c48b0e524718b04b4bf26f30e2faa0 100644 --- a/test/a64/traces/sim-facgt-s-trace-a64.h +++ b/test/a64/traces/sim-facgt-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-2d-trace-a64.h b/test/a64/traces/sim-fadd-2d-trace-a64.h index a87172bf3d93491aafc0c4bfa2936df2484f35e4..ee3ccee464d08c50e5ec137c5de7078542aa2cae 100644 --- a/test/a64/traces/sim-fadd-2d-trace-a64.h +++ b/test/a64/traces/sim-fadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-2s-trace-a64.h b/test/a64/traces/sim-fadd-2s-trace-a64.h index 11d2a878b3348e47860257c606ba3cc3341d0ede..cfca985b01e9b16eb6989fe6d86fb0a4bfb5afa7 100644 --- a/test/a64/traces/sim-fadd-2s-trace-a64.h +++ b/test/a64/traces/sim-fadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-4s-trace-a64.h b/test/a64/traces/sim-fadd-4s-trace-a64.h index ce6e479b987124b3de1218f9621a529756b16c69..d9b4f875262c06cccce29935ca3267db7e580349 100644 --- a/test/a64/traces/sim-fadd-4s-trace-a64.h +++ b/test/a64/traces/sim-fadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-d-trace-a64.h b/test/a64/traces/sim-fadd-d-trace-a64.h index 0855c492257fdfe69117577dd0746e72b23538f6..1cee6e200cc191499cbdd26cd4efc0011b877e31 100644 --- a/test/a64/traces/sim-fadd-d-trace-a64.h +++ b/test/a64/traces/sim-fadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-s-trace-a64.h b/test/a64/traces/sim-fadd-s-trace-a64.h index 55acac4eda5b5765425c9a9e6e32df3076b60c9b..d14b44e27322e3f7ad5f20cb474776965e78d240 100644 --- a/test/a64/traces/sim-fadd-s-trace-a64.h +++ b/test/a64/traces/sim-fadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-2d-trace-a64.h b/test/a64/traces/sim-faddp-2d-trace-a64.h index acd6146db9d89b064a1927261c23deee80f59999..037ec27ae3da37895cd4dc300f9b2f14ff39ea13 100644 --- a/test/a64/traces/sim-faddp-2d-trace-a64.h +++ b/test/a64/traces/sim-faddp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-2s-trace-a64.h b/test/a64/traces/sim-faddp-2s-trace-a64.h index d8a1a6a20c36a54e15e3885776dfb44a8612b847..5ffeb0a7100d3c6151a2caa06314472e615b956e 100644 --- a/test/a64/traces/sim-faddp-2s-trace-a64.h +++ b/test/a64/traces/sim-faddp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-4s-trace-a64.h b/test/a64/traces/sim-faddp-4s-trace-a64.h index 413dabc5fcf050ec7a3ddc327c68f856fc7e538b..8d6a53e76019752f0e8db87e45cdb6a1f9fc82ae 100644 --- a/test/a64/traces/sim-faddp-4s-trace-a64.h +++ b/test/a64/traces/sim-faddp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-d-trace-a64.h b/test/a64/traces/sim-faddp-d-trace-a64.h index 0c25dfcdabea526b7297a74f32c70dc9c6c98189..b6697c0187ea8b414988ca0d3339a8a14fb315fc 100644 --- a/test/a64/traces/sim-faddp-d-trace-a64.h +++ b/test/a64/traces/sim-faddp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-s-trace-a64.h b/test/a64/traces/sim-faddp-s-trace-a64.h index b5bf9eb281bf6abb13c381e841a5a3dd036ac5b6..4cf857d964e6254d4b7f1ae3eae3644434b994ee 100644 --- a/test/a64/traces/sim-faddp-s-trace-a64.h +++ b/test/a64/traces/sim-faddp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h index 4b8fd4d081896d8e8136c3e9685d3a647ba91d81..43d10903027dbc2ec5ee0d9d6b32050ebe5dcf22 100644 --- a/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2d-trace-a64.h b/test/a64/traces/sim-fcmeq-2d-trace-a64.h index 88bf49a5d95a1eca14131754ceee13de35765832..a7463c843783acfcd8e5381043c345ed85d8a4cf 100644 --- a/test/a64/traces/sim-fcmeq-2d-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h index 9a420c2e9ef225fc7efa04b100ccfb677b822088..e77b9b297c99faab3c3019b30a47c084e1bf70d8 100644 --- a/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2s-trace-a64.h b/test/a64/traces/sim-fcmeq-2s-trace-a64.h index dce7dc229819e37c5d7796cc9f5f1c41f229da3f..58e74a82f79ee36cb5d1dfeaff98b306bd7cacce 100644 --- a/test/a64/traces/sim-fcmeq-2s-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h index b7a4207cd071f5bee941ef88c86e48ede5e15b86..f9b038eff1ea4791841cf21a54f192fa4529bc0a 100644 --- a/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-4s-trace-a64.h b/test/a64/traces/sim-fcmeq-4s-trace-a64.h index 72a5d69ecc5d9532b4f7fd51e94f4fc67369f708..a8487c0a9ea1284be323ac8231a81636e765f64e 100644 --- a/test/a64/traces/sim-fcmeq-4s-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h index 242d9a0cbb49c2d55fba4a564f283e962d40a4aa..0327fdbd7a0029721ccf5991ae0707c442b0367a 100644 --- a/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-d-trace-a64.h b/test/a64/traces/sim-fcmeq-d-trace-a64.h index 8053f9c62c95cbb3320894ce0b689639fd578863..36071924d87939ab1085996fee297cf38ee9cbbd 100644 --- a/test/a64/traces/sim-fcmeq-d-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h index 86bde33ffad1509d01d5f1ff5a4e4023655f48f3..6cccf00f2e99e58ec0d33af4fbd5085c544bdcb5 100644 --- a/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-s-trace-a64.h b/test/a64/traces/sim-fcmeq-s-trace-a64.h index b1a9007181008b119404ed58ea64dedf27f59f4e..8fbb7be9264241476abe4bdaf2091c2b673a440d 100644 --- a/test/a64/traces/sim-fcmeq-s-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h index 11ef8cdb08def5edb81d87639a3c7da9cbf3b71c..624a72879aae9224d590325f6dfedc01d9d8cb43 100644 --- a/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2d-trace-a64.h b/test/a64/traces/sim-fcmge-2d-trace-a64.h index cc6ea5a554f5ca868e2ea5419358b1a21dec3ef3..ff21c2f7f522696eedc7b6dea3db07d4c2dacd4d 100644 --- a/test/a64/traces/sim-fcmge-2d-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h index 899e981e664e9544517adff3324d20e6e6129e4e..19a568b0af7a86b63eb94aad6a076ccefc32cbca 100644 --- a/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2s-trace-a64.h b/test/a64/traces/sim-fcmge-2s-trace-a64.h index afd7ebd4980c98818ac2e59f40c4c8539ebbb03a..37d0e76deb95f3613621f3e8df557265466a13db 100644 --- a/test/a64/traces/sim-fcmge-2s-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h index aae0e2a08d76b6ad4bbb2711147eb3a4f40a2b02..633537d6a8b8257ead4b4f4d1e7ef7cd7bcaf01d 100644 --- a/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-4s-trace-a64.h b/test/a64/traces/sim-fcmge-4s-trace-a64.h index bfbf70d8bd53ec4dfcacd82751222466d82d574a..d42899b54db703a3638ba552b8505ce935b373b4 100644 --- a/test/a64/traces/sim-fcmge-4s-trace-a64.h +++ b/test/a64/traces/sim-fcmge-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h index 4d4b69c1476f02346d9eb27d18655a0e2072bf62..fd04688aacbe01792f29eba018e216672a8e5a27 100644 --- a/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-d-trace-a64.h b/test/a64/traces/sim-fcmge-d-trace-a64.h index 841f54634b099fd24f79221c0003ee8bd7d65202..39779cbccabfdd7c50886eafa2c3614ad5da39b0 100644 --- a/test/a64/traces/sim-fcmge-d-trace-a64.h +++ b/test/a64/traces/sim-fcmge-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h index 7a0d59a0e93ec90722087c4a3226e18ca2954c7f..5dd34a1de49eaa588fcb783aaeb1f91d34045961 100644 --- a/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-s-trace-a64.h b/test/a64/traces/sim-fcmge-s-trace-a64.h index 15601d2bfe0f56762aff48141b6d67dd05a7f5d3..a2d92aa634698af0b0e01e0a1aa97dbaacc6fc1c 100644 --- a/test/a64/traces/sim-fcmge-s-trace-a64.h +++ b/test/a64/traces/sim-fcmge-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h index 9514d2d93ac8a4ebe7dd70c249a151d6c3da0f49..f832c9766c90279c03eea59e5960da7ccc639326 100644 --- a/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2d-trace-a64.h b/test/a64/traces/sim-fcmgt-2d-trace-a64.h index 891f1013709784830a5bf3d5c550392e76fad0ac..5fd316072a6d339dd39cf1430f803aef02f83839 100644 --- a/test/a64/traces/sim-fcmgt-2d-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h index 5109c260ad813c88ee5f22f86560b9e3ea429978..8a823b22555ab75612fab361bae4dde5e9937a73 100644 --- a/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2s-trace-a64.h b/test/a64/traces/sim-fcmgt-2s-trace-a64.h index 8e2a51ef099fb670beccd7261767a94c18aebfb5..a520ca25fdedbf24eb1b8814d9673a5636b6d8b3 100644 --- a/test/a64/traces/sim-fcmgt-2s-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h index 862fc8bb42d491819b5d1daf311bba500bb93df5..e8ddfd7551d401f51d3aaeaf689416ffbea343e5 100644 --- a/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-4s-trace-a64.h b/test/a64/traces/sim-fcmgt-4s-trace-a64.h index 6a4ab1ab2e0de86c8a4fee43f39d2f3a332d8608..c4ee21fb7385c12a2631a1249193a6ec2b2b147b 100644 --- a/test/a64/traces/sim-fcmgt-4s-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h index f53d2ee7d04beaa1794cf36b9e15352ac4251613..5b0f82cf325f240cabb69541851f7be0d31c0ad2 100644 --- a/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-d-trace-a64.h b/test/a64/traces/sim-fcmgt-d-trace-a64.h index cb19f8019a9ce0999d64ba9a4ffad5bb2acf57d9..f8edf1bf48815b119a82f7a7b1817991bd128c7d 100644 --- a/test/a64/traces/sim-fcmgt-d-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h index 265bce1a3ddfcb62cb3e7e80ded2e0723f2ee9f6..933d9f45febfc268de116b09a26f30ed6624c06c 100644 --- a/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-s-trace-a64.h b/test/a64/traces/sim-fcmgt-s-trace-a64.h index 6b181cc2cceea763066e98607d02f8c4d2a7f4b4..5689325af45b42f4e04ef73ec9a00c2c9614ddd5 100644 --- a/test/a64/traces/sim-fcmgt-s-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h index 48f881bceea2029bc62b65ccc7f7eb003c9624e0..aba854c021c125e4e4e51e12a29f696af9acfbd1 100644 --- a/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h index 6223d933a1ece2cbc1843edbe995c9579037c5f5..56c794b592509675fbe526e90ce46c7ec491f396 100644 --- a/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h index f430950342e59b6d46d79e517fa8e6d822e61b9d..9f86bdf15018e78fd8d3b9678f9b1770e0e259b3 100644 --- a/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h index 6c3298676b42f473a8e7e18e94538df7c3e3835f..072910c5f96a65a14579555bb88b8d4e16910936 100644 --- a/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h index b6138de75f09fe1a2b1cdab682a8114c9d1e7c13..6bc29bc919317a9fe13d0a2d46b80274af8f4989 100644 --- a/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h index 08fcf106f4c9c2327d8b339d97076b6ad78d264c..fcf8377e04f89753f8f6ae1e745a6a35f0d74979 100644 --- a/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h index 676d0d54c0dee8dc386534c0ca9b1e7bffe6d510..4ee40e2f3973a3b0ada87d27893bb716df6fb1cd 100644 --- a/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h index 7f84795eda663d69f8244e536146adc14a829700..0e379ea9f5ee9341ec67b269940b48b9ab245bfc 100644 --- a/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h index 2aff2c9c0770b939ee620c7e347491920fe5e375..f7ebac8ad391d4721b866dd8db48f5e2f1946bff 100644 --- a/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h index d3efa3762db5751c1bf2ed1ce73e130e5500905d..3941dc45a0926227d634276272381604ff245bc7 100644 --- a/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-d-trace-a64.h b/test/a64/traces/sim-fcmp-d-trace-a64.h index 0f3d77933050e17bf48d9697b6e2596401438253..7bb811941fff1cfedd5fb5707db8cf5749e5577f 100644 --- a/test/a64/traces/sim-fcmp-d-trace-a64.h +++ b/test/a64/traces/sim-fcmp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-dz-trace-a64.h b/test/a64/traces/sim-fcmp-dz-trace-a64.h index d8c2bc51e3258d99834de326361cae38c9d9ad81..f7863df6720d307bc36c9e981bc68d9065e38e1f 100644 --- a/test/a64/traces/sim-fcmp-dz-trace-a64.h +++ b/test/a64/traces/sim-fcmp-dz-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-s-trace-a64.h b/test/a64/traces/sim-fcmp-s-trace-a64.h index 2ea6a26542732990719a2f43fec5c108f653411a..92ba3a948c201aa4dc190c3d07db82443262e33a 100644 --- a/test/a64/traces/sim-fcmp-s-trace-a64.h +++ b/test/a64/traces/sim-fcmp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-sz-trace-a64.h b/test/a64/traces/sim-fcmp-sz-trace-a64.h index 6604adee1b1032cc8c9472fc3194b1b81e663e5e..53eca2813cfc25b2cea955ac61e96ca0a8feb5f8 100644 --- a/test/a64/traces/sim-fcmp-sz-trace-a64.h +++ b/test/a64/traces/sim-fcmp-sz-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvt-ds-trace-a64.h b/test/a64/traces/sim-fcvt-ds-trace-a64.h index 3fa2e6a4c3e38a34765704b3682732ef1b1d50f9..6faf8a2b878542cda6c84e7f2e57fa2cde0a52d5 100644 --- a/test/a64/traces/sim-fcvt-ds-trace-a64.h +++ b/test/a64/traces/sim-fcvt-ds-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvt-sd-trace-a64.h b/test/a64/traces/sim-fcvt-sd-trace-a64.h index 49b37d1b06eec6635b49475a21387ba68bdff229..2f93fcacd72f1acd07de684cf63c9fb8ab9ac80d 100644 --- a/test/a64/traces/sim-fcvt-sd-trace-a64.h +++ b/test/a64/traces/sim-fcvt-sd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-2d-trace-a64.h b/test/a64/traces/sim-fcvtas-2d-trace-a64.h index cbe9dc0bcab2570d0c6f6802efa77f08d07a1d1b..1eae034a050218a06e3645d199f899f003720b97 100644 --- a/test/a64/traces/sim-fcvtas-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-2s-trace-a64.h b/test/a64/traces/sim-fcvtas-2s-trace-a64.h index dec068d2bfb1ebe2f2cd772f18f19cefaf78ef16..759564f3642ecf045c509b174735d822cf3ad204 100644 --- a/test/a64/traces/sim-fcvtas-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-4s-trace-a64.h b/test/a64/traces/sim-fcvtas-4s-trace-a64.h index 6b99aab4f0fe4eef0b7d89bac6b6d478458bb49a..0fd75900a0fdd74da43303465421d874b1105015 100644 --- a/test/a64/traces/sim-fcvtas-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-d-trace-a64.h b/test/a64/traces/sim-fcvtas-d-trace-a64.h index 1ffe153b06ad14b71cb791fe37007bf45300ed23..c7a73952fda435a444e7e7ffb6c3dbf2ee66d077 100644 --- a/test/a64/traces/sim-fcvtas-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-s-trace-a64.h b/test/a64/traces/sim-fcvtas-s-trace-a64.h index 7c5dd93c0259400cbe76da26a1022cf81fa5f742..a3015e169b2b383338001391d1c8c35afba190f3 100644 --- a/test/a64/traces/sim-fcvtas-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-wd-trace-a64.h b/test/a64/traces/sim-fcvtas-wd-trace-a64.h index 9df9e4ee2a4490ea5d8082d1001a459fe735c4da..a57a9883321e4bb3b3e5b435f14174ac3af29eeb 100644 --- a/test/a64/traces/sim-fcvtas-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-ws-trace-a64.h b/test/a64/traces/sim-fcvtas-ws-trace-a64.h index 9b8c9f92a08fd18aa5fad1b458a7572536e3dec0..fa06fc16b5c6cc7b70bf018127f9c61d61a8bfa9 100644 --- a/test/a64/traces/sim-fcvtas-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-xd-trace-a64.h b/test/a64/traces/sim-fcvtas-xd-trace-a64.h index 09b23470a1c82f947c517362ccbca87352b44f22..e6c92c260fcd3a9d3396ffeca270a99c70e62666 100644 --- a/test/a64/traces/sim-fcvtas-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-xs-trace-a64.h b/test/a64/traces/sim-fcvtas-xs-trace-a64.h index 9612b481f9c9a125dc591da6fc2d6aca50185f28..2a1396e1228b573372d81ac1fd0195dd3c875bf7 100644 --- a/test/a64/traces/sim-fcvtas-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-2d-trace-a64.h b/test/a64/traces/sim-fcvtau-2d-trace-a64.h index e07bc3d42e90a27050dfa39dadad6a0b73044078..8427cf9e97e0843317e62235c24a8e2a2bec34df 100644 --- a/test/a64/traces/sim-fcvtau-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-2s-trace-a64.h b/test/a64/traces/sim-fcvtau-2s-trace-a64.h index b02e31bbd93e9a1409b0e47f4e57a3313ab2b9c5..5748bc578edcda1d6831ab2a9f33ff7bace03603 100644 --- a/test/a64/traces/sim-fcvtau-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-4s-trace-a64.h b/test/a64/traces/sim-fcvtau-4s-trace-a64.h index e506203a8bb7e4eb4a563574a761af6fcd222399..4509e14b7e987766cc4beffc79b4eda7b80f12f2 100644 --- a/test/a64/traces/sim-fcvtau-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-d-trace-a64.h b/test/a64/traces/sim-fcvtau-d-trace-a64.h index 6c12a594ad04b75e361c3034149b85ac83d5cc41..53e567cf80f2baadf2c420338b1ca07cd50c7ad7 100644 --- a/test/a64/traces/sim-fcvtau-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-s-trace-a64.h b/test/a64/traces/sim-fcvtau-s-trace-a64.h index 806b93d587663e78b50ffda4d39540b108b17b1e..749314b5a3cdc811b96805227398306ab1395baa 100644 --- a/test/a64/traces/sim-fcvtau-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-wd-trace-a64.h b/test/a64/traces/sim-fcvtau-wd-trace-a64.h index 82d04381322771f4e6f97d0bd75ca3c16258f274..7cec3d0128b610b38f6e6de8641286809c69a3da 100644 --- a/test/a64/traces/sim-fcvtau-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-ws-trace-a64.h b/test/a64/traces/sim-fcvtau-ws-trace-a64.h index eabdeea8d7f458e37278d21d39a783b2a63b0d16..36e03a0aeca4e6be8ed99c6eb1f0ebf5478ac3da 100644 --- a/test/a64/traces/sim-fcvtau-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-xd-trace-a64.h b/test/a64/traces/sim-fcvtau-xd-trace-a64.h index 9389cbc336760ffa3ebc4007ddd8648315c4dc25..2a8d0d84dfa7f16b1c4f89b664ed601619d7b79b 100644 --- a/test/a64/traces/sim-fcvtau-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-xs-trace-a64.h b/test/a64/traces/sim-fcvtau-xs-trace-a64.h index 76eba48c9c1bc5460a9116c7309078b012728375..18c9fb51c971db6686fd954f8c1ee50e8b07a142 100644 --- a/test/a64/traces/sim-fcvtau-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl-2d-trace-a64.h b/test/a64/traces/sim-fcvtl-2d-trace-a64.h index 63f031f0d39a4609514a10130553621a7453e37d..924d2a3803f5f2d03f1fab725f5cad3588750f89 100644 --- a/test/a64/traces/sim-fcvtl-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl-4s-trace-a64.h b/test/a64/traces/sim-fcvtl-4s-trace-a64.h index 3c880420ab22b01448f3b5fc64d25138172df168..dc564b65a682110e2603f1e7ec88d30b5d78086e 100644 --- a/test/a64/traces/sim-fcvtl-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl2-2d-trace-a64.h b/test/a64/traces/sim-fcvtl2-2d-trace-a64.h index a5769e6bc3a2c13152523ef02924c16cdbe18494..22dfe5362051b571f6cdcf0545c35d8237ef7e8e 100644 --- a/test/a64/traces/sim-fcvtl2-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl2-4s-trace-a64.h b/test/a64/traces/sim-fcvtl2-4s-trace-a64.h index 1fda45ad0b632e92be72feff78910e1329458b21..fbc9313dd4da12d5c918473b0dd2635e36b8a98e 100644 --- a/test/a64/traces/sim-fcvtl2-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-2d-trace-a64.h b/test/a64/traces/sim-fcvtms-2d-trace-a64.h index 32981512e7e2ec55d1f3a58daa9f28a1ca6aaae3..69fdb83569b32655cb7a57e22ed8816317a3db70 100644 --- a/test/a64/traces/sim-fcvtms-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-2s-trace-a64.h b/test/a64/traces/sim-fcvtms-2s-trace-a64.h index a1c6d13fa1ddf6ecc4df741d43d59f432fbf9ee1..3136e3e42f175f6c88b5313083524907e37378bd 100644 --- a/test/a64/traces/sim-fcvtms-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-4s-trace-a64.h b/test/a64/traces/sim-fcvtms-4s-trace-a64.h index f9e41ce9fd73a99566ebfa45234a4729c0cc8660..8430d6f20b835e4f6d94d50f5b07291e27dcf203 100644 --- a/test/a64/traces/sim-fcvtms-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-d-trace-a64.h b/test/a64/traces/sim-fcvtms-d-trace-a64.h index be14012642e2d081859ccf1da37d1e30aafaa80a..3d7f11a9530e463508e3ecfab731d741c9ee1813 100644 --- a/test/a64/traces/sim-fcvtms-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-s-trace-a64.h b/test/a64/traces/sim-fcvtms-s-trace-a64.h index f14324af6c6027030b36e501f745811f51d9b599..17f56b3ddf3d95d5ee5b5495496ed896eb002e7d 100644 --- a/test/a64/traces/sim-fcvtms-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-wd-trace-a64.h b/test/a64/traces/sim-fcvtms-wd-trace-a64.h index 5f933713c89c02bf4173694350b48066ae069b37..e0e9ff83ad6b5cc555e1abfcd9828f6490bc2cf7 100644 --- a/test/a64/traces/sim-fcvtms-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-ws-trace-a64.h b/test/a64/traces/sim-fcvtms-ws-trace-a64.h index 555fb404e6410ba3335a88266947781a7f462872..6bda41e278c8a66ad1170e8e2e803100fd7ad442 100644 --- a/test/a64/traces/sim-fcvtms-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-xd-trace-a64.h b/test/a64/traces/sim-fcvtms-xd-trace-a64.h index 87b67b9c9865c084d7010c1830aafc5db55d4bd0..936888e796797f5be869e005aa4c34f5f1c74071 100644 --- a/test/a64/traces/sim-fcvtms-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-xs-trace-a64.h b/test/a64/traces/sim-fcvtms-xs-trace-a64.h index 033ba17ef1eb1d5577e3aaeee53c3256a237034b..41c696da362fb57a62ea63e430aa4fe8b1848adb 100644 --- a/test/a64/traces/sim-fcvtms-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-2d-trace-a64.h b/test/a64/traces/sim-fcvtmu-2d-trace-a64.h index d940ab4805ffefab4d01272e3e6d37ca6f11fe81..c3f99d0cea522adc83f8a30d9dd85b0fde73d707 100644 --- a/test/a64/traces/sim-fcvtmu-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-2s-trace-a64.h b/test/a64/traces/sim-fcvtmu-2s-trace-a64.h index a02d831b1f21b7f2d1359746f8377d2d97ba7a0e..38a10b8577ceb096021b26da9244e3dc2e1090e0 100644 --- a/test/a64/traces/sim-fcvtmu-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-4s-trace-a64.h b/test/a64/traces/sim-fcvtmu-4s-trace-a64.h index ca2fb816be42abc84cd2ac6e6895bcfac0b749f4..d4e1d91d0d1f3383b24f40929cccdfe9df05da2e 100644 --- a/test/a64/traces/sim-fcvtmu-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-d-trace-a64.h b/test/a64/traces/sim-fcvtmu-d-trace-a64.h index d595801b16176bb8b3f9fc0cd6617fbea1f5adf8..916adaa1dce165225677a22c0734a4bc32589030 100644 --- a/test/a64/traces/sim-fcvtmu-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-s-trace-a64.h b/test/a64/traces/sim-fcvtmu-s-trace-a64.h index 8b83baafbb6a3beea6de8ad13d8046a9f0803e10..084fcf0f92a472d95f6ab8e7fea33b3bd65801d1 100644 --- a/test/a64/traces/sim-fcvtmu-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-wd-trace-a64.h b/test/a64/traces/sim-fcvtmu-wd-trace-a64.h index 57c55a29c1a4b795cbf3de402f112d073da494b3..4939feb156091f3390d3e1c4cc9ffb659ef5353c 100644 --- a/test/a64/traces/sim-fcvtmu-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-ws-trace-a64.h b/test/a64/traces/sim-fcvtmu-ws-trace-a64.h index 8b760ca11b00c6759719cd4db3b627ce537d87db..9f3bee2a3a33d7e7d1b2b6a6b82b1d26cd9f99c7 100644 --- a/test/a64/traces/sim-fcvtmu-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-xd-trace-a64.h b/test/a64/traces/sim-fcvtmu-xd-trace-a64.h index ee6ccec77388e1661c21b6e8923520c2d4a81543..2993d653b7be57a65ce97938fa8b97bf1e9ee927 100644 --- a/test/a64/traces/sim-fcvtmu-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-xs-trace-a64.h b/test/a64/traces/sim-fcvtmu-xs-trace-a64.h index c1a82415be011426749c313854dde9fe0c674ff0..562fa778426d33f62b94e538002f68aee45a0107 100644 --- a/test/a64/traces/sim-fcvtmu-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn-2s-trace-a64.h b/test/a64/traces/sim-fcvtn-2s-trace-a64.h index b81ab4bbbf28cf73245f09a6996e6e9cd9041c7b..6dab851d5332f057411da94539bd6d80cb23173d 100644 --- a/test/a64/traces/sim-fcvtn-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn-4h-trace-a64.h b/test/a64/traces/sim-fcvtn-4h-trace-a64.h index 15c424979b68e9f4298d7e89735b9bb1ea4375b6..81dddc1b6fd36a7d1a788d78eb3a05c720ac9fdb 100644 --- a/test/a64/traces/sim-fcvtn-4h-trace-a64.h +++ b/test/a64/traces/sim-fcvtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn2-4s-trace-a64.h b/test/a64/traces/sim-fcvtn2-4s-trace-a64.h index 30d5387feb306a0a0c60a98afa213c150ee53bff..e1bf259c921cc1c0d3630fa184346197f62689dc 100644 --- a/test/a64/traces/sim-fcvtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn2-8h-trace-a64.h b/test/a64/traces/sim-fcvtn2-8h-trace-a64.h index 98a3f8cbfeda9e268e24b38aeba99512ac20752c..eeb7a9e03a9b67d17d5ff714d5d3d95aa10d47e9 100644 --- a/test/a64/traces/sim-fcvtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-fcvtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-2d-trace-a64.h b/test/a64/traces/sim-fcvtns-2d-trace-a64.h index 8513045298c36ee7b2d19f6d29cf8cff16d2722b..464e6185b3b15a8428d7d5d038fdb8df0637b3e3 100644 --- a/test/a64/traces/sim-fcvtns-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-2s-trace-a64.h b/test/a64/traces/sim-fcvtns-2s-trace-a64.h index 86285dcb959c7ca2bf5864b03f69f544860c474f..474baac07daf87cc9e0f0d30582a00743d1d3653 100644 --- a/test/a64/traces/sim-fcvtns-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-4s-trace-a64.h b/test/a64/traces/sim-fcvtns-4s-trace-a64.h index c8c022ad45bde9021781742b0798c5d2dd91f723..3475c44f4dd6e5192e91acdc187d4fb98a7a7163 100644 --- a/test/a64/traces/sim-fcvtns-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-d-trace-a64.h b/test/a64/traces/sim-fcvtns-d-trace-a64.h index 8aa44ee3e43474f76350676c292bb0fd22642a9a..bf64ee26674a1d9f69b640cbc58d701b0446e969 100644 --- a/test/a64/traces/sim-fcvtns-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-s-trace-a64.h b/test/a64/traces/sim-fcvtns-s-trace-a64.h index 7e7dd1462347674792da4ac3116d5c100cd1a999..4b631596fde2b08d173bbc0450df04ea3e1f154b 100644 --- a/test/a64/traces/sim-fcvtns-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-wd-trace-a64.h b/test/a64/traces/sim-fcvtns-wd-trace-a64.h index 570bb3ee7289a8c0cc41da28fbea21f79ac68126..0b8837edf7f98d40118dbb8f3eb60baac700d6ea 100644 --- a/test/a64/traces/sim-fcvtns-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-ws-trace-a64.h b/test/a64/traces/sim-fcvtns-ws-trace-a64.h index 031b0fce91fce6c263ae285cee86d6c0e09bf4a4..be3266bd5630a3f01597e222223f7a02a20316fa 100644 --- a/test/a64/traces/sim-fcvtns-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-xd-trace-a64.h b/test/a64/traces/sim-fcvtns-xd-trace-a64.h index 43a1cbf1e419db58c3eae5399b3ec9f70fc24330..7fcdeceefdeeb3fa1f8eecfd43c0e7b99ef7d9b1 100644 --- a/test/a64/traces/sim-fcvtns-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-xs-trace-a64.h b/test/a64/traces/sim-fcvtns-xs-trace-a64.h index 14cbd914e403bd4dfe5b8caf0292405ddfb09cdd..cd67dec9f6b609ad44d228f4d972d4f2b36c5f96 100644 --- a/test/a64/traces/sim-fcvtns-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-2d-trace-a64.h b/test/a64/traces/sim-fcvtnu-2d-trace-a64.h index c5cf7177204f4f230da2603abd920b9e9d848b33..c5176c05f89c9ce823f44bce7e6a9116102e5ccd 100644 --- a/test/a64/traces/sim-fcvtnu-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-2s-trace-a64.h b/test/a64/traces/sim-fcvtnu-2s-trace-a64.h index fe1171cf436dd9b7223365515d06c83eadbea687..8fd18752911c56469cf10db21c245252859770b4 100644 --- a/test/a64/traces/sim-fcvtnu-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-4s-trace-a64.h b/test/a64/traces/sim-fcvtnu-4s-trace-a64.h index 0e4add8e97cdd556d65e80c09cfe9831f79f7bd5..aef9227d8b846b9ef97854aca24df3f410d2796c 100644 --- a/test/a64/traces/sim-fcvtnu-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-d-trace-a64.h b/test/a64/traces/sim-fcvtnu-d-trace-a64.h index 4bddc99cdd0e61ad2ca48afff962060e1ed6c3d1..03325e242c9c28ca0934129392fdc20264ef7a72 100644 --- a/test/a64/traces/sim-fcvtnu-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-s-trace-a64.h b/test/a64/traces/sim-fcvtnu-s-trace-a64.h index 06ccc94cee8dd3fa835d0db3f00bf16bea7a59f8..9a7956ce90f7bfefd0e318ce727b6d4c14a897a3 100644 --- a/test/a64/traces/sim-fcvtnu-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-wd-trace-a64.h b/test/a64/traces/sim-fcvtnu-wd-trace-a64.h index a798636cf9b0aabf8ea7c11c9fec117536cf4ef5..b0bd34cdb8273d79951ec3ba6bfdac4422277066 100644 --- a/test/a64/traces/sim-fcvtnu-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-ws-trace-a64.h b/test/a64/traces/sim-fcvtnu-ws-trace-a64.h index fc1efdac545a6b828a55bb4b5890aceb962bc786..84e8832ff0c9bde83da5f10e5c81f7a38159c9d1 100644 --- a/test/a64/traces/sim-fcvtnu-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-xd-trace-a64.h b/test/a64/traces/sim-fcvtnu-xd-trace-a64.h index 8d79a32c6ab16f473fbac93b46c42fd4a4ca8fc4..3517979e5129bc03b70ad93b8c46c6bd6160d317 100644 --- a/test/a64/traces/sim-fcvtnu-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-xs-trace-a64.h b/test/a64/traces/sim-fcvtnu-xs-trace-a64.h index 73c133b6465a0ef62842a5fd8e1f08b4e894ad50..3b106ba3c59a1c0a1fd3ed2aba6ac16f233cf03f 100644 --- a/test/a64/traces/sim-fcvtnu-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-2d-trace-a64.h b/test/a64/traces/sim-fcvtps-2d-trace-a64.h index 9decab10210f1382e600b95dd837e8ff2b76e361..e13ae760dde9e14d9f0b93d6d49c897654c20d7a 100644 --- a/test/a64/traces/sim-fcvtps-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-2s-trace-a64.h b/test/a64/traces/sim-fcvtps-2s-trace-a64.h index f922ec18658d3b24d97845162f49f6ae16fdd618..eea61c3d4589891aaab23bad0623f6a6410eec62 100644 --- a/test/a64/traces/sim-fcvtps-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-4s-trace-a64.h b/test/a64/traces/sim-fcvtps-4s-trace-a64.h index 3cb221b7aa68e5d1e3c9d97892ca4b13678d72d4..a2caf2abd12145734806b9801543a507ff4c78c2 100644 --- a/test/a64/traces/sim-fcvtps-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-d-trace-a64.h b/test/a64/traces/sim-fcvtps-d-trace-a64.h index ae90702a53c14c237183ff09806117de59b6f673..7ecf88a62e2d517ad862f34fed4b384e2b05e2cf 100644 --- a/test/a64/traces/sim-fcvtps-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-s-trace-a64.h b/test/a64/traces/sim-fcvtps-s-trace-a64.h index 8584db813821aeda549cb4a3e40de2b27c678369..9efee290c54b3cdec7b236ec84b85ef4a173c878 100644 --- a/test/a64/traces/sim-fcvtps-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-2d-trace-a64.h b/test/a64/traces/sim-fcvtpu-2d-trace-a64.h index 847610b596cb6adefa3b909a2ea0ad8797da26ac..402328c1502a50a3a76078371059aeb2de86753c 100644 --- a/test/a64/traces/sim-fcvtpu-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-2s-trace-a64.h b/test/a64/traces/sim-fcvtpu-2s-trace-a64.h index 236ad8be63c034def04f806c553367b486abc3e5..8dde4962768014ac70b11c8c0f411c64bee2d4ea 100644 --- a/test/a64/traces/sim-fcvtpu-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-4s-trace-a64.h b/test/a64/traces/sim-fcvtpu-4s-trace-a64.h index 3b2532f7bae2d64ce0cfa4e73be55c25e8f63690..0660ca6cf6862a7108b7168844fc9a7b59b1ec8f 100644 --- a/test/a64/traces/sim-fcvtpu-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-d-trace-a64.h b/test/a64/traces/sim-fcvtpu-d-trace-a64.h index 7d0fba79156d15e12135cf00d8a1a2a51d903a61..c357c7fd17f955cf8caedd9634c6c17251b8a901 100644 --- a/test/a64/traces/sim-fcvtpu-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-s-trace-a64.h b/test/a64/traces/sim-fcvtpu-s-trace-a64.h index e370a94c53c84d3200caa309afc8e0265a9a408f..7585eed4474168ae86107a6d03566f4e661d8a89 100644 --- a/test/a64/traces/sim-fcvtpu-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtxn-2s-trace-a64.h b/test/a64/traces/sim-fcvtxn-2s-trace-a64.h index 1e0fb1ea826fa1e0ee4e96f7d9e7c8cf81ae4a19..a60637fbb6b3e14531c23be04bb78d7f92cdfd29 100644 --- a/test/a64/traces/sim-fcvtxn-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtxn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h b/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h index 1b2f25dae85cb814c8920070bf3c77dd68d0b896..314c7561ca12eb12f8124b8ff07f32094d25fba1 100644 --- a/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h +++ b/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h b/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h index 2dcb89bcf042f23958e31c2009f07f8c47441054..61ec44052cd2cd8867d07f714c12b966f36584e1 100644 --- a/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h index f42d39b2d5a05e7c86616af67e368f7a5b8da221..08443478371810117b79803ff62d618adb03eba7 100644 --- a/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h index 7d1f8f180b7fd8cb530ea9e4f573b5dc8ca79a33..4ad8d2552b1bae3720604e79675d2feb414af73a 100644 --- a/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h index cba5214d132a887771ca6f12c52017a9ec1a6764..6202a39bbd3d1cc6bada2630b27f291f0d4f87ac 100644 --- a/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h index e0641c94e652fb64dbd7bfe16914901744dcf871..e97b36ae8f5447b3a5d503605400e1f27c805ae1 100644 --- a/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h index 49720aed1e01f76900ff90d5fe116dfb82a79824..8ffb044bd193d2e1bc9bc57a3f2af3b83f37ff67 100644 --- a/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-wd-trace-a64.h b/test/a64/traces/sim-fcvtzs-wd-trace-a64.h index ce0b33951c424ac748cd948febd432e9b713719f..38f7546e9e14db814201685ecb16d4661ae62f36 100644 --- a/test/a64/traces/sim-fcvtzs-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-ws-trace-a64.h b/test/a64/traces/sim-fcvtzs-ws-trace-a64.h index 3b951fd510d28856b007b2d9587f12c05519cc48..8c856e57310860989e33096f1dc69365b665f2f6 100644 --- a/test/a64/traces/sim-fcvtzs-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-xd-trace-a64.h b/test/a64/traces/sim-fcvtzs-xd-trace-a64.h index 5bd00c1099213681d775b20f2d4fc66da78e5207..ae40abad92ec49b5ac19ced9d7bf619cd21c7c96 100644 --- a/test/a64/traces/sim-fcvtzs-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-xs-trace-a64.h b/test/a64/traces/sim-fcvtzs-xs-trace-a64.h index dc2ea437066a32791e489fa1fb086bf9dbb1be13..5a5be0764fe1fab1345cb10dcd9d4846b12f545a 100644 --- a/test/a64/traces/sim-fcvtzs-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h index 1ed0e8f917bf812f7d7cfe3ad897dcb8304e14ca..c0562fffd84ce9c5dd829304be9fe5f8d8c38077 100644 --- a/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h index 02c8cb1edef2ba5f33404b619202a64575d24d1b..29aa2565e10c930ed8b4d558c758a127fe70dfa2 100644 --- a/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h index a7679405a6d042fe4dcef68d47c02dfc627dd885..2ebfe61863598621070c88cc51c4cd6942c0392f 100644 --- a/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h index 50161ed01e69e747db2963338448fd63d2a193c5..dc64c7fe43a16c822aad62e470fbcdde24da8009 100644 --- a/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h index 86421d9443498c7b870e979dfde380b4d3abc7bf..8e7e90763cb5ae145d5a3c7baf871f30d5a15787 100644 --- a/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-wd-trace-a64.h b/test/a64/traces/sim-fcvtzu-wd-trace-a64.h index 3084fd885bb1473f6b3612b06ec9fcb84a03ca32..8aa8f0fcc51f5c0e64c02a608e3b8528ce4aac39 100644 --- a/test/a64/traces/sim-fcvtzu-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-ws-trace-a64.h b/test/a64/traces/sim-fcvtzu-ws-trace-a64.h index 671deb4cd1bf478efbb2ea90db7bddf55fbdddad..05229be26e1727831d076f0b532e1477d1adbba5 100644 --- a/test/a64/traces/sim-fcvtzu-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-xd-trace-a64.h b/test/a64/traces/sim-fcvtzu-xd-trace-a64.h index 87fb3fc4f33650f13a4ee6d58418d1928a3763a0..1a0d7939f2734cb3cabb1b99fc5c2868d6cde407 100644 --- a/test/a64/traces/sim-fcvtzu-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-xs-trace-a64.h b/test/a64/traces/sim-fcvtzu-xs-trace-a64.h index 55210f9740cd351c973e8bf7798b00466d14b708..895301aa45354a36f8675d9d24683455a3338e69 100644 --- a/test/a64/traces/sim-fcvtzu-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-2d-trace-a64.h b/test/a64/traces/sim-fdiv-2d-trace-a64.h index 1b7a187d177bc39bfc2cb5e5e62ebbc83e8416b4..a5c20300e3171a6b35826f14f43046c72885c2d0 100644 --- a/test/a64/traces/sim-fdiv-2d-trace-a64.h +++ b/test/a64/traces/sim-fdiv-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-2s-trace-a64.h b/test/a64/traces/sim-fdiv-2s-trace-a64.h index dce2d571ffdb8ffd787335907fecce01a11b9f10..f21c1bab01bb8a6bfe1f8b345ce3c6857753b8b0 100644 --- a/test/a64/traces/sim-fdiv-2s-trace-a64.h +++ b/test/a64/traces/sim-fdiv-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-4s-trace-a64.h b/test/a64/traces/sim-fdiv-4s-trace-a64.h index 9966251209c8fb35e602a55bb7802deaef133eea..bc7852e6ba0b1758fa23fdbfd4113511367303e9 100644 --- a/test/a64/traces/sim-fdiv-4s-trace-a64.h +++ b/test/a64/traces/sim-fdiv-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-d-trace-a64.h b/test/a64/traces/sim-fdiv-d-trace-a64.h index 9da3a5ebb8d2cf85e4f8c70f08e53275f07ce089..f6a89a0152af9abd25f57b2ad41294a99fc6011c 100644 --- a/test/a64/traces/sim-fdiv-d-trace-a64.h +++ b/test/a64/traces/sim-fdiv-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-s-trace-a64.h b/test/a64/traces/sim-fdiv-s-trace-a64.h index eebb80d68990b155aae6896259a4e69c34beaeae..7144cb4b1b3e6ee786e5aee04514b8a3e61a0f4a 100644 --- a/test/a64/traces/sim-fdiv-s-trace-a64.h +++ b/test/a64/traces/sim-fdiv-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmadd-d-trace-a64.h b/test/a64/traces/sim-fmadd-d-trace-a64.h index 650b50765af105846a41940a95bbbaf4ceb45e09..dde34d942735ac8c68b281a1ba942b2ef589f377 100644 --- a/test/a64/traces/sim-fmadd-d-trace-a64.h +++ b/test/a64/traces/sim-fmadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmadd-s-trace-a64.h b/test/a64/traces/sim-fmadd-s-trace-a64.h index 4e5a39f9ac8e90f37d0b3907db1f4ee9498ec4e4..c8483d994ec7384512cb3f2e4869c932d827ad87 100644 --- a/test/a64/traces/sim-fmadd-s-trace-a64.h +++ b/test/a64/traces/sim-fmadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-2d-trace-a64.h b/test/a64/traces/sim-fmax-2d-trace-a64.h index d6d5615d6b2d29447de166bc25d12877b69515f7..7759192a5f008808de4923eb6876f14667e04857 100644 --- a/test/a64/traces/sim-fmax-2d-trace-a64.h +++ b/test/a64/traces/sim-fmax-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-2s-trace-a64.h b/test/a64/traces/sim-fmax-2s-trace-a64.h index d017fb5541354096e450bca81077900e7c9f883a..5e2bee90afad8448262356a6d4e0c209321319b1 100644 --- a/test/a64/traces/sim-fmax-2s-trace-a64.h +++ b/test/a64/traces/sim-fmax-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-4s-trace-a64.h b/test/a64/traces/sim-fmax-4s-trace-a64.h index e7564125974dc217ffbc37490d26d350a3eb4e03..27e985c2c14d9ef9c28fd8968a74faa0f1766082 100644 --- a/test/a64/traces/sim-fmax-4s-trace-a64.h +++ b/test/a64/traces/sim-fmax-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-d-trace-a64.h b/test/a64/traces/sim-fmax-d-trace-a64.h index da3adb754e5d7b04cb714f78f853d5ea2c2b1f05..6941cac0a2f09e62240ebc513be3f477abbe6d2d 100644 --- a/test/a64/traces/sim-fmax-d-trace-a64.h +++ b/test/a64/traces/sim-fmax-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-s-trace-a64.h b/test/a64/traces/sim-fmax-s-trace-a64.h index 8722ca36548a8d476106b8bd9996e3437bfa129c..b402a4c9f10b78fddcf6c9f7a9be17bab3b41544 100644 --- a/test/a64/traces/sim-fmax-s-trace-a64.h +++ b/test/a64/traces/sim-fmax-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-2d-trace-a64.h b/test/a64/traces/sim-fmaxnm-2d-trace-a64.h index 71edb6d24f6eaee76ed555531be30764ec123a29..e7458b2c006a900f81ce855e08f9f61f69af0eb7 100644 --- a/test/a64/traces/sim-fmaxnm-2d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-2s-trace-a64.h b/test/a64/traces/sim-fmaxnm-2s-trace-a64.h index 8a9f1cf3702b825b436e2445d8a0c38bf992ac54..e7af6d455a2e413ac28daae6794690112f905903 100644 --- a/test/a64/traces/sim-fmaxnm-2s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-4s-trace-a64.h b/test/a64/traces/sim-fmaxnm-4s-trace-a64.h index 093fa5d3bc2e6ab3c179d786fd6db75a6b964150..19571ed97828c81962ff7319eaff28f6bedc18ed 100644 --- a/test/a64/traces/sim-fmaxnm-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-d-trace-a64.h b/test/a64/traces/sim-fmaxnm-d-trace-a64.h index 2b45858cb04464817acbeadbd2be42d213a4083c..b36a3d046a086eeee052ac11823858a683bb7d03 100644 --- a/test/a64/traces/sim-fmaxnm-d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-s-trace-a64.h b/test/a64/traces/sim-fmaxnm-s-trace-a64.h index 09bb86ef845130a6ab2af5733cf7feb39e0cd56a..52adc88d66ccdab47a27da6db608a1147f0e5987 100644 --- a/test/a64/traces/sim-fmaxnm-s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h b/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h index 1738b98934459fceb923d1df5fc4404e1ff8b3bd..14a9b06c37151c74f601f180318f0207704df743 100644 --- a/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h b/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h index faacde2428c95257805c69fa676de3e815d6ec99..d98215ae88a283f438c30680ab0ef958ec974d26 100644 --- a/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h b/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h index 2fae29819d11c9fbeae31c443482a26a01fcfda4..17cebc2c111798fc2a97693ef82dd553ebef5478 100644 --- a/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-d-trace-a64.h b/test/a64/traces/sim-fmaxnmp-d-trace-a64.h index db22f6077b4bf3c54e8e35b868d2ee2b7e5fcd5b..77cee2f0fe3c3031adfad5cfab98bb1a5e5ba3cb 100644 --- a/test/a64/traces/sim-fmaxnmp-d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-s-trace-a64.h b/test/a64/traces/sim-fmaxnmp-s-trace-a64.h index 2ae78a2f95dba02f7abfd724e7ccdfc8288d25a7..5a61032068deb06e8e7a49ba8a52b763cc243446 100644 --- a/test/a64/traces/sim-fmaxnmp-s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h b/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h index 6075defad8e2a636c2a07bc6c16a5f0bc5190ed6..35d433b2ca347befe2e28f13da14de896f7f5885 100644 --- a/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-2d-trace-a64.h b/test/a64/traces/sim-fmaxp-2d-trace-a64.h index 8511277704f527c2a13f7034d0d861d3f39438e1..75633306cdf94262308b5c3d09e7ea8f9cd01672 100644 --- a/test/a64/traces/sim-fmaxp-2d-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-2s-trace-a64.h b/test/a64/traces/sim-fmaxp-2s-trace-a64.h index f1f9a7d77800dcd2b4c0907be00c4faee8a6219d..9794c59c8fc6114f0dfd6274475cf113a5356eaa 100644 --- a/test/a64/traces/sim-fmaxp-2s-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-4s-trace-a64.h b/test/a64/traces/sim-fmaxp-4s-trace-a64.h index f0742ce261c71f191811f2d60fbe4b8bcafb1dc3..e2a07540c3f0452379db95d0895f86f7f91d3719 100644 --- a/test/a64/traces/sim-fmaxp-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-d-trace-a64.h b/test/a64/traces/sim-fmaxp-d-trace-a64.h index f953c9d175717265dfeca7e755981470a12a5fd0..e07a512fd1b9b72795ab52d143baee901a17e50c 100644 --- a/test/a64/traces/sim-fmaxp-d-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-s-trace-a64.h b/test/a64/traces/sim-fmaxp-s-trace-a64.h index 5722ec2ee287a9a9e9cc5b22b527c9707804f409..5a9c89ecabc245274273077c110b0f8b87b7850c 100644 --- a/test/a64/traces/sim-fmaxp-s-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h b/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h index 5217714839dad14cb0c9d0a7b8466993183cac9a..6e7d206234cb4eb81b29f64b3a0a5f65bd86b4e6 100644 --- a/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-2d-trace-a64.h b/test/a64/traces/sim-fmin-2d-trace-a64.h index 189bb872861fabf6f4bbf5b4112dc286e568a399..165c91eb56ec53fdc51070d49ad5809891177644 100644 --- a/test/a64/traces/sim-fmin-2d-trace-a64.h +++ b/test/a64/traces/sim-fmin-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-2s-trace-a64.h b/test/a64/traces/sim-fmin-2s-trace-a64.h index 739baa211ffbae3ee9a99d0c866c31e1892fc704..df1864b4aa31f49314aca2151f7416d735e60a5a 100644 --- a/test/a64/traces/sim-fmin-2s-trace-a64.h +++ b/test/a64/traces/sim-fmin-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-4s-trace-a64.h b/test/a64/traces/sim-fmin-4s-trace-a64.h index 1cac405ba9e8c57ffc058d5de138d80916410fb2..09aec7629c8cdeb889c602ea8d8707ded5174ea9 100644 --- a/test/a64/traces/sim-fmin-4s-trace-a64.h +++ b/test/a64/traces/sim-fmin-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-d-trace-a64.h b/test/a64/traces/sim-fmin-d-trace-a64.h index 2b4541c86545d624183bb82f823186753d5a9a77..6acfa86592de3fe7beb7d66b7d224a51836136a0 100644 --- a/test/a64/traces/sim-fmin-d-trace-a64.h +++ b/test/a64/traces/sim-fmin-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-s-trace-a64.h b/test/a64/traces/sim-fmin-s-trace-a64.h index e9a02094a4f2085ba82f80f60edcf0f9f575213a..4fc21f663e341bb7e31869994fee35204b7caf93 100644 --- a/test/a64/traces/sim-fmin-s-trace-a64.h +++ b/test/a64/traces/sim-fmin-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-2d-trace-a64.h b/test/a64/traces/sim-fminnm-2d-trace-a64.h index 975863d09dd90a9adf79b29509059748685e3e35..547a69a1ccba0bd1623cf09e12385dfb85452e9f 100644 --- a/test/a64/traces/sim-fminnm-2d-trace-a64.h +++ b/test/a64/traces/sim-fminnm-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-2s-trace-a64.h b/test/a64/traces/sim-fminnm-2s-trace-a64.h index 767d70700406896e42be6743ae367987acf78079..e8ec3cd547797ccfeb83981bfd12bcccc74b5bac 100644 --- a/test/a64/traces/sim-fminnm-2s-trace-a64.h +++ b/test/a64/traces/sim-fminnm-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-4s-trace-a64.h b/test/a64/traces/sim-fminnm-4s-trace-a64.h index c61e0176f173770656591a46590e3b92ab383eff..1562093323505ea77cdeb8f4dbde46628636a8d4 100644 --- a/test/a64/traces/sim-fminnm-4s-trace-a64.h +++ b/test/a64/traces/sim-fminnm-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-d-trace-a64.h b/test/a64/traces/sim-fminnm-d-trace-a64.h index ba9a0bc2516560b30a179903af603723f4e80061..8b06a2dafed8b64dbcd7a9c7340011dbe8f54f83 100644 --- a/test/a64/traces/sim-fminnm-d-trace-a64.h +++ b/test/a64/traces/sim-fminnm-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-s-trace-a64.h b/test/a64/traces/sim-fminnm-s-trace-a64.h index cb673505c000dd9deab21b4fd16b8357f350d8be..77f7b19031770cd4bab77047f5bb635e04553a63 100644 --- a/test/a64/traces/sim-fminnm-s-trace-a64.h +++ b/test/a64/traces/sim-fminnm-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-2d-trace-a64.h b/test/a64/traces/sim-fminnmp-2d-trace-a64.h index 37029e4e716a654086aa7965b1224d177b3321a5..16357ef0675c32d2dede6e63f75e7a37f8e4b68a 100644 --- a/test/a64/traces/sim-fminnmp-2d-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-2s-trace-a64.h b/test/a64/traces/sim-fminnmp-2s-trace-a64.h index 7a76135af98ea188f7247c3d3a715e71103028b6..d34fc6d85f62b5490e59a7107ab58dfdcf655716 100644 --- a/test/a64/traces/sim-fminnmp-2s-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-4s-trace-a64.h b/test/a64/traces/sim-fminnmp-4s-trace-a64.h index 158dc3b3c155d3b00126090228e5807fb2ece1c8..7649eb3ea3d96db812b171b1e8c9a001785bd9e7 100644 --- a/test/a64/traces/sim-fminnmp-4s-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-d-trace-a64.h b/test/a64/traces/sim-fminnmp-d-trace-a64.h index 74868a21f652f7f541d9cd8b3cc0a1bf11087f62..268961d538f2753a402e984dce53c765cf51c727 100644 --- a/test/a64/traces/sim-fminnmp-d-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-s-trace-a64.h b/test/a64/traces/sim-fminnmp-s-trace-a64.h index 99dc2eb12778a8d1263b3bd0791b9fd036f5e162..0ba9f86b279a1dfb6c21c155e797ebdb64f6a48f 100644 --- a/test/a64/traces/sim-fminnmp-s-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h b/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h index c784f2407f6d378a157bf630ef1936da55c78d99..4bc0f968861981e65634a36dbe49f5a3b582fc66 100644 --- a/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-2d-trace-a64.h b/test/a64/traces/sim-fminp-2d-trace-a64.h index 9ba35da2a6a97bcc809a75d945eb255dbbeb9eab..0837915af074d80d00be299900c6ddab63dcfe18 100644 --- a/test/a64/traces/sim-fminp-2d-trace-a64.h +++ b/test/a64/traces/sim-fminp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-2s-trace-a64.h b/test/a64/traces/sim-fminp-2s-trace-a64.h index 61d2d5b735ae7457c2d6606a1b3fb17cd55b576b..a78f4cb56464f136063e7a405940cd4d0072a500 100644 --- a/test/a64/traces/sim-fminp-2s-trace-a64.h +++ b/test/a64/traces/sim-fminp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-4s-trace-a64.h b/test/a64/traces/sim-fminp-4s-trace-a64.h index 045340da3b13ad298799bd70a8b460da2f67816b..808570808328a15e05230aead433bfa152ca03e9 100644 --- a/test/a64/traces/sim-fminp-4s-trace-a64.h +++ b/test/a64/traces/sim-fminp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-d-trace-a64.h b/test/a64/traces/sim-fminp-d-trace-a64.h index 2744ca5ed8d4495d6af2b7ec06b1d9f03f54dd8f..16e0c8d0925432b45916b12e2874cc1b6e583ef0 100644 --- a/test/a64/traces/sim-fminp-d-trace-a64.h +++ b/test/a64/traces/sim-fminp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-s-trace-a64.h b/test/a64/traces/sim-fminp-s-trace-a64.h index f76a5fdefdedd17115969b0c099aeea1d678bf0b..2f7e72c623f0c706f289ade4cc2b95bef62f4c0d 100644 --- a/test/a64/traces/sim-fminp-s-trace-a64.h +++ b/test/a64/traces/sim-fminp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminv-s-4s-trace-a64.h b/test/a64/traces/sim-fminv-s-4s-trace-a64.h index b4d6c15e545268f972ac8670a9a302c0248ef261..ec53fa4c501c32ad2d5fd8db7bcb0813397f6c82 100644 --- a/test/a64/traces/sim-fminv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fminv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h index 8c6ec3262adf4935b27ee36da14979d95bd4e174..e3b3b7f51c057612f611036193d29dda5637453e 100644 --- a/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2d-trace-a64.h b/test/a64/traces/sim-fmla-2d-trace-a64.h index c9b5899c2e905e267d461ac707ec932651d9e9ad..bc0cc6a8dbb51dda46ca3fdd6d0c584f1521871c 100644 --- a/test/a64/traces/sim-fmla-2d-trace-a64.h +++ b/test/a64/traces/sim-fmla-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h index e9b9cbc1803e0138a63dd2d43f26fc2de23e3001..d2a196869c17022c8f3ff8ca1b51bd051d9ff322 100644 --- a/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2s-trace-a64.h b/test/a64/traces/sim-fmla-2s-trace-a64.h index d56969bdd5ab60bbfe95cdc2e375aa64165551ec..af0d2cd080d1d4b1129cf4145b0c5012415dc4c1 100644 --- a/test/a64/traces/sim-fmla-2s-trace-a64.h +++ b/test/a64/traces/sim-fmla-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h index 7081207147d70e0ab21f02c144fe3f6f480c2d5c..6d032c6318b49468a7d8a349ce7992f5604ff819 100644 --- a/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-4s-trace-a64.h b/test/a64/traces/sim-fmla-4s-trace-a64.h index ff04947cf266b27c67f63b1cd23b4b840a74aef5..07973caa2e5cbca7053e00ea0f286cc2a47b193b 100644 --- a/test/a64/traces/sim-fmla-4s-trace-a64.h +++ b/test/a64/traces/sim-fmla-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-d-d-d-trace-a64.h b/test/a64/traces/sim-fmla-d-d-d-trace-a64.h index b75be38743a929477c713853f75360a0c514e3da..d6d7c97e5eca2f927ad3238e5ba8a6cf97aeb7c4 100644 --- a/test/a64/traces/sim-fmla-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmla-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-s-s-s-trace-a64.h b/test/a64/traces/sim-fmla-s-s-s-trace-a64.h index 8986f57b6bbd6336a817d540ce293ef72c0182ed..a681c6a5cb008b4868bf8b35e8f4dfd3388a8b32 100644 --- a/test/a64/traces/sim-fmla-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmla-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h index 0d9eeb3e3dc727d52825f126c0cfb3e020d411a6..7a283035232dcec8bc8969414e9014b89db2fbc8 100644 --- a/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2d-trace-a64.h b/test/a64/traces/sim-fmls-2d-trace-a64.h index 3626d0b5de9a81a0414f110573c1e7ded5f9db3f..c7259c810ce3352bc8cc0ad17963febc85e0b96f 100644 --- a/test/a64/traces/sim-fmls-2d-trace-a64.h +++ b/test/a64/traces/sim-fmls-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h index cfb1481b29cd3db24cd6f6f7cd183fe064b875c8..6ce4530cb82f7910412465c16c78947f0cdcbb6d 100644 --- a/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2s-trace-a64.h b/test/a64/traces/sim-fmls-2s-trace-a64.h index 4d7a63b2fa7f90a3b306a971cb448b47834a7968..c5a0c034c274b08f453b54a7a75ae03d271be3a2 100644 --- a/test/a64/traces/sim-fmls-2s-trace-a64.h +++ b/test/a64/traces/sim-fmls-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h index 9e7b9c7476737e0f943d0cff88345568bfb44bbd..ecb75d1567660e307f11f9c69a8c9c3af3579fed 100644 --- a/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-4s-trace-a64.h b/test/a64/traces/sim-fmls-4s-trace-a64.h index 4924b0edb54d3a7d738b0bd3eec4be15e4e0233b..261dbcc67cfb8688a93a18cc225b953bad1bf927 100644 --- a/test/a64/traces/sim-fmls-4s-trace-a64.h +++ b/test/a64/traces/sim-fmls-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-d-d-d-trace-a64.h b/test/a64/traces/sim-fmls-d-d-d-trace-a64.h index ec18868256b79b016d4992a80b02b85fefab6aac..6291b492fc8975faef71c6c7e144cdadfeff58ac 100644 --- a/test/a64/traces/sim-fmls-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmls-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-s-s-s-trace-a64.h b/test/a64/traces/sim-fmls-s-s-s-trace-a64.h index e55e4a66768ded93e888bba452f023da384a1c84..92bb11a70088bcc4e49355ef14e624cb78d137e2 100644 --- a/test/a64/traces/sim-fmls-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmls-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmov-d-trace-a64.h b/test/a64/traces/sim-fmov-d-trace-a64.h index bd609e0ead1e47b57962d1e81d031988504bceeb..4cba47c91a096ee33d4a518e5f727ea819b97969 100644 --- a/test/a64/traces/sim-fmov-d-trace-a64.h +++ b/test/a64/traces/sim-fmov-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmov-s-trace-a64.h b/test/a64/traces/sim-fmov-s-trace-a64.h index 42fd8d7f450ad41cff3fd220b7c1952e3ad19e19..8c2bab74540b29cf52060e42e8121ef405603f59 100644 --- a/test/a64/traces/sim-fmov-s-trace-a64.h +++ b/test/a64/traces/sim-fmov-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmsub-d-trace-a64.h b/test/a64/traces/sim-fmsub-d-trace-a64.h index e09b947ffb7cfe4522b2f37e2bc6ea3a01d6ae55..f7bb57dfb178cc545503a54181808ba4c24b20c7 100644 --- a/test/a64/traces/sim-fmsub-d-trace-a64.h +++ b/test/a64/traces/sim-fmsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmsub-s-trace-a64.h b/test/a64/traces/sim-fmsub-s-trace-a64.h index 81948a405c2d7fbf9196fec2766110324f877f9b..53b75e0065f818319b973104e7f0bceec933307e 100644 --- a/test/a64/traces/sim-fmsub-s-trace-a64.h +++ b/test/a64/traces/sim-fmsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h index 033720def028c14f97f679e354ed8968d7b41a16..a2ed1913cb9a13e8bcbd36d4598531ecedc04b04 100644 --- a/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2d-trace-a64.h b/test/a64/traces/sim-fmul-2d-trace-a64.h index 1e161c6106d5ea58fff4542ebc421c634572b13d..ca3d62a816812fe995c953a3ebb88a71e5f7842d 100644 --- a/test/a64/traces/sim-fmul-2d-trace-a64.h +++ b/test/a64/traces/sim-fmul-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h index 038e1f723179e1463f39fd8009efb7a46a11f5d7..05141428e2d9d974e41e3fdebc7f8c5c69965694 100644 --- a/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2s-trace-a64.h b/test/a64/traces/sim-fmul-2s-trace-a64.h index 975702a037ef82af1e0ba1e221919faafdcd6232..37fb9469c0cc042a82dfd3a21773200e4d661d21 100644 --- a/test/a64/traces/sim-fmul-2s-trace-a64.h +++ b/test/a64/traces/sim-fmul-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h index d09164b009a03b309db9ada317658a2cf5e92c43..197306069ff05698ae841840e62ad503168af7ff 100644 --- a/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-4s-trace-a64.h b/test/a64/traces/sim-fmul-4s-trace-a64.h index 90dccbc25ad986515057b9ca199bc9c587a23924..6f80e4655cc3184ec57459856c910c8c41468fa8 100644 --- a/test/a64/traces/sim-fmul-4s-trace-a64.h +++ b/test/a64/traces/sim-fmul-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-d-d-d-trace-a64.h b/test/a64/traces/sim-fmul-d-d-d-trace-a64.h index 8de9eb77f88f29df55cb422d66e4a64da6169b28..0498b11829e4343a2ca087a2dbb88e09acb8b209 100644 --- a/test/a64/traces/sim-fmul-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmul-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-d-trace-a64.h b/test/a64/traces/sim-fmul-d-trace-a64.h index ac2bed2b931c390eac2c4cc3d5d4e4379a14f4d1..a76e42cc842358ae919d3acc98d83a8a338e9849 100644 --- a/test/a64/traces/sim-fmul-d-trace-a64.h +++ b/test/a64/traces/sim-fmul-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-s-s-s-trace-a64.h b/test/a64/traces/sim-fmul-s-s-s-trace-a64.h index ac66709e7c5e8891e340f1742d14ff4aaebec553..87f94dece5f6c99376cef4033615303600ddca9a 100644 --- a/test/a64/traces/sim-fmul-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-s-trace-a64.h b/test/a64/traces/sim-fmul-s-trace-a64.h index 88c9acb9de2571e190260de2e2e42bb096c500d9..670afc971a5f7d496b437e29ac119201957b803a 100644 --- a/test/a64/traces/sim-fmul-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h index f4ec615bd3237fb21a14fdde8ea1fd5de0e0b4d3..548b62fd11097b701c0c8cb86a83fd11513cad8d 100644 --- a/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2d-trace-a64.h b/test/a64/traces/sim-fmulx-2d-trace-a64.h index 9ef4f2b799dac91d5ea0b99002bfb3bf546f08bb..8b1df1d2d2998318743c6727191aec237f2bb952 100644 --- a/test/a64/traces/sim-fmulx-2d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h index 9be20e6cd45ed683b6451526445125551ce6e217..51f1c41243b45bc233ee55749224c56c301c8f8e 100644 --- a/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2s-trace-a64.h b/test/a64/traces/sim-fmulx-2s-trace-a64.h index 5d25de60e7c41bb633a298b5ae99d79c9d54526c..fa5286fe9138f62c84053f25b6c17c298da2b0d2 100644 --- a/test/a64/traces/sim-fmulx-2s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h index 9e168c2abbaaae4339feedf392512313e8806dae..e213dc1066934b139f1f29049d2be680cb78383d 100644 --- a/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-4s-trace-a64.h b/test/a64/traces/sim-fmulx-4s-trace-a64.h index 67cef5826fd499187800c2ba54f705a09d9b92b5..57c9f1e8b548b45e00f8c9444049ee8e4054cdc7 100644 --- a/test/a64/traces/sim-fmulx-4s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h b/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h index 38e62c79c49a28cdfbc1e22e705b2715d62c9663..9290be1b84f85a246e20cfbd3147d688b87eb315 100644 --- a/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-d-trace-a64.h b/test/a64/traces/sim-fmulx-d-trace-a64.h index 0005cc9a2f4470c5da9e376302c65d180d9991cf..c7f2e1cc9f43b33798511ea503dc0def4f06d9bd 100644 --- a/test/a64/traces/sim-fmulx-d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h b/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h index a3b42b81d3526e6f41b37ccf8ca2fbcf3e349d14..d0f85f16040df7b3c80d1bbb5bb9105d117248c1 100644 --- a/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-s-trace-a64.h b/test/a64/traces/sim-fmulx-s-trace-a64.h index 2f8ab7c64497e77a96c1a756777987a2b9d1d37f..eeb12d03fb07879cf2011d87719dbfa4265b59c6 100644 --- a/test/a64/traces/sim-fmulx-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-2d-trace-a64.h b/test/a64/traces/sim-fneg-2d-trace-a64.h index 37a364df2e0d403170ff4477bfa6faa37f5d9eeb..7d79d9101ebf35c50c881a3a4f274fb7d85337d3 100644 --- a/test/a64/traces/sim-fneg-2d-trace-a64.h +++ b/test/a64/traces/sim-fneg-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-2s-trace-a64.h b/test/a64/traces/sim-fneg-2s-trace-a64.h index 2c023fca5b3ab59b90cc7515e7f2a784673d63fc..f344b86d20f09be7e88326e887848b5494102b68 100644 --- a/test/a64/traces/sim-fneg-2s-trace-a64.h +++ b/test/a64/traces/sim-fneg-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-4s-trace-a64.h b/test/a64/traces/sim-fneg-4s-trace-a64.h index 0b021f340af671e8cd4d2bc2c1a956e5e599a25a..54e5bb645a9e95060f45092d5a9aff79ebe9bcc6 100644 --- a/test/a64/traces/sim-fneg-4s-trace-a64.h +++ b/test/a64/traces/sim-fneg-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-d-trace-a64.h b/test/a64/traces/sim-fneg-d-trace-a64.h index 08b34d0904bfbbde86c3f56d0366c3072ab29fb0..e29df68ecaf455a1ca2b1ffa7e7c5fcf97fd1bce 100644 --- a/test/a64/traces/sim-fneg-d-trace-a64.h +++ b/test/a64/traces/sim-fneg-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-s-trace-a64.h b/test/a64/traces/sim-fneg-s-trace-a64.h index 5aebcedfc386cb55b0ef1f38a82d4982d1853dd4..6ad6176b53402bbbd83e0621f30c0af43f5214cb 100644 --- a/test/a64/traces/sim-fneg-s-trace-a64.h +++ b/test/a64/traces/sim-fneg-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmadd-d-trace-a64.h b/test/a64/traces/sim-fnmadd-d-trace-a64.h index d75bed6ed01d33e3b43c5c3079cfe29f3c08c484..a1fc51ca8b05f914f04198185084e20dafe37f55 100644 --- a/test/a64/traces/sim-fnmadd-d-trace-a64.h +++ b/test/a64/traces/sim-fnmadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmadd-s-trace-a64.h b/test/a64/traces/sim-fnmadd-s-trace-a64.h index d3cab31bd90be78e3ac533af21e311c6fea50c43..ef7c76c34db0b3f7ac8639beeb64ff6a095a1548 100644 --- a/test/a64/traces/sim-fnmadd-s-trace-a64.h +++ b/test/a64/traces/sim-fnmadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmsub-d-trace-a64.h b/test/a64/traces/sim-fnmsub-d-trace-a64.h index 9750f3c717c16ef4478e596fa91503ca5a65a786..a0feecf1fe177f0e7c6a5e1888116ab6f612f325 100644 --- a/test/a64/traces/sim-fnmsub-d-trace-a64.h +++ b/test/a64/traces/sim-fnmsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmsub-s-trace-a64.h b/test/a64/traces/sim-fnmsub-s-trace-a64.h index de5ef104008ef2571e456054d6da81d14734c2dd..ae27c6312ad8ba118ac2072e24e6fa152454caa0 100644 --- a/test/a64/traces/sim-fnmsub-s-trace-a64.h +++ b/test/a64/traces/sim-fnmsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmul-d-trace-a64.h b/test/a64/traces/sim-fnmul-d-trace-a64.h index cf07bb0180bce4bf75637846a35f258601d1f51c..78c1d39d11e9efa8c2571f45d26bdb09c800117b 100644 --- a/test/a64/traces/sim-fnmul-d-trace-a64.h +++ b/test/a64/traces/sim-fnmul-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmul-s-trace-a64.h b/test/a64/traces/sim-fnmul-s-trace-a64.h index 7652ee10aee69bd1d778c9da370494d297e9bd8b..75c26bc48539392eed52a4d5df74c8c289ed7a1d 100644 --- a/test/a64/traces/sim-fnmul-s-trace-a64.h +++ b/test/a64/traces/sim-fnmul-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-2d-trace-a64.h b/test/a64/traces/sim-frecpe-2d-trace-a64.h index 6f995826cb745ebcf54e4ad661241e0b0f26b3f3..3dd3b6d63b8598fce7d1893566ee6b5ccbae2232 100644 --- a/test/a64/traces/sim-frecpe-2d-trace-a64.h +++ b/test/a64/traces/sim-frecpe-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-2s-trace-a64.h b/test/a64/traces/sim-frecpe-2s-trace-a64.h index 16ffde95ad11e53038d3aa083b791d02cb775376..7d469ba41aa7f8463b68dab266d8f9355daecd71 100644 --- a/test/a64/traces/sim-frecpe-2s-trace-a64.h +++ b/test/a64/traces/sim-frecpe-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-4s-trace-a64.h b/test/a64/traces/sim-frecpe-4s-trace-a64.h index 77593b57407a6550a920dc6b04e45f4d4676e31c..adb4107f9b5fc2b0c62dd43047f8aab5cca47b48 100644 --- a/test/a64/traces/sim-frecpe-4s-trace-a64.h +++ b/test/a64/traces/sim-frecpe-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-d-trace-a64.h b/test/a64/traces/sim-frecpe-d-trace-a64.h index 7757b03606b0ae3a1d93d066040159560d448360..767af248b5c9645157776695ddd0a23bbc9ab2bf 100644 --- a/test/a64/traces/sim-frecpe-d-trace-a64.h +++ b/test/a64/traces/sim-frecpe-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-s-trace-a64.h b/test/a64/traces/sim-frecpe-s-trace-a64.h index 3edbf1b93f3d3efdaa752d75f2447ba895a03731..c1d5acb63fc645ddc38f03bdc6879ae044850ab9 100644 --- a/test/a64/traces/sim-frecpe-s-trace-a64.h +++ b/test/a64/traces/sim-frecpe-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-2d-trace-a64.h b/test/a64/traces/sim-frecps-2d-trace-a64.h index 45f09b872cf252a725292acb65d9b6b9165ee569..0970925c30786c58fe8b723beec0863b14356a32 100644 --- a/test/a64/traces/sim-frecps-2d-trace-a64.h +++ b/test/a64/traces/sim-frecps-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-2s-trace-a64.h b/test/a64/traces/sim-frecps-2s-trace-a64.h index e584e4528d9d6f023748b8572e3f6be449229718..4cd44f3b61e5ae3de4df1e56d38cff97cb8a3f55 100644 --- a/test/a64/traces/sim-frecps-2s-trace-a64.h +++ b/test/a64/traces/sim-frecps-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-4s-trace-a64.h b/test/a64/traces/sim-frecps-4s-trace-a64.h index 92a6d370c83a05bad8a14e6f723d5c66d6525a45..467516c098c1306a067c5ff2fcdf9cb4620bc92f 100644 --- a/test/a64/traces/sim-frecps-4s-trace-a64.h +++ b/test/a64/traces/sim-frecps-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-d-trace-a64.h b/test/a64/traces/sim-frecps-d-trace-a64.h index 384caac758debe0f3a7c52487d2ed28ddd0010bb..208140df951a0a5a48607b204a3b79d1e275ed1f 100644 --- a/test/a64/traces/sim-frecps-d-trace-a64.h +++ b/test/a64/traces/sim-frecps-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-s-trace-a64.h b/test/a64/traces/sim-frecps-s-trace-a64.h index c00ae0c23db3037e808b8cf07f8dde0f8d367edf..5d38654dc3402963b0b0047544db4d4c7abc07ac 100644 --- a/test/a64/traces/sim-frecps-s-trace-a64.h +++ b/test/a64/traces/sim-frecps-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpx-d-trace-a64.h b/test/a64/traces/sim-frecpx-d-trace-a64.h index 1991f4c4daad236b9e6e732bb97d91022f60781b..6b82dd52a7a69644628951b686983639d67bd81a 100644 --- a/test/a64/traces/sim-frecpx-d-trace-a64.h +++ b/test/a64/traces/sim-frecpx-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpx-s-trace-a64.h b/test/a64/traces/sim-frecpx-s-trace-a64.h index 8194b1bf542c8e49dc5bfbc04d00370eb5e6c1dc..d56c8590e0440e2d077c58414f21f7ea382a8111 100644 --- a/test/a64/traces/sim-frecpx-s-trace-a64.h +++ b/test/a64/traces/sim-frecpx-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-2d-trace-a64.h b/test/a64/traces/sim-frinta-2d-trace-a64.h index 4286d8963adc3bcab45a059a34b126d1dd8846b0..0dd591d49a9fff058f523cb49ddc1000b3c61a07 100644 --- a/test/a64/traces/sim-frinta-2d-trace-a64.h +++ b/test/a64/traces/sim-frinta-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-2s-trace-a64.h b/test/a64/traces/sim-frinta-2s-trace-a64.h index 798a1d0b652d1a6abbe9337008e1c80206288f8a..1658262b89cb7eb04c3ac3038dd0720635c4e935 100644 --- a/test/a64/traces/sim-frinta-2s-trace-a64.h +++ b/test/a64/traces/sim-frinta-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-4s-trace-a64.h b/test/a64/traces/sim-frinta-4s-trace-a64.h index 2b609986c84e684ed31ff18418c2d786bb68957e..27a0bc5d7e74c3ea29718e1c0362a688cab80efe 100644 --- a/test/a64/traces/sim-frinta-4s-trace-a64.h +++ b/test/a64/traces/sim-frinta-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-d-trace-a64.h b/test/a64/traces/sim-frinta-d-trace-a64.h index 53e8d29a7104f649ccb34f75a99cfa516056c8b1..e4395da04e5b16e07a0f7de8f3b3859ab83bcb08 100644 --- a/test/a64/traces/sim-frinta-d-trace-a64.h +++ b/test/a64/traces/sim-frinta-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-s-trace-a64.h b/test/a64/traces/sim-frinta-s-trace-a64.h index cd65c4ae420ad2f2afd3771cfd4e360d2d8dc32d..3c7e203ad6b8f9fdd5a925ac41126d23eb8ca919 100644 --- a/test/a64/traces/sim-frinta-s-trace-a64.h +++ b/test/a64/traces/sim-frinta-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-2d-trace-a64.h b/test/a64/traces/sim-frinti-2d-trace-a64.h index 29bdec01f999070649a4bd16fcc5a666f0d11706..c3fcfa8d8e5eb2d2be9da07429997af0b6525662 100644 --- a/test/a64/traces/sim-frinti-2d-trace-a64.h +++ b/test/a64/traces/sim-frinti-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-2s-trace-a64.h b/test/a64/traces/sim-frinti-2s-trace-a64.h index b3d792010561e4f268c0a782bcab4e75e9773e19..e411676c016c324db9b385bef9268ddc692cf9bb 100644 --- a/test/a64/traces/sim-frinti-2s-trace-a64.h +++ b/test/a64/traces/sim-frinti-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-4s-trace-a64.h b/test/a64/traces/sim-frinti-4s-trace-a64.h index bfbedbf5ca98e1cd50c53371c57a9f9b47991a9e..29e94afa3700eacee0af69228ecb2f1043951f52 100644 --- a/test/a64/traces/sim-frinti-4s-trace-a64.h +++ b/test/a64/traces/sim-frinti-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-d-trace-a64.h b/test/a64/traces/sim-frinti-d-trace-a64.h index 5f21304f262601b4b35b6b165345ebcb8e71ffb4..3fa4ad3f73a72f07770464ce9eb00751981079f1 100644 --- a/test/a64/traces/sim-frinti-d-trace-a64.h +++ b/test/a64/traces/sim-frinti-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-s-trace-a64.h b/test/a64/traces/sim-frinti-s-trace-a64.h index 31894b307aad7dd6e61860fd029d161245a035f2..cf4a109f51c55aaab4c35f5c1a81208d62b880fe 100644 --- a/test/a64/traces/sim-frinti-s-trace-a64.h +++ b/test/a64/traces/sim-frinti-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-2d-trace-a64.h b/test/a64/traces/sim-frintm-2d-trace-a64.h index 686813b7b684dcb90cd93a7d98cb987f94b60785..663e60beb74d2a3c6c9326e81aab117ec8b4a589 100644 --- a/test/a64/traces/sim-frintm-2d-trace-a64.h +++ b/test/a64/traces/sim-frintm-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-2s-trace-a64.h b/test/a64/traces/sim-frintm-2s-trace-a64.h index dd9e5128d6e9afc704e126b54b4670979615991f..3f4940fde0d4e0cc79bb010ab019648ac8d5e33c 100644 --- a/test/a64/traces/sim-frintm-2s-trace-a64.h +++ b/test/a64/traces/sim-frintm-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-4s-trace-a64.h b/test/a64/traces/sim-frintm-4s-trace-a64.h index 707283ceeb5ea2cee6eb6b1fd37599b738b8a19f..8905e8d46523f0c79cb059c0b85400c4d2ecdf57 100644 --- a/test/a64/traces/sim-frintm-4s-trace-a64.h +++ b/test/a64/traces/sim-frintm-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-d-trace-a64.h b/test/a64/traces/sim-frintm-d-trace-a64.h index 23d1d1e420e5767fa52821c7d3cdca19e66f7ece..0a32c7c1700042008dfd613a0bb3fae6b40670eb 100644 --- a/test/a64/traces/sim-frintm-d-trace-a64.h +++ b/test/a64/traces/sim-frintm-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-s-trace-a64.h b/test/a64/traces/sim-frintm-s-trace-a64.h index bc2c81035ad92a413125956c645d68c66f1d9d9f..53ea4dd5f457d6248e36463de0d207dc0ae360ab 100644 --- a/test/a64/traces/sim-frintm-s-trace-a64.h +++ b/test/a64/traces/sim-frintm-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-2d-trace-a64.h b/test/a64/traces/sim-frintn-2d-trace-a64.h index 4f147362962904138dd6949e9c4826fd571be695..c4a1e404b5a6f53c87bcb8844df7633e776dd55a 100644 --- a/test/a64/traces/sim-frintn-2d-trace-a64.h +++ b/test/a64/traces/sim-frintn-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-2s-trace-a64.h b/test/a64/traces/sim-frintn-2s-trace-a64.h index 5224365db99e39b79f08f607300a6a08606d0200..09c8b286a4b9271d3fee2fd37bd9fbc37f5a5545 100644 --- a/test/a64/traces/sim-frintn-2s-trace-a64.h +++ b/test/a64/traces/sim-frintn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-4s-trace-a64.h b/test/a64/traces/sim-frintn-4s-trace-a64.h index e14b11646df0225396ce201d6b23855fe2a63f98..3e6a576694633391a9ee56371322e030ebb47401 100644 --- a/test/a64/traces/sim-frintn-4s-trace-a64.h +++ b/test/a64/traces/sim-frintn-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-d-trace-a64.h b/test/a64/traces/sim-frintn-d-trace-a64.h index 597fb3c5e654dd2ca2c35216d98ba490aa0efb1c..5d7d532f9de7d97b15864cee9c23d135987768b0 100644 --- a/test/a64/traces/sim-frintn-d-trace-a64.h +++ b/test/a64/traces/sim-frintn-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-s-trace-a64.h b/test/a64/traces/sim-frintn-s-trace-a64.h index 7ec7cf82ad204db4986367edc7d8329d86ed7fc8..0a3f41f2b14f2ff8fb67fceaef39b51e86c47709 100644 --- a/test/a64/traces/sim-frintn-s-trace-a64.h +++ b/test/a64/traces/sim-frintn-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-2d-trace-a64.h b/test/a64/traces/sim-frintp-2d-trace-a64.h index 51e00f78e8d4af133aa8a58befeaa515e16e5d30..d669ebd3c0eef88c808b16578ce0b045952f101a 100644 --- a/test/a64/traces/sim-frintp-2d-trace-a64.h +++ b/test/a64/traces/sim-frintp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-2s-trace-a64.h b/test/a64/traces/sim-frintp-2s-trace-a64.h index a2140b5dc81901f98a9e0483ff939d2cae3c7379..693a85543b850878077e112482bfc1c3de9766fe 100644 --- a/test/a64/traces/sim-frintp-2s-trace-a64.h +++ b/test/a64/traces/sim-frintp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-4s-trace-a64.h b/test/a64/traces/sim-frintp-4s-trace-a64.h index 2d5376fb15ca07911764093e13f39f6ff53ba912..28ad4b9874a0b86c139b02d7ac1be77fd0112c3b 100644 --- a/test/a64/traces/sim-frintp-4s-trace-a64.h +++ b/test/a64/traces/sim-frintp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-d-trace-a64.h b/test/a64/traces/sim-frintp-d-trace-a64.h index 98f05676da8547c7416b467d8248272fbc0437a5..6dde88363b621176f90799af9f0182d6064bcc86 100644 --- a/test/a64/traces/sim-frintp-d-trace-a64.h +++ b/test/a64/traces/sim-frintp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-s-trace-a64.h b/test/a64/traces/sim-frintp-s-trace-a64.h index 35bfe6fca4bbc6989ec37e11ffcd40a04222eeec..393080ba0605129572d517b5a4ab269c776146fa 100644 --- a/test/a64/traces/sim-frintp-s-trace-a64.h +++ b/test/a64/traces/sim-frintp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-2d-trace-a64.h b/test/a64/traces/sim-frintx-2d-trace-a64.h index 8e2e31386ed271ddbd703e6599179ef099bdb49b..813a002e243e1866068526e33bbf0990a20e3ba9 100644 --- a/test/a64/traces/sim-frintx-2d-trace-a64.h +++ b/test/a64/traces/sim-frintx-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-2s-trace-a64.h b/test/a64/traces/sim-frintx-2s-trace-a64.h index 1d0b68638bbeee4ca4d01e8fc419f90a5accf5be..3c5190ec2df153835c9e0582de030c22a14d7de2 100644 --- a/test/a64/traces/sim-frintx-2s-trace-a64.h +++ b/test/a64/traces/sim-frintx-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-4s-trace-a64.h b/test/a64/traces/sim-frintx-4s-trace-a64.h index 49a5c518b82c7b0314e15bf4991310ad5f863a71..c26fb61b1f5ab02557994fb4f41771e6f8b8d1c9 100644 --- a/test/a64/traces/sim-frintx-4s-trace-a64.h +++ b/test/a64/traces/sim-frintx-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-d-trace-a64.h b/test/a64/traces/sim-frintx-d-trace-a64.h index b07b264392b98a606f3de918eb2bbdb5e5b63744..b8aef2c9adf3ed21d77adc183071d69477405d9f 100644 --- a/test/a64/traces/sim-frintx-d-trace-a64.h +++ b/test/a64/traces/sim-frintx-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-s-trace-a64.h b/test/a64/traces/sim-frintx-s-trace-a64.h index 1c8f4f3ead4af3825462ec94168a856e60d28853..8c2f976da7c95aa9b4c781b0a8737a8ae4616072 100644 --- a/test/a64/traces/sim-frintx-s-trace-a64.h +++ b/test/a64/traces/sim-frintx-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-2d-trace-a64.h b/test/a64/traces/sim-frintz-2d-trace-a64.h index f84a844f47c13ebd4f30403484cb3b374eae331e..f1d9df6c419369e287f6ec063d65a2d524da0e9a 100644 --- a/test/a64/traces/sim-frintz-2d-trace-a64.h +++ b/test/a64/traces/sim-frintz-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-2s-trace-a64.h b/test/a64/traces/sim-frintz-2s-trace-a64.h index e49651ad08239b4305c6296b55187dd27a182640..9dd1709a6f9e592734127e6ef186afd23bf1e8a2 100644 --- a/test/a64/traces/sim-frintz-2s-trace-a64.h +++ b/test/a64/traces/sim-frintz-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-4s-trace-a64.h b/test/a64/traces/sim-frintz-4s-trace-a64.h index 168963152e2cc116ce75d4a41f62c03a8f3f4230..171783204074e9b55c37b7c7d51e04f970b2cba0 100644 --- a/test/a64/traces/sim-frintz-4s-trace-a64.h +++ b/test/a64/traces/sim-frintz-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-d-trace-a64.h b/test/a64/traces/sim-frintz-d-trace-a64.h index e3d939a15da48393bffa8cc3b6af75d886ff68be..d35fc440129e839706bf004469a53006668fa0a8 100644 --- a/test/a64/traces/sim-frintz-d-trace-a64.h +++ b/test/a64/traces/sim-frintz-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-s-trace-a64.h b/test/a64/traces/sim-frintz-s-trace-a64.h index d00b77d337d88e447893e5d9774bebe4d3fa9e87..b8c049b5aab0640cdb356a2faa528832a19e13a1 100644 --- a/test/a64/traces/sim-frintz-s-trace-a64.h +++ b/test/a64/traces/sim-frintz-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-2d-trace-a64.h b/test/a64/traces/sim-frsqrte-2d-trace-a64.h index 2f7a55ff143a7a04dc1a06925f145a5c907f8f60..2007cfb371a2c26cb766ee43eb9ba8b253c33f3e 100644 --- a/test/a64/traces/sim-frsqrte-2d-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-2s-trace-a64.h b/test/a64/traces/sim-frsqrte-2s-trace-a64.h index 8b764f55c5b4c2670661947e9209eb3250edd301..da40a84c9ef16dacdc5cfcd23f861e7da31e3eed 100644 --- a/test/a64/traces/sim-frsqrte-2s-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-4s-trace-a64.h b/test/a64/traces/sim-frsqrte-4s-trace-a64.h index 97d345dbee921dd6784fa48835246758ad248299..9d95d1010638069514550160c8b6f7c922f37a67 100644 --- a/test/a64/traces/sim-frsqrte-4s-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-d-trace-a64.h b/test/a64/traces/sim-frsqrte-d-trace-a64.h index 85e83627f5c1d9cdc581d7c4a51f8c619506f722..afdbb3031f43a6e373bbd70b65456476c35e5261 100644 --- a/test/a64/traces/sim-frsqrte-d-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-s-trace-a64.h b/test/a64/traces/sim-frsqrte-s-trace-a64.h index 067bac0ce258151b3deef178918ac97793cfeb6a..22e4609938dccbce8a8a3009d93746221866f548 100644 --- a/test/a64/traces/sim-frsqrte-s-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-2d-trace-a64.h b/test/a64/traces/sim-frsqrts-2d-trace-a64.h index d90f1d3551ba48bf1d5995712e1db27f37609e89..fd97991afbb1b8d339dc8ac36b48b25a6e642399 100644 --- a/test/a64/traces/sim-frsqrts-2d-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-2s-trace-a64.h b/test/a64/traces/sim-frsqrts-2s-trace-a64.h index 5f703c4fd227731bd4f00ae3a7cd91e2ff4a16c7..aae3987d2b82a94862964ddad3658af9281f21fd 100644 --- a/test/a64/traces/sim-frsqrts-2s-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-4s-trace-a64.h b/test/a64/traces/sim-frsqrts-4s-trace-a64.h index 04814073b8e7babb16b7ae44b4570acfb485d457..cc2a5a35688added058d9597c9868ff79e8d6cdb 100644 --- a/test/a64/traces/sim-frsqrts-4s-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-d-trace-a64.h b/test/a64/traces/sim-frsqrts-d-trace-a64.h index 9fa4a7474dd20812924ff9be2028a03e64cf62e0..bddbd3f7b1629a2e8a3936af398f13ff0c72d08e 100644 --- a/test/a64/traces/sim-frsqrts-d-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-s-trace-a64.h b/test/a64/traces/sim-frsqrts-s-trace-a64.h index 64bf1918978e203c33310990d399c1ee84e64d3c..55c420c72861842426ad6be8b0f50e4a08e637cb 100644 --- a/test/a64/traces/sim-frsqrts-s-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-2d-trace-a64.h b/test/a64/traces/sim-fsqrt-2d-trace-a64.h index f442ca9a7c197824cfa4c70c327c84c5fcf75226..4781230929352484fd31546febbc7bf5ab03748d 100644 --- a/test/a64/traces/sim-fsqrt-2d-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-2s-trace-a64.h b/test/a64/traces/sim-fsqrt-2s-trace-a64.h index 2c3f278b8c24673f66a9989f5fb75a5b931ba160..aaee8eaf8b781538f01e16ed3135a863601673b4 100644 --- a/test/a64/traces/sim-fsqrt-2s-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-4s-trace-a64.h b/test/a64/traces/sim-fsqrt-4s-trace-a64.h index 9d4486c04ac4ce7d2ae8151bb13f85c1cd97b1c2..3515c8a8223906c92f1ca265cedd4221eff8b7e7 100644 --- a/test/a64/traces/sim-fsqrt-4s-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-d-trace-a64.h b/test/a64/traces/sim-fsqrt-d-trace-a64.h index 4eb9af449d2c8aaeb451dccbd9c158e4575793c9..df43b00e0cc035e18422dce7812f645e89fc2d33 100644 --- a/test/a64/traces/sim-fsqrt-d-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-s-trace-a64.h b/test/a64/traces/sim-fsqrt-s-trace-a64.h index 561ca770759ec4ee570dfa71a59958c589da1dc6..16195df2e6b2f6fd08272d3a44c6744a38e5ce94 100644 --- a/test/a64/traces/sim-fsqrt-s-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-2d-trace-a64.h b/test/a64/traces/sim-fsub-2d-trace-a64.h index 5982c5a6e68f6f3a2696899844dd4958c4270410..8dbdf34e30ff0daf21808fbe6b5cf5334107433e 100644 --- a/test/a64/traces/sim-fsub-2d-trace-a64.h +++ b/test/a64/traces/sim-fsub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-2s-trace-a64.h b/test/a64/traces/sim-fsub-2s-trace-a64.h index d1ae7b09e5d22d3a5afe1147bdcb906f67d7b917..e8e9d2d76c63fc02fac08454153c54c38caf051b 100644 --- a/test/a64/traces/sim-fsub-2s-trace-a64.h +++ b/test/a64/traces/sim-fsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-4s-trace-a64.h b/test/a64/traces/sim-fsub-4s-trace-a64.h index ab7a53a23137437d6167d218eec141a9d10df994..dde394285c5070b6c8559f76dd804375e13e118d 100644 --- a/test/a64/traces/sim-fsub-4s-trace-a64.h +++ b/test/a64/traces/sim-fsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-d-trace-a64.h b/test/a64/traces/sim-fsub-d-trace-a64.h index 6c84a3f9c9b75d85cf9d28f7936a17bb9915624c..f1ae7699aeae92f00fc09ca6d0338403d65c1efe 100644 --- a/test/a64/traces/sim-fsub-d-trace-a64.h +++ b/test/a64/traces/sim-fsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-s-trace-a64.h b/test/a64/traces/sim-fsub-s-trace-a64.h index 1029a0ca2f26c3ad31ce0e23a7482b07b4786c78..d6c98f5e6b51aff9ba728ec2847b2b39f0ba9a31 100644 --- a/test/a64/traces/sim-fsub-s-trace-a64.h +++ b/test/a64/traces/sim-fsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-b-trace-a64.h b/test/a64/traces/sim-ins-b-trace-a64.h index 6232d6a6c0a976d7cf41670394048dd44bae8bac..8cb66b457f2056e575757eca952dcf916b68fdf1 100644 --- a/test/a64/traces/sim-ins-b-trace-a64.h +++ b/test/a64/traces/sim-ins-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-d-trace-a64.h b/test/a64/traces/sim-ins-d-trace-a64.h index 91c54f025270ca1e30d8fcaeb928c40f6503f07d..78f4dfc29afb3d0e989655401c8d244ced11b0c3 100644 --- a/test/a64/traces/sim-ins-d-trace-a64.h +++ b/test/a64/traces/sim-ins-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-h-trace-a64.h b/test/a64/traces/sim-ins-h-trace-a64.h index 0ec1dd590fff5c243c4b94720c078a5bc6591c87..84c8a5d51197bd220f2cb590620b7c6c0c88ab5d 100644 --- a/test/a64/traces/sim-ins-h-trace-a64.h +++ b/test/a64/traces/sim-ins-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-s-trace-a64.h b/test/a64/traces/sim-ins-s-trace-a64.h index 7057eaa5026dcf1ecaaf8a668ad9b2945297e35e..5fc3db7404769cb9a09b153ae584896681bf75de 100644 --- a/test/a64/traces/sim-ins-s-trace-a64.h +++ b/test/a64/traces/sim-ins-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-16b-trace-a64.h b/test/a64/traces/sim-mla-16b-trace-a64.h index 739fa8a9be54f90ec001329a6cd949a83427f72d..13edeec35b1ce592decedd3f343802b25c6d6054 100644 --- a/test/a64/traces/sim-mla-16b-trace-a64.h +++ b/test/a64/traces/sim-mla-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h b/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h index 6088487f09c934f7dce5ef91db812e17e308d009..ccc7250360d323a201ad242577ed60988f235a60 100644 --- a/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-2s-trace-a64.h b/test/a64/traces/sim-mla-2s-trace-a64.h index 83d786c3f92e6f41c8901ff31d4eab9d732b4971..39b1ff65236d59887f8e0108bb3b09aa19f5642d 100644 --- a/test/a64/traces/sim-mla-2s-trace-a64.h +++ b/test/a64/traces/sim-mla-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h b/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h index fcfe502554e51b9758d2a26da3090c8318487a9d..0fc31bca40f4d564ae6456557ba5d304a40a3088 100644 --- a/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4h-trace-a64.h b/test/a64/traces/sim-mla-4h-trace-a64.h index 0f32e20bcbc767d0e447fbf762b605d4906a3f55..cc9b984cb28a4498818950df09f7ab496cb185e4 100644 --- a/test/a64/traces/sim-mla-4h-trace-a64.h +++ b/test/a64/traces/sim-mla-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h b/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h index 1b67c3632d5472e68f28fe7f798afeb90724efad..cee1f7d27f3a4eb929f4e287764c8b41e6924fb1 100644 --- a/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4s-trace-a64.h b/test/a64/traces/sim-mla-4s-trace-a64.h index 85d24e95ad7e0569b41aa36134ad812f374cadf7..6cd44a455dd88916a334787b8a7fcd0182220f51 100644 --- a/test/a64/traces/sim-mla-4s-trace-a64.h +++ b/test/a64/traces/sim-mla-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-8b-trace-a64.h b/test/a64/traces/sim-mla-8b-trace-a64.h index c67cfa761f277d2307d37e58d619fdfdac4679da..28e34eda48f148b987bf68ee163bcfc5a2db01b2 100644 --- a/test/a64/traces/sim-mla-8b-trace-a64.h +++ b/test/a64/traces/sim-mla-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h b/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h index 9cf9af5ab66a59295f432c8b201dda127121bbca..8a627411a1f6eb24950432445d546760225f68cf 100644 --- a/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-8h-trace-a64.h b/test/a64/traces/sim-mla-8h-trace-a64.h index fe480919e8169122bf11c099b3a20082d8ca90ac..25ef05421ebc96bdf27ac1bca864222e66951b7f 100644 --- a/test/a64/traces/sim-mla-8h-trace-a64.h +++ b/test/a64/traces/sim-mla-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-16b-trace-a64.h b/test/a64/traces/sim-mls-16b-trace-a64.h index ca5ba78251a8cfdf4bbc2a42418d42c581fffb33..a82c82ca013a964498b28d4323fe164e016b888f 100644 --- a/test/a64/traces/sim-mls-16b-trace-a64.h +++ b/test/a64/traces/sim-mls-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h b/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h index 18e2bc7ca809914e0a10cecd9135d1fcfab4122e..e1489243c8e8f074af063cc2fe62ab0396d8ad5a 100644 --- a/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-2s-trace-a64.h b/test/a64/traces/sim-mls-2s-trace-a64.h index 9400b0371e628d63fed87ea038f3a998ffc34ba5..59d7bae28f266ba7fd892359a8cd565fb3a9d37f 100644 --- a/test/a64/traces/sim-mls-2s-trace-a64.h +++ b/test/a64/traces/sim-mls-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h b/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h index 0707a0906bdbb11e1691033a87232432822b332b..15c707e137220579cfd78de6a3cbae7f023bb1a4 100644 --- a/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4h-trace-a64.h b/test/a64/traces/sim-mls-4h-trace-a64.h index db4d0b1a383262774c0bbde2b24f070f833892c8..16cc60989d9ea112ee369682815dcfa3c9d9e67b 100644 --- a/test/a64/traces/sim-mls-4h-trace-a64.h +++ b/test/a64/traces/sim-mls-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h b/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h index 710991857cebf0eb0d67fb898896c8023ec997ea..9e4f104bec2c167696174d494f7963f60a2e1c6d 100644 --- a/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4s-trace-a64.h b/test/a64/traces/sim-mls-4s-trace-a64.h index 97cc5705b88e8915d49e9b260123210310388b62..dc9cb451f68f02793e86a99be74eba66407aaa63 100644 --- a/test/a64/traces/sim-mls-4s-trace-a64.h +++ b/test/a64/traces/sim-mls-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-8b-trace-a64.h b/test/a64/traces/sim-mls-8b-trace-a64.h index 6f6a2e0278b45e6346292cb4100868c0a75ffc45..96662abb817805c985a23ea04cbdb027e200d200 100644 --- a/test/a64/traces/sim-mls-8b-trace-a64.h +++ b/test/a64/traces/sim-mls-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h b/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h index 8e3175d0481378c34d41c53cd439f954fce29466..2b8b7ab8aa5472046c4d82c0b4cf240952cb0214 100644 --- a/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-8h-trace-a64.h b/test/a64/traces/sim-mls-8h-trace-a64.h index ca4d32f59f44e096fa5c540fd676fac83387c10e..3fbc7a06bdc82a30c75b9421ca6813d2b88fe9e2 100644 --- a/test/a64/traces/sim-mls-8h-trace-a64.h +++ b/test/a64/traces/sim-mls-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-16b-trace-a64.h b/test/a64/traces/sim-mul-16b-trace-a64.h index 3f32e22f711ba7331ada1f3a9b27d641114190d0..cf1fdd128b227fbd3daaee22b30cbb457a488e26 100644 --- a/test/a64/traces/sim-mul-16b-trace-a64.h +++ b/test/a64/traces/sim-mul-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h b/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h index 6dd81ef4afb9449301ac1c6704ddc624e60b784f..cd463d13d6aa95307dc633ff384c68422828b44b 100644 --- a/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-2s-trace-a64.h b/test/a64/traces/sim-mul-2s-trace-a64.h index 35e051c498378bd02b5adae7ba684785678623b5..60cd330aad534eb432f60936c91ebd87c9e7ff3c 100644 --- a/test/a64/traces/sim-mul-2s-trace-a64.h +++ b/test/a64/traces/sim-mul-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h b/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h index bb381271fbc84064fcc2c42a0cda5644225191ed..be00e9695e41c3aed3d9523620b77bd0ac2fdca2 100644 --- a/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4h-trace-a64.h b/test/a64/traces/sim-mul-4h-trace-a64.h index e041eddba29600a55bdef2088936101b9723d389..ef917e4dc15f8a56d24a8f7603506cd43c3b6bb9 100644 --- a/test/a64/traces/sim-mul-4h-trace-a64.h +++ b/test/a64/traces/sim-mul-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h b/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h index e772eef561764dec30f610d44444437dad837e85..8159edd1652c0c6f3ca7ddd099c2b1331b26bb56 100644 --- a/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4s-trace-a64.h b/test/a64/traces/sim-mul-4s-trace-a64.h index 97fd28ebe490ec1d82cb76208a6b4cec4990d68e..60a04b025db36cada27cc7407394befd4724601d 100644 --- a/test/a64/traces/sim-mul-4s-trace-a64.h +++ b/test/a64/traces/sim-mul-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-8b-trace-a64.h b/test/a64/traces/sim-mul-8b-trace-a64.h index b9aa2b11695c6ac927c0e7574ab303bd165c77a0..6ac055216fa9596f0f243e56bf41b52c15cbba57 100644 --- a/test/a64/traces/sim-mul-8b-trace-a64.h +++ b/test/a64/traces/sim-mul-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h b/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h index 04aa4b58fba09c9da22236e9a120d7e59ce66796..d7d8a8b7e7d6e1c9c93b193c11c8d4078e3864a1 100644 --- a/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-8h-trace-a64.h b/test/a64/traces/sim-mul-8h-trace-a64.h index cbb0f56dc90d3e345c89627608920cc0ed16cde6..481b683ecb4c74e33fd1e2216fcb6858ceec9ecc 100644 --- a/test/a64/traces/sim-mul-8h-trace-a64.h +++ b/test/a64/traces/sim-mul-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-16b-trace-a64.h b/test/a64/traces/sim-neg-16b-trace-a64.h index eabf84666875a529a7266b5952aee2d422bd84f6..2e62f45c047844db418acbdab99cf6dfdecc9362 100644 --- a/test/a64/traces/sim-neg-16b-trace-a64.h +++ b/test/a64/traces/sim-neg-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-2d-trace-a64.h b/test/a64/traces/sim-neg-2d-trace-a64.h index 201899d32771ce7eaf51aea59083e0733e3eb720..1da604300d5975c3d05ab00cb1e0d2e8bc5f6aff 100644 --- a/test/a64/traces/sim-neg-2d-trace-a64.h +++ b/test/a64/traces/sim-neg-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-2s-trace-a64.h b/test/a64/traces/sim-neg-2s-trace-a64.h index f90a8e9ad965b7d1f5408dd86ad6d4f68c1fd61b..9168acc9c21f6ef5d7d5511600029325bc7ffd0a 100644 --- a/test/a64/traces/sim-neg-2s-trace-a64.h +++ b/test/a64/traces/sim-neg-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-4h-trace-a64.h b/test/a64/traces/sim-neg-4h-trace-a64.h index 1b4ffb138149de2265b94bc750b3c438f98ebd4c..222f7de1e239ef19539cd0d20ffbd960a9e2d21f 100644 --- a/test/a64/traces/sim-neg-4h-trace-a64.h +++ b/test/a64/traces/sim-neg-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-4s-trace-a64.h b/test/a64/traces/sim-neg-4s-trace-a64.h index b7384c224e0840fa0f9b40c2d100321d329edb90..e6c0413584070f62c0d3d8f80169e08942d2e837 100644 --- a/test/a64/traces/sim-neg-4s-trace-a64.h +++ b/test/a64/traces/sim-neg-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-8b-trace-a64.h b/test/a64/traces/sim-neg-8b-trace-a64.h index 54683c4f46f94337eaf3fd2e2ad4e92717da3237..e77c30c029944e03dbe0ff45784b6f5fef984c73 100644 --- a/test/a64/traces/sim-neg-8b-trace-a64.h +++ b/test/a64/traces/sim-neg-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-8h-trace-a64.h b/test/a64/traces/sim-neg-8h-trace-a64.h index 67e93a39e3a911b4b8318ee723299cd0bdafc5fb..1ed65683597b2108ee8aa0a175c337ec6b0e4f3f 100644 --- a/test/a64/traces/sim-neg-8h-trace-a64.h +++ b/test/a64/traces/sim-neg-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-d-trace-a64.h b/test/a64/traces/sim-neg-d-trace-a64.h index a7b2c7d7af2bdf610057a7fda75239cd3043f4d9..6b72d49017923731d8930f30d798423207a61ea6 100644 --- a/test/a64/traces/sim-neg-d-trace-a64.h +++ b/test/a64/traces/sim-neg-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-not--16b-trace-a64.h b/test/a64/traces/sim-not--16b-trace-a64.h index b85ab90a15597e8653c7d80a0ae533a57d9ff0d2..e1c3965bb95947fa148388ea5c0ec296238d9ba6 100644 --- a/test/a64/traces/sim-not--16b-trace-a64.h +++ b/test/a64/traces/sim-not--16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-not--8b-trace-a64.h b/test/a64/traces/sim-not--8b-trace-a64.h index 2aa69777339481fd0d0fad63763735030215d936..5b49a009afd2aef978bee164adcfd4fae7ca134e 100644 --- a/test/a64/traces/sim-not--8b-trace-a64.h +++ b/test/a64/traces/sim-not--8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orn-16b-trace-a64.h b/test/a64/traces/sim-orn-16b-trace-a64.h index 4ba6425bf671ab073894eb2c0f97062469c27f57..8b4b8052138ca1c3c406b9fc619d47b709624381 100644 --- a/test/a64/traces/sim-orn-16b-trace-a64.h +++ b/test/a64/traces/sim-orn-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orn-8b-trace-a64.h b/test/a64/traces/sim-orn-8b-trace-a64.h index c4e9d416c19cac200574bd6afecb629e344bf95d..c5d79210b2ca6b36d9582b63c3bdf1acabf51be8 100644 --- a/test/a64/traces/sim-orn-8b-trace-a64.h +++ b/test/a64/traces/sim-orn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orr-16b-trace-a64.h b/test/a64/traces/sim-orr-16b-trace-a64.h index 8771145d401f8d54d0db089d01b0903ab9944c5e..0a2ae6279b8bb5583fded59b2e805a744410752a 100644 --- a/test/a64/traces/sim-orr-16b-trace-a64.h +++ b/test/a64/traces/sim-orr-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orr-8b-trace-a64.h b/test/a64/traces/sim-orr-8b-trace-a64.h index 7f6d349fde5fe58836a3a39a62a8baa6bdce200f..22b5386f78542ed3de2a8c5985b5f8d195fa21d5 100644 --- a/test/a64/traces/sim-orr-8b-trace-a64.h +++ b/test/a64/traces/sim-orr-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmul-16b-trace-a64.h b/test/a64/traces/sim-pmul-16b-trace-a64.h index 1092c5c22a164ee80ea6fa88d9a564a940ee523e..5c5353480773f9f94430f177cd99313db85cce7a 100644 --- a/test/a64/traces/sim-pmul-16b-trace-a64.h +++ b/test/a64/traces/sim-pmul-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmul-8b-trace-a64.h b/test/a64/traces/sim-pmul-8b-trace-a64.h index 7fa9a19fcb17303a7491362975638f98703488df..b96c3d1939b4817e77f95f08652d113890e8250f 100644 --- a/test/a64/traces/sim-pmul-8b-trace-a64.h +++ b/test/a64/traces/sim-pmul-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmull-8h-trace-a64.h b/test/a64/traces/sim-pmull-8h-trace-a64.h index 243cf8615d243dcf3284e9c0f754f71ea0ba25dd..c45e72056c3e0a95434eda9c9b97ef3766f4238e 100644 --- a/test/a64/traces/sim-pmull-8h-trace-a64.h +++ b/test/a64/traces/sim-pmull-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmull2-8h-trace-a64.h b/test/a64/traces/sim-pmull2-8h-trace-a64.h index 57a2d62e7cb0edb156f7f47b5987105dad349fd8..b022ca3e15e2c530a6c188781ad63641cb7634af 100644 --- a/test/a64/traces/sim-pmull2-8h-trace-a64.h +++ b/test/a64/traces/sim-pmull2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn-2s-trace-a64.h b/test/a64/traces/sim-raddhn-2s-trace-a64.h index fc75c34c58db88ee617f0490723cdfdb5cc947ad..8c4e3e68534e0dab23e0215a4621df2e8d6e5866 100644 --- a/test/a64/traces/sim-raddhn-2s-trace-a64.h +++ b/test/a64/traces/sim-raddhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn-4h-trace-a64.h b/test/a64/traces/sim-raddhn-4h-trace-a64.h index d5dde137d0abd5b8901ca6529ecc27dc2708afb9..9554ca4e906209f643e08aa4efa137184d51e3b5 100644 --- a/test/a64/traces/sim-raddhn-4h-trace-a64.h +++ b/test/a64/traces/sim-raddhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn-8b-trace-a64.h b/test/a64/traces/sim-raddhn-8b-trace-a64.h index 283fc296279558074afdf9bbfe81a2923143d05a..5d383e7fc94982d6860083c5b53ffda6e1592856 100644 --- a/test/a64/traces/sim-raddhn-8b-trace-a64.h +++ b/test/a64/traces/sim-raddhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn2-16b-trace-a64.h b/test/a64/traces/sim-raddhn2-16b-trace-a64.h index 7f209d11d348a3c9d28d068e2177aac5cd8cfdcd..6e6d005df636360cf7b3db6c69dd6a7049c7b224 100644 --- a/test/a64/traces/sim-raddhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-raddhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn2-4s-trace-a64.h b/test/a64/traces/sim-raddhn2-4s-trace-a64.h index d33d9d72357b4c5a94ba9b0411a345c362967d57..0675231b9f8876d4c1c7044bbcb6947068c7bc44 100644 --- a/test/a64/traces/sim-raddhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-raddhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn2-8h-trace-a64.h b/test/a64/traces/sim-raddhn2-8h-trace-a64.h index bb2114c1de91d8c728b804f12e7ba41f2d670146..1068411c61e6d28807685b25373718e59e42eeef 100644 --- a/test/a64/traces/sim-raddhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-raddhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rbit-16b-trace-a64.h b/test/a64/traces/sim-rbit-16b-trace-a64.h index 88a3601def85c2e5bf52e8786cfa6dd4c237ceef..ddc40d89e9b8ef52aa4a001241e736c21830c743 100644 --- a/test/a64/traces/sim-rbit-16b-trace-a64.h +++ b/test/a64/traces/sim-rbit-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rbit-8b-trace-a64.h b/test/a64/traces/sim-rbit-8b-trace-a64.h index f757c994916db328ffcd7bb6bd44679354a20545..3570dddbbb83d311c07b710d7a6b7dac9c1c0b0c 100644 --- a/test/a64/traces/sim-rbit-8b-trace-a64.h +++ b/test/a64/traces/sim-rbit-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev16-16b-trace-a64.h b/test/a64/traces/sim-rev16-16b-trace-a64.h index 2cbc4645fd62cce882e82799c1af6843041d40a4..788251c9e104736872457c3a3087bc7b113b0fec 100644 --- a/test/a64/traces/sim-rev16-16b-trace-a64.h +++ b/test/a64/traces/sim-rev16-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev16-8b-trace-a64.h b/test/a64/traces/sim-rev16-8b-trace-a64.h index d915d54edf9e5c51acff4c424440578cdcc812cd..8d2f6af448a51aeeecfc11ad2ad789c77e0e5f84 100644 --- a/test/a64/traces/sim-rev16-8b-trace-a64.h +++ b/test/a64/traces/sim-rev16-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-16b-trace-a64.h b/test/a64/traces/sim-rev32-16b-trace-a64.h index 913f38f0bb944552848ed9eca4d1b9b1a047899f..dc35d77495a7bafe79690f4ad08c1df4116eb01f 100644 --- a/test/a64/traces/sim-rev32-16b-trace-a64.h +++ b/test/a64/traces/sim-rev32-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-4h-trace-a64.h b/test/a64/traces/sim-rev32-4h-trace-a64.h index 43e283b6c778691902b686165f7ca78fb3a3c44f..59a1bcdae731151aaac394c283c9747732eb6ba6 100644 --- a/test/a64/traces/sim-rev32-4h-trace-a64.h +++ b/test/a64/traces/sim-rev32-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-8b-trace-a64.h b/test/a64/traces/sim-rev32-8b-trace-a64.h index 3b0affca89fdccd8369fe29ad2112e2411372e5e..5f0cd06f5f3e4c3c365323c6459c4dfa01f6ef76 100644 --- a/test/a64/traces/sim-rev32-8b-trace-a64.h +++ b/test/a64/traces/sim-rev32-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-8h-trace-a64.h b/test/a64/traces/sim-rev32-8h-trace-a64.h index 53d8929f8a194cc8bd5d1f898de4a8999de6d595..df7cea93b4cb02b81569aa354e79281c906b13a7 100644 --- a/test/a64/traces/sim-rev32-8h-trace-a64.h +++ b/test/a64/traces/sim-rev32-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-16b-trace-a64.h b/test/a64/traces/sim-rev64-16b-trace-a64.h index 6a29b4cc66b63e0719f8f81cb775f41fb281f012..4fa8ca51b037dd9a6f132b476c230fa56582fe21 100644 --- a/test/a64/traces/sim-rev64-16b-trace-a64.h +++ b/test/a64/traces/sim-rev64-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-2s-trace-a64.h b/test/a64/traces/sim-rev64-2s-trace-a64.h index a1ab4962d46bf8255fcd3f60f081bbf7b3d79790..0f2e6c36f7f57de1c0745dfb778fb60e586641f7 100644 --- a/test/a64/traces/sim-rev64-2s-trace-a64.h +++ b/test/a64/traces/sim-rev64-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-4h-trace-a64.h b/test/a64/traces/sim-rev64-4h-trace-a64.h index 448319468f518465b46baf54cb9bc8baffffc964..54f6cceda75f4deb81eaa4497de777ddd9441898 100644 --- a/test/a64/traces/sim-rev64-4h-trace-a64.h +++ b/test/a64/traces/sim-rev64-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-4s-trace-a64.h b/test/a64/traces/sim-rev64-4s-trace-a64.h index 671637232d7318c39f09bf75faecbdf5e4d57db2..6d859f0a69c2428f143da46f4cd566c924f2cfcc 100644 --- a/test/a64/traces/sim-rev64-4s-trace-a64.h +++ b/test/a64/traces/sim-rev64-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-8b-trace-a64.h b/test/a64/traces/sim-rev64-8b-trace-a64.h index cdc1b6269e3173fa4fa10a755e386ea01d0b3992..5ca8aeaed3cee18a450f3ee15717701743559500 100644 --- a/test/a64/traces/sim-rev64-8b-trace-a64.h +++ b/test/a64/traces/sim-rev64-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-8h-trace-a64.h b/test/a64/traces/sim-rev64-8h-trace-a64.h index a079523d56d2b604defbd6ceb0e5ff49ba64a447..aa8a0237b253f548c6f347002b51caf0c994e84c 100644 --- a/test/a64/traces/sim-rev64-8h-trace-a64.h +++ b/test/a64/traces/sim-rev64-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h index 786a30b10bc67ba3cf0f4f6ead7f105ed52cd5a6..0183a1d22ccaf69645f8a4d811cf03abcddb2333 100644 --- a/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h index 9dbbacacbaa00a53d1a9ff920358a95e77de8a6c..a753e966b7e6a97668eddbc59d695276cfc733d3 100644 --- a/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h index 7d0de81726ec039b2bffbd6061d551c2b77f6d43..db3b101c0c481d4240e3a139c8c8f31cf9cc0360 100644 --- a/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h index b837072359195e0adcbbdd483cd0bef561aa7c4a..b0784e229f010e901f2c123a38c4f2dcbe6e7813 100644 --- a/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h index a1dc00dc2d3acc6eafa591b4b30182008caca8e5..c5da514848976d5503e64461b188328602bb5b24 100644 --- a/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h index d398c516e0dd565611a2257848740a96e554cfbc..783c772411be55cb02688e0d6ed4683a78a79c2b 100644 --- a/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn-2s-trace-a64.h b/test/a64/traces/sim-rsubhn-2s-trace-a64.h index 59bea78f892ac94a57900a577e7905ae7fe17e25..7307f2dd82142e272f7b5ceebdc2f7d874ad9237 100644 --- a/test/a64/traces/sim-rsubhn-2s-trace-a64.h +++ b/test/a64/traces/sim-rsubhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn-4h-trace-a64.h b/test/a64/traces/sim-rsubhn-4h-trace-a64.h index cf4f1997c8063e54a728f934f48846d143e71f0f..24b2ca3545f0a4e2547de19e7d1e21a6514f016b 100644 --- a/test/a64/traces/sim-rsubhn-4h-trace-a64.h +++ b/test/a64/traces/sim-rsubhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn-8b-trace-a64.h b/test/a64/traces/sim-rsubhn-8b-trace-a64.h index 2d17e9ccb30b3262b0a3999807c33656c63e9b60..08f3ce31dd1d27a4f9c92d90b4e3cf7670d19802 100644 --- a/test/a64/traces/sim-rsubhn-8b-trace-a64.h +++ b/test/a64/traces/sim-rsubhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn2-16b-trace-a64.h b/test/a64/traces/sim-rsubhn2-16b-trace-a64.h index 98360f332a31fed9ef6786ba551b7ca0e76b896b..9d5b76ed728ff4f26d94dace3cb124839d981ac0 100644 --- a/test/a64/traces/sim-rsubhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-rsubhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn2-4s-trace-a64.h b/test/a64/traces/sim-rsubhn2-4s-trace-a64.h index f7b83e75878261d98d159c2483e3d17cfb13785e..e86bf2409376bb78e81789c4a9a8f49ec52a5039 100644 --- a/test/a64/traces/sim-rsubhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-rsubhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn2-8h-trace-a64.h b/test/a64/traces/sim-rsubhn2-8h-trace-a64.h index 490c31317f794ea9945ea47895fb1bba524bfa43..b7f07fda88b85817590650fa50059972bd02a1b1 100644 --- a/test/a64/traces/sim-rsubhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-rsubhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-16b-trace-a64.h b/test/a64/traces/sim-saba-16b-trace-a64.h index 61b230c07d7c426077661746f7a09efbf5fb5f85..a95dea8300b7f2347720fb9135db7954712f183d 100644 --- a/test/a64/traces/sim-saba-16b-trace-a64.h +++ b/test/a64/traces/sim-saba-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-2s-trace-a64.h b/test/a64/traces/sim-saba-2s-trace-a64.h index 5d456556557cdbec2b29e9e336719b362686b7b9..e899163cc91d343b017ca258fc72884479ba9e76 100644 --- a/test/a64/traces/sim-saba-2s-trace-a64.h +++ b/test/a64/traces/sim-saba-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-4h-trace-a64.h b/test/a64/traces/sim-saba-4h-trace-a64.h index bfea42660882269a12135fb040ac5b140054d81c..851b8bac0b865f582c1c9802f13fa5678d1b099e 100644 --- a/test/a64/traces/sim-saba-4h-trace-a64.h +++ b/test/a64/traces/sim-saba-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-4s-trace-a64.h b/test/a64/traces/sim-saba-4s-trace-a64.h index 7490dd5a2fc851bd8fccc7d53f00d34345d6924d..8937d686cd8743d61a1f5e8c25ed0a3da7fdcebc 100644 --- a/test/a64/traces/sim-saba-4s-trace-a64.h +++ b/test/a64/traces/sim-saba-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-8b-trace-a64.h b/test/a64/traces/sim-saba-8b-trace-a64.h index e2848ddf16dd6e887b188bac85bbafc6ce8b8ae9..b4d2af18ed70013b610cc35db22710c0860b3d7b 100644 --- a/test/a64/traces/sim-saba-8b-trace-a64.h +++ b/test/a64/traces/sim-saba-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-8h-trace-a64.h b/test/a64/traces/sim-saba-8h-trace-a64.h index a5843df660987c222bf917e2db49bad7576fe239..0f9080b445dd3420a899b490146d8106bbc9c2dd 100644 --- a/test/a64/traces/sim-saba-8h-trace-a64.h +++ b/test/a64/traces/sim-saba-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal-2d-trace-a64.h b/test/a64/traces/sim-sabal-2d-trace-a64.h index c3a18a9924dfa32fd468de8e1cde9ef05673b1b7..1fca3dba79acfb3032103e8fac7cade9c581c989 100644 --- a/test/a64/traces/sim-sabal-2d-trace-a64.h +++ b/test/a64/traces/sim-sabal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal-4s-trace-a64.h b/test/a64/traces/sim-sabal-4s-trace-a64.h index 456f5736ac8e01ea82750ec229055c634ec8dfd8..c66b1c597b58fc48c6aa01ce0392da86652a4798 100644 --- a/test/a64/traces/sim-sabal-4s-trace-a64.h +++ b/test/a64/traces/sim-sabal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal-8h-trace-a64.h b/test/a64/traces/sim-sabal-8h-trace-a64.h index 307bb0cf22551c2ac1beb7587f831fd64ed4aaa3..378613775d86f1461dac2cdfeed5404c2891a154 100644 --- a/test/a64/traces/sim-sabal-8h-trace-a64.h +++ b/test/a64/traces/sim-sabal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal2-2d-trace-a64.h b/test/a64/traces/sim-sabal2-2d-trace-a64.h index ce69974f686ffa8144a7aee36a91835e6c47850c..256cf33f45e7874e13d9793a68663afcb20ee2af 100644 --- a/test/a64/traces/sim-sabal2-2d-trace-a64.h +++ b/test/a64/traces/sim-sabal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal2-4s-trace-a64.h b/test/a64/traces/sim-sabal2-4s-trace-a64.h index 9336414c88826e2a48d9e1c34caabd8a394caffa..8d7c03b4f70e4ede58a0ee15a522f483c1704c91 100644 --- a/test/a64/traces/sim-sabal2-4s-trace-a64.h +++ b/test/a64/traces/sim-sabal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal2-8h-trace-a64.h b/test/a64/traces/sim-sabal2-8h-trace-a64.h index b9c3b4679f6861ef79a5126ae21211b2e6b8613b..c220f62ed1ae2bb67cab3658f332b79c51a2a2ef 100644 --- a/test/a64/traces/sim-sabal2-8h-trace-a64.h +++ b/test/a64/traces/sim-sabal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-16b-trace-a64.h b/test/a64/traces/sim-sabd-16b-trace-a64.h index 58cb43e2f77e533687d944201d5c69210b2e3910..27b3c353d77ed05d49f5e744a11eedbcb9b3ff25 100644 --- a/test/a64/traces/sim-sabd-16b-trace-a64.h +++ b/test/a64/traces/sim-sabd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-2s-trace-a64.h b/test/a64/traces/sim-sabd-2s-trace-a64.h index f4a6aa78099efeaab004d6bec72d76b6e8e24e2d..29d6aec3bc318eab10dff501aa42bffff4c1bd75 100644 --- a/test/a64/traces/sim-sabd-2s-trace-a64.h +++ b/test/a64/traces/sim-sabd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-4h-trace-a64.h b/test/a64/traces/sim-sabd-4h-trace-a64.h index 621f4b64ea816fb77854370f3ae52422efd5777f..ec29a7d84245b90d8de5bb2db868df90608420b0 100644 --- a/test/a64/traces/sim-sabd-4h-trace-a64.h +++ b/test/a64/traces/sim-sabd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-4s-trace-a64.h b/test/a64/traces/sim-sabd-4s-trace-a64.h index 565587a3e86d1b3656adf3571069cd17db2a0c1c..3b1407fb8bfbc39c8699bc91a1a19a758e208a53 100644 --- a/test/a64/traces/sim-sabd-4s-trace-a64.h +++ b/test/a64/traces/sim-sabd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-8b-trace-a64.h b/test/a64/traces/sim-sabd-8b-trace-a64.h index 19dc4a229620138c54d8c2799242c7998f1dff5d..122afd1ce862c07bee540077ecdf340e4198ed65 100644 --- a/test/a64/traces/sim-sabd-8b-trace-a64.h +++ b/test/a64/traces/sim-sabd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-8h-trace-a64.h b/test/a64/traces/sim-sabd-8h-trace-a64.h index a42445acb87d0af62f92b65f607bb292690a45f3..6612f1ed02f838aea5a3efd7692ff83da3481b2e 100644 --- a/test/a64/traces/sim-sabd-8h-trace-a64.h +++ b/test/a64/traces/sim-sabd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl-2d-trace-a64.h b/test/a64/traces/sim-sabdl-2d-trace-a64.h index 3597ab3bf599add831effadf3f8c488f72a3c6f4..7703a40270a4fd2e0664b46622333aad1276e2ad 100644 --- a/test/a64/traces/sim-sabdl-2d-trace-a64.h +++ b/test/a64/traces/sim-sabdl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl-4s-trace-a64.h b/test/a64/traces/sim-sabdl-4s-trace-a64.h index 6cea86b93a5847c67ebcfd5c97cb066db719afdf..2be19dee70fc4308a45e2c5bc36a6afd1bee8957 100644 --- a/test/a64/traces/sim-sabdl-4s-trace-a64.h +++ b/test/a64/traces/sim-sabdl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl-8h-trace-a64.h b/test/a64/traces/sim-sabdl-8h-trace-a64.h index 324dc57f12dd1c95ffe0020b55697288e78ef9f2..6ed521e0714dde01084a632d801c600cd9ae37f2 100644 --- a/test/a64/traces/sim-sabdl-8h-trace-a64.h +++ b/test/a64/traces/sim-sabdl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl2-2d-trace-a64.h b/test/a64/traces/sim-sabdl2-2d-trace-a64.h index 0094ea30aa3307c01f4f143c89cf6f1edce6e387..e7f25be5481db879d3fcf4f1c028500e0b805864 100644 --- a/test/a64/traces/sim-sabdl2-2d-trace-a64.h +++ b/test/a64/traces/sim-sabdl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl2-4s-trace-a64.h b/test/a64/traces/sim-sabdl2-4s-trace-a64.h index 029f73f0df538800b0f415c383af0647da06508f..ce98c9be4b2e05b85330348c5d869312ef207d68 100644 --- a/test/a64/traces/sim-sabdl2-4s-trace-a64.h +++ b/test/a64/traces/sim-sabdl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl2-8h-trace-a64.h b/test/a64/traces/sim-sabdl2-8h-trace-a64.h index e5e9b89c16fd50e14a25b5a9c0a52de95431d1eb..8698a4a80d10ed331d9c709a616598eee5228e05 100644 --- a/test/a64/traces/sim-sabdl2-8h-trace-a64.h +++ b/test/a64/traces/sim-sabdl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-1d-trace-a64.h b/test/a64/traces/sim-sadalp-1d-trace-a64.h index 47445a9c25fc2b1305c644991798c412b8878308..50411b29c2c40b3cbf55e1f34841db084232803b 100644 --- a/test/a64/traces/sim-sadalp-1d-trace-a64.h +++ b/test/a64/traces/sim-sadalp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-2d-trace-a64.h b/test/a64/traces/sim-sadalp-2d-trace-a64.h index 434038c919f4148fd1ef40c059efe9de3c6aad40..a6f7abab7324e0b0f7be457e3c40b3b067db229e 100644 --- a/test/a64/traces/sim-sadalp-2d-trace-a64.h +++ b/test/a64/traces/sim-sadalp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-2s-trace-a64.h b/test/a64/traces/sim-sadalp-2s-trace-a64.h index 3c2f75891eed5243ee377b1354477114af9783d8..7d5f6f658810c1df116d9945a3d8b8f7f17ea0c8 100644 --- a/test/a64/traces/sim-sadalp-2s-trace-a64.h +++ b/test/a64/traces/sim-sadalp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-4h-trace-a64.h b/test/a64/traces/sim-sadalp-4h-trace-a64.h index cc6ae82c7ae88baf54b5746d0a37bd640796cc01..1e73a5c0a051b51bbf393be1a0de86b6b2853cd2 100644 --- a/test/a64/traces/sim-sadalp-4h-trace-a64.h +++ b/test/a64/traces/sim-sadalp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-4s-trace-a64.h b/test/a64/traces/sim-sadalp-4s-trace-a64.h index 548c4ad81ccaabc5793071dcec0eab0d1874b531..33281c4f015ca5a54ab1e19d6d83d118980ebf8a 100644 --- a/test/a64/traces/sim-sadalp-4s-trace-a64.h +++ b/test/a64/traces/sim-sadalp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-8h-trace-a64.h b/test/a64/traces/sim-sadalp-8h-trace-a64.h index 69233627aa4f6e21cea3124199d3da882bbc7683..791b2e7f7b5dcfec3e06ee4cf8feef04157c9ca3 100644 --- a/test/a64/traces/sim-sadalp-8h-trace-a64.h +++ b/test/a64/traces/sim-sadalp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl-2d-trace-a64.h b/test/a64/traces/sim-saddl-2d-trace-a64.h index ef9d7ee9f4da653cc63736ad0d0dfc1fd67a668b..012507d2d43e77d93b193ae1d400355a6dc86d5d 100644 --- a/test/a64/traces/sim-saddl-2d-trace-a64.h +++ b/test/a64/traces/sim-saddl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl-4s-trace-a64.h b/test/a64/traces/sim-saddl-4s-trace-a64.h index 07fa6e9b97069205a9979bef69f408d307e594a4..0b06f4256d9c9515413adc06ddde465f5d787975 100644 --- a/test/a64/traces/sim-saddl-4s-trace-a64.h +++ b/test/a64/traces/sim-saddl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl-8h-trace-a64.h b/test/a64/traces/sim-saddl-8h-trace-a64.h index b81669379cbf4915dfd818e1238427309c966a23..53d311315df82be41aee12ef880bd205f24ce416 100644 --- a/test/a64/traces/sim-saddl-8h-trace-a64.h +++ b/test/a64/traces/sim-saddl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl2-2d-trace-a64.h b/test/a64/traces/sim-saddl2-2d-trace-a64.h index 8fd7f6f8fc8041b4549f2855f6ce53a36ed168bb..a19cf06ace45bbf8ff102a6417e938ee92ae9d8b 100644 --- a/test/a64/traces/sim-saddl2-2d-trace-a64.h +++ b/test/a64/traces/sim-saddl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl2-4s-trace-a64.h b/test/a64/traces/sim-saddl2-4s-trace-a64.h index 9fb4bf4f55b78aa0742e4d610643349f17d8309e..f5a25bc93afa69ff70ae984fb3c2b48c7efd3e37 100644 --- a/test/a64/traces/sim-saddl2-4s-trace-a64.h +++ b/test/a64/traces/sim-saddl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl2-8h-trace-a64.h b/test/a64/traces/sim-saddl2-8h-trace-a64.h index e8be84a469162db53a7fb876880a6418394e9531..b79e98787544b32cd578a5f65b3b0141d67dd5cf 100644 --- a/test/a64/traces/sim-saddl2-8h-trace-a64.h +++ b/test/a64/traces/sim-saddl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-1d-trace-a64.h b/test/a64/traces/sim-saddlp-1d-trace-a64.h index f57030aedbd8c03356e11e0018de92873ddabd7d..adafcab40e512fffc38a758f523e479b1873b764 100644 --- a/test/a64/traces/sim-saddlp-1d-trace-a64.h +++ b/test/a64/traces/sim-saddlp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-2d-trace-a64.h b/test/a64/traces/sim-saddlp-2d-trace-a64.h index 0257555198973530b679be4f63cae6ad4a765bac..0a788b59054dbbf5b605faaa29e9541b73603cc4 100644 --- a/test/a64/traces/sim-saddlp-2d-trace-a64.h +++ b/test/a64/traces/sim-saddlp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-2s-trace-a64.h b/test/a64/traces/sim-saddlp-2s-trace-a64.h index 8b864a385bd4ac98f21c34ed2d6660a1d2c56f4d..9f1d8128ca6198a593b11017829973ea633bb907 100644 --- a/test/a64/traces/sim-saddlp-2s-trace-a64.h +++ b/test/a64/traces/sim-saddlp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-4h-trace-a64.h b/test/a64/traces/sim-saddlp-4h-trace-a64.h index e56ce81fb12c15a42ad6b60c580dc2c348583f4a..cc4936b3d11f3f290ada2b63f83429358d9adefb 100644 --- a/test/a64/traces/sim-saddlp-4h-trace-a64.h +++ b/test/a64/traces/sim-saddlp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-4s-trace-a64.h b/test/a64/traces/sim-saddlp-4s-trace-a64.h index ab7820b1516c64e45028d071145a2421b13360df..92ff3fab2218795b489d4c1252a305684f624cfc 100644 --- a/test/a64/traces/sim-saddlp-4s-trace-a64.h +++ b/test/a64/traces/sim-saddlp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-8h-trace-a64.h b/test/a64/traces/sim-saddlp-8h-trace-a64.h index 57e44bcd4ed7d59422708c4a12c4dc759a3d567e..ed7423fd91caf292bbca049ed8d6327f3339fe80 100644 --- a/test/a64/traces/sim-saddlp-8h-trace-a64.h +++ b/test/a64/traces/sim-saddlp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-d-4s-trace-a64.h b/test/a64/traces/sim-saddlv-d-4s-trace-a64.h index 0aa8c06e3cdc2dc121fad4160279feac6d189156..e5a73cf86dc73a4587d0c90a098e291ea37993e1 100644 --- a/test/a64/traces/sim-saddlv-d-4s-trace-a64.h +++ b/test/a64/traces/sim-saddlv-d-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-h-16b-trace-a64.h b/test/a64/traces/sim-saddlv-h-16b-trace-a64.h index 861588923f60f977a31335ef69c8470fb7ac4454..138efaa10e971cd4f28b6a6db7d2b00a945fef90 100644 --- a/test/a64/traces/sim-saddlv-h-16b-trace-a64.h +++ b/test/a64/traces/sim-saddlv-h-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-h-8b-trace-a64.h b/test/a64/traces/sim-saddlv-h-8b-trace-a64.h index ad590ece7db006cba59424d1289eee0773fd28eb..72ae7124d499dd748211195b8894b0a686851f1d 100644 --- a/test/a64/traces/sim-saddlv-h-8b-trace-a64.h +++ b/test/a64/traces/sim-saddlv-h-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-s-4h-trace-a64.h b/test/a64/traces/sim-saddlv-s-4h-trace-a64.h index 894499226b59507d334616b6b78acdbbba69b54b..d74d6d13f006729e97d231cad093656f823e6f4f 100644 --- a/test/a64/traces/sim-saddlv-s-4h-trace-a64.h +++ b/test/a64/traces/sim-saddlv-s-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-s-8h-trace-a64.h b/test/a64/traces/sim-saddlv-s-8h-trace-a64.h index a34e7ee3ff0a5dd67202bc0f552890bccbb8ed0a..37334f39a2e6f2cb7a912f5071e8a729d58e763f 100644 --- a/test/a64/traces/sim-saddlv-s-8h-trace-a64.h +++ b/test/a64/traces/sim-saddlv-s-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw-2d-trace-a64.h b/test/a64/traces/sim-saddw-2d-trace-a64.h index 0bbef07ec1829707af8211abd52882a0d5969fd8..1725c5f509cb891d38c08cf92d7f120f7efde495 100644 --- a/test/a64/traces/sim-saddw-2d-trace-a64.h +++ b/test/a64/traces/sim-saddw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw-4s-trace-a64.h b/test/a64/traces/sim-saddw-4s-trace-a64.h index e4c0abde00da36903ca734d226c54bd2813622f4..884ee92427f9606dfb62c5e0c4596cb4a473c733 100644 --- a/test/a64/traces/sim-saddw-4s-trace-a64.h +++ b/test/a64/traces/sim-saddw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw-8h-trace-a64.h b/test/a64/traces/sim-saddw-8h-trace-a64.h index c4e352d844e0dc75d91f8766d3e7b631d3b914e1..c211bfd3e1642ab9da0f525efb58fa749aeb1b51 100644 --- a/test/a64/traces/sim-saddw-8h-trace-a64.h +++ b/test/a64/traces/sim-saddw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw2-2d-trace-a64.h b/test/a64/traces/sim-saddw2-2d-trace-a64.h index 998f5d8c8ce4a213d929ecae9b12425f0bcded9a..ec3bcf2e05fb7e55c9b53ed8148550035f1cdc31 100644 --- a/test/a64/traces/sim-saddw2-2d-trace-a64.h +++ b/test/a64/traces/sim-saddw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw2-4s-trace-a64.h b/test/a64/traces/sim-saddw2-4s-trace-a64.h index 553c2cb91636df1114b204289c839b6d37ad6979..98c73cbb301e14ddeb15296c6c9cdb7f7c167137 100644 --- a/test/a64/traces/sim-saddw2-4s-trace-a64.h +++ b/test/a64/traces/sim-saddw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw2-8h-trace-a64.h b/test/a64/traces/sim-saddw2-8h-trace-a64.h index 38339213937ff7fda88d25d9e769f50ad52c0c03..0992046c94a92e33f0b411f1485512a4f8bcca94 100644 --- a/test/a64/traces/sim-saddw2-8h-trace-a64.h +++ b/test/a64/traces/sim-saddw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h index 11c8c581acab4ee8b3001771f8740d5a59cfcd02..111230d5c8c2dc62771ec410c51e0f5afd7720aa 100644 --- a/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h index 46b29421b9c70510c56f53c4f844fb7f159d3167..0ee80334c46481910b6678d07cfd1eaa9e23fa2a 100644 --- a/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h index 16ef9fad4fa10a3e74c5e802550bf7db6dde6b44..3e1094866c29f1c67bfb874e92a2b5ca351e3d9a 100644 --- a/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h index 04b6f74e48ccb5a52de458406b5f4ae504d4ba01..73ff655db8e2b5e3ca7a885b4494b811e4ff748f 100644 --- a/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h index 5d405f1b0b907cfca27a7493188f672c6d758856..f6a2cf8f1e3dc4ec91124bf7b16b4e25852a11ea 100644 --- a/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-16b-trace-a64.h b/test/a64/traces/sim-shadd-16b-trace-a64.h index 7d6b3a22ca74ec60e929029742b63bf3d149cae6..0cbf5beac2104e71fcc41d221eceb1f201938b93 100644 --- a/test/a64/traces/sim-shadd-16b-trace-a64.h +++ b/test/a64/traces/sim-shadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-2s-trace-a64.h b/test/a64/traces/sim-shadd-2s-trace-a64.h index 6a2f199e50da4f0e838f46f9282906510857f320..0bb1b046f29fb3bfa678d6379027aee4be4e9217 100644 --- a/test/a64/traces/sim-shadd-2s-trace-a64.h +++ b/test/a64/traces/sim-shadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-4h-trace-a64.h b/test/a64/traces/sim-shadd-4h-trace-a64.h index 26c5c2e24edd0965936121297c5aed8d21677ce9..b72c5b77113418a6e6f35422f344ca0934418953 100644 --- a/test/a64/traces/sim-shadd-4h-trace-a64.h +++ b/test/a64/traces/sim-shadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-4s-trace-a64.h b/test/a64/traces/sim-shadd-4s-trace-a64.h index c53364f2d10498b8c61649f789e37d3300be412d..0871738d1abe0caf9b460cf2d30c8a26c21c5286 100644 --- a/test/a64/traces/sim-shadd-4s-trace-a64.h +++ b/test/a64/traces/sim-shadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-8b-trace-a64.h b/test/a64/traces/sim-shadd-8b-trace-a64.h index cd748d63d7fc31ad79ea6647b74e3c8aecc2fdc7..dffa2275a017d4e61c98656be84c9eb0d3a7f24a 100644 --- a/test/a64/traces/sim-shadd-8b-trace-a64.h +++ b/test/a64/traces/sim-shadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-8h-trace-a64.h b/test/a64/traces/sim-shadd-8h-trace-a64.h index bf9bedbc92abc7b0a78134d8a57d0ce022e79481..5400a4c70afbb8487a6387ef0cd0c1293cab422d 100644 --- a/test/a64/traces/sim-shadd-8h-trace-a64.h +++ b/test/a64/traces/sim-shadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h b/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h index b9f33975c1e9a0bd4822d39a058bd56097ab3a28..d2c484f1b87cdd8001651224a2c84d2057149299 100644 --- a/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h b/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h index 2a38cd36b161527a8e2ab08e8b1ca466c553f091..7dfa34e61dd0c0a6a919061c8ec18a8e22127f28 100644 --- a/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h b/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h index 8eb273130a7317673890a6f5d58eac5f3b35ae86..f9c5577b8e0da6a0c812185b6f400c63c774cb85 100644 --- a/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h b/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h index d5e038e258233439bc035767a45b806ad73fc900..e691f58517febf56b0dd7ed4ab6e5ef27efe921c 100644 --- a/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h index 8f48f40167cd1ac41510f49471d8c4f1650e3f92..eb4448ada8531b6d37c6aa48734471f423cc96a2 100644 --- a/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h b/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h index c5d1e9a70dda0f56d2fa46888ecc5acd34b2c6cf..60eb1122487c32ecc3011a88eb2c5de689a0e778 100644 --- a/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h index c82bd02c2e394674b31b0ef0f4bf86af1a98e30d..e0dc91d964d26f51ec456be7eb11c06aa16a59a1 100644 --- a/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-d-2opimm-trace-a64.h b/test/a64/traces/sim-shl-d-2opimm-trace-a64.h index 326f24de5bbdafaf83a6a1dfe31d995086454ca3..543d5551b09a7d546afe155426008e1fb0de602b 100644 --- a/test/a64/traces/sim-shl-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h b/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h index 4b7d36cbbe1189a4ef801474e4b7dee3c823873c..eff9a160b1b770f98427e17c0623ca10324298e2 100644 --- a/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h index e00786cd7dddb054504ac93518ff002a148f8833..6a9dd14e6d8ed2f00fcd5834f657af4aca73bd72 100644 --- a/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h index 9c8d8a80763b1a1e70eed7acf21faa4908f8ec60..8b78bdeb9a91e8f4cc1bc0e0a2b22f972f8170d2 100644 --- a/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h b/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h index 0b204a58f8f6a28c1b1c23423bbc6ff9e5698041..79510e841e404c1f5461592f7737b0a46b9cc29f 100644 --- a/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h index 32401cfec4036e27ec6594a5036d777760b5e45d..048808988866cb5f6223cc13044f91f2fef2a401 100644 --- a/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h index 06d66c4e6564503c3415612d39b88c5c797b66de..5bb6a789dca5ef55fa8049f2f15aecb09092c85f 100644 --- a/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h index a343f1cc1fbc7bd1b41d7e7f4a6f8b740a070d03..ecf58eab2fce9c152863fb337373f88ff8b49591 100644 --- a/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h index 64f886a1d942af4e7b9b7f1dec7deb61483b58dc..c46a8f63f74f4fedd500a8bfeb2992df01629929 100644 --- a/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h index 2261852a938655158d6d72641bd37298fa9a0d55..5ee61dd05db177af9a0d4442d0f21c1e0a21bae6 100644 --- a/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h index 63ad09881f6f5a361351937145426c573b942cf5..0c829e1bee670ae838180e2f1901f51fe26defa1 100644 --- a/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h index ea42c85c477cae13f58aceb98e531a67b71ae7e3..73fd53c6651cb999460942c5edd440bddc19ec85 100644 --- a/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h index a058bef259a69439abb06094c2ccdc0c00410c7b..4e76131316bffed02496387d7fe7a53f4b052fd2 100644 --- a/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-16b-trace-a64.h b/test/a64/traces/sim-shsub-16b-trace-a64.h index c4fb646b53800ff0cd5826c5f63082610d101bb3..fe31d0d772f3f78ea4d2cbeaaca08ae581882712 100644 --- a/test/a64/traces/sim-shsub-16b-trace-a64.h +++ b/test/a64/traces/sim-shsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-2s-trace-a64.h b/test/a64/traces/sim-shsub-2s-trace-a64.h index d0a1eef79b6e335e5ad48fa226479f4b38cb2f70..48da33294846a35374f6e314a45277285f7531b6 100644 --- a/test/a64/traces/sim-shsub-2s-trace-a64.h +++ b/test/a64/traces/sim-shsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-4h-trace-a64.h b/test/a64/traces/sim-shsub-4h-trace-a64.h index d0fc0d83cd96900e2fdc1e2011a3cfb601372c2d..5bdfc887dd4cf26d90bc2aa8a40aaea17493041d 100644 --- a/test/a64/traces/sim-shsub-4h-trace-a64.h +++ b/test/a64/traces/sim-shsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-4s-trace-a64.h b/test/a64/traces/sim-shsub-4s-trace-a64.h index 2d36c341e35fd6e19ed146bc4f24a10ce447760c..ee19345131f83061d2275b026ff00260aadee383 100644 --- a/test/a64/traces/sim-shsub-4s-trace-a64.h +++ b/test/a64/traces/sim-shsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-8b-trace-a64.h b/test/a64/traces/sim-shsub-8b-trace-a64.h index 89c5f9e212c4e13dcdc05e5fcb9244c100497472..a462280e3fbcfb509f444b2378ab79c7bdbccb33 100644 --- a/test/a64/traces/sim-shsub-8b-trace-a64.h +++ b/test/a64/traces/sim-shsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-8h-trace-a64.h b/test/a64/traces/sim-shsub-8h-trace-a64.h index f10ae780173257848b77cb23fa69bfee1b0c03ea..00c4051dadc1fcc70ae58d5018fa6f79e7cf7041 100644 --- a/test/a64/traces/sim-shsub-8h-trace-a64.h +++ b/test/a64/traces/sim-shsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h index 2e41d49a9c85b3fc126c43f69552f0d038a36118..ff5650ccd0d06a2364b1f03dc9f2a8ee384adb40 100644 --- a/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h index c391e42e6fca64c243712c191635cccae1961363..9fe0fbe453f9617e3f9ec37dae5e6796440ed5bd 100644 --- a/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h index 3cadd54d62738385c97d57d446cfaadd05eb19b4..56359393639eb75ea981d877ed65f4640bdfa0f8 100644 --- a/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h index 79e0140f2951f3bc4274c20cddb3fba6451faec7..7b9686b2adc72e8629f3208ac1597c58f4ba5e0a 100644 --- a/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h index 0381fac974f3b5d17c69b71ebffbbcb34fc63636..b86e8d0514f689878a95aab7732eae83415010f8 100644 --- a/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h index 1c4115563fbd72684964db6564c63b74af34a29d..f06c9a5d07239b2d3b3488bcc48a4f43ada96428 100644 --- a/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h index dc446fd538ff1497aebb99f1e6bd7fa9b22d0e47..63c11e3d15248dd7b2c53602ddc4a1c379887cb5 100644 --- a/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-d-2opimm-trace-a64.h b/test/a64/traces/sim-sli-d-2opimm-trace-a64.h index 7746a0184b6243aa40c051411731b2c8e768ab6c..043642e35e53fd45e867caef8c981cc2d17de3e2 100644 --- a/test/a64/traces/sim-sli-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-16b-trace-a64.h b/test/a64/traces/sim-smax-16b-trace-a64.h index 12f5d180b8a0a3ae88d6819cbe5329ed32d1effd..1a7cb01114cc5612171fbb140a082baf2486ac38 100644 --- a/test/a64/traces/sim-smax-16b-trace-a64.h +++ b/test/a64/traces/sim-smax-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-2s-trace-a64.h b/test/a64/traces/sim-smax-2s-trace-a64.h index 54a13697bf83c4e65f0473f8a7f79222629545c5..95c62ae49fe06d7d11427f29936cfd420c5f5117 100644 --- a/test/a64/traces/sim-smax-2s-trace-a64.h +++ b/test/a64/traces/sim-smax-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-4h-trace-a64.h b/test/a64/traces/sim-smax-4h-trace-a64.h index bffe3e12ea8f1354860d075cf487a1a5d2d2841f..c7f2178aa9b86c919d74d9aa3b78422bf218f7d2 100644 --- a/test/a64/traces/sim-smax-4h-trace-a64.h +++ b/test/a64/traces/sim-smax-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-4s-trace-a64.h b/test/a64/traces/sim-smax-4s-trace-a64.h index 03c22ccd5967adec048a787ef57cfe9954350aad..a9356ef90f9d3bbd1c9f90b2b73916af705c0c5b 100644 --- a/test/a64/traces/sim-smax-4s-trace-a64.h +++ b/test/a64/traces/sim-smax-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-8b-trace-a64.h b/test/a64/traces/sim-smax-8b-trace-a64.h index 7c4706080e13ad601a9151291e9756ed4dd932c5..2df8ed7853e34480166f2f264b117a1da3fc9264 100644 --- a/test/a64/traces/sim-smax-8b-trace-a64.h +++ b/test/a64/traces/sim-smax-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-8h-trace-a64.h b/test/a64/traces/sim-smax-8h-trace-a64.h index 099ebfb97f39d84f0d09b66c26757ce09b5735e3..42714e30b457fc0214af714cad15a729a82263c7 100644 --- a/test/a64/traces/sim-smax-8h-trace-a64.h +++ b/test/a64/traces/sim-smax-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-16b-trace-a64.h b/test/a64/traces/sim-smaxp-16b-trace-a64.h index 55d06d627d10e7340a7a6410c63aef20980f572f..8c3c2cc9713c7315bf9bcae535b896131ecfc12c 100644 --- a/test/a64/traces/sim-smaxp-16b-trace-a64.h +++ b/test/a64/traces/sim-smaxp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-2s-trace-a64.h b/test/a64/traces/sim-smaxp-2s-trace-a64.h index d3212603c9f4b0f904924c6f65540154f7e59321..a335132c669e089a0ef0b139d69b16229b0eb0b9 100644 --- a/test/a64/traces/sim-smaxp-2s-trace-a64.h +++ b/test/a64/traces/sim-smaxp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-4h-trace-a64.h b/test/a64/traces/sim-smaxp-4h-trace-a64.h index 6913f66aa64edda64cf01cf8663399804df9abf7..3c3f68bdb4ab8470ab2c02a51df025a5e9f0c24e 100644 --- a/test/a64/traces/sim-smaxp-4h-trace-a64.h +++ b/test/a64/traces/sim-smaxp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-4s-trace-a64.h b/test/a64/traces/sim-smaxp-4s-trace-a64.h index f246047681683a8f56b91b5734ac6cb9b914d6dd..86e2b953bd3b50e8963fd89d43e87ff831a0044d 100644 --- a/test/a64/traces/sim-smaxp-4s-trace-a64.h +++ b/test/a64/traces/sim-smaxp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-8b-trace-a64.h b/test/a64/traces/sim-smaxp-8b-trace-a64.h index a62a9eec8a24ab6455a776064cca33fb94ae4559..d46af76c5f06440ddc77b66f92a67afbda34a936 100644 --- a/test/a64/traces/sim-smaxp-8b-trace-a64.h +++ b/test/a64/traces/sim-smaxp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-8h-trace-a64.h b/test/a64/traces/sim-smaxp-8h-trace-a64.h index 060488a90266c20b1c98548343b250625ebf0d18..360c6d8c1bcee1737380c65c37a5c4cfeda9dd98 100644 --- a/test/a64/traces/sim-smaxp-8h-trace-a64.h +++ b/test/a64/traces/sim-smaxp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-b-16b-trace-a64.h b/test/a64/traces/sim-smaxv-b-16b-trace-a64.h index eb58d66ab18bbb1aed7f48a0e7888517b1fe9bfb..44afea799a2ebdd3c0d32c63e03af10b5be8023e 100644 --- a/test/a64/traces/sim-smaxv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-smaxv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-b-8b-trace-a64.h b/test/a64/traces/sim-smaxv-b-8b-trace-a64.h index fcb166c953376949226442768ed70f483a6b807c..7fcac4895625a2dab475a0a1c7d8dbf963bd71a5 100644 --- a/test/a64/traces/sim-smaxv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-smaxv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-h-4h-trace-a64.h b/test/a64/traces/sim-smaxv-h-4h-trace-a64.h index 25d08bdb45a690e12aa3fcc1d4d723e29abd38fd..8ecb2769d60e7f3dbcf092d3fab6e2038a6fa5bc 100644 --- a/test/a64/traces/sim-smaxv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-smaxv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-h-8h-trace-a64.h b/test/a64/traces/sim-smaxv-h-8h-trace-a64.h index 2833e9cc6e7f092901c98049c0eb2388661c6888..23b113753ddce80a2b8a9f349956d3ed74aab1ef 100644 --- a/test/a64/traces/sim-smaxv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-smaxv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-s-4s-trace-a64.h b/test/a64/traces/sim-smaxv-s-4s-trace-a64.h index 650d7f51f54a769e34eacc09c26371bc0c082586..b9cb8dcc1ed67f43cbb42a26c302898e1dd7f496 100644 --- a/test/a64/traces/sim-smaxv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-smaxv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-16b-trace-a64.h b/test/a64/traces/sim-smin-16b-trace-a64.h index 7475c339007fe3b29367ab69277f64ec0a9a0791..3ea00f15040434fd518ce1f55c8758028a694918 100644 --- a/test/a64/traces/sim-smin-16b-trace-a64.h +++ b/test/a64/traces/sim-smin-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-2s-trace-a64.h b/test/a64/traces/sim-smin-2s-trace-a64.h index 2decbacfd59e58b48c84f35eeb9712f48045dbb1..f32a6fff527a665d6f3eb8a6b555a8866fb19cd3 100644 --- a/test/a64/traces/sim-smin-2s-trace-a64.h +++ b/test/a64/traces/sim-smin-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-4h-trace-a64.h b/test/a64/traces/sim-smin-4h-trace-a64.h index 6fd4e2a837d269a25a16eefcb908bb1ea4f2b51b..586551ffcc446333951fe8ff2eadd500b6a1e5ea 100644 --- a/test/a64/traces/sim-smin-4h-trace-a64.h +++ b/test/a64/traces/sim-smin-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-4s-trace-a64.h b/test/a64/traces/sim-smin-4s-trace-a64.h index 237617488e6a8075e2f0c8f1d1febac2b88c276d..574fe4e5bcf428e3f771fc1e793106661602c8cf 100644 --- a/test/a64/traces/sim-smin-4s-trace-a64.h +++ b/test/a64/traces/sim-smin-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-8b-trace-a64.h b/test/a64/traces/sim-smin-8b-trace-a64.h index f0bfcd5fac1ba87cb5fd4e1553cf3b990627f1f0..903613a380cd424cf1c4625fc2708f5ca6b861d7 100644 --- a/test/a64/traces/sim-smin-8b-trace-a64.h +++ b/test/a64/traces/sim-smin-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-8h-trace-a64.h b/test/a64/traces/sim-smin-8h-trace-a64.h index c111c6a80bec93b0e1ee0fce1208c0f8102882cd..1d65084760c66dde1e3149e7f1570ee4e361238e 100644 --- a/test/a64/traces/sim-smin-8h-trace-a64.h +++ b/test/a64/traces/sim-smin-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-16b-trace-a64.h b/test/a64/traces/sim-sminp-16b-trace-a64.h index 9742afe8fae5f981fc69c6b4c08bc888474e2a45..9a1b7816183ee1f4433ff2dcca462ef131813ada 100644 --- a/test/a64/traces/sim-sminp-16b-trace-a64.h +++ b/test/a64/traces/sim-sminp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-2s-trace-a64.h b/test/a64/traces/sim-sminp-2s-trace-a64.h index 8272627636b3ab357727a4ac2171170f6badb760..645966e73a4c6225befdc5ff10b6f5612ad28f1b 100644 --- a/test/a64/traces/sim-sminp-2s-trace-a64.h +++ b/test/a64/traces/sim-sminp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-4h-trace-a64.h b/test/a64/traces/sim-sminp-4h-trace-a64.h index 32fed096e9cb2128ed0129ae49dacab7463d9ae3..922f6608bb9702dd371d57416bb3f395c6f02ef3 100644 --- a/test/a64/traces/sim-sminp-4h-trace-a64.h +++ b/test/a64/traces/sim-sminp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-4s-trace-a64.h b/test/a64/traces/sim-sminp-4s-trace-a64.h index 0d42ef0826ead47cc51cb6662d7bb236f44ca946..48b42a92cad02cf2bb632d898684623245cc2cf6 100644 --- a/test/a64/traces/sim-sminp-4s-trace-a64.h +++ b/test/a64/traces/sim-sminp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-8b-trace-a64.h b/test/a64/traces/sim-sminp-8b-trace-a64.h index 4afd881298ca99aad850676d7081f3ccb4b41edb..64566018fc592090b3266880d77202e7a891a05a 100644 --- a/test/a64/traces/sim-sminp-8b-trace-a64.h +++ b/test/a64/traces/sim-sminp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-8h-trace-a64.h b/test/a64/traces/sim-sminp-8h-trace-a64.h index 471d6b0141715badcb975a8864508fde2a7bc895..aee4d693119c39396d26139fb8d95a07424b2026 100644 --- a/test/a64/traces/sim-sminp-8h-trace-a64.h +++ b/test/a64/traces/sim-sminp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-b-16b-trace-a64.h b/test/a64/traces/sim-sminv-b-16b-trace-a64.h index 0df4fb40f4d75391225d83a8652a62f52c5d8b9d..c13a258d311683d0103c6e773c8a6a5c7a70d99c 100644 --- a/test/a64/traces/sim-sminv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-sminv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-b-8b-trace-a64.h b/test/a64/traces/sim-sminv-b-8b-trace-a64.h index 948a38ea4bd4667791dd1657d4c9dd76e8612f4a..6c3f9749c3a79481a487367c6a47dbd843e72f0e 100644 --- a/test/a64/traces/sim-sminv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-sminv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-h-4h-trace-a64.h b/test/a64/traces/sim-sminv-h-4h-trace-a64.h index fb26bf150fe5153f138ba88ad807718c6a42b331..06f35c629ea792f58bfb87901ef9242d5b4ce598 100644 --- a/test/a64/traces/sim-sminv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-sminv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-h-8h-trace-a64.h b/test/a64/traces/sim-sminv-h-8h-trace-a64.h index 6afb0093aa9d6de5af56237bad1b7b5841aa32ba..14ba3c96d32947f3e754612aef0b8257124a444f 100644 --- a/test/a64/traces/sim-sminv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-sminv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-s-4s-trace-a64.h b/test/a64/traces/sim-sminv-s-4s-trace-a64.h index fc64c04a4bd0efeae728fec57f57c8c9e6bd7540..422f561106c6c32c47ff81f3e7ec11133d280712 100644 --- a/test/a64/traces/sim-sminv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-sminv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h b/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h index abf65807c847e5a88c3f4b04675aa81abd1e601a..447601f98effb858caab349e01ebbfd5b33f88fd 100644 --- a/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-2d-trace-a64.h b/test/a64/traces/sim-smlal-2d-trace-a64.h index 2ea965d14c721fdea7d6c6fed2c90603cf486c32..702c8adb29f018507daf144c33a09ee59886935e 100644 --- a/test/a64/traces/sim-smlal-2d-trace-a64.h +++ b/test/a64/traces/sim-smlal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h b/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h index 592230ae2b27a1df224e1637dce104efd530f84a..828ae51d6dc0ee2058b23ddb4fe8c0fe81ffc4ea 100644 --- a/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-4s-trace-a64.h b/test/a64/traces/sim-smlal-4s-trace-a64.h index 563143f4ca75ce5b331ea6382f6ff678dddb8109..d6b9d8677222f5271a3fcfc8923cad72fae2b961 100644 --- a/test/a64/traces/sim-smlal-4s-trace-a64.h +++ b/test/a64/traces/sim-smlal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-8h-trace-a64.h b/test/a64/traces/sim-smlal-8h-trace-a64.h index 249de616d03a2096fd3298e4d05b5778f4355e59..617cc45c14a1fe61354ed59e952f3edb46da9871 100644 --- a/test/a64/traces/sim-smlal-8h-trace-a64.h +++ b/test/a64/traces/sim-smlal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h index 4702ec278fddac671aa7d41d18305433359f2f3f..fc79afb4dfb6e2164a89c7246a39dfeb8473ed53 100644 --- a/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-2d-trace-a64.h b/test/a64/traces/sim-smlal2-2d-trace-a64.h index 5dce51d9ebd69516f2ce89a433ffb2cf4d781f2f..0a8cc5156707ba1aac409a38937d648ca81d5858 100644 --- a/test/a64/traces/sim-smlal2-2d-trace-a64.h +++ b/test/a64/traces/sim-smlal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h index a5d2f934c5a2f3e582cf84bee4ff9d219c6932b0..263f0c4dd6cf409aa1e211cf39aba41946dedbdb 100644 --- a/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-4s-trace-a64.h b/test/a64/traces/sim-smlal2-4s-trace-a64.h index 7e23218d69c851bf0917cfc4a28a79ad747aef82..d87171df6c99eda211e33e3f376d42a1efc4d1c6 100644 --- a/test/a64/traces/sim-smlal2-4s-trace-a64.h +++ b/test/a64/traces/sim-smlal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-8h-trace-a64.h b/test/a64/traces/sim-smlal2-8h-trace-a64.h index bc08d1dced41721e970ad5d7a474234b509e7bc2..19787fe4a24598e2c0fd489a443fe7a30275b9fa 100644 --- a/test/a64/traces/sim-smlal2-8h-trace-a64.h +++ b/test/a64/traces/sim-smlal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h b/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h index eb7f5b0d68512a7f8996aee2bee791bb504f32a8..a1ee17d25a1d794156658f303aff1bd594ac9477 100644 --- a/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-2d-trace-a64.h b/test/a64/traces/sim-smlsl-2d-trace-a64.h index 9a1c6172850424695722ecf9fec5eadb1d5cb974..adba287eeecb2e89dc42556e621b429e986608d9 100644 --- a/test/a64/traces/sim-smlsl-2d-trace-a64.h +++ b/test/a64/traces/sim-smlsl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h b/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h index ac8535b6cc06b4e113a8dc7ff6c44ca0bfda5d3f..070d1ec3fd0eb95a5cdc431b63ed404cf194d173 100644 --- a/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-4s-trace-a64.h b/test/a64/traces/sim-smlsl-4s-trace-a64.h index a70ae7b2b07dd8083b23f711e14e92d4e567e2be..700732d670a6b00459342fb3dd98e4289bb363ff 100644 --- a/test/a64/traces/sim-smlsl-4s-trace-a64.h +++ b/test/a64/traces/sim-smlsl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-8h-trace-a64.h b/test/a64/traces/sim-smlsl-8h-trace-a64.h index 1f8d57bd0fdab932268f4dbaa00041e8db641314..aed346c83a63e8ee775b19bdd8656c50ce530ea1 100644 --- a/test/a64/traces/sim-smlsl-8h-trace-a64.h +++ b/test/a64/traces/sim-smlsl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h index 5fd95a47e90fd6a69883c4adca383798430a7826..412ea2e97fff8a6e5ae4af58c7261e5e0b74fbb6 100644 --- a/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-2d-trace-a64.h b/test/a64/traces/sim-smlsl2-2d-trace-a64.h index bb959a8d3ac611f5957b2068b567d77f5ccb5e46..9a58f11c773e0c1f2d54b70d6dd927d36ded08cf 100644 --- a/test/a64/traces/sim-smlsl2-2d-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h index e9c2423b93bf15a83f8d5baa725f712ff3b61285..9d36d4d1611fd920cbdd8c3bd582e850bd0756a3 100644 --- a/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-4s-trace-a64.h b/test/a64/traces/sim-smlsl2-4s-trace-a64.h index 3216f61e6e5ec3b7f78b21eb77d06729adbcac3d..017376d30a952d8fe2028e7807c2ff2dfe084893 100644 --- a/test/a64/traces/sim-smlsl2-4s-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-8h-trace-a64.h b/test/a64/traces/sim-smlsl2-8h-trace-a64.h index 2677d753a37c73fbca4f98a82959060f3b22aa79..d8f4213eacce0fb7be9496b49ea935d443cacf21 100644 --- a/test/a64/traces/sim-smlsl2-8h-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h b/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h index 80d544d31dcb7a9c23a14243cc0bb61e01af37c7..fee76b73775e68323a708a3fb6b2742a4c38959a 100644 --- a/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-2d-trace-a64.h b/test/a64/traces/sim-smull-2d-trace-a64.h index 80d90f45fbdfe4e2c3c6e77e22608c739932742c..462fed7e49ee9a00a6a4c31ec3b578fc1463269c 100644 --- a/test/a64/traces/sim-smull-2d-trace-a64.h +++ b/test/a64/traces/sim-smull-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h b/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h index cdbbb043326ca9a1f0181b80911e36eb729c06ae..c14707e023744a4682c21f9f7f8e6b80b44274eb 100644 --- a/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-4s-trace-a64.h b/test/a64/traces/sim-smull-4s-trace-a64.h index 20001e576168fca6440934a3da619dcd99dc967a..32df1e2caf66361e7641dde3133eb797f00eff26 100644 --- a/test/a64/traces/sim-smull-4s-trace-a64.h +++ b/test/a64/traces/sim-smull-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-8h-trace-a64.h b/test/a64/traces/sim-smull-8h-trace-a64.h index ef25a60ce311be15909f0bfcb6d7b8d3ed766b77..ef8a31645b3be6532c8bfc8d669cbd095ba40eef 100644 --- a/test/a64/traces/sim-smull-8h-trace-a64.h +++ b/test/a64/traces/sim-smull-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h index e09ea5297f319af0c066f371f1f60d93d41923b9..8b58b73ca50accb46b847d0c2f517d6fae5523c1 100644 --- a/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-2d-trace-a64.h b/test/a64/traces/sim-smull2-2d-trace-a64.h index 33ebaefa6c8de7c164b988c809f7582ec182ffd2..b5388fbfedb8325fbc3083215f4e42471e6fe62a 100644 --- a/test/a64/traces/sim-smull2-2d-trace-a64.h +++ b/test/a64/traces/sim-smull2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h index f3a5c29b229f1cd7affc1f1c3e224caef41d9e5c..2c92e28cc7fcef466037b21aac9d78bbd304a2f7 100644 --- a/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-4s-trace-a64.h b/test/a64/traces/sim-smull2-4s-trace-a64.h index a28e86f6302c88b8556f754d2c80bc2a70031147..f32ed21d9a4771ce171e085d5e02c173482911bd 100644 --- a/test/a64/traces/sim-smull2-4s-trace-a64.h +++ b/test/a64/traces/sim-smull2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-8h-trace-a64.h b/test/a64/traces/sim-smull2-8h-trace-a64.h index 1db54dbee6ae8009e99c4694ffbba87c3e50a655..70c11944523c47c8b0579cb276e82c2b220e06ae 100644 --- a/test/a64/traces/sim-smull2-8h-trace-a64.h +++ b/test/a64/traces/sim-smull2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-16b-trace-a64.h b/test/a64/traces/sim-sqabs-16b-trace-a64.h index 74a185a552c82608e88a9a76e084c331ebe68fc6..1c5e4ebbaf6fe472bcd3ab23350b42a746ba486e 100644 --- a/test/a64/traces/sim-sqabs-16b-trace-a64.h +++ b/test/a64/traces/sim-sqabs-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-2d-trace-a64.h b/test/a64/traces/sim-sqabs-2d-trace-a64.h index 6e8816190c506fc010009a44f9f650462c544e19..09f010b54fde6ad2f39dedeb557473749d3d9349 100644 --- a/test/a64/traces/sim-sqabs-2d-trace-a64.h +++ b/test/a64/traces/sim-sqabs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-2s-trace-a64.h b/test/a64/traces/sim-sqabs-2s-trace-a64.h index 5ac09b38fb1e7ab78c5499d25160cd69fc423a6b..68d6e7c2390aedb23d7ec6ccca1cc9a9b1c89138 100644 --- a/test/a64/traces/sim-sqabs-2s-trace-a64.h +++ b/test/a64/traces/sim-sqabs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-4h-trace-a64.h b/test/a64/traces/sim-sqabs-4h-trace-a64.h index dcf0fc69584e9cf48438f3a2c4489934d001da19..0128354923cdf0daef6e41fe3212be61e306c11a 100644 --- a/test/a64/traces/sim-sqabs-4h-trace-a64.h +++ b/test/a64/traces/sim-sqabs-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-4s-trace-a64.h b/test/a64/traces/sim-sqabs-4s-trace-a64.h index 881a976ccef9407fc0cfa17291350f6dd3501c5c..f209ba5adb2dc9bfdd8282e7a4dd6e6ef422408f 100644 --- a/test/a64/traces/sim-sqabs-4s-trace-a64.h +++ b/test/a64/traces/sim-sqabs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-8b-trace-a64.h b/test/a64/traces/sim-sqabs-8b-trace-a64.h index ab61e760a07b9135be46c81ddb645223b7d55fa0..f0e99b0077d49802cbfcf8180b528624c65850e0 100644 --- a/test/a64/traces/sim-sqabs-8b-trace-a64.h +++ b/test/a64/traces/sim-sqabs-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-8h-trace-a64.h b/test/a64/traces/sim-sqabs-8h-trace-a64.h index d0cb0ccea674611545e5b8cf9c261dcdcc3a84d3..241450601845fbb2fe4da1312804270150483bc2 100644 --- a/test/a64/traces/sim-sqabs-8h-trace-a64.h +++ b/test/a64/traces/sim-sqabs-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-b-trace-a64.h b/test/a64/traces/sim-sqabs-b-trace-a64.h index a8d67eeeed24de15709e787220627b999fe90a17..7d659fa881fb7a40f1604d6f6ed6186e856c7f3f 100644 --- a/test/a64/traces/sim-sqabs-b-trace-a64.h +++ b/test/a64/traces/sim-sqabs-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-d-trace-a64.h b/test/a64/traces/sim-sqabs-d-trace-a64.h index 6a31a60cc54a3e851bf8970ae9f34a43682165b8..c7edf923e7b626b91a13e4f4858d0a530fab24a7 100644 --- a/test/a64/traces/sim-sqabs-d-trace-a64.h +++ b/test/a64/traces/sim-sqabs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-h-trace-a64.h b/test/a64/traces/sim-sqabs-h-trace-a64.h index a7fec4245defb09d9463250866b555ca57a5d7fd..b31ace3d861e5200830877b0463d6535cbddd32f 100644 --- a/test/a64/traces/sim-sqabs-h-trace-a64.h +++ b/test/a64/traces/sim-sqabs-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-s-trace-a64.h b/test/a64/traces/sim-sqabs-s-trace-a64.h index a459ed0d9e92d4ab262ef6737ef6fb9474ee6f8b..8de38aeead86c1c0384415012c82a6dba27e2ec1 100644 --- a/test/a64/traces/sim-sqabs-s-trace-a64.h +++ b/test/a64/traces/sim-sqabs-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-16b-trace-a64.h b/test/a64/traces/sim-sqadd-16b-trace-a64.h index 64c35043effbd4c2fa5ea8315a50c62d13b38f3f..66f73efc9462388b25744bfb6df849644fcf0218 100644 --- a/test/a64/traces/sim-sqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-sqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-2d-trace-a64.h b/test/a64/traces/sim-sqadd-2d-trace-a64.h index 3e8f9e58465bd952e9b83c0a19af7dc309d3571c..4c6b4d5b92deef189229f3f65f4a956d5a2a9083 100644 --- a/test/a64/traces/sim-sqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-sqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-2s-trace-a64.h b/test/a64/traces/sim-sqadd-2s-trace-a64.h index 44b28cd7d1ac08d5df90ef36f6fb2ddf4c056d4a..fb3af75dcdb5a391c24790d37ec1a05e97f95857 100644 --- a/test/a64/traces/sim-sqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-sqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-4h-trace-a64.h b/test/a64/traces/sim-sqadd-4h-trace-a64.h index 46d80b53fcc0475b365c0276769935f6bd25ba15..562f5585ca6039819de1a67f1fb686f1549624b0 100644 --- a/test/a64/traces/sim-sqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-sqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-4s-trace-a64.h b/test/a64/traces/sim-sqadd-4s-trace-a64.h index f13d94bfdaedff1cbdccfc91afd9db1d1a2e6ef2..916beb35678e4a8b951cffb5b67a4b8be0f7d3d6 100644 --- a/test/a64/traces/sim-sqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-sqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-8b-trace-a64.h b/test/a64/traces/sim-sqadd-8b-trace-a64.h index d32354bc1d5b1e3112df26d6db540cd4f0d5ffbd..d17df960e4054ee0786f54bf45344dfd680c27e5 100644 --- a/test/a64/traces/sim-sqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-sqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-8h-trace-a64.h b/test/a64/traces/sim-sqadd-8h-trace-a64.h index aa0a9f65833de62378bf4e014f714a7fedf665e5..4f9b14caedb13935d7e8be2d713532073d32b45b 100644 --- a/test/a64/traces/sim-sqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-sqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-b-trace-a64.h b/test/a64/traces/sim-sqadd-b-trace-a64.h index 10b76c1abe960adf0fd8db1bfadd3c7abbbb40b0..775e569f395bfa25809a16aacafdb0c0bcce0f6a 100644 --- a/test/a64/traces/sim-sqadd-b-trace-a64.h +++ b/test/a64/traces/sim-sqadd-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-d-trace-a64.h b/test/a64/traces/sim-sqadd-d-trace-a64.h index 1aba133e08b5f303967976a2cd63f7aa822f29db..5161957a033db8a6316c0065d1cc1f33e0fd9313 100644 --- a/test/a64/traces/sim-sqadd-d-trace-a64.h +++ b/test/a64/traces/sim-sqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-h-trace-a64.h b/test/a64/traces/sim-sqadd-h-trace-a64.h index 80a5013b4167005045855c6d11e6f80e32f1a19f..d56f555a2dc2d5bc44f799dea0989ba5a06f1f41 100644 --- a/test/a64/traces/sim-sqadd-h-trace-a64.h +++ b/test/a64/traces/sim-sqadd-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-s-trace-a64.h b/test/a64/traces/sim-sqadd-s-trace-a64.h index 02b6c464d43f91874322def9a37ab326af7a00f3..98064dd986ab8bc7773a25b28bb0fb277a9c63ae 100644 --- a/test/a64/traces/sim-sqadd-s-trace-a64.h +++ b/test/a64/traces/sim-sqadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h index 275a6dfefe860a10b0195595d4108decd2ec2d70..fc1787fb92be3f97336de9095f88aacfa5306e17 100644 --- a/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-2d-trace-a64.h b/test/a64/traces/sim-sqdmlal-2d-trace-a64.h index 8e6ab2c77667e2bebfe1c3310c5000be47ed8c1c..9666867fde82a61aa43770362341f1849b338cbe 100644 --- a/test/a64/traces/sim-sqdmlal-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h index 207576f2f5304ac20358f17f28aa667b9729caae..c3567b8f66a2f795960576413b871f264698b43e 100644 --- a/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-4s-trace-a64.h b/test/a64/traces/sim-sqdmlal-4s-trace-a64.h index 3efc72fc3205b7b2e0ab512ea6d77079fa96a294..fbce444400a9e8c5aa5be7d0cc7ebafaae532633 100644 --- a/test/a64/traces/sim-sqdmlal-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h b/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h index 53820287aeb55d12b0233d511376d8ce681bf58c..f5fe3fcf97a0f797908ad676bcb6f5c04c5efe71 100644 --- a/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-d-trace-a64.h b/test/a64/traces/sim-sqdmlal-d-trace-a64.h index cca0dea256c3ec57b33bd58031e2834031870a3a..4ccfe4c217827f59995d0997f0db3ad7a3b63974 100644 --- a/test/a64/traces/sim-sqdmlal-d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h b/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h index c3cdfae569a83a5495270956e62955fb4ee43b14..bb1c997489ff70aee60ded6671940250622c763d 100644 --- a/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-s-trace-a64.h b/test/a64/traces/sim-sqdmlal-s-trace-a64.h index 64d6f3e3c25f0c32b4e0a3726fec3c2d88d485ac..834b5c850721a7893440cdfa63e0175ce11dab90 100644 --- a/test/a64/traces/sim-sqdmlal-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h index 1b7ccd2fc03e24c478c8e6bda1581e20a3819308..6e2566d5eceaaa98e4799f9c030198bea6d6b87b 100644 --- a/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h b/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h index 8df519f75b2f55886e19e6f2a4ac5bc5b7cd6665..c022a1bb03e4ebd28e69bb74d061ac2e44ef7e7e 100644 --- a/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h index 1beb0b996a52bea5a886ced5b941b72e6c0eff78..3bbfa5075e6b38c164d774c75dd517d29c5a71e8 100644 --- a/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h b/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h index 89f2420ceeb2155b4fed794ecc8e374940804304..44a75108cc5940dd7bbdaab52662a187655625fe 100644 --- a/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h index ea73824d429923d73a81c1213a305c7423c949ce..a46a5434782fc6ae24296525a35a065dd4c5d02e 100644 --- a/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h b/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h index 4764ce6550b827b5f779c59a562a522aa8efe7fa..f1fe47a90dc1ac0f43500d490bfe17ac791f251c 100644 --- a/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h index 27b00dc5f9a4c6662e64fd26f866615082fa45ef..5062ef4961ce7277533b8b5d16216f4706cda0ce 100644 --- a/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h index d1acb151f1be15c2b78fecf97dc3d0b590ed381d..7e0d6c4dfe5f2e1fee4938d9f1f2f4c64679560a 100644 --- a/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h index 69072690cb7a9b37b3f44f1de5d32bc961a5de80..1f005cc1f1afda9d5d87288ee5b12a650c85c9e8 100644 --- a/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-d-trace-a64.h b/test/a64/traces/sim-sqdmlsl-d-trace-a64.h index 471e075165d79246976ca6344da1ad1a5a5456a8..bddc78cb975afccdd209890b7013ddb350ea5465 100644 --- a/test/a64/traces/sim-sqdmlsl-d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h b/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h index 9c8c12717271671d9f50cd4687e3370c53d011e1..75bd7d2392281d6f951e8ac40ba244bd68d7f6af 100644 --- a/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-s-trace-a64.h index 7031b724045185533e396e4a0a68fa4c4b4d8a84..2725041640cd15f3815f00e0803559e02d8b9b50 100644 --- a/test/a64/traces/sim-sqdmlsl-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h index ecd50a140ba1ae82df284919b79eabb319f8f98e..c3f0fc8d597c9b98b7e8373ccffb0f8c226ee975 100644 --- a/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h index c15c12a757c59599542afda14f60595c18cb5595..10ecea596e3210f66ba73d46fd1cc3658924ecf1 100644 --- a/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h index 29d94daf390459af4c78a6c3b8e9ab27fc5fba1a..0172344e1a9170638f936fc38f493b3bbde0e093 100644 --- a/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h index 01b1d75aab12892c42c926aabb4cc9afbeaf52f6..d552cc9e7d53793cbaf94746f92b6e4ccf4a2028 100644 --- a/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h index 302f59c3dc9e4c272168c5678c2ec3d9c3b21a67..caa7a4aebd3be5abed06d67f93163021baed63e2 100644 --- a/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-2s-trace-a64.h b/test/a64/traces/sim-sqdmulh-2s-trace-a64.h index 79897d6dba7bbf3cc265fd9755f738840abb42ad..0999d62b659f04e572e40c5a3f4f8dc3d64f754f 100644 --- a/test/a64/traces/sim-sqdmulh-2s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h index 69be6752f51ffe09b1399402ee63eaaada7bd080..c3879ef1b8e94041d435ab9c839efd414198472d 100644 --- a/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4h-trace-a64.h b/test/a64/traces/sim-sqdmulh-4h-trace-a64.h index ef93016d99ab87cc2e651e011abc5c7d3d847a38..86a07a5066af36efb557effd7e9e8c966acf663b 100644 --- a/test/a64/traces/sim-sqdmulh-4h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h index 6fea21c78773cd4d01dfecdfbd672adc58c0ca9b..91df5665fae71bf0e39da7850426091455bb7b33 100644 --- a/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4s-trace-a64.h b/test/a64/traces/sim-sqdmulh-4s-trace-a64.h index 40ceeab886d0bd03dfcc8038a925fb7ff8208177..8b2a69197188970eb361e6362e4842d442de6f8f 100644 --- a/test/a64/traces/sim-sqdmulh-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h index b7322e31c44da804cb809dab8e4cdef780c5e4d7..042cd4af1ed858593a63f7d869a86bfe3bdff342 100644 --- a/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-8h-trace-a64.h b/test/a64/traces/sim-sqdmulh-8h-trace-a64.h index af98cd56e6c614aa52ab61da45764376e83d3ef0..d8e15fb8aa5770025b094f0e6251c93929d7f9e7 100644 --- a/test/a64/traces/sim-sqdmulh-8h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h index a5cb5cb7598e2eacc26dac720b62ae5dbfa6aacc..0790b1a6f902b2d75696d8b04176940b946f9e20 100644 --- a/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-h-trace-a64.h index 7924e567b53962fa40db9a925aaa002dae75d110..95ad42e68829338cbd7fd37b48f9928cc0c43c7a 100644 --- a/test/a64/traces/sim-sqdmulh-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h index c257e68bd70cbcb2cd21f8427f437d093d0eeca3..d561b913c033ab5be4f51b5625949cd733aa3cba 100644 --- a/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-s-trace-a64.h index 114c28281f7f02f2ddca737861e77c833a659065..5b34501882bf3b9fe99c8145e311b1258ace012d 100644 --- a/test/a64/traces/sim-sqdmulh-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h index 27a647ce465e56025fc31a9d1e4720059c927c62..a119d55a0b066dce240167df625c0df85c4e8f28 100644 --- a/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-2d-trace-a64.h b/test/a64/traces/sim-sqdmull-2d-trace-a64.h index 94130a161ec67ceb0d82ecd95aa7dfd9983a6d6d..aa06fa2fef316c7aa64386d230ea36fe105e71ce 100644 --- a/test/a64/traces/sim-sqdmull-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h index 31f8ccfd2db4c60fac72cac7be1325c03ad78233..ad6edf6f3af19966f0fb69b7ac3188bf18c1c8d7 100644 --- a/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-4s-trace-a64.h b/test/a64/traces/sim-sqdmull-4s-trace-a64.h index 32b2f647e60b0629f5b7db31c96456716cab082e..9f7567ce692abb62293a26a9337775f93d842ac9 100644 --- a/test/a64/traces/sim-sqdmull-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h b/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h index 7bcb11477b997153a31978d6f40053c087c60e73..9a9dba936e0eb17ec9e596f492c70c1610eafed0 100644 --- a/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-d-trace-a64.h b/test/a64/traces/sim-sqdmull-d-trace-a64.h index a067746b2fe5f3f28774311509933f03a337ac5e..05bc7b68fa5a2480906a9864e9d05da2e64ef113 100644 --- a/test/a64/traces/sim-sqdmull-d-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h b/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h index b086ee030c60da5dda286a1a71b2c13c1f575fc0..ce50ec3eb8701a387b735a107b96a2a910b88b18 100644 --- a/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-s-trace-a64.h b/test/a64/traces/sim-sqdmull-s-trace-a64.h index 3336b1e8465569802589671104a20f9a9dba5e45..8a68f72a817585e8b64975feacc3565cb3997d6e 100644 --- a/test/a64/traces/sim-sqdmull-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h index 80cfa9a24b92daa61c5f717ca2e8c19526076f04..a7b04bf8eb9e82dc038cf57711becbf21698151f 100644 --- a/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-2d-trace-a64.h b/test/a64/traces/sim-sqdmull2-2d-trace-a64.h index e955be6e7308a7294f2907e768fa01be973543fc..b236c6d8b979d1d6280f32d6ea848587eb70b7da 100644 --- a/test/a64/traces/sim-sqdmull2-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h index 4086f9f0743b81aeb523bc38666f92439ff1f05b..33591fd853e91480f8afdd5190189665679a3984 100644 --- a/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-4s-trace-a64.h b/test/a64/traces/sim-sqdmull2-4s-trace-a64.h index 13ccf7d050be08a87e8491a25c342fd8a29635b4..791f827f6e39292d6792c88ca3b21dee23219eed 100644 --- a/test/a64/traces/sim-sqdmull2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-16b-trace-a64.h b/test/a64/traces/sim-sqneg-16b-trace-a64.h index 17c0b3708744c68b0873f27e146a958dba009303..77df50c529d6fa16ed9502fe15c3a5edbdda9320 100644 --- a/test/a64/traces/sim-sqneg-16b-trace-a64.h +++ b/test/a64/traces/sim-sqneg-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-2d-trace-a64.h b/test/a64/traces/sim-sqneg-2d-trace-a64.h index 4d45bbc01030ed74f71aa1c4e1896ffc7f22490b..bba95ba85db5e338cb276bc475483d79650d55da 100644 --- a/test/a64/traces/sim-sqneg-2d-trace-a64.h +++ b/test/a64/traces/sim-sqneg-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-2s-trace-a64.h b/test/a64/traces/sim-sqneg-2s-trace-a64.h index 27d4b9b71d9c252378c3d5b27ea82ac6bb2e349d..02bb4b197041df6cba7522539d05d298f997655f 100644 --- a/test/a64/traces/sim-sqneg-2s-trace-a64.h +++ b/test/a64/traces/sim-sqneg-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-4h-trace-a64.h b/test/a64/traces/sim-sqneg-4h-trace-a64.h index f10c092406569cf8f1b2ea155adebdaa05eca02a..f4c88b35ee188b055b5fcf931d90688226b0db6d 100644 --- a/test/a64/traces/sim-sqneg-4h-trace-a64.h +++ b/test/a64/traces/sim-sqneg-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-4s-trace-a64.h b/test/a64/traces/sim-sqneg-4s-trace-a64.h index 5ecbe56065e746a60b64da3d66d0c1669ec45a59..53e1b43668a8c99f3efd550b9a9d8313ba5cec80 100644 --- a/test/a64/traces/sim-sqneg-4s-trace-a64.h +++ b/test/a64/traces/sim-sqneg-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-8b-trace-a64.h b/test/a64/traces/sim-sqneg-8b-trace-a64.h index 8bf9d6ff01cc78c0cea005013ddce1fc94a0fea7..f987ba7b0eb42079e8e23485c52e405650c5ca20 100644 --- a/test/a64/traces/sim-sqneg-8b-trace-a64.h +++ b/test/a64/traces/sim-sqneg-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-8h-trace-a64.h b/test/a64/traces/sim-sqneg-8h-trace-a64.h index 2adcf245acc135f52fd258e434e5dd68a3c1d5f5..decdec89ca7f94469d6461fc7a72b29f9168d49d 100644 --- a/test/a64/traces/sim-sqneg-8h-trace-a64.h +++ b/test/a64/traces/sim-sqneg-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-b-trace-a64.h b/test/a64/traces/sim-sqneg-b-trace-a64.h index a7646a43d199e81099d930a75ee1b96f9b854ba0..469ec4d80f9f24d9d90d74ce9876ca2b6298c845 100644 --- a/test/a64/traces/sim-sqneg-b-trace-a64.h +++ b/test/a64/traces/sim-sqneg-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-d-trace-a64.h b/test/a64/traces/sim-sqneg-d-trace-a64.h index af1ad3388b7ab47900f28b52ae9c251a89bf6db4..72457911c64a872296e217b7b64c9f9bf6e8c8e4 100644 --- a/test/a64/traces/sim-sqneg-d-trace-a64.h +++ b/test/a64/traces/sim-sqneg-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-h-trace-a64.h b/test/a64/traces/sim-sqneg-h-trace-a64.h index 2663beb6bdbc4f3fcf8bf4a54b0ace12ce29e99a..78be96ccd77c5a7ba75757a247a6e95d85b595b9 100644 --- a/test/a64/traces/sim-sqneg-h-trace-a64.h +++ b/test/a64/traces/sim-sqneg-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-s-trace-a64.h b/test/a64/traces/sim-sqneg-s-trace-a64.h index a41fd3a59f0bd248b8aa2f30a8f73c3652ef005e..b3f89b9744eed465821d8ca017e9afe9f1499747 100644 --- a/test/a64/traces/sim-sqneg-s-trace-a64.h +++ b/test/a64/traces/sim-sqneg-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h index 99618a7d9e26497a9c6102cd71bb33d9b01c2ff5..5991dbef76741322a1ba9227a65494e55616ebab 100644 --- a/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h index 9089eb3a48523375808e11f1fb71da3340631a6b..05011d4fa65ad3eda1a0cadb152b2ce6b02ea431 100644 --- a/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h index db7c7eeb52cbe677af089edde155fb46889bf42c..8f78bcf100a9d26784f6f06a8f9b822e7b2ae8c7 100644 --- a/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h index 31ce5162e6b2e30efc65df2b4b1d386f9a16636c..1ce6f3fb4b557b99e4c055809f383c18034fa742 100644 --- a/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h index d7d48bc1465b1f2c37b71e611641e8eb00b0be4e..7ed9f3a29dc996db9e94574e93121e926478790e 100644 --- a/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h index 13402e2f288c4213ce6beba3ef5460daf10dc3f4..e466dbec540b3e4177baeef2f2d9e0dd96d17854 100644 --- a/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h index c1756f659f4d9d0863616e6a95680799653f9f73..d94d9ac4789a29ffca7e31364b3998b85c52ff90 100644 --- a/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h index db51061e1d0c35c0b1bfbcbdf4c973f817716bd2..6a303ee145a37e02678eaadea4d3d163ba39ff65 100644 --- a/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h index 510c60eef58e52185f9d3903f28f08db89d75063..a36ef28428ca0322f3a925c5dce280448da9f75c 100644 --- a/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-h-trace-a64.h index 320cf64fb173fa021aabb12d2c68da4dbafe3099..d3d9559913c5d5ad3c1d6d0aafa2d80b45d6473d 100644 --- a/test/a64/traces/sim-sqrdmulh-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h index 44a4aa28929d0f12bbf05aca4af962dae824f125..a3bba9c5c8e8142eaa121da8a22bc58f17982f79 100644 --- a/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-s-trace-a64.h index 82ae091c2c27d4ea83b737bd166ccf51c38b3d5c..c5d1a975a4df420100c2d8f480e93900bc409e50 100644 --- a/test/a64/traces/sim-sqrdmulh-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-16b-trace-a64.h b/test/a64/traces/sim-sqrshl-16b-trace-a64.h index aaa88a697d8419ad2eaa31405d2a44267b812a6c..9873f85263f92829d0239df1d2aa064c427fb953 100644 --- a/test/a64/traces/sim-sqrshl-16b-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-2d-trace-a64.h b/test/a64/traces/sim-sqrshl-2d-trace-a64.h index bdda8015e91b454281b08c3e5c7498157e59e8a8..83d346f6fa3094bcf3fe19dbcd671a9f7e27c054 100644 --- a/test/a64/traces/sim-sqrshl-2d-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-2s-trace-a64.h b/test/a64/traces/sim-sqrshl-2s-trace-a64.h index bba1f43574bc7f4e805fa41dfbdb84e52c7df5b6..7e3953e985271a397396288c14529ae18bdca7b7 100644 --- a/test/a64/traces/sim-sqrshl-2s-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-4h-trace-a64.h b/test/a64/traces/sim-sqrshl-4h-trace-a64.h index 34720d613c5cf26f0805c02eb62b67d7849f0ccf..e93179d87b907d3fe303fdb394833d7db7be26f9 100644 --- a/test/a64/traces/sim-sqrshl-4h-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-4s-trace-a64.h b/test/a64/traces/sim-sqrshl-4s-trace-a64.h index 2007102577d5ecce2279165e130a58ab72c0cade..a9904545ef9bcd3417ba5d205665da7c5023a3f2 100644 --- a/test/a64/traces/sim-sqrshl-4s-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-8b-trace-a64.h b/test/a64/traces/sim-sqrshl-8b-trace-a64.h index 5e10ea97ad6bfb235c402e4aa9699d6ccc6e10ba..78468cd9247178e21cc1b5977313969d22655cc9 100644 --- a/test/a64/traces/sim-sqrshl-8b-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-8h-trace-a64.h b/test/a64/traces/sim-sqrshl-8h-trace-a64.h index 270950d607b4bdfeb62bf8da18d90fab6fa737c9..2dbe4fb2563b6b6cbab256523d8adca9be39bc73 100644 --- a/test/a64/traces/sim-sqrshl-8h-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-b-trace-a64.h b/test/a64/traces/sim-sqrshl-b-trace-a64.h index efb867210c8965296b2363547465ee06d749fbce..c9b123c524e4e42ba75d047cc75569bbfffdbab6 100644 --- a/test/a64/traces/sim-sqrshl-b-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-d-trace-a64.h b/test/a64/traces/sim-sqrshl-d-trace-a64.h index 4edafe68152a1a31ff392119ee7a0514fe03aeba..b3fe97903b514553cb27bcf53f99453c90983029 100644 --- a/test/a64/traces/sim-sqrshl-d-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-h-trace-a64.h b/test/a64/traces/sim-sqrshl-h-trace-a64.h index 46f2e85d3634288b61b9151be87e645cb4352d8c..94dbe5b934fd5e5de884e2a98e171ec50ee59359 100644 --- a/test/a64/traces/sim-sqrshl-h-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-s-trace-a64.h b/test/a64/traces/sim-sqrshl-s-trace-a64.h index 3d0494806ccc5821f7c5816be3452a4409efe7fa..f51e0ad8d616035080e19185a103f4002868d870 100644 --- a/test/a64/traces/sim-sqrshl-s-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h index e78c176fb02aff3cfbfce34d7ad59e1b311fcf70..6a8f0e9efafa5bf1d02a66ece15f4b3f74d9bb1c 100644 --- a/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h index 5b1101f9890f51ee17272727983c520116e5b3af..904fa1ff2ca2e6613a8d519d76b4cfb3d70450f5 100644 --- a/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h index 15d942debcc2f2f19172cf603127b08b5df97a92..0362bdea40623d846c87a6ab2809d40ace004324 100644 --- a/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h index fcb807d8fb2faed7cf2638fa171fa3bca8fbbee2..d26c9bc437476574286c3a4aa518f1c0b213a964 100644 --- a/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h index 12464ebf891a004ae520f4694a638643a4fc95ac..b033e17e5da2d98b9e6b7aabac4f705ac78b2d30 100644 --- a/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h index 355c9a77157c834048463302d68c78b4b3355a8d..1a0768489cd9be783477b6d6ef10f82faac20644 100644 --- a/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h index a7bf243f59efbc4ac7d8e8154812c38acff0d445..95905e4b7041a9225fe9e70f835bc854e48d8901 100644 --- a/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h index 68fd20ebf263bc570a3483e5f15d6acb0948edfd..8dd1076ca51397687bb95392e9e56b7c92ecd483 100644 --- a/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h index f476c527965f8748a16c78e842fa0581efa7cef4..dbad8ef5521825d5f1681805665642d3789bc350 100644 --- a/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h index 321c75e7d7c655680cff26188920afb441ec23a1..debe901bea7801fc7d1e4b5a9fac722a6191c662 100644 --- a/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h index 2f5731751785798e2538446757d494a4f6d51ad1..3539f79b3ae41bfde19b9844e47066ea11e5fdef 100644 --- a/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h index 4d690ead775c12ff67b07e18dec44fae879c3124..3bc936d9e0252601636cf06920c66d5dd4d42d32 100644 --- a/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h index 73e9ba4265a5bd968bca859d6ec8da42bb76ba2a..288a26bd27d4de2213124c988ce9fbb67496c0f5 100644 --- a/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h index 6d93ff596a2d98b2e8cc0512802740b2dc59f0e8..7723e0fce9077fb3625a9b243ba11596a47bc838 100644 --- a/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h index 5a6e863f184fa70e135a1dfee5f0bec0d2b05c3e..e7c0238fa5ca4c341405d441a032a923d4ec0da0 100644 --- a/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h index 9718dc1230ceea742e649b1a9cda28be97c0f2f9..c647c5b6d3bd3618d684d9101a09dec7b4aac039 100644 --- a/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h index cd56e8c958974bd07e598f0e16c76bfa81ea01b4..5038b4130f49d3732388f46e7ab987fe6978ff23 100644 --- a/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h index e4f81d0538509c4c5453bcb9d80cdb843042e885..0ac441b90229a971776c420e88eb7dd24b4e5294 100644 --- a/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h index eaf120ac2594ba9428958a5622206b838c4360f8..ff1adbf27205415d73e831dfea0b44756fcdc058 100644 --- a/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-16b-trace-a64.h b/test/a64/traces/sim-sqshl-16b-trace-a64.h index 90b1f70545b347f73a4af7c1ee7d4c9cb0c94320..778bef6762935871d3f795f54e12fc9341af9d9f 100644 --- a/test/a64/traces/sim-sqshl-16b-trace-a64.h +++ b/test/a64/traces/sim-sqshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h index ca812f7f0f4263990502271a6092ba85aeb71b72..f00c37870657b60bdcda52c62e4b4d967491169e 100644 --- a/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2d-trace-a64.h b/test/a64/traces/sim-sqshl-2d-trace-a64.h index f0e063926bae9e164a012020c2257d30db6070b8..9df0b9dd967485f25e4db1ed03856e603bbbdc51 100644 --- a/test/a64/traces/sim-sqshl-2d-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h index 79699038355a494538dcaa0d06068e8f020e2b0f..88bf9c62be1ea94f7e16ae8a9bf0ad411c4f793f 100644 --- a/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2s-trace-a64.h b/test/a64/traces/sim-sqshl-2s-trace-a64.h index ce633edd92e31aabcce3212b8610b5c1ae474858..d89d9086082c26f48bf6a0692f4744a2d600c027 100644 --- a/test/a64/traces/sim-sqshl-2s-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h index bdf24a7d04319efe931f126a336ef0df9f18efd2..664293a61230df007b5bf40683a95a5d2c6ed88e 100644 --- a/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4h-trace-a64.h b/test/a64/traces/sim-sqshl-4h-trace-a64.h index 078f8ec18a26a76338d615826627e7765948f3c2..35866af5e61d66cd499ffefd60ad32d9a35288fd 100644 --- a/test/a64/traces/sim-sqshl-4h-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h index 40c3e3cb5585fbcc852ff0356d54753d819ed321..8035632e4bd435e27b38062a14a27bc88896ace5 100644 --- a/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4s-trace-a64.h b/test/a64/traces/sim-sqshl-4s-trace-a64.h index c4c4fa86780340b644ad0769278408af74c19e30..d037d2292442a541e29d2ee48c9ed8fd7f677292 100644 --- a/test/a64/traces/sim-sqshl-4s-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h index 5410eab2910391a9f4e734c389bebd92c28f2863..2f5c448601506fb1c298447a261195fc19cbe46a 100644 --- a/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8b-trace-a64.h b/test/a64/traces/sim-sqshl-8b-trace-a64.h index 8639ec9d440310608e19d7cf513c577813c636cd..f0402d797b9897962282f1127a32850d41ec0fbb 100644 --- a/test/a64/traces/sim-sqshl-8b-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h index 4e4a7fe2b3ca1119ca5b5c3082afd22865b3d4be..90eefd26df66432cd4ade19336e66e53d38e1dd7 100644 --- a/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8h-trace-a64.h b/test/a64/traces/sim-sqshl-8h-trace-a64.h index 98407f2b4b9627767161e327d64daf03a8d4c470..17b0d3a27ab3cf9688aa2b9f61ccadefa6381295 100644 --- a/test/a64/traces/sim-sqshl-8h-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h index 9edbc91568ad637c1ac29b69ae1324ca5c563744..8106176b3526fa8859be6295d5d0b33d3097ae5e 100644 --- a/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-b-trace-a64.h b/test/a64/traces/sim-sqshl-b-trace-a64.h index ceabf62ed117a64f9b02d1b4323c2a2da1e15487..41c6097aacb091673874ea68632e7865d4267ad4 100644 --- a/test/a64/traces/sim-sqshl-b-trace-a64.h +++ b/test/a64/traces/sim-sqshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h index 58f82239d690fb7fda7f61ef4208e67c8dc948c4..7a73959a94fc7a6a7959b0add9f38cbcd30e472a 100644 --- a/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-d-trace-a64.h b/test/a64/traces/sim-sqshl-d-trace-a64.h index 2a920062fd085876bf1c3d1a83edac16312cdfaf..9f63ef7f82e9a833b9c05bcd7ff9f3948b871133 100644 --- a/test/a64/traces/sim-sqshl-d-trace-a64.h +++ b/test/a64/traces/sim-sqshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h index 5d284f71a4ca4c6ef3e1393258f76f44968c9c0a..adb02c4f84e0569ec42030e6032d7c9fc89416e8 100644 --- a/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-h-trace-a64.h b/test/a64/traces/sim-sqshl-h-trace-a64.h index 31400921ea6831c40f157f29f7ff9b7ad86af24e..c552621998b0fd0b71e8a868dfe889ddd211fed6 100644 --- a/test/a64/traces/sim-sqshl-h-trace-a64.h +++ b/test/a64/traces/sim-sqshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h index a9563d6c28dd095b338578b89f7ec422dda6726d..b9c83912578bc86d3df75e00b518e8ed654ef45c 100644 --- a/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-s-trace-a64.h b/test/a64/traces/sim-sqshl-s-trace-a64.h index 6137c33e129ab28c1e032e9b5d21a89469fc8b47..2fdfa5b54c3ba953b0deafd626e5c1db24d6e2c3 100644 --- a/test/a64/traces/sim-sqshl-s-trace-a64.h +++ b/test/a64/traces/sim-sqshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h index 4a4c669e748fe5041e1cb2dd2fe9dc22aa7ae7e2..a68b1896b3d026154324ca22b468e2232f41f9b4 100644 --- a/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h index 5304240d25c56dd383d4e94865d0686e6d43ac97..b07ff6511591db7392d07a98a4952ec6ca3c5708 100644 --- a/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h index ccc3047287bc6564922ce6ec9e2562d78b248587..a01fd38a1cba114358c38cc3b1539eb2b8507028 100644 --- a/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h index efdd93cc603643349936bd49f2d74346c1235884..cebc23422a3feb34f402dc07f6fa81bc34b06d6f 100644 --- a/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h index b4210052e30f2d8f43f3dc437fa998ebf75a67e1..af96e2cb1895acae601159bb91f7d4c1ca661a8f 100644 --- a/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h index b208fe2c7ca687bc7dc8c4dbf82ad23c9e5b6cf1..1dee4cd6526bce106142a0f9a204706b4f8e7633 100644 --- a/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h index 58e14b682f3f32285abeca7eacb5bdd5230742a7..3f6f5efcb7fc9ac10ddd02a71e91515ab2cda9bb 100644 --- a/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h index dd62cd87c1eb0141815487f520246a0d5f76db0b..3cdab4af86af13b201c80bde5adfda9c8ec0de44 100644 --- a/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h index 9b3e472af376c10423360bf96271b8eac85e8145..58941be7c43c1078c89bcaed1f329310eda75f9c 100644 --- a/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h index 0f92352d274f4418f1ea062fc168adf18eb61234..85128fcd346c09d0d22bc459d50b049931383c91 100644 --- a/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h index 7ce436b78297751aca590402d823ade1fbcf05fd..bcd4546a5ee423c1a764c680136dd3cb6d0e14fe 100644 --- a/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h index 2748094971e7de2c2be476d549a7745866f0e0b1..51c9d27b80ceaa42d23523999684149bfd7adf16 100644 --- a/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h index 5f5577ebfd2724bcf0b6065cef6543a34bd0252a..3a173958a7d65a3a72cb895b32a6fb6f72f9d85c 100644 --- a/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h index 789337206258169c4f559421936a5297ccdc808a..cba9f8caee05f8b834dfdcb9026a6787ce1ddd6c 100644 --- a/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h index 8c1a0d6153b14d1944737908e7b49cb252b2a277..d5609c9d8f6c2d09a8f54e9f882028d119bed44d 100644 --- a/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h index 874a6f1a72a2164730f89e2ebdb15f9c5f0c512b..a1ff41c6958ccc8f0abafa3de4b1ee9d5541fb93 100644 --- a/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h index 9d1471a06bdea8db8f2f55d171136e67b5a299d5..a4fd9833993d24352b3e336ec94f03b94482ecd0 100644 --- a/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h index b98d0ee2951bc392ef82835facdb60c2c78768b6..bff5cd6e6a334f076d7e1ea30d66ff3b3cf25445 100644 --- a/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h index 47a0d5020b1ca617f66eabccbada39c03b3846b7..23863a11ff592953577959e5609d92eaedb085fc 100644 --- a/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h index 4491a26cb3063d4d75af98d7e9015a606854566a..fef87a8d51ab1a1ddcfd44d45ba5e9f74e59f425 100644 --- a/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h index 03c00fa2038e80b8dc273fd7106dd55ac248f4ff..36f376cb2fa6bf50f64cdfc5c459107bcfa643fb 100644 --- a/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h index 2d4971eba5dd121aa13d6cdb403c5586fdb8bc1f..d44a69a96497f95a66a05f59e5091d20f60192aa 100644 --- a/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h index 691a9181bdef2cab3c07ddac2994aa8a68db4a2f..7d03eb1cac9f15cf1215c5fd9b2c8772549f5f16 100644 --- a/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h index 4ad7add8fd7c4cbd45f3173af92671b45d831d1e..80dee542a53989c9ee306ba993f5d2fcd9b348c8 100644 --- a/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h index 6f5718e65ed18612292be2de4c306556f614b8fe..bf6cc694c620060a21ec6ad010d0ebd33e16ae70 100644 --- a/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h index 84a3ead4b9cab6d6d462f6f002903f7b9a694bc1..cb8a502788ee1e75e968c8f1a0046f4dfea11d0a 100644 --- a/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h index e7cc89a10ba3f261cec4b524c637ebd07fdf6d13..2c7f94551f67b9123c7f42448a0ff33e8316b3b6 100644 --- a/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h index b264f9f97fd4cd629af0161b49ff2ab8b0bf36ca..51751468740ed41b6cab60ea75532d01f6db875a 100644 --- a/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h index f68fe9faaac200e00c659f49854bc7c709744e72..b8af360e66662f1c858aace26ee121394b85fbfe 100644 --- a/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-16b-trace-a64.h b/test/a64/traces/sim-sqsub-16b-trace-a64.h index 506c0a3120f13d291d08967757dc25991a1aa7e9..acf0a49f800ac4374b2eeb37ac83584fee1aa879 100644 --- a/test/a64/traces/sim-sqsub-16b-trace-a64.h +++ b/test/a64/traces/sim-sqsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-2d-trace-a64.h b/test/a64/traces/sim-sqsub-2d-trace-a64.h index 01f957702aebd168359cb08bafa23f45f4b5d119..e58dced3380aa11a1db8fa4ff81d7187ded73624 100644 --- a/test/a64/traces/sim-sqsub-2d-trace-a64.h +++ b/test/a64/traces/sim-sqsub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-2s-trace-a64.h b/test/a64/traces/sim-sqsub-2s-trace-a64.h index aa64d1adba067567a8f9a6e638bbcd455c847af9..57e6c61f8d966e83f2c6a17ac1f18fa3ba83bb0e 100644 --- a/test/a64/traces/sim-sqsub-2s-trace-a64.h +++ b/test/a64/traces/sim-sqsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-4h-trace-a64.h b/test/a64/traces/sim-sqsub-4h-trace-a64.h index 66d70d76eb5888ad14becbe7972287ee15f80301..05388bac21e8bfdbf3f9b8d925ce6fe8b5318c2a 100644 --- a/test/a64/traces/sim-sqsub-4h-trace-a64.h +++ b/test/a64/traces/sim-sqsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-4s-trace-a64.h b/test/a64/traces/sim-sqsub-4s-trace-a64.h index f65de688883395f48dc99a5f7074e2febbc68145..2eca3d49a80018fdff8ceb06a1a0cd82721a647b 100644 --- a/test/a64/traces/sim-sqsub-4s-trace-a64.h +++ b/test/a64/traces/sim-sqsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-8b-trace-a64.h b/test/a64/traces/sim-sqsub-8b-trace-a64.h index 7a734cbbca27ff0dce2bf020aa2a0dd10926a187..2f5ce4c4356e2b5cd9da1693f7b67bd4c8e61c32 100644 --- a/test/a64/traces/sim-sqsub-8b-trace-a64.h +++ b/test/a64/traces/sim-sqsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-8h-trace-a64.h b/test/a64/traces/sim-sqsub-8h-trace-a64.h index e94f0a61698058b9f0bf94408cf52a0bff42e3f2..23bc1e83e6e7904ec469e1089e411dda878f29cb 100644 --- a/test/a64/traces/sim-sqsub-8h-trace-a64.h +++ b/test/a64/traces/sim-sqsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-b-trace-a64.h b/test/a64/traces/sim-sqsub-b-trace-a64.h index 090357653530fbadd80d3c076c4dd1b6b569ffdb..1b7c221669c59913081be8cc85c47ad844c88257 100644 --- a/test/a64/traces/sim-sqsub-b-trace-a64.h +++ b/test/a64/traces/sim-sqsub-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-d-trace-a64.h b/test/a64/traces/sim-sqsub-d-trace-a64.h index fc36ff3eeb93305466a6946e117a01a2ccd4c9d7..4f93861e7a026c57033a04fdedfad0fef47ac8c2 100644 --- a/test/a64/traces/sim-sqsub-d-trace-a64.h +++ b/test/a64/traces/sim-sqsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-h-trace-a64.h b/test/a64/traces/sim-sqsub-h-trace-a64.h index 17a02639ee1b282051ef746f72af97fe4b4b4e38..68aef5320b7c7de0e23afb04c48c6d442bc83ee6 100644 --- a/test/a64/traces/sim-sqsub-h-trace-a64.h +++ b/test/a64/traces/sim-sqsub-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-s-trace-a64.h b/test/a64/traces/sim-sqsub-s-trace-a64.h index 5999dc3b46d3e50e14648f5057400019e6b5f78a..1ae965eeeeb884be19fc835e3fd28379fd72621d 100644 --- a/test/a64/traces/sim-sqsub-s-trace-a64.h +++ b/test/a64/traces/sim-sqsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-2s-trace-a64.h b/test/a64/traces/sim-sqxtn-2s-trace-a64.h index 6c2ac718ec82949ca9e93fb27622ff5e85989f91..09255a091f5acd847c1284ce860209e3814f66b9 100644 --- a/test/a64/traces/sim-sqxtn-2s-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-4h-trace-a64.h b/test/a64/traces/sim-sqxtn-4h-trace-a64.h index 31730882495cf382c1cd4caa1cdbdbb4a8ee4cc5..8c3804d7f5012e08a20c6e5e7edc7d3fd9b60226 100644 --- a/test/a64/traces/sim-sqxtn-4h-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-8b-trace-a64.h b/test/a64/traces/sim-sqxtn-8b-trace-a64.h index a8771a68b0f1dc7e8c843bf89ee99d5b7d148bf5..e038c5820276ca789ae860707cb4ca0e0b86bbef 100644 --- a/test/a64/traces/sim-sqxtn-8b-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-b-trace-a64.h b/test/a64/traces/sim-sqxtn-b-trace-a64.h index 8491177d7befae3d1cb1cf7fb0733da8f21da313..4e31b2f0bc9e595fe9638b5e2d5ad9193159869e 100644 --- a/test/a64/traces/sim-sqxtn-b-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-h-trace-a64.h b/test/a64/traces/sim-sqxtn-h-trace-a64.h index 0eaae7f0abce16d9dabf5f8415d1081dae96b5e8..462c9d172f5ef9ff7f5258e65a7e7d0057ee733a 100644 --- a/test/a64/traces/sim-sqxtn-h-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-s-trace-a64.h b/test/a64/traces/sim-sqxtn-s-trace-a64.h index 3af19756b8cee711ed1c368af44b012d0856325f..667365429b5092904e1d2917ac2d1d45323ca2ed 100644 --- a/test/a64/traces/sim-sqxtn-s-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn2-16b-trace-a64.h b/test/a64/traces/sim-sqxtn2-16b-trace-a64.h index f5855562190985d99258f59852f020d2d03ac418..4aa4eaebf80b9cef8acc7203897a83f6d463cdfc 100644 --- a/test/a64/traces/sim-sqxtn2-16b-trace-a64.h +++ b/test/a64/traces/sim-sqxtn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn2-4s-trace-a64.h b/test/a64/traces/sim-sqxtn2-4s-trace-a64.h index 79596c351678ed83cc18657009f2c29e3adc684f..0d9cca73ce0ece8ab2dcc643bca35aa9591bc7a7 100644 --- a/test/a64/traces/sim-sqxtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqxtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn2-8h-trace-a64.h b/test/a64/traces/sim-sqxtn2-8h-trace-a64.h index c05100aaa713347acfd2032b80e9e62d453d9924..c83bc12e125e8532f8f548f431c44b3d9222bc1a 100644 --- a/test/a64/traces/sim-sqxtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-sqxtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-2s-trace-a64.h b/test/a64/traces/sim-sqxtun-2s-trace-a64.h index 3bb7b9e9f174460e17a196ed29afe5e3d5dfbf70..9006fff43eff9563b946028e4719256a1addc6a0 100644 --- a/test/a64/traces/sim-sqxtun-2s-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-4h-trace-a64.h b/test/a64/traces/sim-sqxtun-4h-trace-a64.h index b9ed73afb134a7764e95e9d3de479b75ba44ffd8..57f6f794ea30901730319256619566f2716e9414 100644 --- a/test/a64/traces/sim-sqxtun-4h-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-8b-trace-a64.h b/test/a64/traces/sim-sqxtun-8b-trace-a64.h index 7221366e836187d63ccde622b778c3741aff8f76..50dc1cda72eca86e7d7229c5278418bc9215f29d 100644 --- a/test/a64/traces/sim-sqxtun-8b-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-b-trace-a64.h b/test/a64/traces/sim-sqxtun-b-trace-a64.h index 16501ea08053b0e3841ffe9e4aa71191ed5cfbd3..257f5ae3df8e09707aff8e2e8ccb73c22f148f1f 100644 --- a/test/a64/traces/sim-sqxtun-b-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-h-trace-a64.h b/test/a64/traces/sim-sqxtun-h-trace-a64.h index c653c58acdcb5df5b3dc8bfecd6829f31adbba23..d022aa52c7de22d7b436ef6508eccca044206261 100644 --- a/test/a64/traces/sim-sqxtun-h-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-s-trace-a64.h b/test/a64/traces/sim-sqxtun-s-trace-a64.h index 1babed645c0a15df0299322b6aaf28fd93c1721e..f7f31ee2646d2ae151c741f60190a2ca67af99ed 100644 --- a/test/a64/traces/sim-sqxtun-s-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun2-16b-trace-a64.h b/test/a64/traces/sim-sqxtun2-16b-trace-a64.h index 54995228f7bde884efd7c92af73022a136e2c517..efb0c45c5d126e427b2a2a5a4081995833a6151f 100644 --- a/test/a64/traces/sim-sqxtun2-16b-trace-a64.h +++ b/test/a64/traces/sim-sqxtun2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun2-4s-trace-a64.h b/test/a64/traces/sim-sqxtun2-4s-trace-a64.h index da5c682c02836fbeb9bf61b456ac326b19ac8bb3..136f9e7d73c0e7e7dd164c273b5dbe417b772592 100644 --- a/test/a64/traces/sim-sqxtun2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqxtun2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun2-8h-trace-a64.h b/test/a64/traces/sim-sqxtun2-8h-trace-a64.h index c0c51627f843f4e5a6fb0d509dd4d76ca8d9cc31..cec02fbec0dec19de1925553a81b164421e4cdf0 100644 --- a/test/a64/traces/sim-sqxtun2-8h-trace-a64.h +++ b/test/a64/traces/sim-sqxtun2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-16b-trace-a64.h b/test/a64/traces/sim-srhadd-16b-trace-a64.h index f59a5b84dd6779ef17fb9b6633240fbe65e87ffb..1cbf242298656681fc840b05863e3fe79fc710fc 100644 --- a/test/a64/traces/sim-srhadd-16b-trace-a64.h +++ b/test/a64/traces/sim-srhadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-2s-trace-a64.h b/test/a64/traces/sim-srhadd-2s-trace-a64.h index 1b0d9d25e04047c85e0e81910bee2ddb3f84a140..e2b19d8462b635d0421295e1ebedaf280afda078 100644 --- a/test/a64/traces/sim-srhadd-2s-trace-a64.h +++ b/test/a64/traces/sim-srhadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-4h-trace-a64.h b/test/a64/traces/sim-srhadd-4h-trace-a64.h index 488ebc82f761831eb623f266c40d486e27e06619..2c2593fd2541f740dd831234285d5a0f482b49e3 100644 --- a/test/a64/traces/sim-srhadd-4h-trace-a64.h +++ b/test/a64/traces/sim-srhadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-4s-trace-a64.h b/test/a64/traces/sim-srhadd-4s-trace-a64.h index 3a33abedb269d443a1408b862ff470e1d3273688..df14525ce625ae1b7896c5d06e12296bd451b206 100644 --- a/test/a64/traces/sim-srhadd-4s-trace-a64.h +++ b/test/a64/traces/sim-srhadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-8b-trace-a64.h b/test/a64/traces/sim-srhadd-8b-trace-a64.h index 38eaaee1a9c1ee92ca4f4e8da4184ea7736a292a..adc1ac77f9a5dab8bde72d96ff3b0800eacd7a8b 100644 --- a/test/a64/traces/sim-srhadd-8b-trace-a64.h +++ b/test/a64/traces/sim-srhadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-8h-trace-a64.h b/test/a64/traces/sim-srhadd-8h-trace-a64.h index feed3b9e5504f8193fb8a515a157bf2ea2cb6618..956066fa2f38491b50e988f8e9bb9867f90dcfbb 100644 --- a/test/a64/traces/sim-srhadd-8h-trace-a64.h +++ b/test/a64/traces/sim-srhadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h index b35cfa0781cd8955d36399cfc19354f9cc853b88..059152f32fdf753aa6e12e097dfb83b14d242e32 100644 --- a/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h index 1c88c68770d23f7a5858801ce882dfed18eae985..7631259bd448867c4fc6a006f881b60be60a4f52 100644 --- a/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h index f627cbc810fbbfa994d3af5c401376093060ef6a..6bf9d9e389bddb2844b564c8be992a16c6f7183f 100644 --- a/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h index 774cac7055793a023966ff3ce52eaffe8861fa9b..d88977d65faa91b9625dc5f65148e04c5d47a375 100644 --- a/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h index d563c869e6d6f7ab479a1883fdfd27c871a4fc58..aec1697580299e9810fbedf71b8f46a1e81f2219 100644 --- a/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h index 9b38a568e5888957d38fb58234035c301910029e..5b6a8f5674151e2c1e168ac128f45afea86fa160 100644 --- a/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h index ec1805423ccbe0f612b09da0c1309cf958f7dd92..6accb8d7a52e27b9beebef814f665d496151d380 100644 --- a/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-d-2opimm-trace-a64.h b/test/a64/traces/sim-sri-d-2opimm-trace-a64.h index b58bc89904b899fa1cb183cde05948a8d94cc270..3fe9a7da5b27d9f59f6cc9b9b3137bf507feb287 100644 --- a/test/a64/traces/sim-sri-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-16b-trace-a64.h b/test/a64/traces/sim-srshl-16b-trace-a64.h index de5e0d1718bbb4ca96e4d8c07507eadc555672ea..36454e171531e822be64e76af324a4920943fa91 100644 --- a/test/a64/traces/sim-srshl-16b-trace-a64.h +++ b/test/a64/traces/sim-srshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-2d-trace-a64.h b/test/a64/traces/sim-srshl-2d-trace-a64.h index 99d390eb86d2dce388e815bc7a8caf81e8ec77ab..86591cfd821fb6c145ca3dadd88ab83076bd3101 100644 --- a/test/a64/traces/sim-srshl-2d-trace-a64.h +++ b/test/a64/traces/sim-srshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-2s-trace-a64.h b/test/a64/traces/sim-srshl-2s-trace-a64.h index ce2c326b91e095e8d964cdfca5150c99fd53490c..8b433d51458ab80598e3c6dbc581914a9cbbccae 100644 --- a/test/a64/traces/sim-srshl-2s-trace-a64.h +++ b/test/a64/traces/sim-srshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-4h-trace-a64.h b/test/a64/traces/sim-srshl-4h-trace-a64.h index f21f4fa776fa5c1fa2b1ea7fc51c5b6e9628353c..059a3dff87181b2583d4ff13b427075cd1e9c0c6 100644 --- a/test/a64/traces/sim-srshl-4h-trace-a64.h +++ b/test/a64/traces/sim-srshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-4s-trace-a64.h b/test/a64/traces/sim-srshl-4s-trace-a64.h index ef4f6f51b96ee7cc3935e1efd821ca036451a917..5e44a9f77b7df1e66b626a289bef7c1db5fb43d6 100644 --- a/test/a64/traces/sim-srshl-4s-trace-a64.h +++ b/test/a64/traces/sim-srshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-8b-trace-a64.h b/test/a64/traces/sim-srshl-8b-trace-a64.h index c42141c9ef9c8e34cd3f8d696b647c951ea2e9b4..cda7942860f53387fb46d788be762ec537dfdf2c 100644 --- a/test/a64/traces/sim-srshl-8b-trace-a64.h +++ b/test/a64/traces/sim-srshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-8h-trace-a64.h b/test/a64/traces/sim-srshl-8h-trace-a64.h index aaf660e189c37d66da3432a6d41cd7528b9d3938..43fc114f924caa6b3ea81530bbbf0ea2b04cde7a 100644 --- a/test/a64/traces/sim-srshl-8h-trace-a64.h +++ b/test/a64/traces/sim-srshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-d-trace-a64.h b/test/a64/traces/sim-srshl-d-trace-a64.h index 58b2cb3c0425c8f0cfc81f94ad8c09018080cec5..38c6926645f2fe2c86a3176966ca379268569c65 100644 --- a/test/a64/traces/sim-srshl-d-trace-a64.h +++ b/test/a64/traces/sim-srshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h index 998a192237efab8f1fe81c8b2b0c54dc8e418d01..9d8710f7395e6b2fa6cb71402ac2a83169a3327a 100644 --- a/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h index 3f3abd992c4e65765a9130c682e6c4f467b18251..8970eb5225c2d986c90f4931110ff76d3121b0b4 100644 --- a/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h index 533cda50b82bc6da68b220947f36159192d21901..3bb36819810f8708b675e3f6efb04c0bc36b1c58 100644 --- a/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h index b8b903c2e04a97e4d3115a0f047981017cecdbac..6e886b051d500f040c81c4d25cfa8550d7f430c1 100644 --- a/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h index bc313e9ac22658f2f0de2e82700c6c9fd695dac0..0f9b353cfa598e4a90be0e1ee34037a5dd7402a8 100644 --- a/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h index c8dab33aa5d4d96ae207d0efa85125b33998baff..9f6f779bb782335e2b7bf33f3e82b27aaba988b4 100644 --- a/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h index a54f6205fc1e8d4ead7c81479b91669ae5d8505e..d2dad19ef8c3079ca91691edcb2da3171bed4afc 100644 --- a/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h index a0a0ee328e98f223e0fa2ac79a02b128c40e367b..367b1cddee58db9006c7ffc9f47d8662f1874c37 100644 --- a/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h index 9b32579ced3c319aa34c86f9bb80801f27cd3cd8..5af95960de777ac8c489586602f939f5479deb48 100644 --- a/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h index 41505d2027b86c1dc6bbf7c7fa09589a909e935d..6cd53161324f6f84b96f4bbcec3fd892c62926a7 100644 --- a/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h index 4cb0f07f2e98b4db33ced0c44729e0e23a675f28..dfdb96ead65d7b84e395484edaf2c4ef1e24791a 100644 --- a/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h index 774e215731753b164bfb74eb225bf1506f8f9120..076f660c67c9f88d85a6d72c6ef3795e66f03dd6 100644 --- a/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h index 7018a8986c185cc85ec9e10bf4862ff11859fc24..ad9b675fd4a2a624b0731bca4b5cfeb9f50350ee 100644 --- a/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h index 2f9d52db3783ac5b09199b315882eac1625aa61f..23dd51a31339daf8641e4f395385a7b11058b2be 100644 --- a/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h index 44093715d60828d779f100ff7944f550c2c05264..5f027765c8febb93c4513511b2c6c471294b5eeb 100644 --- a/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h index c0710f1f227a28c6d1359c5d038b04bb81287f8f..b9795d50a58162b807e18e8ecb9c5d7c33d2648e 100644 --- a/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-16b-trace-a64.h b/test/a64/traces/sim-sshl-16b-trace-a64.h index 69558116943e59cc1d4e1fb344ab009f1eb244e6..5cc4d9158234181d974cfe537a92a951477bd6d3 100644 --- a/test/a64/traces/sim-sshl-16b-trace-a64.h +++ b/test/a64/traces/sim-sshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-2d-trace-a64.h b/test/a64/traces/sim-sshl-2d-trace-a64.h index e2645bc9f80069a62df8775d2c79e38abda9cb66..badcf175830966b4f9543dc0e731d008c17bc976 100644 --- a/test/a64/traces/sim-sshl-2d-trace-a64.h +++ b/test/a64/traces/sim-sshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-2s-trace-a64.h b/test/a64/traces/sim-sshl-2s-trace-a64.h index ff80f97e4477788be96c49f732d9d8d6a2775877..4538f9c1eee6380a9fda04108e6dcc83d69c521a 100644 --- a/test/a64/traces/sim-sshl-2s-trace-a64.h +++ b/test/a64/traces/sim-sshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-4h-trace-a64.h b/test/a64/traces/sim-sshl-4h-trace-a64.h index 84378da8662cec52a80e404fd485412a4b64c544..a3639406c35be34ff775314f186347cc5c5f8542 100644 --- a/test/a64/traces/sim-sshl-4h-trace-a64.h +++ b/test/a64/traces/sim-sshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-4s-trace-a64.h b/test/a64/traces/sim-sshl-4s-trace-a64.h index 92306bb3c18c2a56d0f107c2827ab9fcc26e4b1d..c1627b51933807b26ae3069666a0d485dae4ff8b 100644 --- a/test/a64/traces/sim-sshl-4s-trace-a64.h +++ b/test/a64/traces/sim-sshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-8b-trace-a64.h b/test/a64/traces/sim-sshl-8b-trace-a64.h index 92cea1fe1ecc7aa38e233d585feb9af235dc4b16..8f0b744d3de50c12e1f3a5fdbd16fb4976f66f7c 100644 --- a/test/a64/traces/sim-sshl-8b-trace-a64.h +++ b/test/a64/traces/sim-sshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-8h-trace-a64.h b/test/a64/traces/sim-sshl-8h-trace-a64.h index 626ff832edc8e98871457e9ad437f685a336178b..46b18ca67f60c01d367e18662bbedd0552c10c39 100644 --- a/test/a64/traces/sim-sshl-8h-trace-a64.h +++ b/test/a64/traces/sim-sshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-d-trace-a64.h b/test/a64/traces/sim-sshl-d-trace-a64.h index 73b57ad467001f4a83e4e15016d7f9e67c08d7eb..acf05428f8e080227788107ff8f294ae055f78c1 100644 --- a/test/a64/traces/sim-sshl-d-trace-a64.h +++ b/test/a64/traces/sim-sshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h index b5fabad59eeb0f4033b0ffe0d6b4001891f83626..03cda2e59d584e4c389bca214ff8aada180b2fb0 100644 --- a/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h index ec38c4561404f0630486c3143f2ef7e60c1c5de8..ad12fda7c488a90be8df14c61a78be7f4ec06d97 100644 --- a/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h index eac755321e05861762c2fb0eb3f27bf3f1098500..aba476e16811e79e32b53539ab887c2a9e450bb1 100644 --- a/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h index fe7382ced3fcbb7b61ad5771bc16325ef58a5fd2..d5acaeada4009dbca275bd5a9a0183d0baa63c5c 100644 --- a/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h index 2e96c92638b3e3f95c03368f92093ff231dd1f0c..6b82223b3c65b1fb655e8504198899d5bc5b999d 100644 --- a/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h index 8a9686a9600046abfffa7c96c025064e73da412b..6803ad161a61cbfb2ba524c55891a650d3ea3201 100644 --- a/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h index 630f57cfc787271b407a144f6ba137c88a9566d1..f7c0e71f05f267b2fa3d5e8781601ac2b9957d6a 100644 --- a/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h index f833f81dbe4c4d6dd1f820fa0596854eaaf72005..464409376e8f22800b671ce09cb756ca31708fa5 100644 --- a/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h index cd300910aed4beda1b9fe30df717254085521d04..56f1245e36fb2ddfbf228270390c34bae087a072 100644 --- a/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h index 3611c15bb03d1227609194148d362ff1e6ab3a75..9797d6886936a3abe5e52b84244b7f00e418c958 100644 --- a/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h index 6077dc5461e483900fe6bafdda5b475949c6f045..2146cf688f1231114aaae7ed00f7263a08e9eeba 100644 --- a/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h index a2907d29c1574472653115e6657c14b5eac0db3a..d15f608efa3c15c3909e415add403362cdcb1a60 100644 --- a/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h index 707a9bce07c2c0feb922c1d54b6e87debb9d4d73..915564011656b9de21f035af71be740ce9b82fbf 100644 --- a/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h index 938a7229ca2f9850e256b29fcd515bc866af5906..ce8e0ff9981654b878ad18c993e8aed5a659b086 100644 --- a/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h index 5e059a575da105bcb36cff5f7849429a44858764..d8ce467f27f81cb6e911d1ad3ddc5e84abb56160 100644 --- a/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h index ccfd71337d7370dc06018aaca24fbf74c8407616..d6a73aabfe3f33000d47053c814a87c967782446 100644 --- a/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h index b954507fe12ef4fd175fa97d3e87af3d2df53cc2..f70aea11ae9c32681ffa68537ae2e7202cc96eab 100644 --- a/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h index 7f093b10b34789c557356e6cc42e171aa87b27d3..c446f5c3aa750f5b7df4194ba8d90df41769f0b8 100644 --- a/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h index a0344d6a4d198100c6e7f7e245a584d43d986e79..09095f585b7eb8f81f0f1d1ac7e5c0858f05dd0d 100644 --- a/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h index 0df9f6048f892d079e0f2cd049be3f9778d4930b..6e0254a4fda57642284ec4b627afa565a815babf 100644 --- a/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h index 579406aa81b9a7bbf6b0479d725b2eca4fb71c88..7d3b2d155591ef8e3df310730a0f993802f3e0e7 100644 --- a/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h index 6e5f2b983d0a0031d8297c12b72f3e546a5bc6a1..8275da0534908dba9c2e5deac5ea22c7f0ea6a7a 100644 --- a/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl-2d-trace-a64.h b/test/a64/traces/sim-ssubl-2d-trace-a64.h index 000ad4d5aa5a64dd09836d250aaf604403277f08..f77fa8673b0db747ea66dbba80cbc2461ed241da 100644 --- a/test/a64/traces/sim-ssubl-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl-4s-trace-a64.h b/test/a64/traces/sim-ssubl-4s-trace-a64.h index 0de4c15ef407130172dcf2eee386e5f5b0dfa9a8..a048c64defb3005807fd3b4d8b5b850fc089fb37 100644 --- a/test/a64/traces/sim-ssubl-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl-8h-trace-a64.h b/test/a64/traces/sim-ssubl-8h-trace-a64.h index 79bf0ff704119702b0d4db9117ec90e42af1a7fb..78bb9fc09df6916edc08b4b67ecf5e9314feff10 100644 --- a/test/a64/traces/sim-ssubl-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl2-2d-trace-a64.h b/test/a64/traces/sim-ssubl2-2d-trace-a64.h index 03f8e45977782055cc383b79cea131d67a06d982..7e1a004c77e21f5c8b60591dd943c6a205cb3409 100644 --- a/test/a64/traces/sim-ssubl2-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl2-4s-trace-a64.h b/test/a64/traces/sim-ssubl2-4s-trace-a64.h index a39c797068588d8244d37afd50616d1129fcd5b7..bf372ba55f2514cb8ffd1d1f4ceb5b2f00c7465f 100644 --- a/test/a64/traces/sim-ssubl2-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl2-8h-trace-a64.h b/test/a64/traces/sim-ssubl2-8h-trace-a64.h index 210e0297c71d4119a382538d65149a7aeda6a564..a8b2e74d748a9a6cb6cf31cda0e21d36282eb90e 100644 --- a/test/a64/traces/sim-ssubl2-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw-2d-trace-a64.h b/test/a64/traces/sim-ssubw-2d-trace-a64.h index ff7395da9d394c61be1ab9c5c1e5dc715e485288..9eb605101127f9cfcd837eec429e01c9dc49d287 100644 --- a/test/a64/traces/sim-ssubw-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw-4s-trace-a64.h b/test/a64/traces/sim-ssubw-4s-trace-a64.h index 355f492b20a5de046438bed05bff981979ecaedc..60508f0498a4679fdd33d016b1b94b4e15e84cb5 100644 --- a/test/a64/traces/sim-ssubw-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw-8h-trace-a64.h b/test/a64/traces/sim-ssubw-8h-trace-a64.h index c0b18c610ba9e8f2702b5c8cf9ce297e14f06266..c88625dbef4d38a9e851f96fd8732e834bc85fc9 100644 --- a/test/a64/traces/sim-ssubw-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw2-2d-trace-a64.h b/test/a64/traces/sim-ssubw2-2d-trace-a64.h index 3836cb2612825325bb0222d2f75d8318904d808f..37c140c05355515222faa28e35e9931fb3d82564 100644 --- a/test/a64/traces/sim-ssubw2-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw2-4s-trace-a64.h b/test/a64/traces/sim-ssubw2-4s-trace-a64.h index 91dd3cddaff338f7d7a9a039e1418c17479a2191..eb8fc8d3e9d4d5dae8c6b188aca610e1f900d238 100644 --- a/test/a64/traces/sim-ssubw2-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw2-8h-trace-a64.h b/test/a64/traces/sim-ssubw2-8h-trace-a64.h index d34f02e5a15f903cc0fbc00def5eea302a9de89a..56f64376f57b91b6d1eabc5a2de9071fbde376a4 100644 --- a/test/a64/traces/sim-ssubw2-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-16b-trace-a64.h b/test/a64/traces/sim-sub-16b-trace-a64.h index b0fa3331f0086dce3be7189186710d89f34db8ed..2b0236b6176e98c11eab07ee4435708eda343011 100644 --- a/test/a64/traces/sim-sub-16b-trace-a64.h +++ b/test/a64/traces/sim-sub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-2d-trace-a64.h b/test/a64/traces/sim-sub-2d-trace-a64.h index 43c5f3553f5376a6ea1026f99c6661d761a2fbab..1be6cdb563afe8c4b46cc4c3afc3fdb5f831d65a 100644 --- a/test/a64/traces/sim-sub-2d-trace-a64.h +++ b/test/a64/traces/sim-sub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-2s-trace-a64.h b/test/a64/traces/sim-sub-2s-trace-a64.h index 560c5893af548a551a966c1e4cf9b49d8a31c6bf..81913da11e4544505d84c06c0f2a53c09402bd3d 100644 --- a/test/a64/traces/sim-sub-2s-trace-a64.h +++ b/test/a64/traces/sim-sub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-4h-trace-a64.h b/test/a64/traces/sim-sub-4h-trace-a64.h index f7aec505d61d7c54ad697f515e031ec044f38cf4..4784225608af89894a699cc25dbee6bb01550b83 100644 --- a/test/a64/traces/sim-sub-4h-trace-a64.h +++ b/test/a64/traces/sim-sub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-4s-trace-a64.h b/test/a64/traces/sim-sub-4s-trace-a64.h index 38ed21b4c517915137e7fef37df8dfb8dd265b75..7d6903fe4c7d1ba6ef71cf03d2f0580c0a2fe4ae 100644 --- a/test/a64/traces/sim-sub-4s-trace-a64.h +++ b/test/a64/traces/sim-sub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-8b-trace-a64.h b/test/a64/traces/sim-sub-8b-trace-a64.h index 3621ff73c6e9a39652447a41acfe7972c5a70096..3b9056693acb41a4111355d556beab768454bcc7 100644 --- a/test/a64/traces/sim-sub-8b-trace-a64.h +++ b/test/a64/traces/sim-sub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-8h-trace-a64.h b/test/a64/traces/sim-sub-8h-trace-a64.h index 518712c7aeebacae911487179686871b4efbd7ca..8070ae740788f8e154d3b0b41b43baeef72e205a 100644 --- a/test/a64/traces/sim-sub-8h-trace-a64.h +++ b/test/a64/traces/sim-sub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-d-trace-a64.h b/test/a64/traces/sim-sub-d-trace-a64.h index 996139a69a50df7246dae4c291f7240cc7d1f7d1..462167cedd20cc2d6ea65ae5262b87cc32b6b9a3 100644 --- a/test/a64/traces/sim-sub-d-trace-a64.h +++ b/test/a64/traces/sim-sub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn-2s-trace-a64.h b/test/a64/traces/sim-subhn-2s-trace-a64.h index 87d70d2a7a89e4263fc716b86a83165acce7d617..e463664e5f806f4a368fc8aecdcde74c959175bc 100644 --- a/test/a64/traces/sim-subhn-2s-trace-a64.h +++ b/test/a64/traces/sim-subhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn-4h-trace-a64.h b/test/a64/traces/sim-subhn-4h-trace-a64.h index 2ec8b0bdd4dff9b0d058435d3483d5da24fcc36e..beb41272aea1d1eca61ce84a6efc219c54a829ee 100644 --- a/test/a64/traces/sim-subhn-4h-trace-a64.h +++ b/test/a64/traces/sim-subhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn-8b-trace-a64.h b/test/a64/traces/sim-subhn-8b-trace-a64.h index 73656e1ddd7e773ea6bb61096dde184a399c53c2..d98b3ca1f1a370d377ea19cab00217855768a243 100644 --- a/test/a64/traces/sim-subhn-8b-trace-a64.h +++ b/test/a64/traces/sim-subhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn2-16b-trace-a64.h b/test/a64/traces/sim-subhn2-16b-trace-a64.h index e58e07ac99b67f9c0170bc0fa46b3c963088b829..b2f4110baa32e344e71b2d37ebe9cf29b652b6eb 100644 --- a/test/a64/traces/sim-subhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-subhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn2-4s-trace-a64.h b/test/a64/traces/sim-subhn2-4s-trace-a64.h index 01ae1c7db0a12c44c8cb25821dd1ef79aab890b5..fa056bea35500513f816075c8a87abe60203e128 100644 --- a/test/a64/traces/sim-subhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-subhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn2-8h-trace-a64.h b/test/a64/traces/sim-subhn2-8h-trace-a64.h index 051b164c40525440cc5566580ca06b1d6322bd8c..344970db3bce8b7a7418b5240c880381d8acee8a 100644 --- a/test/a64/traces/sim-subhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-subhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-16b-trace-a64.h b/test/a64/traces/sim-suqadd-16b-trace-a64.h index fb0d0fc8d4fc19d4b13e625cf15474642d4885fe..4b8f14bf86ff47476b8f8e9b27ef84fc8596936f 100644 --- a/test/a64/traces/sim-suqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-suqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-2d-trace-a64.h b/test/a64/traces/sim-suqadd-2d-trace-a64.h index 126d916c97bdeb86adc6eafe362832f657e96bef..98f8b6b879deec5a84d61e60c83f8528e650bda7 100644 --- a/test/a64/traces/sim-suqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-suqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-2s-trace-a64.h b/test/a64/traces/sim-suqadd-2s-trace-a64.h index 55b597fdd162b8360885247c2a7c320b92c50802..92af42cd2c7b7c3c7d01fbfbbeffa3c227cd46dc 100644 --- a/test/a64/traces/sim-suqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-suqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-4h-trace-a64.h b/test/a64/traces/sim-suqadd-4h-trace-a64.h index 17fb16d455d89632f686ef8f997ae587614976a0..f0f0e942fdab3db4f2d1fd924672565fe337bb00 100644 --- a/test/a64/traces/sim-suqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-suqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-4s-trace-a64.h b/test/a64/traces/sim-suqadd-4s-trace-a64.h index bc7c15c4411a3a9f5c6e0c84da36f91a558d69e0..b46fbae1e3389409223eadb2274881ab882ed003 100644 --- a/test/a64/traces/sim-suqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-suqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-8b-trace-a64.h b/test/a64/traces/sim-suqadd-8b-trace-a64.h index d13f3779e9e0d1c6051935bf78ef49de8d599bd3..73ff41c9e42e9d5ee22240161c5f2514a6aaf2fc 100644 --- a/test/a64/traces/sim-suqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-suqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-8h-trace-a64.h b/test/a64/traces/sim-suqadd-8h-trace-a64.h index e5b79e63be773ce631034c302b032d3779355a7b..abaac22db6d2caafea2570bed2e02e8b570fcca3 100644 --- a/test/a64/traces/sim-suqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-suqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-b-trace-a64.h b/test/a64/traces/sim-suqadd-b-trace-a64.h index 5d210deb4d4fec386a79d67a5b42b035aa814d6b..dac9cefd373808544be8bda9e57630c4c83720cb 100644 --- a/test/a64/traces/sim-suqadd-b-trace-a64.h +++ b/test/a64/traces/sim-suqadd-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-d-trace-a64.h b/test/a64/traces/sim-suqadd-d-trace-a64.h index da4a185f34d137455ab68d566c35d30971d54ee2..7d3ff8cb1d750d09502a89e58780666de8cbcd86 100644 --- a/test/a64/traces/sim-suqadd-d-trace-a64.h +++ b/test/a64/traces/sim-suqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-h-trace-a64.h b/test/a64/traces/sim-suqadd-h-trace-a64.h index e387d457c7cf9cb06188d1e570023f89d1153941..47665a3a4233dabe0c39c1931fa16934651c3a52 100644 --- a/test/a64/traces/sim-suqadd-h-trace-a64.h +++ b/test/a64/traces/sim-suqadd-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-s-trace-a64.h b/test/a64/traces/sim-suqadd-s-trace-a64.h index c16828a4853ed912f79d34b0863f3795320fcb64..8748f22020155a6e2cf87754451bd3fee6f0f75a 100644 --- a/test/a64/traces/sim-suqadd-s-trace-a64.h +++ b/test/a64/traces/sim-suqadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-16b-trace-a64.h b/test/a64/traces/sim-trn1-16b-trace-a64.h index 62d59f748f51273820387961e0c5b209b2227842..a8319fc0923dee13dc9d924284f34b488b9d89f0 100644 --- a/test/a64/traces/sim-trn1-16b-trace-a64.h +++ b/test/a64/traces/sim-trn1-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-2d-trace-a64.h b/test/a64/traces/sim-trn1-2d-trace-a64.h index 67775a3704daedd84f2e753d16700b98b3fef9fd..3048390a6451f98ebf1f4d1e17af29216c52b794 100644 --- a/test/a64/traces/sim-trn1-2d-trace-a64.h +++ b/test/a64/traces/sim-trn1-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-2s-trace-a64.h b/test/a64/traces/sim-trn1-2s-trace-a64.h index 1f64a92fffbad4371094b69187bcd9bd229d5ec9..e001429093a02e40c07b2be1c9c93cdd4dc15e7b 100644 --- a/test/a64/traces/sim-trn1-2s-trace-a64.h +++ b/test/a64/traces/sim-trn1-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-4h-trace-a64.h b/test/a64/traces/sim-trn1-4h-trace-a64.h index 0811917427e8960ed1aa678f02a859a8f1963940..a9b742d1b824f513e99485f86fc88343abe1c4b1 100644 --- a/test/a64/traces/sim-trn1-4h-trace-a64.h +++ b/test/a64/traces/sim-trn1-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-4s-trace-a64.h b/test/a64/traces/sim-trn1-4s-trace-a64.h index a450bbb76da0c0b3ed0e2cebb8b8a140c80acf8c..b64ff81dee5b89e650d905592dc44fb5c6599bca 100644 --- a/test/a64/traces/sim-trn1-4s-trace-a64.h +++ b/test/a64/traces/sim-trn1-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-8b-trace-a64.h b/test/a64/traces/sim-trn1-8b-trace-a64.h index d7dfbcb88ab4878ff25a2cc401fa583af0fcf20a..816f2f6b8246d89a653d0788bb55ce333d483bb9 100644 --- a/test/a64/traces/sim-trn1-8b-trace-a64.h +++ b/test/a64/traces/sim-trn1-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-8h-trace-a64.h b/test/a64/traces/sim-trn1-8h-trace-a64.h index af184b358da9ab369bff3c7f119786785ba48f0d..c654a0c60dda1724093b9359b2efb042f526095f 100644 --- a/test/a64/traces/sim-trn1-8h-trace-a64.h +++ b/test/a64/traces/sim-trn1-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-16b-trace-a64.h b/test/a64/traces/sim-trn2-16b-trace-a64.h index 360f8db8e6dec7050d7d858ea0dfd87c50f6d349..e1a2989d40f914beb65bb5fc4d87b831777be95a 100644 --- a/test/a64/traces/sim-trn2-16b-trace-a64.h +++ b/test/a64/traces/sim-trn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-2d-trace-a64.h b/test/a64/traces/sim-trn2-2d-trace-a64.h index da6dcf7cb2c68d01b1431b3f89e4de083f7d45c1..926e40b308d4585254aac7efe390e1fc64bb41a0 100644 --- a/test/a64/traces/sim-trn2-2d-trace-a64.h +++ b/test/a64/traces/sim-trn2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-2s-trace-a64.h b/test/a64/traces/sim-trn2-2s-trace-a64.h index 9acc43d49a927103ec98f9d5ddf9a4730a09d12b..2a02b49826ab66e63c065424f08d772cf00d5b68 100644 --- a/test/a64/traces/sim-trn2-2s-trace-a64.h +++ b/test/a64/traces/sim-trn2-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-4h-trace-a64.h b/test/a64/traces/sim-trn2-4h-trace-a64.h index ba85634e2f089021481f3fe410ec3042f4eba7d9..a5edc3d0adf6591807eae71d73d706a985ae2b24 100644 --- a/test/a64/traces/sim-trn2-4h-trace-a64.h +++ b/test/a64/traces/sim-trn2-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-4s-trace-a64.h b/test/a64/traces/sim-trn2-4s-trace-a64.h index 0b800418508c138186bc499fecb3cf0900e37fd6..07acf7732e0f1a627910f6cc187ba32615c793a0 100644 --- a/test/a64/traces/sim-trn2-4s-trace-a64.h +++ b/test/a64/traces/sim-trn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-8b-trace-a64.h b/test/a64/traces/sim-trn2-8b-trace-a64.h index ffdebd27d10f9eee51d4279039a70576c4102ff5..7d21f0be29db552fcb0311738c2b58c2f81ac9e0 100644 --- a/test/a64/traces/sim-trn2-8b-trace-a64.h +++ b/test/a64/traces/sim-trn2-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-8h-trace-a64.h b/test/a64/traces/sim-trn2-8h-trace-a64.h index 413c2d6b9fe41f46ed525ccdfef429163beee2d0..4e07b6394745117f4d96735ee4ba4df26071e900 100644 --- a/test/a64/traces/sim-trn2-8h-trace-a64.h +++ b/test/a64/traces/sim-trn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-16b-trace-a64.h b/test/a64/traces/sim-uaba-16b-trace-a64.h index d43ebe11d666bf1ad1fd978f9dfa14b08091f355..46aeec3eb307b5551bb62eea1dedc4cfbc15ee87 100644 --- a/test/a64/traces/sim-uaba-16b-trace-a64.h +++ b/test/a64/traces/sim-uaba-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-2s-trace-a64.h b/test/a64/traces/sim-uaba-2s-trace-a64.h index 619dd0a1db7d2316acbc597ffa3a16bd58b6b39f..123f3e8a03b32df6b21917c1844c924ba69d4431 100644 --- a/test/a64/traces/sim-uaba-2s-trace-a64.h +++ b/test/a64/traces/sim-uaba-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-4h-trace-a64.h b/test/a64/traces/sim-uaba-4h-trace-a64.h index 3285989f8fbea42ecb9e0b2f4470c4c903ced8cb..70e2f136c90bf101c8cce3840f78684b6ba03b13 100644 --- a/test/a64/traces/sim-uaba-4h-trace-a64.h +++ b/test/a64/traces/sim-uaba-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-4s-trace-a64.h b/test/a64/traces/sim-uaba-4s-trace-a64.h index a5cccffcd97844a6469c5052fb31a4f76d92183a..4b4c9a37dc5579cc3fe1aaa2a3c8e9041ac5ff30 100644 --- a/test/a64/traces/sim-uaba-4s-trace-a64.h +++ b/test/a64/traces/sim-uaba-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-8b-trace-a64.h b/test/a64/traces/sim-uaba-8b-trace-a64.h index a0b7ab4434ad31d15d5d6ad288f34b281894a6be..d1c4a003cc3263a5e16f2302384f4762894677dd 100644 --- a/test/a64/traces/sim-uaba-8b-trace-a64.h +++ b/test/a64/traces/sim-uaba-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-8h-trace-a64.h b/test/a64/traces/sim-uaba-8h-trace-a64.h index 1328c394e8c147f97c461768106679fdfe8baea4..6340c49d3e3c13a5b2ebfb5867e85e68a10b2c6a 100644 --- a/test/a64/traces/sim-uaba-8h-trace-a64.h +++ b/test/a64/traces/sim-uaba-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal-2d-trace-a64.h b/test/a64/traces/sim-uabal-2d-trace-a64.h index c1cbec16e521aea58794eca35cafda536da43fea..903816b0a9d3be2501f494bc3537e8ab7c08f7e8 100644 --- a/test/a64/traces/sim-uabal-2d-trace-a64.h +++ b/test/a64/traces/sim-uabal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal-4s-trace-a64.h b/test/a64/traces/sim-uabal-4s-trace-a64.h index b6cd57be2c8f22e168fd857e3f6557aa68846a28..999b498d7dd744c22bd4cd7af71f96a1789f83fd 100644 --- a/test/a64/traces/sim-uabal-4s-trace-a64.h +++ b/test/a64/traces/sim-uabal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal-8h-trace-a64.h b/test/a64/traces/sim-uabal-8h-trace-a64.h index 582efaee3761bb61cac5540de54bfd344e18dd7e..e2072cc8121deeb908c48d5e928015b964681afa 100644 --- a/test/a64/traces/sim-uabal-8h-trace-a64.h +++ b/test/a64/traces/sim-uabal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal2-2d-trace-a64.h b/test/a64/traces/sim-uabal2-2d-trace-a64.h index 7931dd69edfd71ea233ec68d5bc1792a9f83c639..5522f2949e666e162ff39c23a3eaee2fa7036812 100644 --- a/test/a64/traces/sim-uabal2-2d-trace-a64.h +++ b/test/a64/traces/sim-uabal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal2-4s-trace-a64.h b/test/a64/traces/sim-uabal2-4s-trace-a64.h index c61cc17e955aba7086f8d906a808a40bd709c807..cc1669a4f33d342eb3a1023e2dce7817b5a823f4 100644 --- a/test/a64/traces/sim-uabal2-4s-trace-a64.h +++ b/test/a64/traces/sim-uabal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal2-8h-trace-a64.h b/test/a64/traces/sim-uabal2-8h-trace-a64.h index 0e60c7d1ff2c405f6a6371d64233d7c9381134e4..b1ab7cc1bf2ed199ddeb9d21470ab7a057e1ef35 100644 --- a/test/a64/traces/sim-uabal2-8h-trace-a64.h +++ b/test/a64/traces/sim-uabal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-16b-trace-a64.h b/test/a64/traces/sim-uabd-16b-trace-a64.h index 3126ed3ec33b8521ac6b3ba9d0308b5b6af14a3f..466b17eba5aa60858488f2ad045a118fe4f516f0 100644 --- a/test/a64/traces/sim-uabd-16b-trace-a64.h +++ b/test/a64/traces/sim-uabd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-2s-trace-a64.h b/test/a64/traces/sim-uabd-2s-trace-a64.h index 6077f04f9970f3bda10cd642564d5a9b642cd538..e57b5ca1b753d6ea434ddcaa6aa3c90ae95c496f 100644 --- a/test/a64/traces/sim-uabd-2s-trace-a64.h +++ b/test/a64/traces/sim-uabd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-4h-trace-a64.h b/test/a64/traces/sim-uabd-4h-trace-a64.h index 563ef8ce4c752ec138907ee4c335a4c4ad6e9628..80cdfd9620d059ea5c38f6c7cea8a472271a9ea4 100644 --- a/test/a64/traces/sim-uabd-4h-trace-a64.h +++ b/test/a64/traces/sim-uabd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-4s-trace-a64.h b/test/a64/traces/sim-uabd-4s-trace-a64.h index 787cd86944c1415c7ebde379d0ddb524bce2a638..8714071417a98b473cd852718f14a3b3dbd7f9c4 100644 --- a/test/a64/traces/sim-uabd-4s-trace-a64.h +++ b/test/a64/traces/sim-uabd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-8b-trace-a64.h b/test/a64/traces/sim-uabd-8b-trace-a64.h index d5764abfabc4178e6fb1c7378428c936c9d564d2..e00f91dd7c7bd014305e1ddef9c4fd581f8402b5 100644 --- a/test/a64/traces/sim-uabd-8b-trace-a64.h +++ b/test/a64/traces/sim-uabd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-8h-trace-a64.h b/test/a64/traces/sim-uabd-8h-trace-a64.h index 490e7b5ee6d1145be8574e6d23d01ea386277d9e..6d87b724bc916e01f7a375f043f14dfc9b7bd8dd 100644 --- a/test/a64/traces/sim-uabd-8h-trace-a64.h +++ b/test/a64/traces/sim-uabd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl-2d-trace-a64.h b/test/a64/traces/sim-uabdl-2d-trace-a64.h index 0d739d7b2b3d237c7136b06119afe8478ca974e9..a1401628cdc499232cc916211c3ac6bdf2a840ba 100644 --- a/test/a64/traces/sim-uabdl-2d-trace-a64.h +++ b/test/a64/traces/sim-uabdl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl-4s-trace-a64.h b/test/a64/traces/sim-uabdl-4s-trace-a64.h index 8c503911c62491a3fc1c3845419121e20e052d0b..040f70cecf410f44c6ba58903244bfca87c69654 100644 --- a/test/a64/traces/sim-uabdl-4s-trace-a64.h +++ b/test/a64/traces/sim-uabdl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl-8h-trace-a64.h b/test/a64/traces/sim-uabdl-8h-trace-a64.h index 6340ec5bb61183e53efc83d750a084788071564a..e37e2ee9f233919350158549447d96befd1e80f9 100644 --- a/test/a64/traces/sim-uabdl-8h-trace-a64.h +++ b/test/a64/traces/sim-uabdl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl2-2d-trace-a64.h b/test/a64/traces/sim-uabdl2-2d-trace-a64.h index 6e643d2a44094bdf5ae5d31aaed7b8712d119c17..499832f5f6a8777a72d6b17d117669b8d69e36b4 100644 --- a/test/a64/traces/sim-uabdl2-2d-trace-a64.h +++ b/test/a64/traces/sim-uabdl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl2-4s-trace-a64.h b/test/a64/traces/sim-uabdl2-4s-trace-a64.h index 743462c48469fe644350f280decc618bbb39212d..c3563e32f089cccdfc7cc5c880c68c05b41869f4 100644 --- a/test/a64/traces/sim-uabdl2-4s-trace-a64.h +++ b/test/a64/traces/sim-uabdl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl2-8h-trace-a64.h b/test/a64/traces/sim-uabdl2-8h-trace-a64.h index 87ee09760ee73a39777c5eda06a5777f34fae9c1..bca8f908e33288970f51d0c9412e73ba81cb9f09 100644 --- a/test/a64/traces/sim-uabdl2-8h-trace-a64.h +++ b/test/a64/traces/sim-uabdl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-1d-trace-a64.h b/test/a64/traces/sim-uadalp-1d-trace-a64.h index 566c06064f2df3a99733031e4c30b3b96f067148..1d34705ab84832dbb3541b74ebb98738ebdf0279 100644 --- a/test/a64/traces/sim-uadalp-1d-trace-a64.h +++ b/test/a64/traces/sim-uadalp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-2d-trace-a64.h b/test/a64/traces/sim-uadalp-2d-trace-a64.h index 99e1b752aae14835fa886a1ffde3efd17e52ca69..b5caa1c888b4e7d7b37ff37f9b8121800d6b868e 100644 --- a/test/a64/traces/sim-uadalp-2d-trace-a64.h +++ b/test/a64/traces/sim-uadalp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-2s-trace-a64.h b/test/a64/traces/sim-uadalp-2s-trace-a64.h index 49ebd34c56a16cd4c96122aff7aa7075ce707422..b920afe18d8e2ea2bd7cb039115aabc023848148 100644 --- a/test/a64/traces/sim-uadalp-2s-trace-a64.h +++ b/test/a64/traces/sim-uadalp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-4h-trace-a64.h b/test/a64/traces/sim-uadalp-4h-trace-a64.h index a884f95ae755258431227539785e7faeb59cc874..402121b59fc4823dc1c9af9c383521fd5767b4fc 100644 --- a/test/a64/traces/sim-uadalp-4h-trace-a64.h +++ b/test/a64/traces/sim-uadalp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-4s-trace-a64.h b/test/a64/traces/sim-uadalp-4s-trace-a64.h index f8a69f5e8fc5e93955d4a1dbb1a122d9367faaec..5197ca251f92720d9c294faac4c04dff3d4abb6f 100644 --- a/test/a64/traces/sim-uadalp-4s-trace-a64.h +++ b/test/a64/traces/sim-uadalp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-8h-trace-a64.h b/test/a64/traces/sim-uadalp-8h-trace-a64.h index ac717984f4a1afeec47c0f9227ae48a60b5ddbf8..e7eb5777e39079fe4168637f8e8578c58311c6f3 100644 --- a/test/a64/traces/sim-uadalp-8h-trace-a64.h +++ b/test/a64/traces/sim-uadalp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl-2d-trace-a64.h b/test/a64/traces/sim-uaddl-2d-trace-a64.h index 86dd70734f9d87b290cbc4da39866a870a40a3e5..a876fd3415e67727bd9aa908ed4c1982626e2157 100644 --- a/test/a64/traces/sim-uaddl-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl-4s-trace-a64.h b/test/a64/traces/sim-uaddl-4s-trace-a64.h index 8d72c4968bb1087cafc954dda3207796b8863d4a..6ccc4322519c0a2beb9e362cf2728161a42fae71 100644 --- a/test/a64/traces/sim-uaddl-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl-8h-trace-a64.h b/test/a64/traces/sim-uaddl-8h-trace-a64.h index 6c903e6066ce7ff199f94baa41e77c946741fbd2..c88b787521a87d06190fe8d01b3c5a578a65a5a2 100644 --- a/test/a64/traces/sim-uaddl-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl2-2d-trace-a64.h b/test/a64/traces/sim-uaddl2-2d-trace-a64.h index aff75bc267d3e0b2b688b4afee5b5d04ec50ed2d..9f6e5f77743d02faca37dca3aa9f6f1b009efaf9 100644 --- a/test/a64/traces/sim-uaddl2-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl2-4s-trace-a64.h b/test/a64/traces/sim-uaddl2-4s-trace-a64.h index 19498ba0a7c1d334ca2c7698ad68d841e3a17705..0ed7dda168cfd8af020ffafa179838a2081cf53b 100644 --- a/test/a64/traces/sim-uaddl2-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl2-8h-trace-a64.h b/test/a64/traces/sim-uaddl2-8h-trace-a64.h index 7be45c92a98a1020b9488efddd7bbe8105d77280..d8f1c3f7b1f60e768dee343e7e19a86c5ab74a54 100644 --- a/test/a64/traces/sim-uaddl2-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-1d-trace-a64.h b/test/a64/traces/sim-uaddlp-1d-trace-a64.h index a36c3c1095be93a4c03bdbfd0569866f45ecb0eb..eb8bf19b453d2c19f21bc3d8d883155836af6fce 100644 --- a/test/a64/traces/sim-uaddlp-1d-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-2d-trace-a64.h b/test/a64/traces/sim-uaddlp-2d-trace-a64.h index d6a8ee34e4fb122808b92af0bc0f8a758a51abcf..dc3dae3bfb51a4efa36f1c1cc3b856b3e347c08d 100644 --- a/test/a64/traces/sim-uaddlp-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-2s-trace-a64.h b/test/a64/traces/sim-uaddlp-2s-trace-a64.h index 29ad0fb780e329d0a68f47332c064f607a2e6c41..82cc75c9ac0e4d43e932c4a42e0233fdbb36b67a 100644 --- a/test/a64/traces/sim-uaddlp-2s-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-4h-trace-a64.h b/test/a64/traces/sim-uaddlp-4h-trace-a64.h index 9f24c7fdc2e851bcbcdaf85b89e9375ce9619fcf..035711b8da1e8e4d6463685ebc15d7652278dc0b 100644 --- a/test/a64/traces/sim-uaddlp-4h-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-4s-trace-a64.h b/test/a64/traces/sim-uaddlp-4s-trace-a64.h index 6fbbe9673754e31218cab44cf51b4cdd00eb398d..5d15ef054332032c7be32eb68ff1fd2665fe625a 100644 --- a/test/a64/traces/sim-uaddlp-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-8h-trace-a64.h b/test/a64/traces/sim-uaddlp-8h-trace-a64.h index 78c0f17b0e42ad257062a2cbd952a66f1b86d547..14661c90563c9be623bbe041b9f98baba29ed74e 100644 --- a/test/a64/traces/sim-uaddlp-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h b/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h index 3368efe7b9f662b55908f5e651436c8ce3f09ff8..7479d828f698e4cc561e30b57d5f23749987fe4a 100644 --- a/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h b/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h index f4ab0d39a0a0c696d1ed9c57cef66e546e8dc49a..d978605adf505626b676d4ed0c5a4ee93726481a 100644 --- a/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h b/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h index 03947d05045df75cdc92a849b54b404528291621..c850bd336c15a2532dedb869bcb09574dc2925fe 100644 --- a/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h b/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h index cf5ae1c4e8ae9f14404cedc743e3655acbfce876..a16c1e40f95191a1e15c491f452ae220753ff971 100644 --- a/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h b/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h index 9c232f68501b483f46c012c66b451f4ec748fa61..c96cc8d3c1eba1bb771a653888379ece945204c2 100644 --- a/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw-2d-trace-a64.h b/test/a64/traces/sim-uaddw-2d-trace-a64.h index 289fb4be7ebfd5a9816438d05273ee1eb9d9816d..3cc7a5d2df411b76b7c4d37adc9a52cab4fab1fc 100644 --- a/test/a64/traces/sim-uaddw-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw-4s-trace-a64.h b/test/a64/traces/sim-uaddw-4s-trace-a64.h index ea735317cdee62a34c38755068fc5a936a0d098e..383b2105aa70b7a693f56251720b268a6cac8ae7 100644 --- a/test/a64/traces/sim-uaddw-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw-8h-trace-a64.h b/test/a64/traces/sim-uaddw-8h-trace-a64.h index d714372f6e8790f9a93e8d008fd29e952f48d1a8..6bc732483b324a4091bb1fd9a050b219409dfeb9 100644 --- a/test/a64/traces/sim-uaddw-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw2-2d-trace-a64.h b/test/a64/traces/sim-uaddw2-2d-trace-a64.h index 547466227152fe153f7abea0c2da7c525856e59d..c4f69cc6ecb6e3d8ce3e24686feea91604cfaf03 100644 --- a/test/a64/traces/sim-uaddw2-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw2-4s-trace-a64.h b/test/a64/traces/sim-uaddw2-4s-trace-a64.h index c67b0885487dff105e54b14cead4e8f03144d91d..150aced46dc3305b163bb5ac9c9bd2cadb8fe178 100644 --- a/test/a64/traces/sim-uaddw2-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw2-8h-trace-a64.h b/test/a64/traces/sim-uaddw2-8h-trace-a64.h index b5fcf2a01769b8e2ab18450483e5cfc71131a185..2597d2c1434a9e4920fee872e640f85616fa61f6 100644 --- a/test/a64/traces/sim-uaddw2-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h index 3118302d5081ca61819d5646b9c6f8ed6525e429..48fba8b597b8ab5aa971f84cacd85499f767d1c6 100644 --- a/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h index f028b9da403bd9dd34b5add3a60050cfe33ccf81..0aea058fe036ce10022345bcc533f5d9fa6e8fed 100644 --- a/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h index 9474e13fe7719c72781a6b0aabad1408b92fc56d..dbaee9ebfdcd9a8741206d4fb8ea7553fd410e71 100644 --- a/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h index c983b8f462c601c2dce9643f414edcd30d619f6b..8becec41b6e3a2d5a79650298bf566aa21cc5358 100644 --- a/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h index a292e08ff5c4747f582521398e912b915ad92c27..10ba3f1b7a977cb5200221b7045e68ca5e43072d 100644 --- a/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-16b-trace-a64.h b/test/a64/traces/sim-uhadd-16b-trace-a64.h index effe885357a0df8c972c31240723cede6cd441d8..48d18f502662367551ab61d4b35ea8fd9aff76e0 100644 --- a/test/a64/traces/sim-uhadd-16b-trace-a64.h +++ b/test/a64/traces/sim-uhadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-2s-trace-a64.h b/test/a64/traces/sim-uhadd-2s-trace-a64.h index 7b7c143e3171fa5e9025bc917ffe52c7b754f98e..2d97778370cd202face316968edc49a1274edc50 100644 --- a/test/a64/traces/sim-uhadd-2s-trace-a64.h +++ b/test/a64/traces/sim-uhadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-4h-trace-a64.h b/test/a64/traces/sim-uhadd-4h-trace-a64.h index a794db258450ac2f8e560be1d6ba3f05e2878a1e..de352d6b36fdc8c295776b6ad1db6d875dae457a 100644 --- a/test/a64/traces/sim-uhadd-4h-trace-a64.h +++ b/test/a64/traces/sim-uhadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-4s-trace-a64.h b/test/a64/traces/sim-uhadd-4s-trace-a64.h index f29f2742afee6da1832bfca29711caf3c22bb7de..74c6511832e723c96c37fa0653feb4fed5eaad92 100644 --- a/test/a64/traces/sim-uhadd-4s-trace-a64.h +++ b/test/a64/traces/sim-uhadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-8b-trace-a64.h b/test/a64/traces/sim-uhadd-8b-trace-a64.h index 297f4ddc43cd2dbcc19698f0479dbdbef598259b..21660c1b6a210af61386cbc50c8851833f542eb0 100644 --- a/test/a64/traces/sim-uhadd-8b-trace-a64.h +++ b/test/a64/traces/sim-uhadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-8h-trace-a64.h b/test/a64/traces/sim-uhadd-8h-trace-a64.h index d453d97e6acd5886e56c1f44f30971f09578ee1f..11b5957a4e76ccd8886c128a37dfa255d834391f 100644 --- a/test/a64/traces/sim-uhadd-8h-trace-a64.h +++ b/test/a64/traces/sim-uhadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-16b-trace-a64.h b/test/a64/traces/sim-uhsub-16b-trace-a64.h index 4bc423b311aef5b1ff487ea6fd168a459de24f18..ea7dfbb7fe018c0b2e6219180958ee3ccc2f9e8f 100644 --- a/test/a64/traces/sim-uhsub-16b-trace-a64.h +++ b/test/a64/traces/sim-uhsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-2s-trace-a64.h b/test/a64/traces/sim-uhsub-2s-trace-a64.h index 84f559047d4db86c7dc39da8facc116d1a09257a..27d82432cdb2d61ac553d103692b9575f04d6b9a 100644 --- a/test/a64/traces/sim-uhsub-2s-trace-a64.h +++ b/test/a64/traces/sim-uhsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-4h-trace-a64.h b/test/a64/traces/sim-uhsub-4h-trace-a64.h index 0b2b5fbde5ae28b3c68ba8dbc552bf2789fee5d1..f251f68d2150ecdf637b7fc883ee85916764d86e 100644 --- a/test/a64/traces/sim-uhsub-4h-trace-a64.h +++ b/test/a64/traces/sim-uhsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-4s-trace-a64.h b/test/a64/traces/sim-uhsub-4s-trace-a64.h index a1614eebb45c9b48ed277ac736d074c3cd565a0c..c232ef0ce3230367d7c588688329f2b4dffcd5aa 100644 --- a/test/a64/traces/sim-uhsub-4s-trace-a64.h +++ b/test/a64/traces/sim-uhsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-8b-trace-a64.h b/test/a64/traces/sim-uhsub-8b-trace-a64.h index de5251c266afbd22d5e33dda7468443f32683951..b3677f7bbe0ebeadc18032cc7e725152172426c8 100644 --- a/test/a64/traces/sim-uhsub-8b-trace-a64.h +++ b/test/a64/traces/sim-uhsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-8h-trace-a64.h b/test/a64/traces/sim-uhsub-8h-trace-a64.h index c37bb183c9606462f1ac435b84de342be4faefeb..228a432dcaabc4c09fa5c10d18d9811e8e2cbd51 100644 --- a/test/a64/traces/sim-uhsub-8h-trace-a64.h +++ b/test/a64/traces/sim-uhsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-16b-trace-a64.h b/test/a64/traces/sim-umax-16b-trace-a64.h index 8de9811f7c5ad0b0cf9c692184e40e7eebc4d322..a5d8d9067760adc7681444c8ee7e5d57419bef11 100644 --- a/test/a64/traces/sim-umax-16b-trace-a64.h +++ b/test/a64/traces/sim-umax-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-2s-trace-a64.h b/test/a64/traces/sim-umax-2s-trace-a64.h index 685d58c17c895f40ab737115ce17a7896bbed185..918c37de2587822b58f7102d8d8942c4f1ef0970 100644 --- a/test/a64/traces/sim-umax-2s-trace-a64.h +++ b/test/a64/traces/sim-umax-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-4h-trace-a64.h b/test/a64/traces/sim-umax-4h-trace-a64.h index 9072a521186ea4856d4cab3a93a287b470968f05..1910e920aa79edd8d009c4f0aff783d243a6db07 100644 --- a/test/a64/traces/sim-umax-4h-trace-a64.h +++ b/test/a64/traces/sim-umax-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-4s-trace-a64.h b/test/a64/traces/sim-umax-4s-trace-a64.h index cf4283ccd56ff6dc4b96363438ff078e031e6130..e9c11afa1302870a310ca4cdcd4fd6c25cf142fd 100644 --- a/test/a64/traces/sim-umax-4s-trace-a64.h +++ b/test/a64/traces/sim-umax-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-8b-trace-a64.h b/test/a64/traces/sim-umax-8b-trace-a64.h index 72d6fc0ef51ee9ded93f55ad5f59524bf0fe86bd..35289de15d9d4c5934b36a5d63ddce92d85bb649 100644 --- a/test/a64/traces/sim-umax-8b-trace-a64.h +++ b/test/a64/traces/sim-umax-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-8h-trace-a64.h b/test/a64/traces/sim-umax-8h-trace-a64.h index 65083e5b2ceedab33b4b5eec7b9cc95d5cbb7f58..a6561df45e72f26f9bd707379346afbab6164b91 100644 --- a/test/a64/traces/sim-umax-8h-trace-a64.h +++ b/test/a64/traces/sim-umax-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-16b-trace-a64.h b/test/a64/traces/sim-umaxp-16b-trace-a64.h index 1631aef74cb06767978ebc2ea08768111e3cbabd..6347846ed6e1db956b0d4a70b67ff9965d04eccb 100644 --- a/test/a64/traces/sim-umaxp-16b-trace-a64.h +++ b/test/a64/traces/sim-umaxp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-2s-trace-a64.h b/test/a64/traces/sim-umaxp-2s-trace-a64.h index 54567e5669899a3cb4fecdcf4ec46563808d0911..e024c06b4dc13a50c0feec2c9beb5890d7007eea 100644 --- a/test/a64/traces/sim-umaxp-2s-trace-a64.h +++ b/test/a64/traces/sim-umaxp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-4h-trace-a64.h b/test/a64/traces/sim-umaxp-4h-trace-a64.h index 9977dfa8e81471c5d34d4358cf38d4293ebf1985..6b6e3b98e5976206644752362283a5fb109a5a42 100644 --- a/test/a64/traces/sim-umaxp-4h-trace-a64.h +++ b/test/a64/traces/sim-umaxp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-4s-trace-a64.h b/test/a64/traces/sim-umaxp-4s-trace-a64.h index 23cb091cabcdd6ba0627ef8c75d9b5fb92dad131..b5a641336b462d7fe01dfa0785e3659dc7c6cdf2 100644 --- a/test/a64/traces/sim-umaxp-4s-trace-a64.h +++ b/test/a64/traces/sim-umaxp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-8b-trace-a64.h b/test/a64/traces/sim-umaxp-8b-trace-a64.h index 1c2524b7407ffa56b888abd1b9882ef414e49e7e..bc2b23d7a2cca27770f254b0c7c86e08a6a329c2 100644 --- a/test/a64/traces/sim-umaxp-8b-trace-a64.h +++ b/test/a64/traces/sim-umaxp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-8h-trace-a64.h b/test/a64/traces/sim-umaxp-8h-trace-a64.h index b046a112fef7d04b0777d715ed0f29604b890fcf..8dc11af6c6c25379583336b202da5c9976689c72 100644 --- a/test/a64/traces/sim-umaxp-8h-trace-a64.h +++ b/test/a64/traces/sim-umaxp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-b-16b-trace-a64.h b/test/a64/traces/sim-umaxv-b-16b-trace-a64.h index bd1f2dd79a0fb940a49850a98d9549c983bc87c0..83c65ca182da6d96b700154cb304562f3cd43ed5 100644 --- a/test/a64/traces/sim-umaxv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-umaxv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-b-8b-trace-a64.h b/test/a64/traces/sim-umaxv-b-8b-trace-a64.h index e34802bed36df0933c977f6f8c947ad1d12112b7..d4ec983aafa0f112d48f3c0e0fca3110ac823a8e 100644 --- a/test/a64/traces/sim-umaxv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-umaxv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-h-4h-trace-a64.h b/test/a64/traces/sim-umaxv-h-4h-trace-a64.h index 4e750c3630b8a680731e471f0d7044565f0ab1be..bdebe161c97ebef5392d496ee022be8b16cf205b 100644 --- a/test/a64/traces/sim-umaxv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-umaxv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-h-8h-trace-a64.h b/test/a64/traces/sim-umaxv-h-8h-trace-a64.h index a471cd4540d492eabd9db96d5406c60406ac8361..a923a186cb13eff977bcb5cbd19083134399aac8 100644 --- a/test/a64/traces/sim-umaxv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-umaxv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-s-4s-trace-a64.h b/test/a64/traces/sim-umaxv-s-4s-trace-a64.h index e896ec10a314db24004c553be1a03dc485f4328d..5430b1dbc7a722073e71bbea4702dc178e8b699c 100644 --- a/test/a64/traces/sim-umaxv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-umaxv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-16b-trace-a64.h b/test/a64/traces/sim-umin-16b-trace-a64.h index 550d57bf6e6ffa00aae2d4aaf1d55818020fe6b6..f9063c015d8860e763dccf3e97e63a3e6fc5f1fb 100644 --- a/test/a64/traces/sim-umin-16b-trace-a64.h +++ b/test/a64/traces/sim-umin-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-2s-trace-a64.h b/test/a64/traces/sim-umin-2s-trace-a64.h index ee32a1e334b9971103f1346ffcef4c9dd0f91d43..1c6575b0ba34bc9b609961a587e631a718582cca 100644 --- a/test/a64/traces/sim-umin-2s-trace-a64.h +++ b/test/a64/traces/sim-umin-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-4h-trace-a64.h b/test/a64/traces/sim-umin-4h-trace-a64.h index 151773853379d88318dac197a5708d54c980c036..033150f02a1e486e6f2eaa759408951034b512f6 100644 --- a/test/a64/traces/sim-umin-4h-trace-a64.h +++ b/test/a64/traces/sim-umin-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-4s-trace-a64.h b/test/a64/traces/sim-umin-4s-trace-a64.h index c7f7c81c8c5cba6473aea924962c51db644c2701..e83955d712e3b2bd81b19f560a78bb7c7a377793 100644 --- a/test/a64/traces/sim-umin-4s-trace-a64.h +++ b/test/a64/traces/sim-umin-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-8b-trace-a64.h b/test/a64/traces/sim-umin-8b-trace-a64.h index 77a02895392578c1c072ddfc8bcfaaed28784cc1..5e0eca8a6cc92a22de19273c223d34d1635443ba 100644 --- a/test/a64/traces/sim-umin-8b-trace-a64.h +++ b/test/a64/traces/sim-umin-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-8h-trace-a64.h b/test/a64/traces/sim-umin-8h-trace-a64.h index 0739a6ed56265af42d3472bd4a23875b729b7ae3..1d1d8dcb4526e4a417b6d6f0cfb2caebec64feef 100644 --- a/test/a64/traces/sim-umin-8h-trace-a64.h +++ b/test/a64/traces/sim-umin-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-16b-trace-a64.h b/test/a64/traces/sim-uminp-16b-trace-a64.h index 681f18d96457fa0c73d0f0b51c573a048903bac7..d02f5df90967e8b4e9d6c248beba632c9ed3e05d 100644 --- a/test/a64/traces/sim-uminp-16b-trace-a64.h +++ b/test/a64/traces/sim-uminp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-2s-trace-a64.h b/test/a64/traces/sim-uminp-2s-trace-a64.h index 8183b0f429ea65b7a1f93f11474d8f928aa4f347..18e0bfcbb77b75676e632fa04591dcc5738aa2ed 100644 --- a/test/a64/traces/sim-uminp-2s-trace-a64.h +++ b/test/a64/traces/sim-uminp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-4h-trace-a64.h b/test/a64/traces/sim-uminp-4h-trace-a64.h index 6fa9c5fab22d4dcf7374abc2051d18947859d49c..57721a28f67214b1fd95ec503ad4b974e61f55fb 100644 --- a/test/a64/traces/sim-uminp-4h-trace-a64.h +++ b/test/a64/traces/sim-uminp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-4s-trace-a64.h b/test/a64/traces/sim-uminp-4s-trace-a64.h index 7e477c831599ef80d9ff2aecfa52a89dffd60d26..4c4dfb13b3d99286ced97666741376eb82864b9f 100644 --- a/test/a64/traces/sim-uminp-4s-trace-a64.h +++ b/test/a64/traces/sim-uminp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-8b-trace-a64.h b/test/a64/traces/sim-uminp-8b-trace-a64.h index ca93e638730049e4bc422923b3814d389836d5e1..403dc45b42c28caf7779f1385474dad38924e8e7 100644 --- a/test/a64/traces/sim-uminp-8b-trace-a64.h +++ b/test/a64/traces/sim-uminp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-8h-trace-a64.h b/test/a64/traces/sim-uminp-8h-trace-a64.h index 999c45fac46c5ca4d09bbe4558554b5ce509a42b..516a0527a8a40f8b9d8e15f87592fdb33d40d0f3 100644 --- a/test/a64/traces/sim-uminp-8h-trace-a64.h +++ b/test/a64/traces/sim-uminp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-b-16b-trace-a64.h b/test/a64/traces/sim-uminv-b-16b-trace-a64.h index a47cf9890295af3b8475d1ff61407721ff94311a..3e0df5f2a6692a19e937e602d606720031066e7b 100644 --- a/test/a64/traces/sim-uminv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-uminv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-b-8b-trace-a64.h b/test/a64/traces/sim-uminv-b-8b-trace-a64.h index b44568f41eec7d3721fcea1d15a0c5fe866cd036..ab51f75a76dbc0382183a4cdb1fb20f1d22c488e 100644 --- a/test/a64/traces/sim-uminv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-uminv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-h-4h-trace-a64.h b/test/a64/traces/sim-uminv-h-4h-trace-a64.h index 462361ab8b91606b277d31b32e13742cb006fa29..b8894beacba023f2ae48235cd01aa34b5182d12d 100644 --- a/test/a64/traces/sim-uminv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-uminv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-h-8h-trace-a64.h b/test/a64/traces/sim-uminv-h-8h-trace-a64.h index 8dc205d590aba6a7076d6bbf574392fb9f237105..bc161d75df0508f230ed3e6084b24283a4739a8c 100644 --- a/test/a64/traces/sim-uminv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-uminv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-s-4s-trace-a64.h b/test/a64/traces/sim-uminv-s-4s-trace-a64.h index 3d9f9f35be85e03fb80a7dbe2b7c07f636786063..fbce156219825712dcd4b8fa667ef2628b1844a2 100644 --- a/test/a64/traces/sim-uminv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-uminv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h b/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h index 827ac89dfa547ca1284f160c3312ceb467552112..34eb249217c175da5022e7b18ea7ac6cc095cc4d 100644 --- a/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-2d-trace-a64.h b/test/a64/traces/sim-umlal-2d-trace-a64.h index 2382f4c8c09ed96fade87d557e4764dfdf9d56e4..a405b02e815f354dddbe67a8f2ed8426548e7430 100644 --- a/test/a64/traces/sim-umlal-2d-trace-a64.h +++ b/test/a64/traces/sim-umlal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h b/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h index 34f7155b341b1e63674f45202d14012547bd1d1c..6dbbad63160cf548a9adea1a9b3884714572887d 100644 --- a/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-4s-trace-a64.h b/test/a64/traces/sim-umlal-4s-trace-a64.h index cc54ebfeaabe96c9e3a06caa1f111306a5174cd2..9cd9be507aff4444977c2c9c41d1ec16faad33ae 100644 --- a/test/a64/traces/sim-umlal-4s-trace-a64.h +++ b/test/a64/traces/sim-umlal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-8h-trace-a64.h b/test/a64/traces/sim-umlal-8h-trace-a64.h index a27b8bdcb16ed5d7f29a6d2e8101f02c554a86e1..c7cb95aa4a47f0b7862aeb5579868d87f852c4d6 100644 --- a/test/a64/traces/sim-umlal-8h-trace-a64.h +++ b/test/a64/traces/sim-umlal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h index b40f8b2edbd7c51fc48f4c0a42a957d958a388ed..fa6bbda6ba536d4c9b122bef5b4ad0d0cb2c692f 100644 --- a/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-2d-trace-a64.h b/test/a64/traces/sim-umlal2-2d-trace-a64.h index 62beca666f0def0baf4a3a37979e1320951f20ce..9efe3cc3eae4a5ed9d80b273ec0538c4e1fb512f 100644 --- a/test/a64/traces/sim-umlal2-2d-trace-a64.h +++ b/test/a64/traces/sim-umlal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h index dda4cd1bf71b4e07a1819256a952844ee90b06f2..67a236d011b64a33f3dbbc3a927714383f53e2ad 100644 --- a/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-4s-trace-a64.h b/test/a64/traces/sim-umlal2-4s-trace-a64.h index ee5a57bf88add5ad64dc53e7d479dabdb92133d0..c0b355c7ebeac4267a467cc384d2a82e2354f759 100644 --- a/test/a64/traces/sim-umlal2-4s-trace-a64.h +++ b/test/a64/traces/sim-umlal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-8h-trace-a64.h b/test/a64/traces/sim-umlal2-8h-trace-a64.h index 8217f347a730a592cdcd9b05a634b9adccaedcf8..b9984d3a469257a3d8039330a27167ff5842fe82 100644 --- a/test/a64/traces/sim-umlal2-8h-trace-a64.h +++ b/test/a64/traces/sim-umlal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h b/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h index bd517c71b88219f323e293fb5c67d754e53fea75..687a6a13d6f1ff951a0f9988b0a92ae06f9efadc 100644 --- a/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-2d-trace-a64.h b/test/a64/traces/sim-umlsl-2d-trace-a64.h index 80fc9f554b91f92b0daf5c4967b3e33806e927c8..c694f561729e71a2d5b39d27d4b4c95f817ebcb8 100644 --- a/test/a64/traces/sim-umlsl-2d-trace-a64.h +++ b/test/a64/traces/sim-umlsl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h b/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h index f02e187bef8663ad620803fe467fd095c5dea6b1..6d5c9015c993110a5970e4dae6f09e617b1091fc 100644 --- a/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-4s-trace-a64.h b/test/a64/traces/sim-umlsl-4s-trace-a64.h index 0f02dc642bc50b15d6d31ad349f17010689b5e12..f234833c807151c2ef9c2ac0fa2060a92e9a2510 100644 --- a/test/a64/traces/sim-umlsl-4s-trace-a64.h +++ b/test/a64/traces/sim-umlsl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-8h-trace-a64.h b/test/a64/traces/sim-umlsl-8h-trace-a64.h index cf6560c0aaf975268f0fdbdbf96980c17d3441e4..69404b4d7985c97f35d2306b939af296bb7afb76 100644 --- a/test/a64/traces/sim-umlsl-8h-trace-a64.h +++ b/test/a64/traces/sim-umlsl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h index 221cd3e45d7781c486bb5301fbc84c9377c0f3c2..c25cbf212ce238a4c75ae10a710723c5cbb506da 100644 --- a/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-2d-trace-a64.h b/test/a64/traces/sim-umlsl2-2d-trace-a64.h index 73ecee00521dc23771ff226cc4df49bf984a9f48..ff3c49735d320eef45f0971ebc659a5135e25a82 100644 --- a/test/a64/traces/sim-umlsl2-2d-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h index 91eaafd04b40ab3755141551b59322108f6ac2ac..912631e68ba86b9c73781526819603fcd9e7b344 100644 --- a/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-4s-trace-a64.h b/test/a64/traces/sim-umlsl2-4s-trace-a64.h index 75ec47c7ba08441983a20e647699311423bfc288..3a26852f0f8b6f07101806c55385f59d44bda323 100644 --- a/test/a64/traces/sim-umlsl2-4s-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-8h-trace-a64.h b/test/a64/traces/sim-umlsl2-8h-trace-a64.h index c2f808e6e5a790e491971a945330bf3a0661ef39..7b94b46d9d918381235c0239ca1f6abffc998a3c 100644 --- a/test/a64/traces/sim-umlsl2-8h-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h b/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h index 131d70f0ddce104e6ad70862a404cefdbec68ab6..3db865bc662e1994592ab7cfc07354fb8e18debb 100644 --- a/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-2d-trace-a64.h b/test/a64/traces/sim-umull-2d-trace-a64.h index 1ff8824122881ce0c3c225a28ffc4ffe71d7166c..3bae809b94ffd502abc8ffa7da04806b86956542 100644 --- a/test/a64/traces/sim-umull-2d-trace-a64.h +++ b/test/a64/traces/sim-umull-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h b/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h index eb29becd286334d147e54a28e905507705e04fff..a9038864416420e6d5f28837e6faafe7e771e4e6 100644 --- a/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-4s-trace-a64.h b/test/a64/traces/sim-umull-4s-trace-a64.h index 56edbef46b1c23ad80e605dd03e3742e071a8d6b..0fc612774d3f42126331bb53ed5b4472537347f8 100644 --- a/test/a64/traces/sim-umull-4s-trace-a64.h +++ b/test/a64/traces/sim-umull-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-8h-trace-a64.h b/test/a64/traces/sim-umull-8h-trace-a64.h index c563d2928253a183e06649a033853bc6478848ae..3caf021d1aeffabd8f5c2248b70c80517bbc31c0 100644 --- a/test/a64/traces/sim-umull-8h-trace-a64.h +++ b/test/a64/traces/sim-umull-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h index c687473131a54a07aca687ab8740160bb650d673..c9eb0688116634dd99ab68ad5f81b4d002f14aa3 100644 --- a/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-2d-trace-a64.h b/test/a64/traces/sim-umull2-2d-trace-a64.h index 15581214bb539f2347d6738a4da1b8428639c238..a3c70fadd726bff7ccc07177bb2f643bafbb3355 100644 --- a/test/a64/traces/sim-umull2-2d-trace-a64.h +++ b/test/a64/traces/sim-umull2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h index 473b881c20fc1f563606677045994acc9eb38145..df908429f7db98d64622dfbcd07075a3b9286081 100644 --- a/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-4s-trace-a64.h b/test/a64/traces/sim-umull2-4s-trace-a64.h index 7d9c76be0ba248c5e44d5fbf8d1f7e5730c3c4f7..092bb0f5e5b3b7ffdebc7cdcc74b8fad9018ed96 100644 --- a/test/a64/traces/sim-umull2-4s-trace-a64.h +++ b/test/a64/traces/sim-umull2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-8h-trace-a64.h b/test/a64/traces/sim-umull2-8h-trace-a64.h index 065d80301463686754d7d3e6bbd54f4668690328..ca5c513ee2346fa529241b1317178ae5a2746b70 100644 --- a/test/a64/traces/sim-umull2-8h-trace-a64.h +++ b/test/a64/traces/sim-umull2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-16b-trace-a64.h b/test/a64/traces/sim-uqadd-16b-trace-a64.h index c4488fc2e5417bfce1f8dc8f276c9de866b6b046..358feef79bc7cc504af2f6c0e1f5751851b76c9a 100644 --- a/test/a64/traces/sim-uqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-uqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-2d-trace-a64.h b/test/a64/traces/sim-uqadd-2d-trace-a64.h index cb270c5a7418d1918837a405e817a88de2065cfd..122dd34ddfa7ddc4ba691ffa837f7bd0192b9e45 100644 --- a/test/a64/traces/sim-uqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-uqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-2s-trace-a64.h b/test/a64/traces/sim-uqadd-2s-trace-a64.h index e300ae414a8730a516860578fe3fb77737af6487..cbf2a57e8d500e8ce2347a9ae74044a1675c6606 100644 --- a/test/a64/traces/sim-uqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-uqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-4h-trace-a64.h b/test/a64/traces/sim-uqadd-4h-trace-a64.h index cae2842f8e2f097630f639ade2f93ea020c40e91..b60339ad533fde27fe2d22a1d622dcf46135604e 100644 --- a/test/a64/traces/sim-uqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-uqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-4s-trace-a64.h b/test/a64/traces/sim-uqadd-4s-trace-a64.h index f86d2aa9e634ea86a054019aab9480cb35da99d9..cfbe18bd1975cf9c6c467a231f6bdb1333503161 100644 --- a/test/a64/traces/sim-uqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-uqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-8b-trace-a64.h b/test/a64/traces/sim-uqadd-8b-trace-a64.h index af92d4edde9dfbd265af8ad4917a5298cf5f19db..fa8c632587616b15a8fb36796b74c818f724c321 100644 --- a/test/a64/traces/sim-uqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-uqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-8h-trace-a64.h b/test/a64/traces/sim-uqadd-8h-trace-a64.h index 430a2ca0edb30c24752916706a6c2c3ec0daa0ee..d764686db86923a108bc2a6a8b39eebbd4dd17a2 100644 --- a/test/a64/traces/sim-uqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-uqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-d-trace-a64.h b/test/a64/traces/sim-uqadd-d-trace-a64.h index 37b28a51d6720252740d6c09fb9bc838f8d8ac1b..998049e4edc47637071b3a641907f8a53d6c656c 100644 --- a/test/a64/traces/sim-uqadd-d-trace-a64.h +++ b/test/a64/traces/sim-uqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-16b-trace-a64.h b/test/a64/traces/sim-uqrshl-16b-trace-a64.h index cea54ba2040d57f48ecd2a45884f053092db28a8..1fbbd78d7b52cf9c4e40d6c53fd134495ffdf147 100644 --- a/test/a64/traces/sim-uqrshl-16b-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-2d-trace-a64.h b/test/a64/traces/sim-uqrshl-2d-trace-a64.h index 76f0cd6318a8a0ca1dc27ecc90230a57c19eed32..340dfa78f58dc3bd48906645d7d7eca7cd7f2c70 100644 --- a/test/a64/traces/sim-uqrshl-2d-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-2s-trace-a64.h b/test/a64/traces/sim-uqrshl-2s-trace-a64.h index 8fd69a60b38a24fcf8b6f65e41ebdff45950c19c..f4180b0c9ba22bbe4b2103a92fabbc3d63ad3ebf 100644 --- a/test/a64/traces/sim-uqrshl-2s-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-4h-trace-a64.h b/test/a64/traces/sim-uqrshl-4h-trace-a64.h index 91d045ebe6b50bf71a9abbec6293dfbd0143cc5d..baeb5bb1417df6ebeeae7c9d8a82270b58c4c412 100644 --- a/test/a64/traces/sim-uqrshl-4h-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-4s-trace-a64.h b/test/a64/traces/sim-uqrshl-4s-trace-a64.h index 76a06574cebbe2ab2981b9c65eb451eb0b7a64ca..a6e16a828e62b714044ea798f7b58576f6ab6dd9 100644 --- a/test/a64/traces/sim-uqrshl-4s-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-8b-trace-a64.h b/test/a64/traces/sim-uqrshl-8b-trace-a64.h index 4b9c0a1b0bd351a8294a838b61d9845ec63ab5d6..baa6a828f42c942b10c19eae583eff491deb7c43 100644 --- a/test/a64/traces/sim-uqrshl-8b-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-8h-trace-a64.h b/test/a64/traces/sim-uqrshl-8h-trace-a64.h index cc6efa0c99a6b8a9d43c32468773897fa8cb9a65..c4326fb369e454a0c00808221b9a1c8ee9d0e033 100644 --- a/test/a64/traces/sim-uqrshl-8h-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-b-trace-a64.h b/test/a64/traces/sim-uqrshl-b-trace-a64.h index a9cf6777f56ca00263cb0e47c1e743017fa832e2..680fb9ef21d0364fdefc100378ef1d1e8c565b41 100644 --- a/test/a64/traces/sim-uqrshl-b-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-d-trace-a64.h b/test/a64/traces/sim-uqrshl-d-trace-a64.h index 0e87e6e80c8f68ed9bbdfdc616aea35f3404ef5f..a7f33d3b55e7402aff54baa8ea8dd306731d45ba 100644 --- a/test/a64/traces/sim-uqrshl-d-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-h-trace-a64.h b/test/a64/traces/sim-uqrshl-h-trace-a64.h index 4d0b6a576be24cec7339b565f3a8b8ed8ce971d8..15e997504d961af46260727948ada7fa2663f3df 100644 --- a/test/a64/traces/sim-uqrshl-h-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-s-trace-a64.h b/test/a64/traces/sim-uqrshl-s-trace-a64.h index de2cddba78236246b860340c6ddc13b9e89af136..702342a3e8d5d2fed4b78e0ee295684f693ebf04 100644 --- a/test/a64/traces/sim-uqrshl-s-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h index 090531b6f8c57f3c9aebe50819e3c2dd1966ddde..9523306b2a70d06dcf50129634cf44ecb1100cca 100644 --- a/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h index 66e38454f47f7971a21b757fca24da145f82bd8f..c10a564362142f8e4dd4402549c69e8bcbbcfcad 100644 --- a/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h index b101ea46eb8058816883c2399d391da34975114f..697ae91447c30bec6ef0aa6488e3faf695a88ca0 100644 --- a/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h index cda31349809b36c8628cfdc476efcdb99d135811..d8f18218ed7c9228fcfa57c223aa76f292739242 100644 --- a/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h index a95cccef15cb2adc3f4ed37ac916854fe5d72989..5bb25d7437ec1c37b894a2be98f4aa3697372815 100644 --- a/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h index 468c3b948399832a6318d77db9e794236fd2cf82..98b297bb69ccb66ea40f418ea9ebf725c7888936 100644 --- a/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h index ba29a32240f5329aaba2683bcccabd4af1a3f4ac..6d5a5b183460b66101c64306d0783eb022cfc735 100644 --- a/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h index a8bb6db08697aba364ecbf892189a0edd2e209c3..8662adea397f9139ab951faffcabe6c3bcf1dfd7 100644 --- a/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h index dfa9621829f09a039750c73d56f1ccb799b52e83..35c750b79f3b2eacaf3583d1ea9951f604dec9e0 100644 --- a/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h index bf6e2bd452ad0094606714a861aab1a649994309..1f77d956b2ec828e4295237cf67303e9bdfec737 100644 --- a/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-16b-trace-a64.h b/test/a64/traces/sim-uqshl-16b-trace-a64.h index 695a538115e31412b59032df100fd0a51c6373d8..ed00c0e0eecd75563d7159b6b20a679498eb5be2 100644 --- a/test/a64/traces/sim-uqshl-16b-trace-a64.h +++ b/test/a64/traces/sim-uqshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h index d7433a3463d75032b0467447b2b1c67e0021efdf..14f55245af2cd8b8e796691450cf0cda16df8155 100644 --- a/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2d-trace-a64.h b/test/a64/traces/sim-uqshl-2d-trace-a64.h index e413be2710ac31049cbe3c9b2b5b13d7156df1b5..59af6f46dcaf324c85be0a145f2232dcbbc657ed 100644 --- a/test/a64/traces/sim-uqshl-2d-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h index b0fca439ab92b50a17ba597ec44968036715dede..4e6e5ca97567782637b383c8946b1c5c9d1b6a26 100644 --- a/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2s-trace-a64.h b/test/a64/traces/sim-uqshl-2s-trace-a64.h index 13914126dccba344cd055da4b629813ef7ad91fe..a2e93507b32817999baa1a8a88aaf84d9752417b 100644 --- a/test/a64/traces/sim-uqshl-2s-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h index 75369e3ec8c9de16f60da76457c8b5b9af228946..f435452ae6807f30cc68246554ff3d46771122f8 100644 --- a/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4h-trace-a64.h b/test/a64/traces/sim-uqshl-4h-trace-a64.h index b73be938e097a0c773d10b18e1c6553ef470f35e..dc5df9b704d2598251f97b9f8d4c05fa071ae3ea 100644 --- a/test/a64/traces/sim-uqshl-4h-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h index ed14b6ef4642826ec6facfdbf62ae2d9d79cb627..dc35c0b29267db89b897aeea59df768b4c6831bd 100644 --- a/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4s-trace-a64.h b/test/a64/traces/sim-uqshl-4s-trace-a64.h index 498ad014a7adb25668e4f483e79259179ac28143..df30de22e514287ee706263ca8a4710a514eec60 100644 --- a/test/a64/traces/sim-uqshl-4s-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h index b4a51356fa7a5f7366fe9f9458a997138d1c9297..36a31b808787f1fb67459c08f7200e15566861d6 100644 --- a/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8b-trace-a64.h b/test/a64/traces/sim-uqshl-8b-trace-a64.h index 1ab6a6674b00743059f5df8fc0ecfa0648a3dba2..2bccc8ad899e7c07c46c34c6e79ee017b95076ff 100644 --- a/test/a64/traces/sim-uqshl-8b-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h index aecca54de45178726aa875196093058c2bab311b..d1603d06de97bc57a4df3eda8596e3898d9a8168 100644 --- a/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8h-trace-a64.h b/test/a64/traces/sim-uqshl-8h-trace-a64.h index 6c4065163e4440fedc78da058848662687d0a06b..d91d538e680e601e9879c155a61b9b26f5c01fc8 100644 --- a/test/a64/traces/sim-uqshl-8h-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h index f9142378fcc2abf062ddf9b7a4f42aa72cf81680..c1367abaef71a7feed786a8a1a089ef590b28d20 100644 --- a/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-b-trace-a64.h b/test/a64/traces/sim-uqshl-b-trace-a64.h index edd5ca6e4babe4d6ee38fec3909acac20094a017..0a7c3a555357e6e301959599f470030d00cec0fa 100644 --- a/test/a64/traces/sim-uqshl-b-trace-a64.h +++ b/test/a64/traces/sim-uqshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h index 573c232355a63ebe53798aae0f764b145367d06f..1fb785503809205da7fcc9a3e56888c246e7386e 100644 --- a/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-d-trace-a64.h b/test/a64/traces/sim-uqshl-d-trace-a64.h index 76015d4dd42f49e6eb56061ee18e072efe26cb6d..b6580f026a73f38976098887527c8f4b333c3ba5 100644 --- a/test/a64/traces/sim-uqshl-d-trace-a64.h +++ b/test/a64/traces/sim-uqshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h index 229f3a42c834f9dbf06dcaf5b874ad6a0adde782..f23913f2c30af0fa8a9fe3bccd0132a316b7bc4f 100644 --- a/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-h-trace-a64.h b/test/a64/traces/sim-uqshl-h-trace-a64.h index ab5ff9878bfb6a8e77b5a566c5dc0d0abe8b8f13..fbe74ef73917f82ab141baa7c2dd0444385d8adc 100644 --- a/test/a64/traces/sim-uqshl-h-trace-a64.h +++ b/test/a64/traces/sim-uqshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h index dbc9d8a1b66e2c235cdef63c7710fa275c4ff57b..b44685012d40241c8af3468aa3216b3f4c43093f 100644 --- a/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-s-trace-a64.h b/test/a64/traces/sim-uqshl-s-trace-a64.h index 774db6c75972958532f7797726b7832ecc73f0f8..d6c6e617e7726a1d487e32877aa515af2ab9ed11 100644 --- a/test/a64/traces/sim-uqshl-s-trace-a64.h +++ b/test/a64/traces/sim-uqshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h index d6ce60d8aeaea81bd4d4a5983aef120c46a35ded..b4b05eb64f18d8d2bd05a15a025e03261db0476c 100644 --- a/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h index d25ff8df07ec2f5469180c8e537c920b94cacae9..cedcc099b392f8fa13ed9a34e86057f3b8e19b6e 100644 --- a/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h index ce0684d79f0c9d003ca18a0694e1641642d6ea65..d6e535baaed18e806b41e927acb0313d7ffe88cf 100644 --- a/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h index a207dae9806577a16da4639b08d00d29db6ba888..edc534532a471a0b61bdd286368213a2c0146299 100644 --- a/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h index e9eade1f089c84a7664290eca0a590d3cae111d6..dc1f1ac5e49485cd09582d0c8606f39ac8e448d2 100644 --- a/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h index 701ee25dda7b766e3c0fcff0f0dc9bf697c3a9a9..00137cad8b08b112e3363855d90306b7f3b6b44c 100644 --- a/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h index 37fad16057dc9df7bd79f3749b0afa2a8a1b3ab4..0ff99e033eb1b5844153eeaa602f8f6ccac61298 100644 --- a/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h index 6110e6eaf029364455e143d04f48d3553a522b4e..b7897235b3e1a66c840b1d7483b191ff0702011d 100644 --- a/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h index 8a6c07014d5bb5e9a0a9379cea65bef56bf69645..36b02200ed51cad7aeeb12c43410a6f03cb95fcd 100644 --- a/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-16b-trace-a64.h b/test/a64/traces/sim-uqsub-16b-trace-a64.h index bd9a8dd7ddd8dc2952911c20e25827123f8982dd..086d0aacfa884858d2afcd777b062577285b611c 100644 --- a/test/a64/traces/sim-uqsub-16b-trace-a64.h +++ b/test/a64/traces/sim-uqsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-2d-trace-a64.h b/test/a64/traces/sim-uqsub-2d-trace-a64.h index 61c2f568f84ad2d46b23fb008d16683e906506df..a63629c23e9b2c9e0782c890f6300144b90693f4 100644 --- a/test/a64/traces/sim-uqsub-2d-trace-a64.h +++ b/test/a64/traces/sim-uqsub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-2s-trace-a64.h b/test/a64/traces/sim-uqsub-2s-trace-a64.h index 85da2cfa68c01873e0a3b249e5cfdbf36744c143..4ee0fc6bc90d987679a1b647f86f2ef63c903510 100644 --- a/test/a64/traces/sim-uqsub-2s-trace-a64.h +++ b/test/a64/traces/sim-uqsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-4h-trace-a64.h b/test/a64/traces/sim-uqsub-4h-trace-a64.h index 6435a63dc81961e91d83fc63a9ec5a16a039de62..a18c21d2b8042c73e1405c671fed3ed8e77c5342 100644 --- a/test/a64/traces/sim-uqsub-4h-trace-a64.h +++ b/test/a64/traces/sim-uqsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-4s-trace-a64.h b/test/a64/traces/sim-uqsub-4s-trace-a64.h index ae577201bebcc2dbedd4e24a86a3cebbc0d05f04..afceff281abf9cc67f6d74d55b40030f5b8f22df 100644 --- a/test/a64/traces/sim-uqsub-4s-trace-a64.h +++ b/test/a64/traces/sim-uqsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-8b-trace-a64.h b/test/a64/traces/sim-uqsub-8b-trace-a64.h index b0c4ca35d69a051c30a2560615e2824ae2f2d1b3..3cd26b3dd73a5a34a1d98280cb54bee0db1e5ee6 100644 --- a/test/a64/traces/sim-uqsub-8b-trace-a64.h +++ b/test/a64/traces/sim-uqsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-8h-trace-a64.h b/test/a64/traces/sim-uqsub-8h-trace-a64.h index 805d0adcd7d3f7cd5d65534590d08240595015a3..f40fb3a75cd9540b36f07e63cb2c6b12e2fc12d2 100644 --- a/test/a64/traces/sim-uqsub-8h-trace-a64.h +++ b/test/a64/traces/sim-uqsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-d-trace-a64.h b/test/a64/traces/sim-uqsub-d-trace-a64.h index 5581bcf20e636cb0f420944d71e46acd10b2c890..e907de2adf65f34494136d65d156c53fec16bdae 100644 --- a/test/a64/traces/sim-uqsub-d-trace-a64.h +++ b/test/a64/traces/sim-uqsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-2s-trace-a64.h b/test/a64/traces/sim-uqxtn-2s-trace-a64.h index 9f163741505f91c060d642fef2b10420597522fa..02fca3fb63ba47e4d45be483b8c37905e93c4481 100644 --- a/test/a64/traces/sim-uqxtn-2s-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-4h-trace-a64.h b/test/a64/traces/sim-uqxtn-4h-trace-a64.h index 472094116f3ccd5a5785a85563a5621e3ab63c70..c9853c2a2676f29cc1107c626b2283a91e9e82ce 100644 --- a/test/a64/traces/sim-uqxtn-4h-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-8b-trace-a64.h b/test/a64/traces/sim-uqxtn-8b-trace-a64.h index b2c9bf6af7b0f38e2c40b1b046acbd7f41e19908..894936071e93706c5bbe9397e40737495f345acd 100644 --- a/test/a64/traces/sim-uqxtn-8b-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-b-trace-a64.h b/test/a64/traces/sim-uqxtn-b-trace-a64.h index d9ce6ec1ef9e2730ff893e66f63e74cb9e0d0f29..f27fd282c2789107008a08cd844a2952bab08e93 100644 --- a/test/a64/traces/sim-uqxtn-b-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-h-trace-a64.h b/test/a64/traces/sim-uqxtn-h-trace-a64.h index b5123df0ee9c1efd14623eff04b9f73db53cf199..d78f6288232d9f2896ec5a88743c5adc42db4603 100644 --- a/test/a64/traces/sim-uqxtn-h-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-s-trace-a64.h b/test/a64/traces/sim-uqxtn-s-trace-a64.h index 3b83b0ef88d90dbde0cb7acb98f9abb305505926..52df32d3fd37738ab1f376d39efb62e43420342e 100644 --- a/test/a64/traces/sim-uqxtn-s-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn2-16b-trace-a64.h b/test/a64/traces/sim-uqxtn2-16b-trace-a64.h index 60b909e74847571c46950428ad80ac25aa0af9ee..5958e56644ea664d3f3ada13d6a56e2309cd2f0c 100644 --- a/test/a64/traces/sim-uqxtn2-16b-trace-a64.h +++ b/test/a64/traces/sim-uqxtn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn2-4s-trace-a64.h b/test/a64/traces/sim-uqxtn2-4s-trace-a64.h index d40532b85b0087937d74c750e2440b7f88a5a113..620176164ee1d23c954810f37cc65ae71be7f62f 100644 --- a/test/a64/traces/sim-uqxtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-uqxtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn2-8h-trace-a64.h b/test/a64/traces/sim-uqxtn2-8h-trace-a64.h index f3cc9b37a922ae16199ebc66ac674047ed5c9dab..f430c67c5c57cf68ad5a02a19fa27f6e92468eaa 100644 --- a/test/a64/traces/sim-uqxtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-uqxtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urecpe-2s-trace-a64.h b/test/a64/traces/sim-urecpe-2s-trace-a64.h index f82a0488fbd19c2a848309f229da87f0f802e616..3b7f87c40a89a03cb9f62c60f82bdbb5dd8b538e 100644 --- a/test/a64/traces/sim-urecpe-2s-trace-a64.h +++ b/test/a64/traces/sim-urecpe-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urecpe-4s-trace-a64.h b/test/a64/traces/sim-urecpe-4s-trace-a64.h index f8404d28c7c55d0a40632d4ddf59c8e24fabab54..45154493c2879167b53677edc89a60061cd89486 100644 --- a/test/a64/traces/sim-urecpe-4s-trace-a64.h +++ b/test/a64/traces/sim-urecpe-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-16b-trace-a64.h b/test/a64/traces/sim-urhadd-16b-trace-a64.h index d4396d8713b927341846572fcb7dce29a28556fb..5c27eb34b1f7331387ca7e02a4e576bd3ab81184 100644 --- a/test/a64/traces/sim-urhadd-16b-trace-a64.h +++ b/test/a64/traces/sim-urhadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-2s-trace-a64.h b/test/a64/traces/sim-urhadd-2s-trace-a64.h index c0136d5d1925a092c85062cf650588e7c9ce3d81..3ed6aec1f4a68d608112019bb737abb7afe231a4 100644 --- a/test/a64/traces/sim-urhadd-2s-trace-a64.h +++ b/test/a64/traces/sim-urhadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-4h-trace-a64.h b/test/a64/traces/sim-urhadd-4h-trace-a64.h index 89dcd49d3f70f1daead1dc6d00bbe1ebad40bb31..5f3fb5422a8f2ec725ce167da3f026520cd24d26 100644 --- a/test/a64/traces/sim-urhadd-4h-trace-a64.h +++ b/test/a64/traces/sim-urhadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-4s-trace-a64.h b/test/a64/traces/sim-urhadd-4s-trace-a64.h index b6f71f4ceeff325f7c4851a82ed3eb58374df664..b9dbb79897697168ac6132a01716d2598737a397 100644 --- a/test/a64/traces/sim-urhadd-4s-trace-a64.h +++ b/test/a64/traces/sim-urhadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-8b-trace-a64.h b/test/a64/traces/sim-urhadd-8b-trace-a64.h index 58c69941179ecf61b10c9580b5605c25f284d00e..2171b471c9e63fd086cc47c2e627e11fc5d7ef8e 100644 --- a/test/a64/traces/sim-urhadd-8b-trace-a64.h +++ b/test/a64/traces/sim-urhadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-8h-trace-a64.h b/test/a64/traces/sim-urhadd-8h-trace-a64.h index bbafee085666c07e8af26a34761b8d581d8f6240..7b8c841a083bda2f9a5cc8ea8f2f42ead7df975e 100644 --- a/test/a64/traces/sim-urhadd-8h-trace-a64.h +++ b/test/a64/traces/sim-urhadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-16b-trace-a64.h b/test/a64/traces/sim-urshl-16b-trace-a64.h index 4188bc877b49cd5e6e81f8ef679d93ba52554246..0d9cd9026d479ef5abaea6eac9a2e41c987ba727 100644 --- a/test/a64/traces/sim-urshl-16b-trace-a64.h +++ b/test/a64/traces/sim-urshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-2d-trace-a64.h b/test/a64/traces/sim-urshl-2d-trace-a64.h index 3923c3224bd7217d53acc68a3974dd206cf7d79d..1bd3ec0dca8831146947c78f7ee9b9c7815eda48 100644 --- a/test/a64/traces/sim-urshl-2d-trace-a64.h +++ b/test/a64/traces/sim-urshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-2s-trace-a64.h b/test/a64/traces/sim-urshl-2s-trace-a64.h index d3e6df5ab61f219dd6465df4c1a42709ee5788e9..6f5366531a9c570b477d6294bf4248bf3fbec733 100644 --- a/test/a64/traces/sim-urshl-2s-trace-a64.h +++ b/test/a64/traces/sim-urshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-4h-trace-a64.h b/test/a64/traces/sim-urshl-4h-trace-a64.h index 47990c679bd5488ecf11a13800adb99fb06dfcfd..b5588126a4a5ddb376760540f6a2913d28379637 100644 --- a/test/a64/traces/sim-urshl-4h-trace-a64.h +++ b/test/a64/traces/sim-urshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-4s-trace-a64.h b/test/a64/traces/sim-urshl-4s-trace-a64.h index aa934513081af7ceca2169cbba974a82b421f799..3485e6d32faf875e1f78969c9a55cbd9e0e6d0dd 100644 --- a/test/a64/traces/sim-urshl-4s-trace-a64.h +++ b/test/a64/traces/sim-urshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-8b-trace-a64.h b/test/a64/traces/sim-urshl-8b-trace-a64.h index aa1befc8d80ec76d48b8a5312d49cd522d8f0763..ca9a8f6ce02dc5783fb04000aeca5501f9480682 100644 --- a/test/a64/traces/sim-urshl-8b-trace-a64.h +++ b/test/a64/traces/sim-urshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-8h-trace-a64.h b/test/a64/traces/sim-urshl-8h-trace-a64.h index e6ead440df96deb0a50862d8ff7e6a81bd610bb5..e7aababa5bd8429fae932168cc59c66ffd3a6c0c 100644 --- a/test/a64/traces/sim-urshl-8h-trace-a64.h +++ b/test/a64/traces/sim-urshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-d-trace-a64.h b/test/a64/traces/sim-urshl-d-trace-a64.h index 1f2376420726364c89e22ceadddbb905fddca3ae..bf066628f64c9ccb1c70d316b6bb2630068979a3 100644 --- a/test/a64/traces/sim-urshl-d-trace-a64.h +++ b/test/a64/traces/sim-urshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h index 84e6a6b73774f111184dcd066ee43efb9d05a4ca..2be33daad79242a5f0d7efc455d0a3102beb57ab 100644 --- a/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h index a59a061f536df06f94b08203c581ea944bd90109..b4ac9966bcbdcb6a4c6461aa498ef664448bd2f4 100644 --- a/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h index b0fcf04fa7af4b3407652fa762f239c62de8103b..ddccc6e03387c5868edb490f90c5497be4bd3b75 100644 --- a/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h index 8faeae7f878888ccdc4e21fb28c5d6e80537109e..8a35a3c47496ca25299c0901558911b1fc125f01 100644 --- a/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h index af7477cc637b3a10418866a4266811e591d4db10..9d9ea62c598d068cd31f227190f9025f9f30a2b9 100644 --- a/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h index 084c31153ee6d3f2aa7ecf4ef3835df30d4f2332..f776eaecedec9f7a05f9a8b275b105ca8f62a8be 100644 --- a/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h index 7fe8b0b3a64889de0d3a6965da19e71e8133f859..95f5521fb36dd8fc7cd47787ea7c49aa4d013bca 100644 --- a/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h index af95403b9d9f3c9ac1ba026947d43276f38bdf10..872e639e89cd0ae619894edebf8801914acb2207 100644 --- a/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursqrte-2s-trace-a64.h b/test/a64/traces/sim-ursqrte-2s-trace-a64.h index e5f52b8e00742e2c64bb259097942c16a286f3f4..90eef21ffd8a27441c22269f0b7a67107ea2eeac 100644 --- a/test/a64/traces/sim-ursqrte-2s-trace-a64.h +++ b/test/a64/traces/sim-ursqrte-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursqrte-4s-trace-a64.h b/test/a64/traces/sim-ursqrte-4s-trace-a64.h index 1dfbea60d673e9b7e01a018786d8407bc4e13fde..93f978fa213afed14cf6f698d5cd66c6d61486d8 100644 --- a/test/a64/traces/sim-ursqrte-4s-trace-a64.h +++ b/test/a64/traces/sim-ursqrte-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h index 146c764d349420b4ec4d72de916c22da943ab601..03197d9d7f49bdc1ef7bdc9f7c9c10b60bb6b9b0 100644 --- a/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h index f666722b40a6565a20b8d5302ec17e0569921466..c454d3522bb83ea272cd36082781478be47748fd 100644 --- a/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h index 497a3d1c6d5b1f1e4b2a400c6bbbeb13a7466279..b4b42bbac10aaf53988ad106d8da24770274c6ed 100644 --- a/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h index 9baa46e4861eaba1290fee13fa42ad1e067d1194..fb8b2e320947bd36451264e23562913e961ae355 100644 --- a/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h index a8e4ef74ae274c454876a25850a100516143c53e..f38e17e1658f683ca25dc7b6bbe75de5cf02392d 100644 --- a/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h index 5962619cdb1e1894501aadc755f4ea1c61c202c7..5a8a1f95c7c993a668852233813be9d5c4db5df3 100644 --- a/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h index 784591d32a2130bdb7f178ea3a5b138fc70594a6..1600f100ab536b5b88437a43bf56d34a33c6796f 100644 --- a/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h index 9d6a7e95aa9a6348a17e2f34b1197b89b000501d..17b877dfcf6dbc9f3362cf0fc65c118319e93a26 100644 --- a/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-16b-trace-a64.h b/test/a64/traces/sim-ushl-16b-trace-a64.h index 488459a1fcfb5ea6799a15ba9abe4ebdff000d40..cdd49839caa50e04a4e10142c2627bfe81b71ec5 100644 --- a/test/a64/traces/sim-ushl-16b-trace-a64.h +++ b/test/a64/traces/sim-ushl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-2d-trace-a64.h b/test/a64/traces/sim-ushl-2d-trace-a64.h index 0cebd9902e17df1b4eee7d3d10da497977622642..fde7934a8f8b22af80bb0182eb8acd5c0ad330d7 100644 --- a/test/a64/traces/sim-ushl-2d-trace-a64.h +++ b/test/a64/traces/sim-ushl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-2s-trace-a64.h b/test/a64/traces/sim-ushl-2s-trace-a64.h index 3ed99aff4f05b5f3bebca5908980ea965300084e..8423c0610f78e882416b6b69ebc54807427839b3 100644 --- a/test/a64/traces/sim-ushl-2s-trace-a64.h +++ b/test/a64/traces/sim-ushl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-4h-trace-a64.h b/test/a64/traces/sim-ushl-4h-trace-a64.h index 552de545ef37dd83389714973df06aaa64ad8255..9707bba4488536cdf9b08b86043e9a94d0e03764 100644 --- a/test/a64/traces/sim-ushl-4h-trace-a64.h +++ b/test/a64/traces/sim-ushl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-4s-trace-a64.h b/test/a64/traces/sim-ushl-4s-trace-a64.h index 7b334bd6710d770ad8bf46f2ede270f79a4a6b06..95dee69b707c3cdbbd74da8c224b0919ab8d1c13 100644 --- a/test/a64/traces/sim-ushl-4s-trace-a64.h +++ b/test/a64/traces/sim-ushl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-8b-trace-a64.h b/test/a64/traces/sim-ushl-8b-trace-a64.h index 39f066a87d15513a9819d7e612c2e4f5d513d6e8..80a8ca4929994480e6252c63e4e69fd9170fd049 100644 --- a/test/a64/traces/sim-ushl-8b-trace-a64.h +++ b/test/a64/traces/sim-ushl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-8h-trace-a64.h b/test/a64/traces/sim-ushl-8h-trace-a64.h index 1317dc477808a880e967463b667e026dc133f8f9..7d8901999c88e610a9958baa829ae329de235b03 100644 --- a/test/a64/traces/sim-ushl-8h-trace-a64.h +++ b/test/a64/traces/sim-ushl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-d-trace-a64.h b/test/a64/traces/sim-ushl-d-trace-a64.h index e52b87628c67ae8bca3afdb374cebc3e611448f3..340292c988aa1a963621d113cdecd52d5a417bd1 100644 --- a/test/a64/traces/sim-ushl-d-trace-a64.h +++ b/test/a64/traces/sim-ushl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h index a853db97a0e16ba8cf03a39cb2f192c73308f53c..27b9a99052a22fc83c6c147cbcbdd182fd2c735a 100644 --- a/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h index 3466837b171ee726e90e17e6738d017462547209..0ef23ff6158cfef5dc54ecc84ffa202da07600d7 100644 --- a/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h index 0d52445a2a82963db168e6758bbbe7e34a937bfb..7a1cceb0a30b06614c79082265c4d31c9b8564d7 100644 --- a/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h index 7a70b4676b4643e487aaea174440cd3198df420c..630385f542aa963c2a88d001780543facbee80f4 100644 --- a/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h index dd124ec4cee16daf9727f2db603723cdc8f5c893..3962a17483ee213cb1f57002bd9ac887db9fd96f 100644 --- a/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h index a22b89ed1447239884526503ea495aa334486a75..09383133fcbafdba29682c9317541beed546d6d1 100644 --- a/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h index 9f23cb845394b4a5ac919c5fbd849ad4ba25af31..e31f8ffb35974a4d0c6c5a9fbedfda127283b3f8 100644 --- a/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h index ab9840e4f62524d293a733082df2039f463a2d7b..c4ae9469eb178d81fbc58bc083006b462d67191a 100644 --- a/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h index 5493b5abb48c496f1f57db8f629d8f4e183e3839..f83a4506453a1ca1e9d3bfffb5fd7a13d2f54deb 100644 --- a/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h index f1888ae881f70fd22dee9778ad030e508797d86c..88f9243ac49117012287b6225fb60ff17ea69f88 100644 --- a/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h index 9856e8299bb769e41814f9eba7bd0e48a0ede569..5eba9a0c95c2228119be3fd72a9953d8acf0f0af 100644 --- a/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h index 858214911f4e1ce81cc4a160ecefa42a235039cf..b3080a020b07a9947e5645105787225ea70399fd 100644 --- a/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h index 9de8f9110e5dbdde7bcfeaef07f9cf880ecb65af..4ef79564d4a75f31eeaa786ae38db0399148de42 100644 --- a/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h index f106cc91de37837928dc87063010a8f36c946345..b6212ece0c959abcabd485731a994b74c83606ef 100644 --- a/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-16b-trace-a64.h b/test/a64/traces/sim-usqadd-16b-trace-a64.h index 932a1d0465eae7b376cafb25f148009adc77bc57..d8c7fba6ed38ac7948e3731435d7d0b85a099b46 100644 --- a/test/a64/traces/sim-usqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-usqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-2d-trace-a64.h b/test/a64/traces/sim-usqadd-2d-trace-a64.h index 162717b0ee80c5e3434d52f88efb8544454f62b2..ca4e0bfc18151cb56b31a0f65c9c5016306ce8ea 100644 --- a/test/a64/traces/sim-usqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-usqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-2s-trace-a64.h b/test/a64/traces/sim-usqadd-2s-trace-a64.h index 1243d6e99476c6f8f2b26cee4cc64c5976a4110c..649f8cb33c35506ec021b07fbf04d60a1093266f 100644 --- a/test/a64/traces/sim-usqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-usqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-4h-trace-a64.h b/test/a64/traces/sim-usqadd-4h-trace-a64.h index dbc0e654058a9674730e632326ee25d5870004b4..6546fd54e2ddd8a46d9b00e5ea7738c9f090c3d7 100644 --- a/test/a64/traces/sim-usqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-usqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-4s-trace-a64.h b/test/a64/traces/sim-usqadd-4s-trace-a64.h index 8dbd4d0ccfcf223d83c1a2d28aa6c2b9ac162404..b438fa98c730bc7d402b2009d5760f192ea52bf4 100644 --- a/test/a64/traces/sim-usqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-usqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-8b-trace-a64.h b/test/a64/traces/sim-usqadd-8b-trace-a64.h index 1ac5345d70474c59642105aa03ecf1f325882719..56d4e8cf4be3aa1ca9ea4e6863fcdf312ed675b3 100644 --- a/test/a64/traces/sim-usqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-usqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-8h-trace-a64.h b/test/a64/traces/sim-usqadd-8h-trace-a64.h index 14dc28a41f8395841d0355041de479ab296bf5a1..f9a3b91613a2810996b83eb996541f9bdfdebbe9 100644 --- a/test/a64/traces/sim-usqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-usqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-b-trace-a64.h b/test/a64/traces/sim-usqadd-b-trace-a64.h index 8f1b8863fcd99edbcd5cd36c13ca0f6e53110ec5..104e7dee88198afa70435672799c2f3b909f0b66 100644 --- a/test/a64/traces/sim-usqadd-b-trace-a64.h +++ b/test/a64/traces/sim-usqadd-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-d-trace-a64.h b/test/a64/traces/sim-usqadd-d-trace-a64.h index e7ebd45d4fa5907fb00696aef816a62256e94bec..9ce58c78e9fc4c36b7480a5c60a517606155cc7d 100644 --- a/test/a64/traces/sim-usqadd-d-trace-a64.h +++ b/test/a64/traces/sim-usqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-h-trace-a64.h b/test/a64/traces/sim-usqadd-h-trace-a64.h index 0e0988214886ea23654071a48917ac0f284e3b51..aeab5ba36a3ca08c6d5a4b117defd248096ab2c2 100644 --- a/test/a64/traces/sim-usqadd-h-trace-a64.h +++ b/test/a64/traces/sim-usqadd-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-s-trace-a64.h b/test/a64/traces/sim-usqadd-s-trace-a64.h index f0c4317885338b73b9aef54fad970c231ff20de9..00ce240848a7b4d7c5525b63dc19601bfdae2497 100644 --- a/test/a64/traces/sim-usqadd-s-trace-a64.h +++ b/test/a64/traces/sim-usqadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h index 5fbf674eb5a5669e6c16c0906b0470c2d4e1ec34..238dfbb2ec9c49ec84f0baed0484cbc91f6b2a35 100644 --- a/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h index b87edf7e64bfba8a7bc3271da11cd429526c8d99..952c18d0ccae14b44a58e4ed76afdcba93d18872 100644 --- a/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h index 43ff8dcde6ae221322e4ed234cffca6aedbad4fc..79cc8ae81aaee6d2e3a736a5dd80257cd40f963e 100644 --- a/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h index 7894d15982b6c71b5d9c51f399ef49ace17bd791..4b916fc1bd2882f2e71c4080b6bfe5e4e02fd030 100644 --- a/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h index cf77bc10f1e2077e00035d0803d56f4a3ee759a7..3013bbc66cab12355598ee8ffae76be0c0873fae 100644 --- a/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h index 0c6e73890466b2916d7bbb086c77e786c1b3bb04..0d9bc5e614e6fa61d5037d472a614fa9fff6819e 100644 --- a/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h index 5c016d7858ba0ce96251a37d5a12d08f1b7c1a56..38b24be4aba6e0ea96b15a879d782fc4e951e57f 100644 --- a/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-d-2opimm-trace-a64.h b/test/a64/traces/sim-usra-d-2opimm-trace-a64.h index 9e2378622501b28a4e18814adc30bfc471977fd5..3a1292e2bbc52f6d2dc3fe1ef5a572fddcf07562 100644 --- a/test/a64/traces/sim-usra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl-2d-trace-a64.h b/test/a64/traces/sim-usubl-2d-trace-a64.h index 7e026d837c663ba37b7c9ce0ad0424c50581863f..2192a9739f029be4f84cc5bcc01f6c5531dba03e 100644 --- a/test/a64/traces/sim-usubl-2d-trace-a64.h +++ b/test/a64/traces/sim-usubl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl-4s-trace-a64.h b/test/a64/traces/sim-usubl-4s-trace-a64.h index 50fe58b128323f02c86681688a5d80f9bce7d039..5702929c22c75f1e9e2a5eece68db54ece6f2a5f 100644 --- a/test/a64/traces/sim-usubl-4s-trace-a64.h +++ b/test/a64/traces/sim-usubl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl-8h-trace-a64.h b/test/a64/traces/sim-usubl-8h-trace-a64.h index 6e2897cfcdbe19f305e5031ba5654387d6f5d657..39d57b705787be4c3f0fc602fcb8c2ee79abcd8b 100644 --- a/test/a64/traces/sim-usubl-8h-trace-a64.h +++ b/test/a64/traces/sim-usubl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl2-2d-trace-a64.h b/test/a64/traces/sim-usubl2-2d-trace-a64.h index 62609c76d20695de199e5662b437e8d3757cff27..48cad30811d5db7801240ef2e53488a6d43f4b7b 100644 --- a/test/a64/traces/sim-usubl2-2d-trace-a64.h +++ b/test/a64/traces/sim-usubl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl2-4s-trace-a64.h b/test/a64/traces/sim-usubl2-4s-trace-a64.h index 9d762a05b0a1b1b32ae7c54bea28faa932485121..486ea3cccf5740a4d3acbaacbb0e5873102f4f98 100644 --- a/test/a64/traces/sim-usubl2-4s-trace-a64.h +++ b/test/a64/traces/sim-usubl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl2-8h-trace-a64.h b/test/a64/traces/sim-usubl2-8h-trace-a64.h index 463429127f7c0061d3abdf6806ddaf10187ffc28..7c43743ab596157e8ef0e643a85f7eefc48da625 100644 --- a/test/a64/traces/sim-usubl2-8h-trace-a64.h +++ b/test/a64/traces/sim-usubl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw-2d-trace-a64.h b/test/a64/traces/sim-usubw-2d-trace-a64.h index 88e5109303d12e2cd88f00c56d4152c2f9485bf9..c21af2549a13bf2e15b5b5f17ea128a8d388ae69 100644 --- a/test/a64/traces/sim-usubw-2d-trace-a64.h +++ b/test/a64/traces/sim-usubw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw-4s-trace-a64.h b/test/a64/traces/sim-usubw-4s-trace-a64.h index 440d70bca0dbb535ac7c70e86917c2bc4457e109..0233bca3c1f2d5b6c0589c9ec844bc6439efaaa7 100644 --- a/test/a64/traces/sim-usubw-4s-trace-a64.h +++ b/test/a64/traces/sim-usubw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw-8h-trace-a64.h b/test/a64/traces/sim-usubw-8h-trace-a64.h index daed4072cee790b9cd412750cc2dd11633794724..b972c038c33e5a28760676a1a7574cd6f34a546f 100644 --- a/test/a64/traces/sim-usubw-8h-trace-a64.h +++ b/test/a64/traces/sim-usubw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw2-2d-trace-a64.h b/test/a64/traces/sim-usubw2-2d-trace-a64.h index 5aaa0ffa2a712bd248b2925e35b928db8e04ab58..c58489c92d38d51e5b12ae7dfef5a82e5a04eb91 100644 --- a/test/a64/traces/sim-usubw2-2d-trace-a64.h +++ b/test/a64/traces/sim-usubw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw2-4s-trace-a64.h b/test/a64/traces/sim-usubw2-4s-trace-a64.h index 9c35013e0e2ac1d52e67d1c83e626caebc2662ca..fafc866c34237faba31c9345dcd9fdb883389479 100644 --- a/test/a64/traces/sim-usubw2-4s-trace-a64.h +++ b/test/a64/traces/sim-usubw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw2-8h-trace-a64.h b/test/a64/traces/sim-usubw2-8h-trace-a64.h index af1eb1738d5105ee7200562d4438d75ced239f07..d387c4d00e27e3f798ae29d015892dad5c0031f0 100644 --- a/test/a64/traces/sim-usubw2-8h-trace-a64.h +++ b/test/a64/traces/sim-usubw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-16b-trace-a64.h b/test/a64/traces/sim-uzp1-16b-trace-a64.h index 4636fcd70bf46eb52853bb5299a2634cca1a709d..91d598c87a131009150fe7047792f119fee00989 100644 --- a/test/a64/traces/sim-uzp1-16b-trace-a64.h +++ b/test/a64/traces/sim-uzp1-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-2d-trace-a64.h b/test/a64/traces/sim-uzp1-2d-trace-a64.h index b9f7b887baaa33d498d4f5ee62fcc897479c4c56..d69b43e7259bd2f164faa5d98367b281794eff0e 100644 --- a/test/a64/traces/sim-uzp1-2d-trace-a64.h +++ b/test/a64/traces/sim-uzp1-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-2s-trace-a64.h b/test/a64/traces/sim-uzp1-2s-trace-a64.h index b8848e284c74a8d63eaa691f2db6c221471d7675..8809cc66af9de9db25f1fc585c664064a6467f92 100644 --- a/test/a64/traces/sim-uzp1-2s-trace-a64.h +++ b/test/a64/traces/sim-uzp1-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-4h-trace-a64.h b/test/a64/traces/sim-uzp1-4h-trace-a64.h index b098444fab16dde2fc637b870501835acf0dde5f..1745224fa6517b3b23b0d0af51dcba0940252947 100644 --- a/test/a64/traces/sim-uzp1-4h-trace-a64.h +++ b/test/a64/traces/sim-uzp1-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-4s-trace-a64.h b/test/a64/traces/sim-uzp1-4s-trace-a64.h index 6e23c5082dcd5c4810e694317cbef1465cf96cc0..42a8d203caa2d23c67ee6e0ca107a92b6128a954 100644 --- a/test/a64/traces/sim-uzp1-4s-trace-a64.h +++ b/test/a64/traces/sim-uzp1-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-8b-trace-a64.h b/test/a64/traces/sim-uzp1-8b-trace-a64.h index 5f7c7a9259d54345142bfa17097abb3a9d62e513..bf9ed0524d4787560939e2a79f3e7ee3cc3d8736 100644 --- a/test/a64/traces/sim-uzp1-8b-trace-a64.h +++ b/test/a64/traces/sim-uzp1-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-8h-trace-a64.h b/test/a64/traces/sim-uzp1-8h-trace-a64.h index e7d44531f5e8b3a1164b5b0d229cbbc479eeed76..f973db7856b12b392060cd190df4bc4e3fa2a009 100644 --- a/test/a64/traces/sim-uzp1-8h-trace-a64.h +++ b/test/a64/traces/sim-uzp1-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-16b-trace-a64.h b/test/a64/traces/sim-uzp2-16b-trace-a64.h index 73359032e4edf8859932058d06e7c44d59de65eb..74d5ffa6f82777442cd3308b3f7f8108eae85079 100644 --- a/test/a64/traces/sim-uzp2-16b-trace-a64.h +++ b/test/a64/traces/sim-uzp2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-2d-trace-a64.h b/test/a64/traces/sim-uzp2-2d-trace-a64.h index 6cf4cd55b49565242026b5e9674b96ce33511999..25484cddd9f9eb53684f3f267fc359e978ff1e46 100644 --- a/test/a64/traces/sim-uzp2-2d-trace-a64.h +++ b/test/a64/traces/sim-uzp2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-2s-trace-a64.h b/test/a64/traces/sim-uzp2-2s-trace-a64.h index 4873a9374ca585c08dea7dd4e1162ceccc9d0345..bc5b6cee5c46a04a1d8a02ba0000891820f3fe9a 100644 --- a/test/a64/traces/sim-uzp2-2s-trace-a64.h +++ b/test/a64/traces/sim-uzp2-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-4h-trace-a64.h b/test/a64/traces/sim-uzp2-4h-trace-a64.h index b53738087323c55d4e4347a3a0bc2ba504c01c94..159c0d4fa97412190a54323a342edbfedf721325 100644 --- a/test/a64/traces/sim-uzp2-4h-trace-a64.h +++ b/test/a64/traces/sim-uzp2-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-4s-trace-a64.h b/test/a64/traces/sim-uzp2-4s-trace-a64.h index 7fa602bf26fa3c039fbaa7918e3e607b6a2fc701..454acf70e847d83fd38b082f60398075fb05b0c4 100644 --- a/test/a64/traces/sim-uzp2-4s-trace-a64.h +++ b/test/a64/traces/sim-uzp2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-8b-trace-a64.h b/test/a64/traces/sim-uzp2-8b-trace-a64.h index ecf71aa58982eaaa834173088f39573c53cbd590..7887b4a5197e89e6326888f8bbf7fa720628bcb6 100644 --- a/test/a64/traces/sim-uzp2-8b-trace-a64.h +++ b/test/a64/traces/sim-uzp2-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-8h-trace-a64.h b/test/a64/traces/sim-uzp2-8h-trace-a64.h index 4ed3820008a0ded81b72a0f664df2834932e0f75..b8838b348c735a3bf77c9870576509a408fc2ef4 100644 --- a/test/a64/traces/sim-uzp2-8h-trace-a64.h +++ b/test/a64/traces/sim-uzp2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn-2s-trace-a64.h b/test/a64/traces/sim-xtn-2s-trace-a64.h index 0f3f529d42d9c1879dedffdf99961a7344891dd1..eb52ccd548faa6b685592c2570bc569826e184e3 100644 --- a/test/a64/traces/sim-xtn-2s-trace-a64.h +++ b/test/a64/traces/sim-xtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn-4h-trace-a64.h b/test/a64/traces/sim-xtn-4h-trace-a64.h index 29ca6af6b8874a27799eb38257fa3eb53a58e335..fd1236a1e04c966b1f4ffea7cd7bef2296272771 100644 --- a/test/a64/traces/sim-xtn-4h-trace-a64.h +++ b/test/a64/traces/sim-xtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn-8b-trace-a64.h b/test/a64/traces/sim-xtn-8b-trace-a64.h index f681a48d75004bb312f683d122cb0c5aac71dbad..07869137ed9cc8397089471d34cbcd9cd85df45a 100644 --- a/test/a64/traces/sim-xtn-8b-trace-a64.h +++ b/test/a64/traces/sim-xtn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn2-16b-trace-a64.h b/test/a64/traces/sim-xtn2-16b-trace-a64.h index 37d555d1a677508a6b8df0887b65cec4cbec9a20..43266612a3474f8198be62aacd9623838e260c92 100644 --- a/test/a64/traces/sim-xtn2-16b-trace-a64.h +++ b/test/a64/traces/sim-xtn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn2-4s-trace-a64.h b/test/a64/traces/sim-xtn2-4s-trace-a64.h index 3a985e7426752f03104ad7b2bb77cb8a01cf0ee6..1a9f4a6e24214fcfde721f039747d29195e75ca7 100644 --- a/test/a64/traces/sim-xtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-xtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn2-8h-trace-a64.h b/test/a64/traces/sim-xtn2-8h-trace-a64.h index a5a32807141dd7f472a047444b724eff3f8dbec9..0fe7a1bc4f16592575b789cdf67be07312bcbc54 100644 --- a/test/a64/traces/sim-xtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-xtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-16b-trace-a64.h b/test/a64/traces/sim-zip1-16b-trace-a64.h index 1219f6a3f4973cc6bf84ea4b7458ee7a7beb4933..47443f80afb44a86e1ae17f7b7ebf8c30d5373a4 100644 --- a/test/a64/traces/sim-zip1-16b-trace-a64.h +++ b/test/a64/traces/sim-zip1-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-2d-trace-a64.h b/test/a64/traces/sim-zip1-2d-trace-a64.h index 7241bce321c855ce84f90aab4c9ba9fcc98019d1..9957d33bafefe73bd8f289cbc89e754356875f92 100644 --- a/test/a64/traces/sim-zip1-2d-trace-a64.h +++ b/test/a64/traces/sim-zip1-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-2s-trace-a64.h b/test/a64/traces/sim-zip1-2s-trace-a64.h index b5ff6eb9b562033d920052c3ade99f59f6375c22..41dd27881bcf447e9300991b1a072a1f7d1d8679 100644 --- a/test/a64/traces/sim-zip1-2s-trace-a64.h +++ b/test/a64/traces/sim-zip1-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-4h-trace-a64.h b/test/a64/traces/sim-zip1-4h-trace-a64.h index 3525ef51235445a9d4f1a10cbb7b7da1ef9a8711..4336cf570617a45b926139ab491faa9fef6be7a6 100644 --- a/test/a64/traces/sim-zip1-4h-trace-a64.h +++ b/test/a64/traces/sim-zip1-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-4s-trace-a64.h b/test/a64/traces/sim-zip1-4s-trace-a64.h index e30daf4da01d51edf94ab3497321c06a6de68fd5..eb8eb2a984525d38f42e7c134564fe0fedc3b1d6 100644 --- a/test/a64/traces/sim-zip1-4s-trace-a64.h +++ b/test/a64/traces/sim-zip1-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-8b-trace-a64.h b/test/a64/traces/sim-zip1-8b-trace-a64.h index f53ebb494b52b5623a139be08db5dfb6e1acdb35..4a229e3134ac806bf31a7786a7e98dfab8596e1c 100644 --- a/test/a64/traces/sim-zip1-8b-trace-a64.h +++ b/test/a64/traces/sim-zip1-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-8h-trace-a64.h b/test/a64/traces/sim-zip1-8h-trace-a64.h index 652cba3012cedfbeba857f1ae66bf0c410071145..971866586deea234e6eed3ca39ce1c3d78da4767 100644 --- a/test/a64/traces/sim-zip1-8h-trace-a64.h +++ b/test/a64/traces/sim-zip1-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-16b-trace-a64.h b/test/a64/traces/sim-zip2-16b-trace-a64.h index 34ad61c352436ac2808110115d19ae116c723bd8..3fb964ca08f6757b6eb9a7b7a29549fcba3e3e23 100644 --- a/test/a64/traces/sim-zip2-16b-trace-a64.h +++ b/test/a64/traces/sim-zip2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-2d-trace-a64.h b/test/a64/traces/sim-zip2-2d-trace-a64.h index 3a3a143315c0a45cd8382be5ec33f3b59fab25d8..8e98772844006e7658130f66945755b8fd6bdfb6 100644 --- a/test/a64/traces/sim-zip2-2d-trace-a64.h +++ b/test/a64/traces/sim-zip2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-2s-trace-a64.h b/test/a64/traces/sim-zip2-2s-trace-a64.h index 7273a03ff893a04760ce27b580acd74c17add1d5..985324736fb73f4a1e6da48fad7b79e8039c1100 100644 --- a/test/a64/traces/sim-zip2-2s-trace-a64.h +++ b/test/a64/traces/sim-zip2-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-4h-trace-a64.h b/test/a64/traces/sim-zip2-4h-trace-a64.h index 3963b83462ab6fea5ce287135d859bed875d41b8..1c7748887f12cd962d8e072d95d614f275b40990 100644 --- a/test/a64/traces/sim-zip2-4h-trace-a64.h +++ b/test/a64/traces/sim-zip2-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-4s-trace-a64.h b/test/a64/traces/sim-zip2-4s-trace-a64.h index 57d484830e8187e18216aa12fb9eba0cc1a3654f..0517454341bef1caa8a524446edcf9bc43630257 100644 --- a/test/a64/traces/sim-zip2-4s-trace-a64.h +++ b/test/a64/traces/sim-zip2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-8b-trace-a64.h b/test/a64/traces/sim-zip2-8b-trace-a64.h index cbb4720fe2a67612f900caaa84093b43eb4051da..961917b6de7b5947298ba6fc02024bf6dbb2ea1f 100644 --- a/test/a64/traces/sim-zip2-8b-trace-a64.h +++ b/test/a64/traces/sim-zip2-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-8h-trace-a64.h b/test/a64/traces/sim-zip2-8h-trace-a64.h index 543522a3bc3b41c0dfe3a1ff89ec9ed22af2221a..28b06e930f4c1d6cf7757392cc7d9f563173839e 100644 --- a/test/a64/traces/sim-zip2-8h-trace-a64.h +++ b/test/a64/traces/sim-zip2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-invalset.cc b/test/test-invalset.cc index 4985fbf61e131acb48c7d2cc228e1f8a46346087..f8af5bf8969e7a040260a7c78615eefc531b5a7d 100644 --- a/test/test-invalset.cc +++ b/test/test-invalset.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-runner.cc b/test/test-runner.cc index 3382eb10461e46837167f5aa2012b9c7f71f353a..6a455049a11b78c10d3771f74122912fa4379529 100644 --- a/test/test-runner.cc +++ b/test/test-runner.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-runner.h b/test/test-runner.h index e056c0879c1e404021ee78e9591802bb852889f4..5b60f65095924f5481144b3865376ed480b3370f 100644 --- a/test/test-runner.h +++ b/test/test-runner.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-utils.cc b/test/test-utils.cc index abbc6b9eea66cec9ebfccc50db011aaf4a2ff46b..cc6d2d16f65446365348cf89d510f0b1b3175c85 100644 --- a/test/test-utils.cc +++ b/test/test-utils.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-utils.h b/test/test-utils.h index 5ae32ad48ba4de1da1623da7527264b8912f956f..bf250a2eba4f880e8b9a030bbe3e10f38ab3042e 100644 --- a/test/test-utils.h +++ b/test/test-utils.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/third_party/android/Android.mk.template b/third_party/android/Android.mk.template index dc1c2965dbd7fdd08fd31195e5941032308f7bdb..30210fc79623962b5edcbe16dbe5ddc8921fff7b 100644 --- a/third_party/android/Android.mk.template +++ b/third_party/android/Android.mk.template @@ -30,7 +30,7 @@ # SUCH DAMAGE. # # -# Copyright (c) 2015 ARM Ltd +# Copyright (c) 2015 VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/third_party/android/generate_android_mk.py b/third_party/android/generate_android_mk.py index 80cff31f3d2d79ef5048d4acfcd79006b5e95b53..2c5c6329de34aed8e94f4845fb31022da961fd98 100755 --- a/third_party/android/generate_android_mk.py +++ b/third_party/android/generate_android_mk.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/clang_format.py b/tools/clang_format.py index d838cabbe66fb54c506d2e4ede57c34da60df0f5..12a14be480202ace50a4a6731e76d20fd886a270 100755 --- a/tools/clang_format.py +++ b/tools/clang_format.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/config.py b/tools/config.py index 883045a5d02102572cc1eb6662ad86f77dd334cc..4fceec781e56fdc08eb4b9ff080f1b9b0ca46542 100644 --- a/tools/config.py +++ b/tools/config.py @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/cross_build_gcc.sh b/tools/cross_build_gcc.sh index 1a646dde6b59a84bce9ea88df43ff73c1b19e460..97448ae2ea4450ab541fe72134b3559af1138a9d 100755 --- a/tools/cross_build_gcc.sh +++ b/tools/cross_build_gcc.sh @@ -1,6 +1,6 @@ #!/bin/sh -# Copyright 2013, ARM Limited +# Copyright 2013, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/generate_simulator_traces.py b/tools/generate_simulator_traces.py index 4a5ffe89450f098f87f13df21d7ff7e1876775e3..ef1fd33ec7a7b0f803c9f1d465f4fa9b8f2af6dd 100755 --- a/tools/generate_simulator_traces.py +++ b/tools/generate_simulator_traces.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +32,7 @@ import argparse import re import util -copyright_header = """// Copyright 2015, ARM Limited +copyright_header = """// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/tools/generate_test_trace_a64_reference.py b/tools/generate_test_trace_a64_reference.py index fd2bdb7d707dc32887b9c95b80498f35bd14f838..cef06fb3351ee816512de2d02138ff04e19c2400 100755 --- a/tools/generate_test_trace_a64_reference.py +++ b/tools/generate_test_trace_a64_reference.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/generate_tests.py b/tools/generate_tests.py index 634da52e55988fc1e2e810e8961ffd82da0457e0..1c29bf23fb2ea92db2c6bd0a3c5bf307e9bc4aa4 100755 --- a/tools/generate_tests.py +++ b/tools/generate_tests.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/git.py b/tools/git.py index 2fca3edf57d13d80a1064490a9257e89dc5c4a08..7c234cdb15e2bf5e04202594a0b1382fd730ecea 100644 --- a/tools/git.py +++ b/tools/git.py @@ -1,4 +1,4 @@ -# Copyright 2014, ARM Limited +# Copyright 2014, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/lint.py b/tools/lint.py index fa995252a634283a7ffe987b2c3f13a19e361d5d..14db8b99480f50b3cadd449fb3e2f6878093ce8f 100755 --- a/tools/lint.py +++ b/tools/lint.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/make_instruction_doc.pl b/tools/make_instruction_doc.pl index d5c2c6799b6ab8023bd467bcd2e3ea226d3689fc..f33fd15af33d2fde25a51770817871d7e364a0f0 100755 --- a/tools/make_instruction_doc.pl +++ b/tools/make_instruction_doc.pl @@ -1,6 +1,6 @@ #!/usr/bin/perl -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/printer.py b/tools/printer.py index dc97a5bca968313be2c9e507f0d491be25d408fc..4a37a340575a5bfe31f0e2ba6d39f4b1386b5547 100644 --- a/tools/printer.py +++ b/tools/printer.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2014, ARM Limited +# Copyright 2014, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test.py b/tools/test.py index 5445191f0b1566d4fd86f399da7921a4302c5276..8bfd2c2c60e6277d2acb590a1620ce355d1cc539 100755 --- a/tools/test.py +++ b/tools/test.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test_generator/data_types.py b/tools/test_generator/data_types.py index 432191b8b1db1cf8faba1fe6deb3dada22fc9c67..9957169846aee6f8b64bff202bffd33ec6e3077f 100644 --- a/tools/test_generator/data_types.py +++ b/tools/test_generator/data_types.py @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test_generator/generator.py b/tools/test_generator/generator.py index d8665ce569d60460525b887dec746c800eec70c7..75b99aa974774ff9bcd57aa8bf83ec13e35cfde5 100644 --- a/tools/test_generator/generator.py +++ b/tools/test_generator/generator.py @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test_generator/parser.py b/tools/test_generator/parser.py index 3f3a02489ed96837ee122b9e61e2e8cba5731e82..b9a6797cb6cbfb36c09c13bac17e6e87001fa8b3 100644 --- a/tools/test_generator/parser.py +++ b/tools/test_generator/parser.py @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/threaded_tests.py b/tools/threaded_tests.py index 370014229f42ed39bfff52e78d6f4dc6e58df24d..e48b3bb4077a903d501d14c98c018e9af3a8dab5 100644 --- a/tools/threaded_tests.py +++ b/tools/threaded_tests.py @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/util.py b/tools/util.py index 6a713601c99571ea9afaeda1a3136f701c252da5..f087d86f87559e3ca4af19008fe4d06f6ec6c665 100644 --- a/tools/util.py +++ b/tools/util.py @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/verify_assembler_traces.py b/tools/verify_assembler_traces.py index 1162a85feff892787401665083576d61bbc154a3..3508c86f2942256dbff0b859fa114a612e0d758d 100755 --- a/tools/verify_assembler_traces.py +++ b/tools/verify_assembler_traces.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without