diff --git a/product/totalcompute/tc2/include/clock_soc.h b/product/totalcompute/tc2/include/clock_soc.h index 5ecbb45234a9cbc06d80e5fce17a9ee5d806dcd7..ef241637f83e1a49ee2ef52ec901f16e98dd2a82 100644 --- a/product/totalcompute/tc2/include/clock_soc.h +++ b/product/totalcompute/tc2/include/clock_soc.h @@ -17,9 +17,9 @@ * PLL clock indexes. */ enum clock_pll_idx { - CLOCK_PLL_IDX_CPU_HAYES, - CLOCK_PLL_IDX_CPU_HUNTER, - CLOCK_PLL_IDX_CPU_HUNTER_ELP, + CLOCK_PLL_IDX_CPU_CORTEX_A520, + CLOCK_PLL_IDX_CPU_CORTEX_A720, + CLOCK_PLL_IDX_CPU_CORTEX_X4, CLOCK_PLL_IDX_SYS, CLOCK_PLL_IDX_DPU, CLOCK_PLL_IDX_PIX0, @@ -72,9 +72,9 @@ enum mod_clusclock_source_tc2 { * CSS clock indexes. */ enum clock_css_idx { - CLOCK_CSS_IDX_CPU_GROUP_HAYES, - CLOCK_CSS_IDX_CPU_GROUP_HUNTER, - CLOCK_CSS_IDX_CPU_GROUP_HUNTER_ELP, + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A520, + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A720, + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X4, CLOCK_CSS_IDX_DPU, CLOCK_CSS_IDX_COUNT }; @@ -83,9 +83,9 @@ enum clock_css_idx { * Clock indexes. */ enum clock_idx { - CLOCK_IDX_CPU_GROUP_HAYES, - CLOCK_IDX_CPU_GROUP_HUNTER, - CLOCK_IDX_CPU_GROUP_HUNTER_ELP, + CLOCK_IDX_CPU_GROUP_CORTEX_A520, + CLOCK_IDX_CPU_GROUP_CORTEX_A720, + CLOCK_IDX_CPU_GROUP_CORTEX_X4, CLOCK_IDX_DPU, CLOCK_IDX_PIXEL_0, CLOCK_IDX_PIXEL_1, diff --git a/product/totalcompute/tc2/include/tc2_amu.h b/product/totalcompute/tc2/include/tc2_amu.h index 9aee1309c00e28a32c3aefc699aee576d866093b..78770ce021f5f008ea97ff499ed5f78bba047c77 100644 --- a/product/totalcompute/tc2/include/tc2_amu.h +++ b/product/totalcompute/tc2/include/tc2_amu.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,15 +8,15 @@ #ifndef TC2_AMU_H #define TC2_AMU_H -enum hunter_amu_counter { - HUNTER_AMEVCNTR0_CORE, - HUNTER_AMEVCNTR0_CONST, - HUNTER_AMEVCNTR0_INST_RET, - HUNTER_AMEVCNTR0_MEM_STALL, - HUNTER_AMEVCNTR1_AUX0, - HUNTER_AMEVCNTR1_AUX1, - HUNTER_AMEVCNTR1_AUX2, - HUNTER_AMEVCNTR_COUNT, +enum tc2_core_amu_counter { + AMEVCNTR0_CORE, + AMEVCNTR0_CONST, + AMEVCNTR0_INST_RET, + AMEVCNTR0_MEM_STALL, + AMEVCNTR1_AUX0, + AMEVCNTR1_AUX1, + AMEVCNTR1_AUX2, + AMEVCNTR_COUNT, }; #endif /* TC2_AMU_H */ diff --git a/product/totalcompute/tc2/include/tc2_dvfs.h b/product/totalcompute/tc2/include/tc2_dvfs.h index 950140092ab96aa836ae64a73722743a0b25fc3c..1b913140afb7e2a36e092ee18ac3647a50ced990 100644 --- a/product/totalcompute/tc2/include/tc2_dvfs.h +++ b/product/totalcompute/tc2/include/tc2_dvfs.h @@ -12,9 +12,9 @@ #define TC2_DVFS_H enum dvfs_element_idx { - DVFS_ELEMENT_IDX_HAYES, - DVFS_ELEMENT_IDX_HUNTER, - DVFS_ELEMENT_IDX_HUNTER_ELP, + DVFS_ELEMENT_IDX_CORTEX_A520, + DVFS_ELEMENT_IDX_CORTEX_A720, + DVFS_ELEMENT_IDX_CORTEX_X4, DVFS_ELEMENT_IDX_GPU, DVFS_ELEMENT_IDX_COUNT }; diff --git a/product/totalcompute/tc2/include/tc2_mock_psu.h b/product/totalcompute/tc2/include/tc2_mock_psu.h index 1cfe4810564fe8ec72da573689ff27abb5fff509..a1deefdbc5f4a140ccbb2792cf3996d45cf2c809 100644 --- a/product/totalcompute/tc2/include/tc2_mock_psu.h +++ b/product/totalcompute/tc2/include/tc2_mock_psu.h @@ -12,9 +12,9 @@ #define TC2_MOCK_PSU_H enum mock_psu_id { - MOCK_PSU_ELEMENT_IDX_HAYES, - MOCK_PSU_ELEMENT_IDX_HUNTER, - MOCK_PSU_ELEMENT_IDX_HUNTER_ELP, + MOCK_PSU_ELEMENT_IDX_CORTEX_A520, + MOCK_PSU_ELEMENT_IDX_CORTEX_A720, + MOCK_PSU_ELEMENT_IDX_CORTEX_X4, MOCK_PSU_ELEMENT_IDX_GPU, MOCK_PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/totalcompute/tc2/include/tc2_psu.h b/product/totalcompute/tc2/include/tc2_psu.h index c022423118229be94c16c224353e7a965a816d71..c0cc32b9c9fbd59cd567751cb5ba23ce9e8eb885 100644 --- a/product/totalcompute/tc2/include/tc2_psu.h +++ b/product/totalcompute/tc2/include/tc2_psu.h @@ -12,9 +12,9 @@ #define TC2_PSU_H enum psu_id { - PSU_ELEMENT_IDX_HAYES, - PSU_ELEMENT_IDX_HUNTER, - PSU_ELEMENT_IDX_HUNTER_ELP, + PSU_ELEMENT_IDX_CORTEX_A520, + PSU_ELEMENT_IDX_CORTEX_A720, + PSU_ELEMENT_IDX_CORTEX_X4, PSU_ELEMENT_IDX_GPU, PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/totalcompute/tc2/include/tc2_timer.h b/product/totalcompute/tc2/include/tc2_timer.h index 3f49f839fed123653824283c44a2fdc2c7f39a12..6a6f338bf9535c0a15b5fee6b29684c7e2fac5aa 100644 --- a/product/totalcompute/tc2/include/tc2_timer.h +++ b/product/totalcompute/tc2/include/tc2_timer.h @@ -9,9 +9,9 @@ #define CONFIG_TIMER_H enum config_timer_refclk_sub_element_idx { - TC2_CONFIG_TIMER_DVFS_CPU_HAYES, - TC2_CONFIG_TIMER_DVFS_CPU_HUNTER, - TC2_CONFIG_TIMER_DVFS_CPU_HUNTER_ELP, + TC2_CONFIG_TIMER_DVFS_CPU_CORTEX_A520, + TC2_CONFIG_TIMER_DVFS_CPU_CORTEX_A720, + TC2_CONFIG_TIMER_DVFS_CPU_CORTEX_X4, TC2_CONFIG_TIMER_DVFS_GPU, #ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS TC2_CONFIG_TIMER_FAST_CHANNEL_TIMER_IDX, diff --git a/product/totalcompute/tc2/scp_ramfw/CMakeLists.txt b/product/totalcompute/tc2/scp_ramfw/CMakeLists.txt index 626c2abfb045dee112ad782ffb8ec83179ef6935..5f46c6b9709993f65a3bb90b222f095ad91dd73a 100644 --- a/product/totalcompute/tc2/scp_ramfw/CMakeLists.txt +++ b/product/totalcompute/tc2/scp_ramfw/CMakeLists.txt @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -15,8 +15,8 @@ add_executable(tc2-bl2) # - 'TC2_VARIANT_STD' for TC2 standard build # - 'TC2_VAR_EXPERIMENT_POWER' for TC2 with power/performance/thermal additions # used for evaluation purpose: -# - TRAFFIC_COP on HAYES cores -# - MPMM on HUNTER cores +# - TRAFFIC_COP on CORTEX_A520 cores +# - MPMM on CORTEX_A520, CORTEX_A720, CORTEX_X4 cores # - THERMAL_MANAGEMENT for the entire system, with a simplified/dummy power # model diff --git a/product/totalcompute/tc2/scp_ramfw/config_amu_mmap.c b/product/totalcompute/tc2/scp_ramfw/config_amu_mmap.c index 545b9c5f24c9f988f38532585df29accbdd1f740..57e6b95d42bb37169f268fbbe5e0bf2234bc26be 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_amu_mmap.c +++ b/product/totalcompute/tc2/scp_ramfw/config_amu_mmap.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,48 +28,48 @@ enum cpu_idx { CORE_COUNT_IDX, }; -uint32_t hunter_layout[] = { - [HUNTER_AMEVCNTR0_CORE] = 0, - [HUNTER_AMEVCNTR0_CONST] = sizeof(uint64_t) * 1, - [HUNTER_AMEVCNTR0_INST_RET] = sizeof(uint64_t) * 2, - [HUNTER_AMEVCNTR0_MEM_STALL] = sizeof(uint64_t) * 3, - [HUNTER_AMEVCNTR1_AUX0] = SCP_AMU_AMEVCNTR1_OFFSET, - [HUNTER_AMEVCNTR1_AUX1] = SCP_AMU_AMEVCNTR1_OFFSET + sizeof(uint64_t) * 1, - [HUNTER_AMEVCNTR1_AUX2] = SCP_AMU_AMEVCNTR1_OFFSET + sizeof(uint64_t) * 2, +uint32_t tc2_core_amu_layout[] = { + [AMEVCNTR0_CORE] = 0, + [AMEVCNTR0_CONST] = sizeof(uint64_t) * 1, + [AMEVCNTR0_INST_RET] = sizeof(uint64_t) * 2, + [AMEVCNTR0_MEM_STALL] = sizeof(uint64_t) * 3, + [AMEVCNTR1_AUX0] = SCP_AMU_AMEVCNTR1_OFFSET, + [AMEVCNTR1_AUX1] = SCP_AMU_AMEVCNTR1_OFFSET + sizeof(uint64_t) * 1, + [AMEVCNTR1_AUX2] = SCP_AMU_AMEVCNTR1_OFFSET + sizeof(uint64_t) * 2, }; static struct mod_core_element_config core_config [CORE_COUNT_IDX] = { [CORE0_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE0_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, }, [CORE1_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE1_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, }, [CORE2_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE2_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, }, [CORE3_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE3_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, }, [CORE4_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE4_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, }, [CORE5_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE5_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, }, [CORE6_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE6_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, }, [CORE7_IDX] = { .counters_base_addr = (uint64_t *)SCP_AMU_CORE_BASE(CORE7_IDX), - .counters_offsets = hunter_layout, + .counters_offsets = tc2_core_amu_layout, } }; @@ -77,42 +77,42 @@ static const struct fwk_element element_table[] = { [CORE0_IDX] = { .name = "Core0 AMU base", .data = &core_config[CORE0_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE1_IDX] = { .name = "Core1 AMU base", .data = &core_config[CORE1_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE2_IDX] = { .name = "Core2 AMU base", .data = &core_config[CORE2_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE3_IDX] = { .name = "Core3 AMU base", .data = &core_config[CORE3_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE4_IDX] = { .name = "Core4 AMU base", .data = &core_config[CORE4_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE5_IDX] = { .name = "Core5 AMU base", .data = &core_config[CORE5_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE6_IDX] = { .name = "Core6 AMU base", .data = &core_config[CORE6_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE7_IDX] = { .name = "Core7 AMU base", .data = &core_config[CORE7_IDX], - .sub_element_count = HUNTER_AMEVCNTR_COUNT, + .sub_element_count = AMEVCNTR_COUNT, }, [CORE_COUNT_IDX] = {0}, }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_clock.c b/product/totalcompute/tc2/scp_ramfw/config_clock.c index 47a661093f5151ef5cbd4d5c432f252723ee9d4f..17f8544df6ba0d1626cf58a16a3c64066c592dd9 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_clock.c +++ b/product/totalcompute/tc2/scp_ramfw/config_clock.c @@ -20,34 +20,34 @@ #include static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { - [CLOCK_IDX_CPU_GROUP_HAYES] = { - .name = "CPU_GROUP_HAYES", + [CLOCK_IDX_CPU_GROUP_CORTEX_A520] = { + .name = "CPU_GROUP_CORTEX_A520", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_HAYES), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A520), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), }), }, - [CLOCK_IDX_CPU_GROUP_HUNTER] = { - .name = "CPU_GROUP_HUNTER", + [CLOCK_IDX_CPU_GROUP_CORTEX_A720] = { + .name = "CPU_GROUP_CORTEX_A720", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_HUNTER), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A720), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), }), }, - [CLOCK_IDX_CPU_GROUP_HUNTER_ELP] = { - .name = "CPU_GROUP_HUNTER_ELP", + [CLOCK_IDX_CPU_GROUP_CORTEX_X4] = { + .name = "CPU_GROUP_CORTEX_X4", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_HUNTER_ELP), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X4), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), @@ -85,9 +85,8 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), }), - }, - [CLOCK_IDX_GPU] = - { + }, + [CLOCK_IDX_GPU] = { .name = "GPU", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( @@ -97,7 +96,7 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), }), - }, + }, { 0 }, /* Termination description. */ }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_css_clock.c b/product/totalcompute/tc2/scp_ramfw/config_css_clock.c index dfc77493f6c23338f64a39cecdea225ffe377e03..a8d69f76dd9c18dd5a9604b03ee4cbdca07db0aa 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_css_clock.c +++ b/product/totalcompute/tc2/scp_ramfw/config_css_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #include #include -static const struct mod_css_clock_rate rate_table_cpu_group_hayes[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_a520[5] = { { /* Super Underdrive */ .rate = 768 * FWK_MHZ, @@ -70,7 +70,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_hayes[5] = { }, }; -static const struct mod_css_clock_rate rate_table_cpu_group_hunter[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_a720[5] = { { /* Super Underdrive */ .rate = 946 * FWK_MHZ, @@ -123,7 +123,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_hunter[5] = { }, }; -static const struct mod_css_clock_rate rate_table_cpu_group_hunter_elp[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_x4[5] = { { /* Super Underdrive */ .rate = 1088 * FWK_MHZ, @@ -176,20 +176,20 @@ static const struct mod_css_clock_rate rate_table_cpu_group_hunter_elp[5] = { }, }; -static const fwk_id_t member_table_cpu_group_hayes[4] = { +static const fwk_id_t member_table_cpu_group_cortex_a520[4] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3), }; -static const fwk_id_t member_table_cpu_group_hunter[3] = { +static const fwk_id_t member_table_cpu_group_cortex_a720[3] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6), }; -static const fwk_id_t member_table_cpu_group_hunter_elp[1] = { +static const fwk_id_t member_table_cpu_group_cortex_x4[1] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7), }; @@ -199,22 +199,22 @@ static const fwk_id_t member_table_dpu[1] = { static const struct fwk_element css_clock_element_table[ CLOCK_CSS_IDX_COUNT + 1] = { - [CLOCK_CSS_IDX_CPU_GROUP_HAYES] = { - .name = "CPU_GROUP_HAYES", + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A520] = { + .name = "CPU_GROUP_CORTEX_A520", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL0, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_HAYES), + CLOCK_PLL_IDX_CPU_CORTEX_A520), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_hayes, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_hayes), + .member_table = member_table_cpu_group_cortex_a520, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_cortex_a520), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), @@ -222,22 +222,22 @@ static const struct fwk_element css_clock_element_table[ .modulation_supported = true, }), }, - [CLOCK_CSS_IDX_CPU_GROUP_HUNTER] = { - .name = "CPU_GROUP_HUNTER", + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A720] = { + .name = "CPU_GROUP_CORTEX_A720", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_hunter, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hunter), + .rate_table = rate_table_cpu_group_cortex_a720, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a720), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL1, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_HUNTER), + CLOCK_PLL_IDX_CPU_CORTEX_A720), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_hunter, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_hunter), + .member_table = member_table_cpu_group_cortex_a720, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_cortex_a720), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), @@ -245,23 +245,23 @@ static const struct fwk_element css_clock_element_table[ .modulation_supported = true, }), }, - [CLOCK_CSS_IDX_CPU_GROUP_HUNTER_ELP] = { - .name = "CPU_GROUP_HUNTER_ELP", + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X4] = { + .name = "CPU_GROUP_CORTEX_X4", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_hunter_elp, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hunter_elp), + .rate_table = rate_table_cpu_group_cortex_x4, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_x4), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL2, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_HUNTER_ELP), + CLOCK_PLL_IDX_CPU_CORTEX_X4), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_hunter_elp, + .member_table = member_table_cpu_group_cortex_x4, .member_count = - FWK_ARRAY_SIZE(member_table_cpu_group_hunter_elp), + FWK_ARRAY_SIZE(member_table_cpu_group_cortex_x4), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), diff --git a/product/totalcompute/tc2/scp_ramfw/config_dvfs.c b/product/totalcompute/tc2/scp_ramfw/config_dvfs.c index 7f8afea1953ecd03a27b72a0bcc4047b1ee127e5..437ef16b8c6f7396114d42c44ead8c554fd1200c 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_dvfs.c +++ b/product/totalcompute/tc2/scp_ramfw/config_dvfs.c @@ -31,108 +31,109 @@ */ /* dynamic-power-coeffient/1000 */ -#define HAYES_DPC 0.230 -#define HUNTER_DPC 0.495 -#define HUNTER_ELP_DPC 1.054 +#define CORTEX_A520_DPC 0.230 +#define CORTEX_A720_DPC 0.495 +#define CORTEX_X4_MIN_DPC 1.054 +#define CORTEX_X4_DPC 1.054 -static struct mod_dvfs_opp operating_points_hayes[6] = { +static struct mod_dvfs_opp operating_points_cortex_a520[6] = { { .level = 768 * 1000000UL, .frequency = 768 * FWK_KHZ, .voltage = 550, - .power = (uint32_t)(HAYES_DPC * 768 * 0.550 * 0.550), + .power = (uint32_t)(CORTEX_A520_DPC * 768 * 0.550 * 0.550), }, { .level = 1153 * 1000000UL, .frequency = 1153 * FWK_KHZ, .voltage = 650, - .power = (uint32_t)(HAYES_DPC * 1153 * 0.650 * 0.650), + .power = (uint32_t)(CORTEX_A520_DPC * 1153 * 0.650 * 0.650), }, { .level = 1537 * 1000000UL, .frequency = 1537 * FWK_KHZ, .voltage = 750, - .power = (uint32_t)(HAYES_DPC * 1537 * 0.750 * 0.750), + .power = (uint32_t)(CORTEX_A520_DPC * 1537 * 0.750 * 0.750), }, { .level = 1844 * 1000000UL, .frequency = 1844 * FWK_KHZ, .voltage = 850, - .power = (uint32_t)(HAYES_DPC * 1844 * 0.850 * 0.850), + .power = (uint32_t)(CORTEX_A520_DPC * 1844 * 0.850 * 0.850), }, { .level = 2152 * 1000000UL, .frequency = 2152 * FWK_KHZ, .voltage = 950, - .power = (uint32_t)(HAYES_DPC * 2152 * 0.950 * 0.950), + .power = (uint32_t)(CORTEX_A520_DPC * 2152 * 0.950 * 0.950), }, { 0 } }; -static struct mod_dvfs_opp operating_points_hunter[6] = { +static struct mod_dvfs_opp operating_points_cortex_a720[6] = { { .level = 946 * 1000000UL, .frequency = 946 * FWK_KHZ, .voltage = 550, - .power = (uint32_t)(HUNTER_DPC * 946 * 0.550 * 0.550), + .power = (uint32_t)(CORTEX_A720_DPC * 946 * 0.550 * 0.550), }, { .level = 1419 * 1000000UL, .frequency = 1419 * FWK_KHZ, .voltage = 650, - .power = (uint32_t)(HUNTER_DPC * 1419 * 0.650 * 0.650), + .power = (uint32_t)(CORTEX_A720_DPC * 1419 * 0.650 * 0.650), }, { .level = 1893 * 1000000UL, .frequency = 1893 * FWK_KHZ, .voltage = 750, - .power = (uint32_t)(HUNTER_DPC * 1893 * 0.750 * 0.750), + .power = (uint32_t)(CORTEX_A720_DPC * 1893 * 0.750 * 0.750), }, { .level = 2271 * 1000000UL, .frequency = 2271 * FWK_KHZ, .voltage = 850, - .power = (uint32_t)(HUNTER_DPC * 2271 * 0.850 * 0.850), + .power = (uint32_t)(CORTEX_A720_DPC * 2271 * 0.850 * 0.850), }, { .level = 2650 * 1000000UL, .frequency = 2650 * FWK_KHZ, .voltage = 950, - .power = (uint32_t)(HUNTER_DPC * 2650 * 0.950 * 0.950), + .power = (uint32_t)(CORTEX_A720_DPC * 2650 * 0.950 * 0.950), }, { 0 } }; -static struct mod_dvfs_opp operating_points_hunter_elp[6] = { +static struct mod_dvfs_opp operating_points_cortex_x4[6] = { { .level = 1088 * 1000000UL, .frequency = 1088 * FWK_KHZ, .voltage = 550, - .power = (uint32_t)(HUNTER_ELP_DPC * 1088 * 0.550 * 0.550), + .power = (uint32_t)(CORTEX_X4_DPC * 1088 * 0.550 * 0.550), }, { .level = 1632 * 1000000UL, .frequency = 1632 * FWK_KHZ, .voltage = 650, - .power = (uint32_t)(HUNTER_ELP_DPC * 1632 * 0.650 * 0.650), + .power = (uint32_t)(CORTEX_X4_DPC * 1632 * 0.650 * 0.650), }, { .level = 2176 * 1000000UL, .frequency = 2176 * FWK_KHZ, .voltage = 750, - .power = (uint32_t)(HUNTER_ELP_DPC * 2176 * 0.750 * 0.750), + .power = (uint32_t)(CORTEX_X4_DPC * 2176 * 0.750 * 0.750), }, { .level = 2612 * 1000000UL, .frequency = 2612 * FWK_KHZ, .voltage = 850, - .power = (uint32_t)(HUNTER_ELP_DPC * 2612 * 0.850 * 0.850), + .power = (uint32_t)(CORTEX_X4_DPC * 2612 * 0.850 * 0.850), }, { .level = 3047 * 1000000UL, .frequency = 3047 * FWK_KHZ, .voltage = 950, - .power = (uint32_t)(HUNTER_ELP_DPC * 3047 * 0.950 * 0.950), + .power = (uint32_t)(CORTEX_X4_DPC * 3047 * 0.950 * 0.950), }, { 0 } }; @@ -161,48 +162,52 @@ static struct mod_dvfs_opp operating_points_gpu[5] = { { 0 } }; -static const struct mod_dvfs_domain_config cpu_group_hayes = { - .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_HAYES), - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_HAYES), +static const struct mod_dvfs_domain_config cpu_group_cortex_a520 = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_CORTEX_A520), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A520), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC2_CONFIG_TIMER_DVFS_CPU_HAYES), + TC2_CONFIG_TIMER_DVFS_CPU_CORTEX_A520), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_hayes, + .opps = operating_points_cortex_a520, }; -static const struct mod_dvfs_domain_config cpu_group_hunter = { - .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_HUNTER), - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_HUNTER), +static const struct mod_dvfs_domain_config cpu_group_cortex_a720 = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_CORTEX_A720), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A720), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC2_CONFIG_TIMER_DVFS_CPU_HUNTER), + TC2_CONFIG_TIMER_DVFS_CPU_CORTEX_A720), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_hunter, + .opps = operating_points_cortex_a720, }; -static const struct mod_dvfs_domain_config cpu_group_hunter_elp = { +static const struct mod_dvfs_domain_config cpu_group_cortex_x4 = { .psu_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_HUNTER_ELP), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_CORTEX_X4), .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_HUNTER_ELP), + CLOCK_IDX_CPU_GROUP_CORTEX_X4), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC2_CONFIG_TIMER_DVFS_CPU_HUNTER_ELP), + TC2_CONFIG_TIMER_DVFS_CPU_CORTEX_X4), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_hunter_elp, + .opps = operating_points_cortex_x4, }; static const struct mod_dvfs_domain_config gpu = { @@ -219,20 +224,20 @@ static const struct mod_dvfs_domain_config gpu = { }; static const struct fwk_element element_table[DVFS_ELEMENT_IDX_COUNT + 1] = { - [DVFS_ELEMENT_IDX_HAYES] = + [DVFS_ELEMENT_IDX_CORTEX_A520] = { - .name = "CPU_GROUP_HAYES", - .data = &cpu_group_hayes, + .name = "CPU_GROUP_CORTEX_A520", + .data = &cpu_group_cortex_a520, }, - [DVFS_ELEMENT_IDX_HUNTER] = + [DVFS_ELEMENT_IDX_CORTEX_A720] = { - .name = "CPU_GROUP_HUNTER", - .data = &cpu_group_hunter, + .name = "CPU_GROUP_CORTEX_A720", + .data = &cpu_group_cortex_a720, }, - [DVFS_ELEMENT_IDX_HUNTER_ELP] = + [DVFS_ELEMENT_IDX_CORTEX_X4] = { - .name = "CPU_GROUP_HUNTER_ELP", - .data = &cpu_group_hunter_elp, + .name = "CPU_GROUP_CORTEX_X4", + .data = &cpu_group_cortex_x4, }, [DVFS_ELEMENT_IDX_GPU] = { diff --git a/product/totalcompute/tc2/scp_ramfw/config_gtimer.c b/product/totalcompute/tc2/scp_ramfw/config_gtimer.c index d297ab21ea9ce50a0415fcaafcf58a5b192c4b89..56a15619f062c39be265628d9632dd1920a0a831 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_gtimer.c +++ b/product/totalcompute/tc2/scp_ramfw/config_gtimer.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ static const struct fwk_element gtimer_dev_table[2] = { .frequency = CLOCK_RATE_REFCLK, .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_HAYES), + CLOCK_IDX_CPU_GROUP_CORTEX_A520), }), }, [1] = { 0 }, diff --git a/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c b/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c index 6d6baae9f3960c7efeb0ee09dc64e48895eba75d..b0e9bc97f06d2ac78e79a7f5c930fa11ac6a4ad1 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c +++ b/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c @@ -13,8 +13,8 @@ #include static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = { - [MOCK_PSU_ELEMENT_IDX_HAYES] = { - .name = "DVFS_GROUP_HAYES", + [MOCK_PSU_ELEMENT_IDX_CORTEX_A520] = { + .name = "DVFS_GROUP_CORTEX_A520", .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, @@ -27,8 +27,8 @@ static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = .default_voltage = 550, }, }, - [MOCK_PSU_ELEMENT_IDX_HUNTER] = { - .name = "DVFS_GROUP_HUNTER", + [MOCK_PSU_ELEMENT_IDX_CORTEX_A720] = { + .name = "DVFS_GROUP_CORTEX_A720", .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, @@ -41,8 +41,8 @@ static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = .default_voltage = 550, }, }, - [MOCK_PSU_ELEMENT_IDX_HUNTER_ELP] = { - .name = "DVFS_GROUP_HUNTER_ELP", + [MOCK_PSU_ELEMENT_IDX_CORTEX_X4] = { + .name = "DVFS_GROUP_CORTEX_X4", .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, diff --git a/product/totalcompute/tc2/scp_ramfw/config_mpmm.c b/product/totalcompute/tc2/scp_ramfw/config_mpmm.c index 988d6e12495781a3746319ba52353839e3465f60..1d08ebf23c2b21ae160bdc000949555d63bf3172 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_mpmm.c +++ b/product/totalcompute/tc2/scp_ramfw/config_mpmm.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,7 +29,7 @@ enum cpu_idx { CORE7_IDX }; -static struct mod_mpmm_pct_table hunter_pct[4] = { +static struct mod_mpmm_pct_table cortex_a720_pct[4] = { { .cores_online = 4, .default_perf_limit = 1419 * 1000000UL, @@ -88,55 +88,55 @@ static struct mod_mpmm_pct_table hunter_pct[4] = { }, }; -static const struct mod_mpmm_core_config hunter_core_config[4] = { +static const struct mod_mpmm_core_config cortex_a720_core_config[4] = { [0] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE4_IDX), .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE4_IDX), .core_starts_online = false, .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_AMU_MMAP, CORE4_IDX, HUNTER_AMEVCNTR1_AUX0), + FWK_MODULE_IDX_AMU_MMAP, CORE4_IDX, AMEVCNTR1_AUX0), }, [1] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE5_IDX), .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE5_IDX), .core_starts_online = false, .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_AMU_MMAP, CORE5_IDX, HUNTER_AMEVCNTR1_AUX0), + FWK_MODULE_IDX_AMU_MMAP, CORE5_IDX, AMEVCNTR1_AUX0), }, [2] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE6_IDX), .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE6_IDX), .core_starts_online = false, .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_AMU_MMAP, CORE6_IDX, HUNTER_AMEVCNTR1_AUX0), + FWK_MODULE_IDX_AMU_MMAP, CORE6_IDX, AMEVCNTR1_AUX0), }, [3] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE7_IDX), .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE7_IDX), .core_starts_online = false, .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_AMU_MMAP, CORE7_IDX, HUNTER_AMEVCNTR1_AUX0), + FWK_MODULE_IDX_AMU_MMAP, CORE7_IDX, AMEVCNTR1_AUX0), }, }; -static const struct mod_mpmm_domain_config hunter_domain_conf[2] = { +static const struct mod_mpmm_domain_config cortex_a720_domain_conf[2] = { [0] = { .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_HUNTER), - .pct = hunter_pct, - .pct_size = FWK_ARRAY_SIZE(hunter_pct), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_CORTEX_A720), + .pct = cortex_a720_pct, + .pct_size = FWK_ARRAY_SIZE(cortex_a720_pct), .btc = 10, .num_threshold_counters = 3, - .core_config = hunter_core_config, + .core_config = cortex_a720_core_config, }, [1] = {0}, }; static const struct fwk_element element_table[2] = { [0] = { - .name = "MPMM_HUNTER_ELEM", + .name = "MPMM_CORTEX_A720_ELEM", .sub_element_count = 1, - .data = hunter_domain_conf, + .data = cortex_a720_domain_conf, }, [1] = { 0 }, }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_pik_clock.c b/product/totalcompute/tc2/scp_ramfw/config_pik_clock.c index f452646c44ba439caa924258c10ffab06dd16547..1d59c080a904018f2fb711af14e3472291ee4787 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_pik_clock.c +++ b/product/totalcompute/tc2/scp_ramfw/config_pik_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,7 @@ /* * Rate lookup tables */ -static const struct mod_pik_clock_rate rate_table_cpu_group_hayes[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_a520[1] = { { .rate = 1537 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL0, @@ -30,7 +30,7 @@ static const struct mod_pik_clock_rate rate_table_cpu_group_hayes[1] = { }, }; -static const struct mod_pik_clock_rate rate_table_cpu_group_hunter[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_a720[1] = { { .rate = 1893 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL1, @@ -39,7 +39,7 @@ static const struct mod_pik_clock_rate rate_table_cpu_group_hunter[1] = { }, }; -static const struct mod_pik_clock_rate rate_table_cpu_group_hunter_elp[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_x4[1] = { { .rate = 2176 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL2, @@ -104,8 +104,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[0].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, [CLOCK_PIK_IDX_CLUS0_CPU1] = { @@ -116,8 +116,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[1].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, [CLOCK_PIK_IDX_CLUS0_CPU2] = { @@ -128,8 +128,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[2].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, [CLOCK_PIK_IDX_CLUS0_CPU3] = { @@ -140,8 +140,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[3].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, [CLOCK_PIK_IDX_CLUS0_CPU4] = { @@ -152,8 +152,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[4].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[4].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[4].MOD, - .rate_table = rate_table_cpu_group_hunter, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hunter), + .rate_table = rate_table_cpu_group_cortex_a720, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a720), }), }, [CLOCK_PIK_IDX_CLUS0_CPU5] = { @@ -164,8 +164,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[5].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[5].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[5].MOD, - .rate_table = rate_table_cpu_group_hunter, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hunter), + .rate_table = rate_table_cpu_group_cortex_a720, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a720), }), }, [CLOCK_PIK_IDX_CLUS0_CPU6] = { @@ -176,8 +176,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[6].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[6].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[6].MOD, - .rate_table = rate_table_cpu_group_hunter, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hunter), + .rate_table = rate_table_cpu_group_cortex_a720, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a720), }), }, [CLOCK_PIK_IDX_CLUS0_CPU7] = { @@ -188,8 +188,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[7].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[7].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[7].MOD, - .rate_table = rate_table_cpu_group_hunter_elp, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hunter_elp), + .rate_table = rate_table_cpu_group_cortex_x4, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_x4), }), }, [CLOCK_PIK_IDX_GIC] = { diff --git a/product/totalcompute/tc2/scp_ramfw/config_psu.c b/product/totalcompute/tc2/scp_ramfw/config_psu.c index 1277158617539775c86723ae07d922712d5aa8de..678cdbddb64d84a14ffd5cabd1cc89af02191f14 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_psu.c +++ b/product/totalcompute/tc2/scp_ramfw/config_psu.c @@ -16,32 +16,32 @@ #include static const struct fwk_element element_table[PSU_ELEMENT_IDX_COUNT + 1] = { - [PSU_ELEMENT_IDX_HAYES] = { - .name = "PSU_GROUP_HAYES", + [PSU_ELEMENT_IDX_CORTEX_A520] = { + .name = "PSU_GROUP_CORTEX_A520", .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_HAYES), + MOCK_PSU_ELEMENT_IDX_CORTEX_A520), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, }, - [PSU_ELEMENT_IDX_HUNTER] = { - .name = "PSU_GROUP_HUNTER", + [PSU_ELEMENT_IDX_CORTEX_A720] = { + .name = "PSU_GROUP_CORTEX_A720", .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_HUNTER), + MOCK_PSU_ELEMENT_IDX_CORTEX_A720), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, }, - [PSU_ELEMENT_IDX_HUNTER_ELP] = { - .name = "PSU_GROUP_HUNTER_ELP", + [PSU_ELEMENT_IDX_CORTEX_X4] = { + .name = "PSU_GROUP_CORTEX_X4", .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_HUNTER_ELP), + MOCK_PSU_ELEMENT_IDX_CORTEX_X4), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, diff --git a/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c b/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c index 650783482753e27d3a7db87090c1674397122956..3e8026e6702d2a6a5d8b1d6ce93e4ea7d01c789f 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c +++ b/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c @@ -56,75 +56,75 @@ static const struct mod_scmi_perf_domain_config domains[DVFS_ELEMENT_IDX_COUNT] = { - [DVFS_ELEMENT_IDX_HAYES] = { + [DVFS_ELEMENT_IDX_CORTEX_A520] = { #ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS .fast_channels_addr_scp = (uint64_t[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), }, .fast_channels_addr_ap = (uint64_t[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_HAYES), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A520), }, #endif }, - [DVFS_ELEMENT_IDX_HUNTER] = { + [DVFS_ELEMENT_IDX_CORTEX_A720] = { #ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS .fast_channels_addr_scp = (uint64_t[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), }, .fast_channels_addr_ap = (uint64_t[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_A720), }, #endif }, - [DVFS_ELEMENT_IDX_HUNTER_ELP] = { + [DVFS_ELEMENT_IDX_CORTEX_X4] = { #ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS .fast_channels_addr_scp = (uint64_t[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), }, .fast_channels_addr_ap = (uint64_t[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_CORTEX_X4), }, #endif }, diff --git a/product/totalcompute/tc2/scp_ramfw/config_sds.c b/product/totalcompute/tc2/scp_ramfw/config_sds.c index 5347dab23a831be5d71f83315ec81e0edcbe5fec..236c9bf92e7c2f1e0fbae5dcce1b0ab9e44d1386 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_sds.c +++ b/product/totalcompute/tc2/scp_ramfw/config_sds.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,8 +39,9 @@ static_assert( const struct mod_sds_config sds_module_config = { .regions = sds_module_regions, .region_count = TC_SDS_REGION_COUNT, - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_HAYES) + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A520) }; static struct fwk_element sds_element_table[3] = { diff --git a/product/totalcompute/tc2/scp_ramfw/config_system_pll.c b/product/totalcompute/tc2/scp_ramfw/config_system_pll.c index da54ce1fd4ac37a1a000bc91a8cd9401eeb82c80..c98702755309834d9e13d0c394ab1d16af2b939d 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_system_pll.c +++ b/product/totalcompute/tc2/scp_ramfw/config_system_pll.c @@ -18,8 +18,8 @@ static const struct fwk_element system_pll_element_table[ CLOCK_PLL_IDX_COUNT + 1] = { - [CLOCK_PLL_IDX_CPU_HAYES] = { - .name = "CPU_PLL_HAYES", + [CLOCK_PLL_IDX_CPU_CORTEX_A520] = { + .name = "CPU_PLL_CORTEX_A520", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU0, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], @@ -30,8 +30,8 @@ static const struct fwk_element system_pll_element_table[ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, }), }, - [CLOCK_PLL_IDX_CPU_HUNTER] = { - .name = "CPU_PLL_HUNTER", + [CLOCK_PLL_IDX_CPU_CORTEX_A720] = { + .name = "CPU_PLL_CORTEX_A720", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU1, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], @@ -42,8 +42,8 @@ static const struct fwk_element system_pll_element_table[ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, }), }, - [CLOCK_PLL_IDX_CPU_HUNTER_ELP] = { - .name = "CPU_PLL_HUNTER_ELP", + [CLOCK_PLL_IDX_CPU_CORTEX_X4] = { + .name = "CPU_PLL_CORTEX_X4", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU2, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], @@ -103,9 +103,8 @@ static const struct fwk_element system_pll_element_table[ .min_step = 25 * FWK_KHZ, .defer_initialization = false, }), - }, - [CLOCK_PLL_IDX_GPU] = - { + }, + [CLOCK_PLL_IDX_GPU] = { .name = "GPU_PLL", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_GPU, @@ -116,7 +115,7 @@ static const struct fwk_element system_pll_element_table[ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, .defer_initialization = false, }), - }, + }, [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_thermal_mgmt.c b/product/totalcompute/tc2/scp_ramfw/config_thermal_mgmt.c index b3a773552054c2461ead4ee570b38faed504287f..de11079ae7ce9f5c80e9e20919e0546e3ad11600 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_thermal_mgmt.c +++ b/product/totalcompute/tc2/scp_ramfw/config_thermal_mgmt.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,14 +22,14 @@ static struct mod_thermal_mgmt_actor_config actor_table_domain0[2] = { .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC2_POWER_MODEL, 0), .dvfs_domain_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_HAYES), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_CORTEX_A520), .weight = 100, }, [1] = { .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC2_POWER_MODEL, 1), .dvfs_domain_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_HUNTER), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_CORTEX_A720), .weight = 100, }, }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_traffic_cop.c b/product/totalcompute/tc2/scp_ramfw/config_traffic_cop.c index 559f6f2ff01e846cb8d48a48320b033475fe9c8a..b30e6a62ba76a23ba2f97e21407baa110a24458c 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_traffic_cop.c +++ b/product/totalcompute/tc2/scp_ramfw/config_traffic_cop.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ enum cpu_idx { CORE7_PD_IDX }; -static struct mod_tcop_pct_table hayes_pct[3] = { +static struct mod_tcop_pct_table cortex_a520_pct[3] = { { /* * Perf limit for 4 cores online. @@ -48,7 +48,7 @@ static struct mod_tcop_pct_table hayes_pct[3] = { }, }; -static const struct mod_tcop_core_config hayes_core_config[4] = { +static const struct mod_tcop_core_config cortex_a520_core_config[4] = { [0] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE0_PD_IDX), .core_starts_online = true, @@ -67,23 +67,23 @@ static const struct mod_tcop_core_config hayes_core_config[4] = { }, }; -static const struct mod_tcop_domain_config hayes_domain_conf[2] = { +static const struct mod_tcop_domain_config cortex_a520_domain_conf[2] = { [0] = { .perf_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_DVFS, - DVFS_ELEMENT_IDX_HAYES), - .pct = hayes_pct, - .pct_size = FWK_ARRAY_SIZE(hayes_pct), - .core_config = hayes_core_config, + DVFS_ELEMENT_IDX_CORTEX_A520), + .pct = cortex_a520_pct, + .pct_size = FWK_ARRAY_SIZE(cortex_a520_pct), + .core_config = cortex_a520_core_config, }, [1] = { { 0 } }, }; static const struct fwk_element element_table[2] = { [0] = { - .name = "TCOP_HAYES", + .name = "TCOP_CORTEX_A520", .sub_element_count = 4, - .data = hayes_domain_conf, + .data = cortex_a520_domain_conf, }, [1] = { 0 }, }; diff --git a/product/totalcompute/tc2/scp_romfw/config_clock.c b/product/totalcompute/tc2/scp_romfw/config_clock.c index 76f0e915fbc4405511c403d43d97dd59764db4ec..937baa5f03695c1435501560a503b8d6054d8a81 100644 --- a/product/totalcompute/tc2/scp_romfw/config_clock.c +++ b/product/totalcompute/tc2/scp_romfw/config_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,12 +21,13 @@ #include static const struct fwk_element clock_dev_desc_table[2] = { - [CLOCK_IDX_CPU_GROUP_HAYES] = { - .name = "CPU_GROUP_HAYES", + [CLOCK_IDX_CPU_GROUP_CORTEX_A520] = + { + .name = "CPU_GROUP_CORTEX_A520", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_HAYES), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A520), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), diff --git a/product/totalcompute/tc2/scp_romfw/config_cmn_booker.c b/product/totalcompute/tc2/scp_romfw/config_cmn_booker.c index b614d7d73a84c1d2f2b38445b03beb535ef86909..bf8da53891fca4655540d8511f75735c39eb0bce 100644 --- a/product/totalcompute/tc2/scp_romfw/config_cmn_booker.c +++ b/product/totalcompute/tc2/scp_romfw/config_cmn_booker.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -116,7 +116,7 @@ const struct fwk_module_config config_cmn_booker = { .mmap_count = FWK_ARRAY_SIZE(mmap), .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_HAYES), + CLOCK_IDX_CPU_GROUP_CORTEX_A520), .hnf_cal_mode = false, .ports_per_xp = 4, }), diff --git a/product/totalcompute/tc2/scp_romfw/config_css_clock.c b/product/totalcompute/tc2/scp_romfw/config_css_clock.c index b7da7b64d99d531110bcc79c5cf396963900a5f6..d45e7edaa3be249209c855b0edb2cc0a1665ca51 100644 --- a/product/totalcompute/tc2/scp_romfw/config_css_clock.c +++ b/product/totalcompute/tc2/scp_romfw/config_css_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #include #include -static const struct mod_css_clock_rate rate_table_cpu_group_hayes[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_a520[5] = { { /* Super Underdrive */ .rate = 768 * FWK_MHZ, @@ -70,7 +70,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_hayes[5] = { }, }; -static const fwk_id_t member_table_cpu_group_hayes[4] = { +static const fwk_id_t member_table_cpu_group_cortex_a520[4] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), @@ -78,22 +78,22 @@ static const fwk_id_t member_table_cpu_group_hayes[4] = { }; static const struct fwk_element css_clock_element_table[2] = { - [CLOCK_CSS_IDX_CPU_GROUP_HAYES] = { - .name = "CPU_GROUP_HAYES", + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A520] = { + .name = "CPU_GROUP_CORTEX_A520", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL0, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_HAYES), + CLOCK_PLL_IDX_CPU_CORTEX_A520), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_hayes, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_hayes), + .member_table = member_table_cpu_group_cortex_a520, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_cortex_a520), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), diff --git a/product/totalcompute/tc2/scp_romfw/config_gtimer.c b/product/totalcompute/tc2/scp_romfw/config_gtimer.c index 382db9c86123b9e59d45239720fdc1b7ba748b31..cd5925d1a791ef1f120fde4db10772da5458073c 100644 --- a/product/totalcompute/tc2/scp_romfw/config_gtimer.c +++ b/product/totalcompute/tc2/scp_romfw/config_gtimer.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ static const struct fwk_element gtimer_dev_table[2] = { .frequency = CLOCK_RATE_REFCLK, .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_HAYES), + CLOCK_IDX_CPU_GROUP_CORTEX_A520), }), }, [1] = { 0 }, diff --git a/product/totalcompute/tc2/scp_romfw/config_pik_clock.c b/product/totalcompute/tc2/scp_romfw/config_pik_clock.c index 382e31769e7855839caef8be4162704c2c4b41cb..b13d9fb30be139265b914ca4bfc19e8beb410344 100644 --- a/product/totalcompute/tc2/scp_romfw/config_pik_clock.c +++ b/product/totalcompute/tc2/scp_romfw/config_pik_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,7 @@ /* * Rate lookup tables */ -static const struct mod_pik_clock_rate rate_table_cpu_group_hayes[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_a520[1] = { { .rate = 1537 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC2_PLL0, @@ -39,8 +39,8 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[0].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, [CLOCK_PIK_IDX_CLUS0_CPU1] = { @@ -51,8 +51,8 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[1].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, [CLOCK_PIK_IDX_CLUS0_CPU2] = { @@ -63,8 +63,8 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[2].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, [CLOCK_PIK_IDX_CLUS0_CPU3] = { @@ -75,8 +75,8 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[3].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_hayes, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_hayes), + .rate_table = rate_table_cpu_group_cortex_a520, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a520), }), }, {0} diff --git a/product/totalcompute/tc2/scp_romfw/config_sds.c b/product/totalcompute/tc2/scp_romfw/config_sds.c index 5745ff925e62c7dcb85f895d4b620b37fd04642b..32890ca719794ef4bf25b89d7260756c22d62877 100644 --- a/product/totalcompute/tc2/scp_romfw/config_sds.c +++ b/product/totalcompute/tc2/scp_romfw/config_sds.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,8 +39,9 @@ static_assert( const struct mod_sds_config sds_module_config = { .regions = sds_module_regions, .region_count = TC_SDS_REGION_COUNT, - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_HAYES) + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A520) }; static struct fwk_element sds_element_table[4] = { diff --git a/product/totalcompute/tc2/scp_romfw/config_system_pll.c b/product/totalcompute/tc2/scp_romfw/config_system_pll.c index c21fce5a2bd141dc34d366cffe1735b724d2a8ec..b0d68ca7bad91a64f9a7b3652439d2f80318abb4 100644 --- a/product/totalcompute/tc2/scp_romfw/config_system_pll.c +++ b/product/totalcompute/tc2/scp_romfw/config_system_pll.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,8 +17,8 @@ #include static const struct fwk_element system_pll_element_table[2] = { - [CLOCK_PLL_IDX_CPU_HAYES] = { - .name = "CPU_PLL_HAYES", + [CLOCK_PLL_IDX_CPU_CORTEX_A520] = { + .name = "CPU_PLL_CORTEX_A520", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU0, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],