From ff5fe059a061fbe0e7e584c1e5c6f28dc0ff8a11 Mon Sep 17 00:00:00 2001 From: Ben Horgan Date: Fri, 21 Jul 2023 14:24:34 +0100 Subject: [PATCH 1/3] tc: Power off the GPU and DPU This is required for FPGA but include for FVP too so can demonstrate controlling power domains. Signed-off-by: Ben Horgan Signed-off-by: Quoc Khanh Le Change-Id: I85b269220ca4f2a3627d8f91ec6516146af984e6 --- .../common/scp_ramfw/config_ppu_v1.c | 43 ++++++++++++++----- .../common/scp_ramfw/config_ppu_v1.h | 19 ++++++++ product/totalcompute/tc2/include/scp_mmap.h | 3 ++ 3 files changed, 55 insertions(+), 10 deletions(-) create mode 100644 product/totalcompute/common/scp_ramfw/config_ppu_v1.h diff --git a/product/totalcompute/common/scp_ramfw/config_ppu_v1.c b/product/totalcompute/common/scp_ramfw/config_ppu_v1.c index d700cecec..77c64f89d 100644 --- a/product/totalcompute/common/scp_ramfw/config_ppu_v1.c +++ b/product/totalcompute/common/scp_ramfw/config_ppu_v1.c @@ -1,11 +1,12 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "config_power_domain.h" +#include "config_ppu_v1.h" #include "scp_mmap.h" #include "tc_core.h" @@ -40,15 +41,37 @@ static struct mod_ppu_v1_config ppu_v1_config_data = { MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), }; -static const struct fwk_element ppu_v1_system_element_table[1] = { - [0] = { - .name = "SYS0", - .data = &((struct mod_ppu_v1_pd_config){ - .pd_type = MOD_PD_TYPE_SYSTEM, - .ppu.reg_base = SCP_PPU_SYS0_BASE, - .observer_id = FWK_ID_NONE_INIT, - }), - }, +static struct fwk_element ppu_v1_system_element_table[] = { + [PPU_V1_ELEMENT_IDX_SYS0] = + { + .name = "SYS0", + .data = &((struct mod_ppu_v1_pd_config){ + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS0_BASE, + .observer_id = FWK_ID_NONE_INIT, + .default_power_on = false, + }), + }, + [PPU_V1_ELEMENT_IDX_GPUTOP0] = + { + .name = "GPUTOP0", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_DEVICE, + .ppu.reg_base = SCP_PPU_GPU_BASE, + .observer_id = FWK_ID_NONE_INIT, + .default_power_on = false, + }), + }, + [PPU_V1_ELEMENT_IDX_DPUTOP0] = + { + .name = "DPUTOP0", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_DEVICE, + .ppu.reg_base = SCP_PPU_DPU_BASE, + .observer_id = FWK_ID_NONE_INIT, + .default_power_on = false, + }), + }, }; static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) diff --git a/product/totalcompute/common/scp_ramfw/config_ppu_v1.h b/product/totalcompute/common/scp_ramfw/config_ppu_v1.h new file mode 100644 index 000000000..dc2f81eff --- /dev/null +++ b/product/totalcompute/common/scp_ramfw/config_ppu_v1.h @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_PPU_V1_H +#define CONFIG_PPU_V1_H + +/* Identifiers for the static table */ +enum ppu_v1_static_element_idx { + PPU_V1_ELEMENT_IDX_SYS0, + PPU_V1_ELEMENT_IDX_GPUTOP0, + PPU_V1_ELEMENT_IDX_DPUTOP0, + PPU_V1_ELEMENT_IDX_COUNT +}; + +#endif /* CONFIG_PPU_V1_H */ diff --git a/product/totalcompute/tc2/include/scp_mmap.h b/product/totalcompute/tc2/include/scp_mmap.h index e4e2abf9e..745e046b7 100644 --- a/product/totalcompute/tc2/include/scp_mmap.h +++ b/product/totalcompute/tc2/include/scp_mmap.h @@ -48,6 +48,7 @@ #define SCP_PIK_CLUSTER_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x60000) #define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x40000) #define SCP_PIK_DPU_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0xE0000) +#define SCP_PIK_GPU_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0xA0000) #define SCP_UTILITY_BUS_BASE \ (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x1000000) @@ -63,6 +64,8 @@ (SCP_AMU_CORE_BASE(CPU_IDX) + SCP_AMU_AMEVCNTR1_OFFSET) #define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000) +#define SCP_PPU_DPU_BASE (SCP_PIK_DPU_BASE + 0x1000) +#define SCP_PPU_GPU_BASE (SCP_PIK_GPU_BASE + 0x1000) #define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE) -- GitLab From 697e60fa3818405698f459da01122788e5302d92 Mon Sep 17 00:00:00 2001 From: Ben Horgan Date: Wed, 21 Jun 2023 13:43:27 +0100 Subject: [PATCH 2/3] tc: Enable GPU DVFS Add the gpu operating points (OPP) and add a gpu domain for the SCMI performance protocol. Signed-off-by: Ben Horgan Signed-off-by: Quoc Khanh Le Change-Id: Id8de0352bc2d39aa196a95d4cdcea347a3a43f04 --- product/totalcompute/tc2/include/clock_soc.h | 4 +- product/totalcompute/tc2/include/scp_mmap.h | 1 + product/totalcompute/tc2/include/tc2_dvfs.h | 3 +- .../totalcompute/tc2/include/tc2_mock_psu.h | 3 +- product/totalcompute/tc2/include/tc2_psu.h | 3 +- product/totalcompute/tc2/include/tc2_timer.h | 3 +- .../totalcompute/tc2/scp_ramfw/config_clock.c | 16 ++++++- .../totalcompute/tc2/scp_ramfw/config_dvfs.c | 44 ++++++++++++++++++- .../tc2/scp_ramfw/config_mock_psu.c | 16 ++++++- .../totalcompute/tc2/scp_ramfw/config_psu.c | 12 ++++- .../tc2/scp_ramfw/config_scmi_perf.c | 26 ++++++++++- .../tc2/scp_ramfw/config_system_pll.c | 17 ++++++- 12 files changed, 135 insertions(+), 13 deletions(-) diff --git a/product/totalcompute/tc2/include/clock_soc.h b/product/totalcompute/tc2/include/clock_soc.h index 8574b7528..5ecbb4523 100644 --- a/product/totalcompute/tc2/include/clock_soc.h +++ b/product/totalcompute/tc2/include/clock_soc.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,7 @@ enum clock_pll_idx { CLOCK_PLL_IDX_DPU, CLOCK_PLL_IDX_PIX0, CLOCK_PLL_IDX_PIX1, + CLOCK_PLL_IDX_GPU, CLOCK_PLL_IDX_COUNT }; @@ -88,6 +89,7 @@ enum clock_idx { CLOCK_IDX_DPU, CLOCK_IDX_PIXEL_0, CLOCK_IDX_PIXEL_1, + CLOCK_IDX_GPU, CLOCK_IDX_COUNT }; diff --git a/product/totalcompute/tc2/include/scp_mmap.h b/product/totalcompute/tc2/include/scp_mmap.h index 745e046b7..01fb0fbd0 100644 --- a/product/totalcompute/tc2/include/scp_mmap.h +++ b/product/totalcompute/tc2/include/scp_mmap.h @@ -79,6 +79,7 @@ #define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000) #define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) +#define SCP_PLL_GPU (SCP_PLL_BASE + 0x00000008) #define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014) #define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018) #define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C) diff --git a/product/totalcompute/tc2/include/tc2_dvfs.h b/product/totalcompute/tc2/include/tc2_dvfs.h index b8cdcd7a5..950140092 100644 --- a/product/totalcompute/tc2/include/tc2_dvfs.h +++ b/product/totalcompute/tc2/include/tc2_dvfs.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,6 +15,7 @@ enum dvfs_element_idx { DVFS_ELEMENT_IDX_HAYES, DVFS_ELEMENT_IDX_HUNTER, DVFS_ELEMENT_IDX_HUNTER_ELP, + DVFS_ELEMENT_IDX_GPU, DVFS_ELEMENT_IDX_COUNT }; diff --git a/product/totalcompute/tc2/include/tc2_mock_psu.h b/product/totalcompute/tc2/include/tc2_mock_psu.h index 571a7fe0a..1cfe48105 100644 --- a/product/totalcompute/tc2/include/tc2_mock_psu.h +++ b/product/totalcompute/tc2/include/tc2_mock_psu.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,6 +15,7 @@ enum mock_psu_id { MOCK_PSU_ELEMENT_IDX_HAYES, MOCK_PSU_ELEMENT_IDX_HUNTER, MOCK_PSU_ELEMENT_IDX_HUNTER_ELP, + MOCK_PSU_ELEMENT_IDX_GPU, MOCK_PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/totalcompute/tc2/include/tc2_psu.h b/product/totalcompute/tc2/include/tc2_psu.h index 9e8bba651..c02242311 100644 --- a/product/totalcompute/tc2/include/tc2_psu.h +++ b/product/totalcompute/tc2/include/tc2_psu.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,6 +15,7 @@ enum psu_id { PSU_ELEMENT_IDX_HAYES, PSU_ELEMENT_IDX_HUNTER, PSU_ELEMENT_IDX_HUNTER_ELP, + PSU_ELEMENT_IDX_GPU, PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/totalcompute/tc2/include/tc2_timer.h b/product/totalcompute/tc2/include/tc2_timer.h index b3d340ef9..3f49f839f 100644 --- a/product/totalcompute/tc2/include/tc2_timer.h +++ b/product/totalcompute/tc2/include/tc2_timer.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ enum config_timer_refclk_sub_element_idx { TC2_CONFIG_TIMER_DVFS_CPU_HAYES, TC2_CONFIG_TIMER_DVFS_CPU_HUNTER, TC2_CONFIG_TIMER_DVFS_CPU_HUNTER_ELP, + TC2_CONFIG_TIMER_DVFS_GPU, #ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS TC2_CONFIG_TIMER_FAST_CHANNEL_TIMER_IDX, #endif diff --git a/product/totalcompute/tc2/scp_ramfw/config_clock.c b/product/totalcompute/tc2/scp_ramfw/config_clock.c index 5801d7245..47a661093 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_clock.c +++ b/product/totalcompute/tc2/scp_ramfw/config_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -85,7 +85,19 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), }), - }, + }, + [CLOCK_IDX_GPU] = + { + .name = "GPU", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_GPU), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + }), + }, { 0 }, /* Termination description. */ }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_dvfs.c b/product/totalcompute/tc2/scp_ramfw/config_dvfs.c index cb2f42f90..7f8afea19 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_dvfs.c +++ b/product/totalcompute/tc2/scp_ramfw/config_dvfs.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -137,6 +137,30 @@ static struct mod_dvfs_opp operating_points_hunter_elp[6] = { { 0 } }; +static struct mod_dvfs_opp operating_points_gpu[5] = { + { + .level = 350 * 1000000UL, + .frequency = 350 * FWK_KHZ, + .voltage = 550, + }, + { + .level = 680 * 1000000UL, + .frequency = 680 * FWK_KHZ, + .voltage = 650, + }, + { + .level = 1000 * 1000000UL, + .frequency = 1000 * FWK_KHZ, + .voltage = 750, + }, + { + .level = 1260 * 1000000UL, + .frequency = 1260 * FWK_KHZ, + .voltage = 850, + }, + { 0 } +}; + static const struct mod_dvfs_domain_config cpu_group_hayes = { .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_HAYES), .clock_id = @@ -181,6 +205,19 @@ static const struct mod_dvfs_domain_config cpu_group_hunter_elp = { .opps = operating_points_hunter_elp, }; +static const struct mod_dvfs_domain_config gpu = { + .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GPU), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_GPU), + .alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + TC2_CONFIG_TIMER_DVFS_GPU), + .retry_ms = 1, + .latency = 1200, + .sustained_idx = 2, + .opps = operating_points_gpu, +}; + static const struct fwk_element element_table[DVFS_ELEMENT_IDX_COUNT + 1] = { [DVFS_ELEMENT_IDX_HAYES] = { @@ -197,6 +234,11 @@ static const struct fwk_element element_table[DVFS_ELEMENT_IDX_COUNT + 1] = { .name = "CPU_GROUP_HUNTER_ELP", .data = &cpu_group_hunter_elp, }, + [DVFS_ELEMENT_IDX_GPU] = + { + .name = "GPU", + .data = &gpu, + }, { 0 }, }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c b/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c index 50bd1f5b2..6d6baae9f 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c +++ b/product/totalcompute/tc2/scp_ramfw/config_mock_psu.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,6 +55,20 @@ static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = .default_voltage = 550, }, }, + [MOCK_PSU_ELEMENT_IDX_GPU] = { + .name = "DVFS_GROUP_GPU", + .data = + &(const struct mod_mock_psu_element_cfg){ + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 550, + }, + }, { 0 } }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_psu.c b/product/totalcompute/tc2/scp_ramfw/config_psu.c index 4fa8778ea..127715861 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_psu.c +++ b/product/totalcompute/tc2/scp_ramfw/config_psu.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,6 +46,16 @@ static const struct fwk_element element_table[PSU_ELEMENT_IDX_COUNT + 1] = { FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, }, + [PSU_ELEMENT_IDX_GPU] = { + .name = "PSU_GROUP_GPU", + .data = + &(const struct mod_psu_element_cfg){ + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, + MOCK_PSU_ELEMENT_IDX_GPU), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER) }, + }, { 0 } }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c b/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c index 003b6e85a..650783482 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c +++ b/product/totalcompute/tc2/scp_ramfw/config_scmi_perf.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -126,6 +126,30 @@ static const struct mod_scmi_perf_domain_config [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_HUNTER_ELP), }, +#endif + }, + [DVFS_ELEMENT_IDX_GPU] = { +#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + .fast_channels_addr_scp = (uint64_t[]) { + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_GPU), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_GPU), + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_GPU), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_GPU), + }, + .fast_channels_addr_ap = (uint64_t[]) { + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + }, #endif }, }; diff --git a/product/totalcompute/tc2/scp_ramfw/config_system_pll.c b/product/totalcompute/tc2/scp_ramfw/config_system_pll.c index c11bc1a7e..da54ce1fd 100644 --- a/product/totalcompute/tc2/scp_ramfw/config_system_pll.c +++ b/product/totalcompute/tc2/scp_ramfw/config_system_pll.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,7 +103,20 @@ static const struct fwk_element system_pll_element_table[ .min_step = 25 * FWK_KHZ, .defer_initialization = false, }), - }, + }, + [CLOCK_PLL_IDX_GPU] = + { + .name = "GPU_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_GPU, + .status_reg = NULL, + .initial_rate = 800 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + .defer_initialization = false, + }), + }, [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ }; -- GitLab From 180275a9fea346b4fe61b1e73db1f5e205fb37f6 Mon Sep 17 00:00:00 2001 From: Ben Horgan Date: Fri, 21 Jul 2023 14:32:18 +0100 Subject: [PATCH 3/3] tc: Add configuration for GPU and DPU power domains GPU and DPU power can now be turned on and off via SCMI power domain protocal. Signed-off-by: Ben Horgan Signed-off-by: Quoc Khanh Le Change-Id: I0cf6ea1758c4101081e35bb95ec9676a5487be95 --- .../common/include/config_power_domain.h | 4 +- .../common/scp_ramfw/config_power_domain.c | 84 +++++++++++++++---- 2 files changed, 72 insertions(+), 16 deletions(-) diff --git a/product/totalcompute/common/include/config_power_domain.h b/product/totalcompute/common/include/config_power_domain.h index ff63fbdf8..9a4b8a0e8 100644 --- a/product/totalcompute/common/include/config_power_domain.h +++ b/product/totalcompute/common/include/config_power_domain.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,8 @@ * core_count + cluster_count + pd_static_dev_idx */ enum pd_static_dev_idx { + PD_STATIC_DEV_IDX_GPUTOP, + PD_STATIC_DEV_IDX_DPUTOP, PD_STATIC_DEV_IDX_SYSTOP, PD_STATIC_DEV_IDX_COUNT, PD_STATIC_DEV_IDX_NONE = UINT32_MAX diff --git a/product/totalcompute/common/scp_ramfw/config_power_domain.c b/product/totalcompute/common/scp_ramfw/config_power_domain.c index f70c85a3e..dab1eb14c 100644 --- a/product/totalcompute/common/scp_ramfw/config_power_domain.c +++ b/product/totalcompute/common/scp_ramfw/config_power_domain.c @@ -1,11 +1,12 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "config_power_domain.h" +#include "config_ppu_v1.h" #include "tc_core.h" #include "tc_power_domain.h" @@ -34,6 +35,26 @@ static const uint32_t systop_allowed_state_mask_table[1] = { [0] = MOD_PD_STATE_ON_MASK }; +/* Mask of the allowed states for the gputop power domain depending on the + * system states. + */ +static const uint32_t gputop_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK +}; + +/* Mask of the allowed states for the dputop power domain depending on the + * system states. + */ +static const uint32_t dputop_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK +}; + /* * Mask of the allowed states for the cluster power domain depending on the * system states. @@ -52,20 +73,53 @@ static const uint32_t core_pd_allowed_state_mask_table[2] = { /* Power module specific configuration data (none) */ static const struct mod_power_domain_config tc_power_domain_config = { 0 }; -static struct fwk_element tc_power_domain_static_element_table[1] = { - [PD_STATIC_DEV_IDX_SYSTOP] = { - .name = "SYSTOP", - .data = &((struct mod_power_domain_element_config){ - .attributes.pd_type = MOD_PD_TYPE_SYSTEM, - .parent_idx = PD_STATIC_DEV_IDX_NONE, - .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_POWER, - MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), - .allowed_state_mask_table = systop_allowed_state_mask_table, - .allowed_state_mask_table_size = - FWK_ARRAY_SIZE(systop_allowed_state_mask_table) }), - }, +static struct fwk_element tc_power_domain_static_element_table[] = { + [PD_STATIC_DEV_IDX_GPUTOP] = + { + .name = "GPUTOP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_DEVICE, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PPU_V1, + CORES_PER_CLUSTER * NUMBER_OF_CLUSTERS + + NUMBER_OF_CLUSTERS + PPU_V1_ELEMENT_IDX_GPUTOP0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = gputop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(gputop_allowed_state_mask_table) }), + }, + [PD_STATIC_DEV_IDX_DPUTOP] = + { + .name = "DPUTOP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_DEVICE, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PPU_V1, + CORES_PER_CLUSTER * NUMBER_OF_CLUSTERS + + NUMBER_OF_CLUSTERS + PPU_V1_ELEMENT_IDX_DPUTOP0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = dputop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(dputop_allowed_state_mask_table) }), + }, + [PD_STATIC_DEV_IDX_SYSTOP] = + { + .name = "SYSTOP", + .data = &((struct mod_power_domain_element_config){ + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .parent_idx = PD_STATIC_DEV_IDX_NONE, + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) }), + }, }; /* -- GitLab