From c8f3fe74e58ae9b4d42f2fc1ec88ec0e7fd93f9a Mon Sep 17 00:00:00 2001 From: Leandro Belli Date: Tue, 8 Aug 2023 17:15:23 +0100 Subject: [PATCH 1/2] [TEST]rdn2: move SCP and MCP to M55 core This patch changes the core from M7 to M55 to SCP and MCP firmware in RDN2 platform. This is only intended to be use for test. Do not merge. Signed-off-by: Leandro Belli Change-Id: I52bbb50170d42225e04db145f8a637d84b248619 --- product/rdn2/include/fmw_cmsis.h | 10 +- product/rdn2/mcp_ramfw/CMakeLists.txt | 4 +- product/rdn2/mcp_ramfw/Firmware.cmake | 4 +- .../rdn2/mcp_ramfw/Toolchain-ArmClang.cmake | 5 +- product/rdn2/mcp_ramfw/Toolchain-Clang.cmake | 4 +- product/rdn2/mcp_ramfw/Toolchain-GNU.cmake | 4 +- product/rdn2/mcp_ramfw/config_armv7m_mpu.c | 64 ------------- product/rdn2/mcp_ramfw/config_armv8m_mpu.c | 61 +++++++++++++ .../rdn2/mcp_romfw/Toolchain-ArmClang.cmake | 5 +- product/rdn2/mcp_romfw/Toolchain-Clang.cmake | 4 +- product/rdn2/mcp_romfw/Toolchain-GNU.cmake | 4 +- product/rdn2/scp_ramfw/CMakeLists.txt | 4 +- product/rdn2/scp_ramfw/Firmware.cmake | 2 +- .../rdn2/scp_ramfw/Toolchain-ArmClang.cmake | 5 +- product/rdn2/scp_ramfw/Toolchain-Clang.cmake | 4 +- product/rdn2/scp_ramfw/Toolchain-GNU.cmake | 4 +- product/rdn2/scp_ramfw/config_armv7m_mpu.c | 91 ------------------- product/rdn2/scp_ramfw/config_armv8m_mpu.c | 70 ++++++++++++++ .../rdn2/scp_romfw/Toolchain-ArmClang.cmake | 5 +- product/rdn2/scp_romfw/Toolchain-Clang.cmake | 4 +- product/rdn2/scp_romfw/Toolchain-GNU.cmake | 4 +- 21 files changed, 173 insertions(+), 189 deletions(-) delete mode 100644 product/rdn2/mcp_ramfw/config_armv7m_mpu.c create mode 100644 product/rdn2/mcp_ramfw/config_armv8m_mpu.c delete mode 100644 product/rdn2/scp_ramfw/config_armv7m_mpu.c create mode 100644 product/rdn2/scp_ramfw/config_armv8m_mpu.c diff --git a/product/rdn2/include/fmw_cmsis.h b/product/rdn2/include/fmw_cmsis.h index 6f8f0ce5f..f81c20ef9 100644 --- a/product/rdn2/include/fmw_cmsis.h +++ b/product/rdn2/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,13 +11,16 @@ #include #define __CHECK_DEVICE_DEFINES -#define __CM7_REV 0x0000U +#define __CM55_REV 0x0000U #define __FPU_PRESENT 0U #define __MPU_PRESENT 1U +#define __PMU_PRESENT 0U +#define __DSP_PRESENT 0U #define __ICACHE_PRESENT 0U #define __DCACHE_PRESENT 0U #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U +#define __SAUREGION_PRESENT 0U #define __Vendor_SysTickConfig 0U #define __VTOR_PRESENT 1U @@ -30,6 +33,7 @@ typedef enum IRQn { MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, + SecureFault_IRQn = -9, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, @@ -51,6 +55,6 @@ typedef enum IRQn { IRQn_MAX = INT16_MAX, } IRQn_Type; -#include +#include #endif /* FMW_CMSIS_H */ diff --git a/product/rdn2/mcp_ramfw/CMakeLists.txt b/product/rdn2/mcp_ramfw/CMakeLists.txt index d99477696..a0da4821e 100644 --- a/product/rdn2/mcp_ramfw/CMakeLists.txt +++ b/product/rdn2/mcp_ramfw/CMakeLists.txt @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -37,7 +37,7 @@ target_include_directories( target_sources( rdn2-mcp-bl2 - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv7m_mpu.c" + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv8m_mpu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_timer.c" diff --git a/product/rdn2/mcp_ramfw/Firmware.cmake b/product/rdn2/mcp_ramfw/Firmware.cmake index e865d6d65..3c9769e59 100644 --- a/product/rdn2/mcp_ramfw/Firmware.cmake +++ b/product/rdn2/mcp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -35,7 +35,7 @@ list(PREPEND SCP_MODULE_PATHS # modules are initialized, bound, started during the pre-runtime phase. # any change in the order will cause firmware initialization errors. -list(APPEND SCP_MODULES "armv7m-mpu") +list(APPEND SCP_MODULES "armv8m-mpu") list(APPEND SCP_MODULES "pl011") list(APPEND SCP_MODULES "clock") list(APPEND SCP_MODULES "pcid") diff --git a/product/rdn2/mcp_ramfw/Toolchain-ArmClang.cmake b/product/rdn2/mcp_ramfw/Toolchain-ArmClang.cmake index 6e9e3fa0f..248b80fb2 100755 --- a/product/rdn2/mcp_ramfw/Toolchain-ArmClang.cmake +++ b/product/rdn2/mcp_ramfw/Toolchain-ArmClang.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,7 +9,8 @@ include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +# No Helium, no FPU, No DSP features +set(CMAKE_SYSTEM_ARCH "armv8.1-m.main") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/mcp_ramfw/Toolchain-Clang.cmake b/product/rdn2/mcp_ramfw/Toolchain-Clang.cmake index 194548802..e250c254a 100644 --- a/product/rdn2/mcp_ramfw/Toolchain-Clang.cmake +++ b/product/rdn2/mcp_ramfw/Toolchain-Clang.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/mcp_ramfw/Toolchain-GNU.cmake b/product/rdn2/mcp_ramfw/Toolchain-GNU.cmake index a4ea7a3f7..29dad4155 100755 --- a/product/rdn2/mcp_ramfw/Toolchain-GNU.cmake +++ b/product/rdn2/mcp_ramfw/Toolchain-GNU.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") diff --git a/product/rdn2/mcp_ramfw/config_armv7m_mpu.c b/product/rdn2/mcp_ramfw/config_armv7m_mpu.c deleted file mode 100644 index 5478a1104..000000000 --- a/product/rdn2/mcp_ramfw/config_armv7m_mpu.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "mcp_mmap.h" - -#include - -#include -#include - -#include - -static const ARM_MPU_Region_t regions[] = { - { - /* 0x0000_0000 - 0xFFFF_FFFF */ - .RBAR = ARM_MPU_RBAR(0, MCP_BOOT_ROM_BASE), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 1, - 0, - 1, - 0, - ARM_MPU_REGION_SIZE_4GB), - }, - { - /* 0x0080_0000 - 0x00A0_0000 */ - .RBAR = ARM_MPU_RBAR(1, MCP_ITC_RAM_BASE), - .RASR = ARM_MPU_RASR( - 0, - ARM_MPU_AP_PRO, - 0, - 0, - 1, - 0, - 0, - ARM_MPU_REGION_SIZE_256KB), - }, - { - /* 0x2000_0000 - 2020_0000 */ - .RBAR = ARM_MPU_RBAR(2, MCP_DTC_RAM_BASE), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 0, - 1, - 1, - 0, - ARM_MPU_REGION_SIZE_256KB), - }, -}; - -const struct fwk_module_config config_armv7m_mpu = { - .data = &((struct mod_armv7m_mpu_config){ - .region_count = FWK_ARRAY_SIZE(regions), - .regions = regions, - }), -}; diff --git a/product/rdn2/mcp_ramfw/config_armv8m_mpu.c b/product/rdn2/mcp_ramfw/config_armv8m_mpu.c new file mode 100644 index 000000000..fea79fd08 --- /dev/null +++ b/product/rdn2/mcp_ramfw/config_armv8m_mpu.c @@ -0,0 +1,61 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mcp_mmap.h" +#include "mod_armv8m_mpu.h" + +#include +#include + +#include + +static const uint8_t attributes[2] = { + /* Device memory, non Gathering, non Re-ordering, non Early Write + Acknowledgement */ + /* + [MPU_ATTR_0] = + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE), + */ + /* Normal memory, non Cacheable */ + /* + [MPU_ATTR_1] = + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE), + */ +}; + +static const ARM_MPU_Region_t regions[] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + /* + .RBAR = ... + .RLAR = ... + */ + }, + { + /* 0x0080_0000 - 0x00A0_0000 */ + /* + .RBAR = ... + .RLAR = ... + */ + }, + { + /* 0x2000_0000 - 2020_0000 */ + /* + .RBAR = ... + .RLAR = ... + */ + }, +}; + +const struct fwk_module_config config_armv8m_mpu = { + .data = &((struct mod_armv8m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + .attributes_count = FWK_ARRAY_SIZE(attributes), + .attributes = attributes, + }), +}; diff --git a/product/rdn2/mcp_romfw/Toolchain-ArmClang.cmake b/product/rdn2/mcp_romfw/Toolchain-ArmClang.cmake index 6e9e3fa0f..248b80fb2 100755 --- a/product/rdn2/mcp_romfw/Toolchain-ArmClang.cmake +++ b/product/rdn2/mcp_romfw/Toolchain-ArmClang.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,7 +9,8 @@ include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +# No Helium, no FPU, No DSP features +set(CMAKE_SYSTEM_ARCH "armv8.1-m.main") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/mcp_romfw/Toolchain-Clang.cmake b/product/rdn2/mcp_romfw/Toolchain-Clang.cmake index 194548802..e250c254a 100644 --- a/product/rdn2/mcp_romfw/Toolchain-Clang.cmake +++ b/product/rdn2/mcp_romfw/Toolchain-Clang.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/mcp_romfw/Toolchain-GNU.cmake b/product/rdn2/mcp_romfw/Toolchain-GNU.cmake index a4ea7a3f7..29dad4155 100755 --- a/product/rdn2/mcp_romfw/Toolchain-GNU.cmake +++ b/product/rdn2/mcp_romfw/Toolchain-GNU.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") diff --git a/product/rdn2/scp_ramfw/CMakeLists.txt b/product/rdn2/scp_ramfw/CMakeLists.txt index 2d4ed8c7d..c887380a7 100644 --- a/product/rdn2/scp_ramfw/CMakeLists.txt +++ b/product/rdn2/scp_ramfw/CMakeLists.txt @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -47,7 +47,7 @@ target_include_directories( target_sources( rdn2-bl2 PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_system_power.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_armv7m_mpu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_armv8m_mpu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_power_domain.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_ppu_v1.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_mhu2.c" diff --git a/product/rdn2/scp_ramfw/Firmware.cmake b/product/rdn2/scp_ramfw/Firmware.cmake index a590a4e2d..abe4e8dbd 100644 --- a/product/rdn2/scp_ramfw/Firmware.cmake +++ b/product/rdn2/scp_ramfw/Firmware.cmake @@ -39,7 +39,7 @@ list(PREPEND SCP_MODULE_PATHS # modules are initialized, bound, started during the pre-runtime phase. # any change in the order will cause firmware initialization errors. -list(APPEND SCP_MODULES "armv7m-mpu") +list(APPEND SCP_MODULES "armv8m-mpu") list(APPEND SCP_MODULES "apremap") list(APPEND SCP_MODULES "sid") list(APPEND SCP_MODULES "system-info") diff --git a/product/rdn2/scp_ramfw/Toolchain-ArmClang.cmake b/product/rdn2/scp_ramfw/Toolchain-ArmClang.cmake index 6e9e3fa0f..248b80fb2 100755 --- a/product/rdn2/scp_ramfw/Toolchain-ArmClang.cmake +++ b/product/rdn2/scp_ramfw/Toolchain-ArmClang.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,7 +9,8 @@ include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +# No Helium, no FPU, No DSP features +set(CMAKE_SYSTEM_ARCH "armv8.1-m.main") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/scp_ramfw/Toolchain-Clang.cmake b/product/rdn2/scp_ramfw/Toolchain-Clang.cmake index 194548802..e250c254a 100644 --- a/product/rdn2/scp_ramfw/Toolchain-Clang.cmake +++ b/product/rdn2/scp_ramfw/Toolchain-Clang.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/scp_ramfw/Toolchain-GNU.cmake b/product/rdn2/scp_ramfw/Toolchain-GNU.cmake index a4ea7a3f7..29dad4155 100755 --- a/product/rdn2/scp_ramfw/Toolchain-GNU.cmake +++ b/product/rdn2/scp_ramfw/Toolchain-GNU.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") diff --git a/product/rdn2/scp_ramfw/config_armv7m_mpu.c b/product/rdn2/scp_ramfw/config_armv7m_mpu.c deleted file mode 100644 index 02a012ab5..000000000 --- a/product/rdn2/scp_ramfw/config_armv7m_mpu.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_mmap.h" -#include "scp_software_mmap.h" - -#include - -#include -#include - -#include - -static const ARM_MPU_Region_t regions[] = { - { - /* 0x0000_0000 - 0xFFFF_FFFF */ - .RBAR = ARM_MPU_RBAR(0, 0x00000000), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 1, - 0, - 1, - 0, - ARM_MPU_REGION_SIZE_4GB), - }, - { - /* 0x0080_0000 - 0x00FF_FFFF */ - .RBAR = ARM_MPU_RBAR(1, SCP_ITC_RAM_BASE), - .RASR = ARM_MPU_RASR( - 0, - ARM_MPU_AP_PRO, - 0, - 0, - 1, - 0, - 0, - ARM_MPU_REGION_SIZE_256KB), - }, - { - /* 0x2000_0000 - 0x20FF_FFFF */ - .RBAR = ARM_MPU_RBAR(2, SCP_DTC_RAM_BASE), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 0, - 1, - 1, - 0, - ARM_MPU_REGION_SIZE_256KB), - }, - { - /* 0xA400_0000 - 0xA400_7FFF*/ - .RBAR = ARM_MPU_RBAR(3, SCP_TRUSTED_RAM_BASE), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 1, - 1, - 1, - 0, - ARM_MPU_REGION_SIZE_4KB), - }, - { - /* 0xA600_0000 - 0xA600_7FFF */ - .RBAR = ARM_MPU_RBAR(4, SCP_NONTRUSTED_RAM_BASE), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 1, - 1, - 1, - 0, - ARM_MPU_REGION_SIZE_256B), - }, -}; - -const struct fwk_module_config config_armv7m_mpu = { - .data = &((struct mod_armv7m_mpu_config){ - .region_count = FWK_ARRAY_SIZE(regions), - .regions = regions, - }), -}; diff --git a/product/rdn2/scp_ramfw/config_armv8m_mpu.c b/product/rdn2/scp_ramfw/config_armv8m_mpu.c new file mode 100644 index 000000000..d4efdb895 --- /dev/null +++ b/product/rdn2/scp_ramfw/config_armv8m_mpu.c @@ -0,0 +1,70 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "scp_software_mmap.h" + +#include + +#include +#include + +#include + +static const uint8_t attributes[2] = { + /* Device memory, non Gathering, non Re-ordering, non Early Write + Acknowledgement */ + /* + [MPU_ATTR_0] = + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE), + */ + /* Normal memory, non Cacheable */ + /* + [MPU_ATTR_1] = + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE), + */ +}; + +static const ARM_MPU_Region_t regions[] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + /* + .RBAR = ... + .RLAR = ... + */ + }, + { + /* 0xA400_0000 - 0xA400_7FFF*/ + /* + .RBAR = ... + .RLAR = ... + */ + }, + { + /* 0xA400_0000 - 0xA400_7FFF*/ + /* + .RBAR = ... + .RLAR = ... + */ + }, + { + /* 0xA600_0000 - 0xA600_7FFF */ + /* + .RBAR = ... + .RLAR = ... + */ + }, +}; + +const struct fwk_module_config config_armv8m_mpu = { + .data = &((struct mod_armv8m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + .attributes_count = FWK_ARRAY_SIZE(attributes), + .attributes = attributes, + }), +}; diff --git a/product/rdn2/scp_romfw/Toolchain-ArmClang.cmake b/product/rdn2/scp_romfw/Toolchain-ArmClang.cmake index 6e9e3fa0f..248b80fb2 100755 --- a/product/rdn2/scp_romfw/Toolchain-ArmClang.cmake +++ b/product/rdn2/scp_romfw/Toolchain-ArmClang.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,7 +9,8 @@ include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +# No Helium, no FPU, No DSP features +set(CMAKE_SYSTEM_ARCH "armv8.1-m.main") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/scp_romfw/Toolchain-Clang.cmake b/product/rdn2/scp_romfw/Toolchain-Clang.cmake index 194548802..e250c254a 100644 --- a/product/rdn2/scp_romfw/Toolchain-Clang.cmake +++ b/product/rdn2/scp_romfw/Toolchain-Clang.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") diff --git a/product/rdn2/scp_romfw/Toolchain-GNU.cmake b/product/rdn2/scp_romfw/Toolchain-GNU.cmake index a4ea7a3f7..29dad4155 100755 --- a/product/rdn2/scp_romfw/Toolchain-GNU.cmake +++ b/product/rdn2/scp_romfw/Toolchain-GNU.cmake @@ -1,13 +1,13 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include_guard() -set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") -- GitLab From 0ff90408ef841250be24eef4aa9849c05b3c1d1c Mon Sep 17 00:00:00 2001 From: Ahmed Gadallah Date: Wed, 9 Aug 2023 15:07:41 +0100 Subject: [PATCH 2/2] [TEST]rdn2: add MPU configuration Do not merge. Signed-off-by: Ahmed Gadallah Change-Id: I16f80de4e02578e4a404618e931a37f483838701 --- product/rdn2/mcp_ramfw/config_armv8m_mpu.c | 51 +++++++++------ product/rdn2/scp_ramfw/config_armv8m_mpu.c | 74 ++++++++++++++-------- 2 files changed, 80 insertions(+), 45 deletions(-) diff --git a/product/rdn2/mcp_ramfw/config_armv8m_mpu.c b/product/rdn2/mcp_ramfw/config_armv8m_mpu.c index fea79fd08..990e4473f 100644 --- a/product/rdn2/mcp_ramfw/config_armv8m_mpu.c +++ b/product/rdn2/mcp_ramfw/config_armv8m_mpu.c @@ -13,41 +13,52 @@ #include -static const uint8_t attributes[2] = { +static const uint8_t attributes[3] = { /* Device memory, non Gathering, non Re-ordering, non Early Write Acknowledgement */ - /* [MPU_ATTR_0] = ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE), - */ + /* Normal memory, non Cacheable */ - /* [MPU_ATTR_1] = ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE), - */ + + /* Normal memory, Inner Cacheable */ + [MPU_ATTR_2] = ARM_MPU_ATTR( + ARM_MPU_ATTR_MEMORY_(0, 1, 1, 1), + ARM_MPU_ATTR_NON_CACHEABLE), }; static const ARM_MPU_Region_t regions[] = { { - /* 0x0000_0000 - 0xFFFF_FFFF */ - /* - .RBAR = ... - .RLAR = ... - */ + /* 0x0000_0000 - 0x007F_FFFF */ + .RBAR = ARM_MPU_RBAR( + MCP_BOOT_ROM_BASE, /* BASE */ + ARM_MPU_SH_INNER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(MCP_ITC_RAM_BASE - 1, MPU_ATTR_1), }, { - /* 0x0080_0000 - 0x00A0_0000 */ - /* - .RBAR = ... - .RLAR = ... - */ + /* 0x0080_0000 - 0x009F_FFFF*/ + .RBAR = ARM_MPU_RBAR( + MCP_ITC_RAM_BASE, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 1, /* RO */ + 0, /* NP */ + 0 /* XN */), + .RLAR = ARM_MPU_RLAR(0x9FFFFF, MPU_ATTR_2), }, { - /* 0x2000_0000 - 2020_0000 */ - /* - .RBAR = ... - .RLAR = ... - */ + /* 0x2000_0000 - 201F_FFFF*/ + .RBAR = ARM_MPU_RBAR( + MCP_DTC_RAM_BASE, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(0x201FFFFF, MPU_ATTR_2), }, }; diff --git a/product/rdn2/scp_ramfw/config_armv8m_mpu.c b/product/rdn2/scp_ramfw/config_armv8m_mpu.c index d4efdb895..bd6d7010b 100644 --- a/product/rdn2/scp_ramfw/config_armv8m_mpu.c +++ b/product/rdn2/scp_ramfw/config_armv8m_mpu.c @@ -15,48 +15,72 @@ #include -static const uint8_t attributes[2] = { +static const uint8_t attributes[3] = { /* Device memory, non Gathering, non Re-ordering, non Early Write Acknowledgement */ - /* [MPU_ATTR_0] = ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE), - */ + /* Normal memory, non Cacheable */ - /* [MPU_ATTR_1] = ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE), - */ + + /* Normal memory, Inner Cacheable */ + [MPU_ATTR_2] = ARM_MPU_ATTR( + ARM_MPU_ATTR_MEMORY_(0, 1, 1, 1), + ARM_MPU_ATTR_NON_CACHEABLE), }; static const ARM_MPU_Region_t regions[] = { { - /* 0x0000_0000 - 0xFFFF_FFFF */ - /* - .RBAR = ... - .RLAR = ... - */ + /* 0x0000_0000 - 0x007F_FFFF */ + .RBAR = ARM_MPU_RBAR( + 0x00000000, /* BASE */ + ARM_MPU_SH_INNER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(0x7fffff, MPU_ATTR_1), }, { - /* 0xA400_0000 - 0xA400_7FFF*/ - /* - .RBAR = ... - .RLAR = ... - */ + /* 0x0080_0000 - 0x00FF_FFFF*/ + .RBAR = ARM_MPU_RBAR( + SCP_ITC_RAM_BASE, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 1, /* RO */ + 0, /* NP */ + 0 /* XN */), + .RLAR = ARM_MPU_RLAR(0xffffff, MPU_ATTR_2), + }, + { + /* 0x2000_0000 - 0x20FF_FFFF */ + .RBAR = ARM_MPU_RBAR( + SCP_DTC_RAM_BASE, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(0xffffff, MPU_ATTR_2), }, { /* 0xA400_0000 - 0xA400_7FFF*/ - /* - .RBAR = ... - .RLAR = ... - */ + .RBAR = ARM_MPU_RBAR( + SCP_TRUSTED_RAM_BASE, /* BASE */ + ARM_MPU_SH_INNER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(0xA4007FFF, MPU_ATTR_2), }, { - /* 0xA600_0000 - 0xA600_7FFF */ - /* - .RBAR = ... - .RLAR = ... - */ + /* 0xA600_0000 - 0xA600_7FFF*/ + .RBAR = ARM_MPU_RBAR( + SCP_NONTRUSTED_RAM_BASE, /* BASE */ + ARM_MPU_SH_INNER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(0xA6007FFF, MPU_ATTR_2), }, }; @@ -67,4 +91,4 @@ const struct fwk_module_config config_armv8m_mpu = { .attributes_count = FWK_ARRAY_SIZE(attributes), .attributes = attributes, }), -}; +}; \ No newline at end of file -- GitLab