diff --git a/product/tc1/include/clock_soc.h b/product/tc1/include/clock_soc.h index ff808e91759dbcddefafe1c748f109f124274a64..c740e6f7fc234a9c7ceb21dc14639345b57fefab 100644 --- a/product/tc1/include/clock_soc.h +++ b/product/tc1/include/clock_soc.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,9 +17,9 @@ * PLL clock indexes. */ enum clock_pll_idx { - CLOCK_PLL_IDX_CPU_KLEIN, - CLOCK_PLL_IDX_CPU_MAKALU, - CLOCK_PLL_IDX_CPU_MAKALU_ELP, + CLOCK_PLL_IDX_CPU_CORTEX_A510, + CLOCK_PLL_IDX_CPU_CORTEX_A715, + CLOCK_PLL_IDX_CPU_CORTEX_X3, CLOCK_PLL_IDX_SYS, CLOCK_PLL_IDX_DPU, CLOCK_PLL_IDX_PIX0, @@ -71,9 +71,9 @@ enum mod_clusclock_source_tc1 { * CSS clock indexes. */ enum clock_css_idx { - CLOCK_CSS_IDX_CPU_GROUP_KLEIN, - CLOCK_CSS_IDX_CPU_GROUP_MAKALU, - CLOCK_CSS_IDX_CPU_GROUP_MAKALU_ELP, + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A510, + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A715, + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X3, CLOCK_CSS_IDX_DPU, CLOCK_CSS_IDX_COUNT }; @@ -82,9 +82,9 @@ enum clock_css_idx { * Clock indexes. */ enum clock_idx { - CLOCK_IDX_CPU_GROUP_KLEIN, - CLOCK_IDX_CPU_GROUP_MAKALU, - CLOCK_IDX_CPU_GROUP_MAKALU_ELP, + CLOCK_IDX_CPU_GROUP_CORTEX_A510, + CLOCK_IDX_CPU_GROUP_CORTEX_A715, + CLOCK_IDX_CPU_GROUP_CORTEX_X3, CLOCK_IDX_DPU, CLOCK_IDX_PIXEL_0, CLOCK_IDX_PIXEL_1, diff --git a/product/tc1/include/tc1_dvfs.h b/product/tc1/include/tc1_dvfs.h index f1e3b50b64fc101b6e2ef3c089339a52d429a034..c75f369b030e5678369f614ad960fbe0f358236a 100644 --- a/product/tc1/include/tc1_dvfs.h +++ b/product/tc1/include/tc1_dvfs.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,9 +12,9 @@ #define TC1_DVFS_H enum dvfs_element_idx { - DVFS_ELEMENT_IDX_KLEIN, - DVFS_ELEMENT_IDX_MAKALU, - DVFS_ELEMENT_IDX_MAKALU_ELP, + DVFS_ELEMENT_IDX_CORTEX_A510, + DVFS_ELEMENT_IDX_CORTEX_A715, + DVFS_ELEMENT_IDX_CORTEX_X3, DVFS_ELEMENT_IDX_COUNT }; diff --git a/product/tc1/include/tc1_mock_psu.h b/product/tc1/include/tc1_mock_psu.h index 42606390b373f0cb3a126a2156903dafc967af2a..ca331608c9034825daeb68155b19ec3dab848972 100644 --- a/product/tc1/include/tc1_mock_psu.h +++ b/product/tc1/include/tc1_mock_psu.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,9 +12,9 @@ #define TC1_MOCK_PSU_H enum mock_psu_id { - MOCK_PSU_ELEMENT_IDX_KLEIN, - MOCK_PSU_ELEMENT_IDX_MAKALU, - MOCK_PSU_ELEMENT_IDX_MAKALU_ELP, + MOCK_PSU_ELEMENT_IDX_CORTEX_A510, + MOCK_PSU_ELEMENT_IDX_CORTEX_A715, + MOCK_PSU_ELEMENT_IDX_CORTEX_X3, MOCK_PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/tc1/include/tc1_psu.h b/product/tc1/include/tc1_psu.h index fc312c98b2f9566b67299c787cf63da25a7f7b69..378e86272f4d6432e41b11048eb909b906abbe16 100644 --- a/product/tc1/include/tc1_psu.h +++ b/product/tc1/include/tc1_psu.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,9 +12,9 @@ #define TC1_PSU_H enum psu_id { - PSU_ELEMENT_IDX_KLEIN, - PSU_ELEMENT_IDX_MAKALU, - PSU_ELEMENT_IDX_MAKALU_ELP, + PSU_ELEMENT_IDX_CORTEX_A510, + PSU_ELEMENT_IDX_CORTEX_A715, + PSU_ELEMENT_IDX_CORTEX_X3, PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/tc1/include/tc1_timer.h b/product/tc1/include/tc1_timer.h index a917a393d4b80d8782392da432757b9f6028faf8..d13a0eaeee87bd5942bfa7b80e989d0d4ef0d9b1 100644 --- a/product/tc1/include/tc1_timer.h +++ b/product/tc1/include/tc1_timer.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,9 +9,9 @@ #define CONFIG_TIMER_H enum config_timer_refclk_sub_element_idx { - TC1_CONFIG_TIMER_DVFS_CPU_KLEIN, - TC1_CONFIG_TIMER_DVFS_CPU_MAKALU, - TC1_CONFIG_TIMER_DVFS_CPU_MAKALU_ELP, + TC1_CONFIG_TIMER_DVFS_CPU_CORTEX_A510, + TC1_CONFIG_TIMER_DVFS_CPU_CORTEX_A715, + TC1_CONFIG_TIMER_DVFS_CPU_CORTEX_X3, TC1_CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT, }; diff --git a/product/tc1/scp_ramfw/config_clock.c b/product/tc1/scp_ramfw/config_clock.c index 89305ff2c014219e78ad82c72020bdaf59a44a03..f95569ce133b5111f491274587d0525588a47f1c 100644 --- a/product/tc1/scp_ramfw/config_clock.c +++ b/product/tc1/scp_ramfw/config_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,37 +20,37 @@ #include static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { - [CLOCK_IDX_CPU_GROUP_KLEIN] = + [CLOCK_IDX_CPU_GROUP_CORTEX_A510] = { - .name = "CPU_GROUP_KLEIN", + .name = "CPU_GROUP_CORTEX_A510", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_KLEIN), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A510), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), }), }, - [CLOCK_IDX_CPU_GROUP_MAKALU] = + [CLOCK_IDX_CPU_GROUP_CORTEX_A715] = { - .name = "CPU_GROUP_MAKALU", + .name = "CPU_GROUP_CORTEX_A715", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_MAKALU), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A715), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), }), }, - [CLOCK_IDX_CPU_GROUP_MAKALU_ELP] = + [CLOCK_IDX_CPU_GROUP_CORTEX_X3] = { - .name = "CPU_GROUP_MAKALU_ELP", + .name = "CPU_GROUP_CORTEX_X3", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_MAKALU_ELP), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X3), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), diff --git a/product/tc1/scp_ramfw/config_css_clock.c b/product/tc1/scp_ramfw/config_css_clock.c index cc97e9ff0ae5679c839d0c30253d1c4aed2a2205..77477ec6ca0f22c844fa0c44b839e8ea0088f04d 100644 --- a/product/tc1/scp_ramfw/config_css_clock.c +++ b/product/tc1/scp_ramfw/config_css_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #include #include -static const struct mod_css_clock_rate rate_table_cpu_group_klein[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_a510[5] = { { /* Super Underdrive */ .rate = 768 * FWK_MHZ, @@ -70,7 +70,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_klein[5] = { }, }; -static const struct mod_css_clock_rate rate_table_cpu_group_makalu[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_a715[5] = { { /* Super Underdrive */ .rate = 946 * FWK_MHZ, @@ -123,7 +123,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_makalu[5] = { }, }; -static const struct mod_css_clock_rate rate_table_cpu_group_makalu_elp[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_x3[5] = { { /* Super Underdrive */ .rate = 1088 * FWK_MHZ, @@ -176,20 +176,20 @@ static const struct mod_css_clock_rate rate_table_cpu_group_makalu_elp[5] = { }, }; -static const fwk_id_t member_table_cpu_group_klein[4] = { +static const fwk_id_t member_table_cpu_group_cortex_a510[4] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3), }; -static const fwk_id_t member_table_cpu_group_makalu[3] = { +static const fwk_id_t member_table_cpu_group_cortex_a715[3] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6), }; -static const fwk_id_t member_table_cpu_group_makalu_elp[1] = { +static const fwk_id_t member_table_cpu_group_cortex_x3[1] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7), }; @@ -199,23 +199,24 @@ static const fwk_id_t member_table_dpu[1] = { static const struct fwk_element css_clock_element_table[ CLOCK_CSS_IDX_COUNT + 1] = { - [CLOCK_CSS_IDX_CPU_GROUP_KLEIN] = + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A510] = { - .name = "CPU_GROUP_KLEIN", + .name = "CPU_GROUP_CORTEX_A510", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL0, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_KLEIN), + CLOCK_PLL_IDX_CPU_CORTEX_A510), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_klein, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_klein), + .member_table = member_table_cpu_group_cortex_a510, + .member_count = + FWK_ARRAY_SIZE(member_table_cpu_group_cortex_a510), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), @@ -223,23 +224,24 @@ static const struct fwk_element css_clock_element_table[ .modulation_supported = true, }), }, - [CLOCK_CSS_IDX_CPU_GROUP_MAKALU] = + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A715] = { - .name = "CPU_GROUP_MAKALU", + .name = "CPU_GROUP_CORTEX_A715", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_makalu, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_makalu), + .rate_table = rate_table_cpu_group_cortex_a715, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a715), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL1, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_MAKALU), + CLOCK_PLL_IDX_CPU_CORTEX_A715), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_makalu, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_makalu), + .member_table = member_table_cpu_group_cortex_a715, + .member_count = + FWK_ARRAY_SIZE(member_table_cpu_group_cortex_a715), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), @@ -247,23 +249,24 @@ static const struct fwk_element css_clock_element_table[ .modulation_supported = true, }), }, - [CLOCK_CSS_IDX_CPU_GROUP_MAKALU_ELP] = + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X3] = { - .name = "CPU_GROUP_MAKALU_ELP", + .name = "CPU_GROUP_CORTEX_X3", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_makalu_elp, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_makalu_elp), + .rate_table = rate_table_cpu_group_cortex_x3, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_x3), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL2, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_MAKALU_ELP), + CLOCK_PLL_IDX_CPU_CORTEX_X3), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_makalu_elp, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_makalu_elp), + .member_table = member_table_cpu_group_cortex_x3, + .member_count = + FWK_ARRAY_SIZE(member_table_cpu_group_cortex_x3), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), diff --git a/product/tc1/scp_ramfw/config_dvfs.c b/product/tc1/scp_ramfw/config_dvfs.c index 3e19c70f16d1c82e1adcaa5b917a40088df8f235..47a502ba058d919b73e7207dc74c270bad13bb95 100644 --- a/product/tc1/scp_ramfw/config_dvfs.c +++ b/product/tc1/scp_ramfw/config_dvfs.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,7 @@ #include #include -static struct mod_dvfs_opp operating_points_klein[6] = { +static struct mod_dvfs_opp operating_points_cortex_a510[6] = { { .level = 768 * 1000000UL, .frequency = 768 * FWK_KHZ, @@ -47,7 +47,7 @@ static struct mod_dvfs_opp operating_points_klein[6] = { { 0 } }; -static struct mod_dvfs_opp operating_points_makalu[6] = { +static struct mod_dvfs_opp operating_points_cortex_a715[6] = { { .level = 946 * 1000000UL, .frequency = 946 * FWK_KHZ, @@ -76,7 +76,7 @@ static struct mod_dvfs_opp operating_points_makalu[6] = { { 0 } }; -static struct mod_dvfs_opp operating_points_makalu_elp[6] = { +static struct mod_dvfs_opp operating_points_cortex_x3[6] = { { .level = 1088 * 1000000UL, .frequency = 1088 * FWK_KHZ, @@ -105,65 +105,69 @@ static struct mod_dvfs_opp operating_points_makalu_elp[6] = { { 0 } }; -static const struct mod_dvfs_domain_config cpu_group_klein = { - .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_KLEIN), - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_KLEIN), +static const struct mod_dvfs_domain_config cpu_group_cortex_a510 = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_CORTEX_A510), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A510), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC1_CONFIG_TIMER_DVFS_CPU_KLEIN), + TC1_CONFIG_TIMER_DVFS_CPU_CORTEX_A510), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_klein, + .opps = operating_points_cortex_a510, }; -static const struct mod_dvfs_domain_config cpu_group_makalu = { - .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_MAKALU), - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_MAKALU), +static const struct mod_dvfs_domain_config cpu_group_cortex_a715 = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_CORTEX_A715), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A715), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC1_CONFIG_TIMER_DVFS_CPU_MAKALU), + TC1_CONFIG_TIMER_DVFS_CPU_CORTEX_A715), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_makalu, + .opps = operating_points_cortex_a715, }; -static const struct mod_dvfs_domain_config cpu_group_makalu_elp = { +static const struct mod_dvfs_domain_config cpu_group_cortex_x3 = { .psu_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_MAKALU_ELP), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_CORTEX_X3), .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_MAKALU_ELP), + CLOCK_IDX_CPU_GROUP_CORTEX_X3), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC1_CONFIG_TIMER_DVFS_CPU_MAKALU_ELP), + TC1_CONFIG_TIMER_DVFS_CPU_CORTEX_X3), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_makalu_elp, + .opps = operating_points_cortex_x3, }; static const struct fwk_element element_table[DVFS_ELEMENT_IDX_COUNT + 1] = { - [DVFS_ELEMENT_IDX_KLEIN] = + [DVFS_ELEMENT_IDX_CORTEX_A510] = { - .name = "CPU_GROUP_KLEIN", - .data = &cpu_group_klein, + .name = "CPU_GROUP_CORTEX_A510", + .data = &cpu_group_cortex_a510, }, - [DVFS_ELEMENT_IDX_MAKALU] = + [DVFS_ELEMENT_IDX_CORTEX_A715] = { - .name = "CPU_GROUP_MAKALU", - .data = &cpu_group_makalu, + .name = "CPU_GROUP_CORTEX_A715", + .data = &cpu_group_cortex_a715, }, - [DVFS_ELEMENT_IDX_MAKALU_ELP] = + [DVFS_ELEMENT_IDX_CORTEX_X3] = { - .name = "CPU_GROUP_MAKALU_ELP", - .data = &cpu_group_makalu_elp, + .name = "CPU_GROUP_CORTEX_X3", + .data = &cpu_group_cortex_x3, }, { 0 }, }; diff --git a/product/tc1/scp_ramfw/config_gtimer.c b/product/tc1/scp_ramfw/config_gtimer.c index 9a66b8cc371e7190342523c99500c1124714080a..23ee19993e24ed09c3f13a35be92707cade2062c 100644 --- a/product/tc1/scp_ramfw/config_gtimer.c +++ b/product/tc1/scp_ramfw/config_gtimer.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ static const struct fwk_element gtimer_dev_table[2] = { .frequency = CLOCK_RATE_REFCLK, .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_KLEIN), + CLOCK_IDX_CPU_GROUP_CORTEX_A510), }), }, [1] = { 0 }, diff --git a/product/tc1/scp_ramfw/config_mock_psu.c b/product/tc1/scp_ramfw/config_mock_psu.c index 6f8da2ac1ce7be74db60e6a308bad26cd23776a8..8ffdde913157e1e6d4915e3d208d3d88e7f9e14d 100644 --- a/product/tc1/scp_ramfw/config_mock_psu.c +++ b/product/tc1/scp_ramfw/config_mock_psu.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,8 @@ #include static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = { - [MOCK_PSU_ELEMENT_IDX_KLEIN] = { - .name = "DVFS_GROUP_KLEIN", + [MOCK_PSU_ELEMENT_IDX_CORTEX_A510] = { + .name = "DVFS_GROUP_CORTEX_A510", .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, @@ -27,8 +27,8 @@ static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = .default_voltage = 550, }, }, - [MOCK_PSU_ELEMENT_IDX_MAKALU] = { - .name = "DVFS_GROUP_MAKALU", + [MOCK_PSU_ELEMENT_IDX_CORTEX_A715] = { + .name = "DVFS_GROUP_CORTEX_A715", .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, @@ -41,8 +41,8 @@ static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = .default_voltage = 550, }, }, - [MOCK_PSU_ELEMENT_IDX_MAKALU_ELP] = { - .name = "DVFS_GROUP_MAKALU_ELP", + [MOCK_PSU_ELEMENT_IDX_CORTEX_X3] = { + .name = "DVFS_GROUP_CORTEX_X3", .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, diff --git a/product/tc1/scp_ramfw/config_pik_clock.c b/product/tc1/scp_ramfw/config_pik_clock.c index 0faa45d755e2257054252b8cac5adf6ec8ec8d89..12974e85c029706c23a403c6766f4892e9b81868 100644 --- a/product/tc1/scp_ramfw/config_pik_clock.c +++ b/product/tc1/scp_ramfw/config_pik_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,7 @@ /* * Rate lookup tables */ -static const struct mod_pik_clock_rate rate_table_cpu_group_klein[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_a510[1] = { { .rate = 1537 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL0, @@ -30,7 +30,7 @@ static const struct mod_pik_clock_rate rate_table_cpu_group_klein[1] = { }, }; -static const struct mod_pik_clock_rate rate_table_cpu_group_makalu[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_a715[1] = { { .rate = 1893 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL1, @@ -39,7 +39,7 @@ static const struct mod_pik_clock_rate rate_table_cpu_group_makalu[1] = { }, }; -static const struct mod_pik_clock_rate rate_table_cpu_group_makalu_elp[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_x3[1] = { { .rate = 2176 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL2, @@ -104,8 +104,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[0].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, [CLOCK_PIK_IDX_CLUS0_CPU1] = { @@ -116,8 +116,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[1].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, [CLOCK_PIK_IDX_CLUS0_CPU2] = { @@ -128,8 +128,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[2].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, [CLOCK_PIK_IDX_CLUS0_CPU3] = { @@ -140,8 +140,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[3].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, [CLOCK_PIK_IDX_CLUS0_CPU4] = { @@ -152,8 +152,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[4].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[4].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[4].MOD, - .rate_table = rate_table_cpu_group_makalu, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_makalu), + .rate_table = rate_table_cpu_group_cortex_a715, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a715), }), }, [CLOCK_PIK_IDX_CLUS0_CPU5] = { @@ -164,8 +164,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[5].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[5].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[5].MOD, - .rate_table = rate_table_cpu_group_makalu, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_makalu), + .rate_table = rate_table_cpu_group_cortex_a715, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a715), }), }, [CLOCK_PIK_IDX_CLUS0_CPU6] = { @@ -176,8 +176,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[6].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[6].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[6].MOD, - .rate_table = rate_table_cpu_group_makalu, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_makalu), + .rate_table = rate_table_cpu_group_cortex_a715, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a715), }), }, [CLOCK_PIK_IDX_CLUS0_CPU7] = { @@ -188,8 +188,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[7].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[7].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[7].MOD, - .rate_table = rate_table_cpu_group_makalu_elp, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_makalu_elp), + .rate_table = rate_table_cpu_group_cortex_x3, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_x3), }), }, [CLOCK_PIK_IDX_GIC] = { diff --git a/product/tc1/scp_ramfw/config_psu.c b/product/tc1/scp_ramfw/config_psu.c index 4c9302349062e1a93810ed7700f9fe442b73b127..5ca7be17877773aee04222e3d7e8bf39e96cd75f 100644 --- a/product/tc1/scp_ramfw/config_psu.c +++ b/product/tc1/scp_ramfw/config_psu.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,32 +16,32 @@ #include static const struct fwk_element element_table[PSU_ELEMENT_IDX_COUNT + 1] = { - [PSU_ELEMENT_IDX_KLEIN] = { - .name = "PSU_GROUP_KLEIN", + [PSU_ELEMENT_IDX_CORTEX_A510] = { + .name = "PSU_GROUP_CORTEX_A510", .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_KLEIN), + MOCK_PSU_ELEMENT_IDX_CORTEX_A510), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, }, - [PSU_ELEMENT_IDX_MAKALU] = { - .name = "PSU_GROUP_MAKALU", + [PSU_ELEMENT_IDX_CORTEX_A715] = { + .name = "PSU_GROUP_CORTEX_A715", .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_MAKALU), + MOCK_PSU_ELEMENT_IDX_CORTEX_A715), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, }, - [PSU_ELEMENT_IDX_MAKALU_ELP] = { - .name = "PSU_GROUP_MAKALU_ELP", + [PSU_ELEMENT_IDX_CORTEX_X3] = { + .name = "PSU_GROUP_CORTEX_X3", .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_MAKALU_ELP), + MOCK_PSU_ELEMENT_IDX_CORTEX_X3), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, diff --git a/product/tc1/scp_ramfw/config_scmi_perf.c b/product/tc1/scp_ramfw/config_scmi_perf.c index 438be2649dc46e9350529f8875f3358823786bec..fe16eb925265eb3c9d99caea4d2fed4c311d04f7 100644 --- a/product/tc1/scp_ramfw/config_scmi_perf.c +++ b/product/tc1/scp_ramfw/config_scmi_perf.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,9 +16,9 @@ static const struct mod_scmi_perf_domain_config domains[DVFS_ELEMENT_IDX_COUNT] = { - [DVFS_ELEMENT_IDX_KLEIN] = {}, - [DVFS_ELEMENT_IDX_MAKALU] = {}, - [DVFS_ELEMENT_IDX_MAKALU_ELP] = {}, + [DVFS_ELEMENT_IDX_CORTEX_A510] = {}, + [DVFS_ELEMENT_IDX_CORTEX_A715] = {}, + [DVFS_ELEMENT_IDX_CORTEX_X3] = {}, }; const struct fwk_module_config config_scmi_perf = { diff --git a/product/tc1/scp_ramfw/config_sds.c b/product/tc1/scp_ramfw/config_sds.c index 0163596e98e2a1602f10a0bed7e025192095300e..9f017b33ba86df9fdcfc774d6742e421986663d3 100644 --- a/product/tc1/scp_ramfw/config_sds.c +++ b/product/tc1/scp_ramfw/config_sds.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,8 +40,9 @@ static_assert( const struct mod_sds_config sds_module_config = { .regions = sds_module_regions, .region_count = TC1_SDS_REGION_COUNT, - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_KLEIN) + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A510) }; static struct fwk_element sds_element_table[3] = { diff --git a/product/tc1/scp_ramfw/config_system_pll.c b/product/tc1/scp_ramfw/config_system_pll.c index 4144e45b5bb9f90df593c71e1dbcef1ce377751d..a11845f8d1c0920fdd275ec37822164d30200f9e 100644 --- a/product/tc1/scp_ramfw/config_system_pll.c +++ b/product/tc1/scp_ramfw/config_system_pll.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,9 +19,9 @@ static const struct fwk_element system_pll_element_table[ CLOCK_PLL_IDX_COUNT + 1] = { - [CLOCK_PLL_IDX_CPU_KLEIN] = + [CLOCK_PLL_IDX_CPU_CORTEX_A510] = { - .name = "CPU_PLL_KLEIN", + .name = "CPU_PLL_CORTEX_A510", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU0, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], @@ -32,9 +32,9 @@ static const struct fwk_element system_pll_element_table[ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, }), }, - [CLOCK_PLL_IDX_CPU_MAKALU] = + [CLOCK_PLL_IDX_CPU_CORTEX_A715] = { - .name = "CPU_PLL_MAKALU", + .name = "CPU_PLL_CORTEX_A715", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU1, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], @@ -45,9 +45,9 @@ static const struct fwk_element system_pll_element_table[ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, }), }, - [CLOCK_PLL_IDX_CPU_MAKALU_ELP] = + [CLOCK_PLL_IDX_CPU_CORTEX_X3] = { - .name = "CPU_PLL_MAKALU_ELP", + .name = "CPU_PLL_CORTEX_X3", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU2, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], diff --git a/product/tc1/scp_romfw/config_clock.c b/product/tc1/scp_romfw/config_clock.c index a1d8a14a7b230d07a9d45cda2821fb122bbbb137..86a41ab8aa9baa5d7c42f6ae6d706e30f0aba40e 100644 --- a/product/tc1/scp_romfw/config_clock.c +++ b/product/tc1/scp_romfw/config_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,13 +21,13 @@ #include static const struct fwk_element clock_dev_desc_table[2] = { - [CLOCK_IDX_CPU_GROUP_KLEIN] = + [CLOCK_IDX_CPU_GROUP_CORTEX_A510] = { - .name = "CPU_GROUP_KLEIN", + .name = "CPU_GROUP_CORTEX_A510", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_KLEIN), + CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A510), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), diff --git a/product/tc1/scp_romfw/config_cmn_booker.c b/product/tc1/scp_romfw/config_cmn_booker.c index c9c6ad7dfb8761e2919d601169509b30fa876ace..db12af47d2df42378523e05d5ca24f90b37a097e 100644 --- a/product/tc1/scp_romfw/config_cmn_booker.c +++ b/product/tc1/scp_romfw/config_cmn_booker.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -116,7 +116,7 @@ const struct fwk_module_config config_cmn_booker = { .mmap_count = FWK_ARRAY_SIZE(mmap), .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_KLEIN), + CLOCK_IDX_CPU_GROUP_CORTEX_A510), .hnf_cal_mode = false, .ports_per_xp = 4, }), diff --git a/product/tc1/scp_romfw/config_css_clock.c b/product/tc1/scp_romfw/config_css_clock.c index aac0c7c9816a3dbc3cb3df14d9683b8a8539fa09..be65c75abfb5a6c13e01880e678697b796e4fe38 100644 --- a/product/tc1/scp_romfw/config_css_clock.c +++ b/product/tc1/scp_romfw/config_css_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #include #include -static const struct mod_css_clock_rate rate_table_cpu_group_klein[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_cortex_a510[5] = { { /* Super Underdrive */ .rate = 768 * FWK_MHZ, @@ -70,7 +70,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_klein[5] = { }, }; -static const fwk_id_t member_table_cpu_group_klein[4] = { +static const fwk_id_t member_table_cpu_group_cortex_a510[4] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), @@ -78,23 +78,24 @@ static const fwk_id_t member_table_cpu_group_klein[4] = { }; static const struct fwk_element css_clock_element_table[2] = { - [CLOCK_CSS_IDX_CPU_GROUP_KLEIN] = + [CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A510] = { - .name = "CPU_GROUP_KLEIN", + .name = "CPU_GROUP_CORTEX_A510", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL0, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_KLEIN), + CLOCK_PLL_IDX_CPU_CORTEX_A510), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_klein, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_klein), + .member_table = member_table_cpu_group_cortex_a510, + .member_count = + FWK_ARRAY_SIZE(member_table_cpu_group_cortex_a510), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), diff --git a/product/tc1/scp_romfw/config_gtimer.c b/product/tc1/scp_romfw/config_gtimer.c index d0f20df8fc1e3cd24e8443dfdb75d71e5d6f310f..b02ba763bb19193e286b7d8f692144adfcd4375c 100644 --- a/product/tc1/scp_romfw/config_gtimer.c +++ b/product/tc1/scp_romfw/config_gtimer.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ static const struct fwk_element gtimer_dev_table[2] = { .frequency = CLOCK_RATE_REFCLK, .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_KLEIN), + CLOCK_IDX_CPU_GROUP_CORTEX_A510), }), }, [1] = { 0 }, diff --git a/product/tc1/scp_romfw/config_pik_clock.c b/product/tc1/scp_romfw/config_pik_clock.c index 7011591c7df8eb5eef0ddd08e2a9ea17f829136c..ab4b4d2952ab89d3332f195985c8ed2995e497c4 100644 --- a/product/tc1/scp_romfw/config_pik_clock.c +++ b/product/tc1/scp_romfw/config_pik_clock.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,7 @@ /* * Rate lookup tables */ -static const struct mod_pik_clock_rate rate_table_cpu_group_klein[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_cortex_a510[1] = { { .rate = 1537 * FWK_MHZ, .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL0, @@ -41,8 +41,9 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[0].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = + FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, [CLOCK_PIK_IDX_CLUS0_CPU1] = @@ -54,8 +55,9 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[1].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = + FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, [CLOCK_PIK_IDX_CLUS0_CPU2] = @@ -67,8 +69,9 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[2].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = + FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, [CLOCK_PIK_IDX_CLUS0_CPU3] = @@ -80,8 +83,9 @@ static const struct fwk_element .control_reg = &CLUSTER_PIK_PTR->CORECLK[3].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), + .rate_table = rate_table_cpu_group_cortex_a510, + .rate_count = + FWK_ARRAY_SIZE(rate_table_cpu_group_cortex_a510), }), }, {0} diff --git a/product/tc1/scp_romfw/config_sds.c b/product/tc1/scp_romfw/config_sds.c index 5c964a93b56239f0f66341f4217f454c95816e32..b0754f37677972840927051809d0ee1e93ea0b63 100644 --- a/product/tc1/scp_romfw/config_sds.c +++ b/product/tc1/scp_romfw/config_sds.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,8 +40,9 @@ static_assert( const struct mod_sds_config sds_module_config = { .regions = sds_module_regions, .region_count = TC1_SDS_REGION_COUNT, - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_KLEIN) + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_CORTEX_A510) }; static struct fwk_element sds_element_table[4] = { diff --git a/product/tc1/scp_romfw/config_system_pll.c b/product/tc1/scp_romfw/config_system_pll.c index 78fb2e5805ba32d772bf2c68715376eb43fd59c8..51faf9b6bcd9bd772200ad5f87c2d3bba211a0d3 100644 --- a/product/tc1/scp_romfw/config_system_pll.c +++ b/product/tc1/scp_romfw/config_system_pll.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,9 +17,9 @@ #include static const struct fwk_element system_pll_element_table[2] = { - [CLOCK_PLL_IDX_CPU_KLEIN] = + [CLOCK_PLL_IDX_CPU_CORTEX_A510] = { - .name = "CPU_PLL_KLEIN", + .name = "CPU_PLL_CORTEX_A510", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU0, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],