From 7dea1d663103add55d21fc04823c0b1ef715c405 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 20 May 2019 12:34:07 +0100 Subject: [PATCH 1/2] n1sdp: return link training status based on CCIX root port This patch return success status for CCIX root port even if link training fails as SCP should continue even if the slot is not connected with any cards. However it should return error code for link training failure on standard PCIe root port as it is connected to on-board PCIe switch. Change-Id: I8a8cc92293efb5b1e1038a1c7cf3a02293eb0546 Signed-off-by: Manoj Kumar --- product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c index 1725e7d0d..fbb435362 100644 --- a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c +++ b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c @@ -161,7 +161,7 @@ static int n1sdp_pcie_setup(struct n1sdp_pcie_dev_ctx *dev_ctx) PCIE_INIT_STAGE_LINK_TRNG); if (status != FWK_SUCCESS) { pcie_ctx.log_api->log(MOD_LOG_GROUP_INFO, "Timeout!\n"); - return status; + return dev_ctx->config->ccix_capable ? FWK_SUCCESS : status; } pcie_ctx.log_api->log(MOD_LOG_GROUP_INFO, "Done\n"); -- GitLab From fb1cd03605fabd6181c73da6b1512e2350726348 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 20 May 2019 13:21:55 +0100 Subject: [PATCH 2/2] n1sdp: modify CCIX root port to start with bus 0 This patch modifies the base addresses for ECAM & IO spaces of CCIX root port such that it starts with bus 0 to be usable with PCIe segment 1. Change-Id: I60417c2ba422565f6c56a2f38e364a1b822f2eb0 Signed-off-by: Manoj Kumar --- product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h b/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h index 047fcc54b..73e668dc4 100644 --- a/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h +++ b/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h @@ -128,7 +128,7 @@ /* * CCIX AXI slave ECAM memory mapping */ -#define CCIX_AXI_ECAM_TYPE0_OFFSET (32 * FWK_MIB) +#define CCIX_AXI_ECAM_TYPE0_OFFSET UINT32_C(0) #define CCIX_AXI_ECAM_TYPE1_OFFSET (CCIX_AXI_ECAM_TYPE0_OFFSET + \ AXI_ECAM_TYPE0_SIZE) @@ -142,7 +142,8 @@ /* CCIX AXI slave MMIO32 & IO offset addresses */ #define CCIX_AXI_MMIO32_OFFSET (CCIX_AXI_ECAM_TYPE1_OFFSET + \ AXI_ECAM_TYPE1_SIZE) -#define CCIX_AXI_IO_OFFSET UINT32_C(0) +#define CCIX_AXI_IO_OFFSET (CCIX_AXI_MMIO32_OFFSET + \ + AXI_MMIO32_SIZE) /* AXI inbound region data */ #define AXI_IB_REGION_BASE UINT64_C(0) -- GitLab