From e41d32cfebe4fb921ee529d19afaf60d2a076621 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 8 Apr 2019 19:25:29 +0530 Subject: [PATCH 1/2] n1sdp: fix cluster and core PIK clock sources Change-Id: I051b9f9751f58f2c796ca2a5fe5d591f6167a407 Signed-off-by: Manoj Kumar --- product/n1sdp/scp_ramfw/config_pik_clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/product/n1sdp/scp_ramfw/config_pik_clock.c b/product/n1sdp/scp_ramfw/config_pik_clock.c index 110d252fd..b97ffd421 100644 --- a/product/n1sdp/scp_ramfw/config_pik_clock.c +++ b/product/n1sdp/scp_ramfw/config_pik_clock.c @@ -157,7 +157,7 @@ static struct mod_pik_clock_rate rate_table_cpu_group_0[] = { static struct mod_pik_clock_rate rate_table_cpu_group_1[] = { { .rate = PIK_CLK_RATE_CLUS1_CPU, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, }, @@ -166,7 +166,7 @@ static struct mod_pik_clock_rate rate_table_cpu_group_1[] = { static struct mod_pik_clock_rate rate_table_clus_0[] = { { .rate = PIK_CLK_RATE_CLUS0, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, }, @@ -175,7 +175,7 @@ static struct mod_pik_clock_rate rate_table_clus_0[] = { static struct mod_pik_clock_rate rate_table_clus_1[] = { { .rate = PIK_CLK_RATE_CLUS1, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, }, -- GitLab From 050fa1304e22cf6b230c5c50de0dcd54211cb3e5 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 8 Apr 2019 20:21:14 +0530 Subject: [PATCH 2/2] n1sdp: increase CPU clock frequency to 2GHz Change-Id: Ied7cfbb7b7cd99ec9eb05a057bcf18585a9631f3 Signed-off-by: Manoj Kumar --- product/n1sdp/scp_ramfw/config_clock.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/product/n1sdp/scp_ramfw/config_clock.h b/product/n1sdp/scp_ramfw/config_clock.h index 61111b867..30c4e6491 100644 --- a/product/n1sdp/scp_ramfw/config_clock.h +++ b/product/n1sdp/scp_ramfw/config_clock.h @@ -28,8 +28,8 @@ #define SCC_CLK_RATE_PCIEAPBCLK (200 * FWK_MHZ) #define SCC_CLK_RATE_CCIXAPBCLK (200 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0_CPU (1600 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1_CPU (1600 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_CPU (2000 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_CPU (2000 * FWK_MHZ) #define PIK_CLK_RATE_CLUS0 (1600 * FWK_MHZ) #define PIK_CLK_RATE_CLUS1 (1600 * FWK_MHZ) #define PIK_CLK_RATE_CLUS0_PPU (300 * FWK_MHZ) @@ -64,8 +64,8 @@ /* * N1SDP PLL clock rates. */ -#define N1SDP_PLL_RATE_CPU_PLL0 (1600 * FWK_MHZ) -#define N1SDP_PLL_RATE_CPU_PLL1 (1600 * FWK_MHZ) +#define N1SDP_PLL_RATE_CPU_PLL0 (2000 * FWK_MHZ) +#define N1SDP_PLL_RATE_CPU_PLL1 (2000 * FWK_MHZ) #define N1SDP_PLL_RATE_CLUSTER_PLL (1600 * FWK_MHZ) #define N1SDP_PLL_RATE_INTERCONNECT_PLL (1600 * FWK_MHZ) #define N1SDP_PLL_RATE_SYSTEM_PLL (2400 * FWK_MHZ) @@ -74,13 +74,13 @@ /* * CSS clock rates. */ -#define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (1600 * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (2000 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE (2700 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_NOMINAL (2800 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_OVERDRIVE (2900 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE (3000 * FWK_MHZ) -#define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (1600 * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (2000 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE (2700 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_NOMINAL (2800 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_OVERDRIVE (2900 * FWK_MHZ) -- GitLab