diff --git a/product/n1sdp/scp_ramfw/config_clock.h b/product/n1sdp/scp_ramfw/config_clock.h index 61111b8678817b4caee4b0159ff12cfa63ee0f48..30c4e649123d5ed9269152f4738a6d0c23a98d01 100644 --- a/product/n1sdp/scp_ramfw/config_clock.h +++ b/product/n1sdp/scp_ramfw/config_clock.h @@ -28,8 +28,8 @@ #define SCC_CLK_RATE_PCIEAPBCLK (200 * FWK_MHZ) #define SCC_CLK_RATE_CCIXAPBCLK (200 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0_CPU (1600 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1_CPU (1600 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_CPU (2000 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_CPU (2000 * FWK_MHZ) #define PIK_CLK_RATE_CLUS0 (1600 * FWK_MHZ) #define PIK_CLK_RATE_CLUS1 (1600 * FWK_MHZ) #define PIK_CLK_RATE_CLUS0_PPU (300 * FWK_MHZ) @@ -64,8 +64,8 @@ /* * N1SDP PLL clock rates. */ -#define N1SDP_PLL_RATE_CPU_PLL0 (1600 * FWK_MHZ) -#define N1SDP_PLL_RATE_CPU_PLL1 (1600 * FWK_MHZ) +#define N1SDP_PLL_RATE_CPU_PLL0 (2000 * FWK_MHZ) +#define N1SDP_PLL_RATE_CPU_PLL1 (2000 * FWK_MHZ) #define N1SDP_PLL_RATE_CLUSTER_PLL (1600 * FWK_MHZ) #define N1SDP_PLL_RATE_INTERCONNECT_PLL (1600 * FWK_MHZ) #define N1SDP_PLL_RATE_SYSTEM_PLL (2400 * FWK_MHZ) @@ -74,13 +74,13 @@ /* * CSS clock rates. */ -#define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (1600 * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (2000 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE (2700 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_NOMINAL (2800 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_OVERDRIVE (2900 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE (3000 * FWK_MHZ) -#define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (1600 * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (2000 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE (2700 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_NOMINAL (2800 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_OVERDRIVE (2900 * FWK_MHZ) diff --git a/product/n1sdp/scp_ramfw/config_pik_clock.c b/product/n1sdp/scp_ramfw/config_pik_clock.c index 110d252fd62563627f3e383f9469610aac49b353..b97ffd421df940a923e0f30676b3695f892f297d 100644 --- a/product/n1sdp/scp_ramfw/config_pik_clock.c +++ b/product/n1sdp/scp_ramfw/config_pik_clock.c @@ -157,7 +157,7 @@ static struct mod_pik_clock_rate rate_table_cpu_group_0[] = { static struct mod_pik_clock_rate rate_table_cpu_group_1[] = { { .rate = PIK_CLK_RATE_CLUS1_CPU, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, }, @@ -166,7 +166,7 @@ static struct mod_pik_clock_rate rate_table_cpu_group_1[] = { static struct mod_pik_clock_rate rate_table_clus_0[] = { { .rate = PIK_CLK_RATE_CLUS0, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, }, @@ -175,7 +175,7 @@ static struct mod_pik_clock_rate rate_table_clus_0[] = { static struct mod_pik_clock_rate rate_table_clus_1[] = { { .rate = PIK_CLK_RATE_CLUS1, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, },