From 232e5f945024bf4d828b0b8e4f12bdefdc3687e1 Mon Sep 17 00:00:00 2001 From: Ahmed Gadallah Date: Thu, 3 Mar 2022 14:17:31 +0000 Subject: [PATCH 1/6] cmsis: update CMSIS pack to 5.8.0 Update to CMSIS pack 5.8.0 is done as it supports cortex-m55 where the current version 5.2.0 doesn't. Additionally __VTOR_PRESENT macro is defined for all platforms that use cortex-m3/7 as it is required by the new cmsis pack. Signed-off-by: Ahmed Gadallah Change-Id: Id7f4119c04b04bbedc0c5e4b5a5b9fa8832bc357 --- contrib/cmsis/git | 2 +- product/juno/include/fmw_cmsis.h | 11 ++++++----- product/morello/include/fmw_cmsis_mcp.h | 3 ++- product/morello/include/fmw_cmsis_scp.h | 3 ++- product/n1sdp/include/fmw_cmsis_mcp.h | 3 ++- product/n1sdp/include/fmw_cmsis_scp.h | 3 ++- product/rdn1e1/include/fmw_cmsis_mcp.h | 3 ++- product/rdn1e1/include/fmw_cmsis_scp.h | 3 ++- product/rdn2/include/fmw_cmsis.h | 3 ++- product/rdv1/include/fmw_cmsis.h | 3 ++- product/rdv1mc/include/fmw_cmsis.h | 3 ++- product/sgi575/include/fmw_cmsis_mcp.h | 3 ++- product/sgi575/include/fmw_cmsis_scp.h | 3 ++- product/sgm775/include/fmw_cmsis.h | 11 ++++++----- product/sgm776/include/fmw_cmsis.h | 11 ++++++----- product/synquacer/include/fmw_cmsis.h | 11 ++++++----- product/tc0/include/fmw_cmsis.h | 3 ++- product/tc1/include/fmw_cmsis.h | 3 ++- 18 files changed, 51 insertions(+), 34 deletions(-) diff --git a/contrib/cmsis/git b/contrib/cmsis/git index 80cc44bba..13b9f72f2 160000 --- a/contrib/cmsis/git +++ b/contrib/cmsis/git @@ -1 +1 @@ -Subproject commit 80cc44bba16cb4c8f495b7aa9709d41ac50e9529 +Subproject commit 13b9f72f212688d2306d0d085d87cbb4bf9e5d3f diff --git a/product/juno/include/fmw_cmsis.h b/product/juno/include/fmw_cmsis.h index 94f831858..2f85d6b21 100644 --- a/product/juno/include/fmw_cmsis.h +++ b/product/juno/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,11 @@ #include #define __CHECK_DEVICE_DEFINES -#define __CM3_REV 0x0201 -#define __MPU_PRESENT 1 -#define __NVIC_PRIO_BITS 3 -#define __Vendor_SysTickConfig 0 +#define __CM3_REV 0x0201U +#define __MPU_PRESENT 1U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ diff --git a/product/morello/include/fmw_cmsis_mcp.h b/product/morello/include/fmw_cmsis_mcp.h index 469d5456c..18f775a19 100644 --- a/product/morello/include/fmw_cmsis_mcp.h +++ b/product/morello/include/fmw_cmsis_mcp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U #define MCP_WDOG_IRQ FWK_INTERRUPT_NMI /* MCP Watchdog (SP805) */ diff --git a/product/morello/include/fmw_cmsis_scp.h b/product/morello/include/fmw_cmsis_scp.h index abd1cd8a0..61dd3eb4e 100644 --- a/product/morello/include/fmw_cmsis_scp.h +++ b/product/morello/include/fmw_cmsis_scp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U #define SCP_WDOG_IRQ FWK_INTERRUPT_NMI /* SCP Watchdog (SP805) */ diff --git a/product/n1sdp/include/fmw_cmsis_mcp.h b/product/n1sdp/include/fmw_cmsis_mcp.h index acceb6b01..6b32a332a 100644 --- a/product/n1sdp/include/fmw_cmsis_mcp.h +++ b/product/n1sdp/include/fmw_cmsis_mcp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ typedef enum IRQn { diff --git a/product/n1sdp/include/fmw_cmsis_scp.h b/product/n1sdp/include/fmw_cmsis_scp.h index 31185689b..72c79530b 100644 --- a/product/n1sdp/include/fmw_cmsis_scp.h +++ b/product/n1sdp/include/fmw_cmsis_scp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ diff --git a/product/rdn1e1/include/fmw_cmsis_mcp.h b/product/rdn1e1/include/fmw_cmsis_mcp.h index 06aa78681..5e2c0e358 100644 --- a/product/rdn1e1/include/fmw_cmsis_mcp.h +++ b/product/rdn1e1/include/fmw_cmsis_mcp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U typedef enum IRQn { Reset_IRQn = -15, diff --git a/product/rdn1e1/include/fmw_cmsis_scp.h b/product/rdn1e1/include/fmw_cmsis_scp.h index c331225d0..90328a968 100644 --- a/product/rdn1e1/include/fmw_cmsis_scp.h +++ b/product/rdn1e1/include/fmw_cmsis_scp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ diff --git a/product/rdn2/include/fmw_cmsis.h b/product/rdn2/include/fmw_cmsis.h index ee386ca27..6f8f0ce5f 100644 --- a/product/rdn2/include/fmw_cmsis.h +++ b/product/rdn2/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ diff --git a/product/rdv1/include/fmw_cmsis.h b/product/rdv1/include/fmw_cmsis.h index 90168af3b..fe12b3d0c 100644 --- a/product/rdv1/include/fmw_cmsis.h +++ b/product/rdv1/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ typedef enum IRQn { diff --git a/product/rdv1mc/include/fmw_cmsis.h b/product/rdv1mc/include/fmw_cmsis.h index ee386ca27..6f8f0ce5f 100644 --- a/product/rdv1mc/include/fmw_cmsis.h +++ b/product/rdv1mc/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ diff --git a/product/sgi575/include/fmw_cmsis_mcp.h b/product/sgi575/include/fmw_cmsis_mcp.h index cf89f6398..2d212a522 100644 --- a/product/sgi575/include/fmw_cmsis_mcp.h +++ b/product/sgi575/include/fmw_cmsis_mcp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U typedef enum IRQn { Reset_IRQn = -15, diff --git a/product/sgi575/include/fmw_cmsis_scp.h b/product/sgi575/include/fmw_cmsis_scp.h index 180d84307..fc9f3a304 100644 --- a/product/sgi575/include/fmw_cmsis_scp.h +++ b/product/sgi575/include/fmw_cmsis_scp.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U typedef enum IRQn { Reset_IRQn = -15, diff --git a/product/sgm775/include/fmw_cmsis.h b/product/sgm775/include/fmw_cmsis.h index 934203779..6e0fc77b0 100644 --- a/product/sgm775/include/fmw_cmsis.h +++ b/product/sgm775/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,11 @@ #include #define __CHECK_DEVICE_DEFINES -#define __CM3_REV 0x0201 -#define __MPU_PRESENT 1 -#define __NVIC_PRIO_BITS 3 -#define __Vendor_SysTickConfig 0 +#define __CM3_REV 0x0201U +#define __MPU_PRESENT 1U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ diff --git a/product/sgm776/include/fmw_cmsis.h b/product/sgm776/include/fmw_cmsis.h index 4db3fda90..62f635b1c 100644 --- a/product/sgm776/include/fmw_cmsis.h +++ b/product/sgm776/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,11 @@ #include #define __CHECK_DEVICE_DEFINES -#define __CM3_REV 0x0201 -#define __MPU_PRESENT 1 -#define __NVIC_PRIO_BITS 3 -#define __Vendor_SysTickConfig 0 +#define __CM3_REV 0x0201U +#define __MPU_PRESENT 1U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ typedef enum IRQn { diff --git a/product/synquacer/include/fmw_cmsis.h b/product/synquacer/include/fmw_cmsis.h index 4ae0dfb30..f530295c1 100644 --- a/product/synquacer/include/fmw_cmsis.h +++ b/product/synquacer/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,11 @@ #include #define __CHECK_DEVICE_DEFINES -#define __CM3_REV 0x0201 -#define __MPU_PRESENT 1 -#define __NVIC_PRIO_BITS 3 -#define __Vendor_SysTickConfig 0 +#define __CM3_REV 0x0201U +#define __MPU_PRESENT 1U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; diff --git a/product/tc0/include/fmw_cmsis.h b/product/tc0/include/fmw_cmsis.h index c7add15cb..8c4a13200 100644 --- a/product/tc0/include/fmw_cmsis.h +++ b/product/tc0/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ diff --git a/product/tc1/include/fmw_cmsis.h b/product/tc1/include/fmw_cmsis.h index a1925c739..f2f78fb60 100644 --- a/product/tc1/include/fmw_cmsis.h +++ b/product/tc1/include/fmw_cmsis.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ #define __DTCM_PRESENT 0U #define __NVIC_PRIO_BITS 3U #define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ -- GitLab From c1c3fc4bc401fc459efeff266068acad730aba2f Mon Sep 17 00:00:00 2001 From: Ahmed Gadallah Date: Fri, 20 Aug 2021 06:21:05 +0100 Subject: [PATCH 2/6] arch: Add ARMv8-M support ARMv7-M support arch directory is modified to support both ARMv7-M and ARMv8-M. The modified directory is renamed from armv7-m to arm-m. This in turn affects the SCP_ARCHITECTURE cmake flag which was previuosly set to armv7-m for armv7m targets and now would be set by arm-m. The ARMv8-M support does not include the security extension. This ARMv8-M support includes support for ARMv8-M Mainline and ARMv8.1-M Mainline. ARMv8.1-M Mainline is supported by GCC ver 10.1 onwards, the latest version can be found here: https://developer.arm.com/tools-and-software/open-source-software /developer-tools/gnu-toolchain/gnu-rm/downloads in addition to LLVM ver 13.0.0 onwards and ArmClang ver 6.14 onwards. Signed-off-by: Ahmed Gadallah Change-Id: I7bdac6c80efbb56a0874daad794111376866a46c --- .armv8m.cppcheck.cfg | 6 ++++ CMakeLists.txt | 8 +++-- arch/CMakeLists.txt | 4 +-- arch/arm/arm-m/Architecture.cmake | 9 +++++ arch/arm/{armv7-m => arm-m}/CMakeLists.txt | 35 ++++++++++++------- .../include/arch_exceptions.h | 2 +- .../{armv7-m => arm-m}/include/arch_helpers.h | 0 .../{armv7-m => arm-m}/include/arch_nvic.h | 2 +- .../{armv7-m => arm-m}/include/arch_scatter.h | 8 ++--- arch/arm/{armv7-m => arm-m}/src/arch.ld.S | 2 +- .../arm/{armv7-m => arm-m}/src/arch.scatter.S | 2 +- .../{armv7-m => arm-m}/src/arch_exceptions.c | 12 ++++--- .../{armv7-m => arm-m}/src/arch_handlers.c | 4 +-- arch/arm/{armv7-m => arm-m}/src/arch_main.c | 9 +++-- arch/arm/{armv7-m => arm-m}/src/arch_nvic.c | 0 arch/arm/armv7-m/Architecture.cmake | 9 ----- arch/arm/armv7-m/arch.mk | 13 ------- cmake/Toolchain/Clang-Baremetal.cmake | 10 ++++-- cmake/Toolchain/GNU-Baremetal.cmake | 4 +-- product/juno/scp_ramfw/Firmware.cmake | 4 +-- product/juno/scp_romfw/Firmware.cmake | 4 +-- product/juno/scp_romfw_bypass/Firmware.cmake | 4 +-- product/morello/mcp_ramfw_fvp/Firmware.cmake | 4 +-- product/morello/mcp_ramfw_soc/Firmware.cmake | 4 +-- product/morello/mcp_romfw/Firmware.cmake | 4 +-- product/morello/scp_ramfw_fvp/Firmware.cmake | 2 +- product/morello/scp_ramfw_soc/Firmware.cmake | 2 +- product/morello/scp_romfw/Firmware.cmake | 4 +-- product/n1sdp/mcp_ramfw/Firmware.cmake | 4 +-- product/n1sdp/mcp_romfw/Firmware.cmake | 4 +-- product/n1sdp/scp_ramfw/Firmware.cmake | 4 +-- product/n1sdp/scp_romfw/Firmware.cmake | 4 +-- product/rdn1e1/mcp_ramfw/Firmware.cmake | 2 +- product/rdn1e1/mcp_romfw/Firmware.cmake | 2 +- product/rdn1e1/scp_ramfw/Firmware.cmake | 4 +-- product/rdn1e1/scp_romfw/Firmware.cmake | 4 +-- product/rdn2/mcp_ramfw/Firmware.cmake | 2 +- product/rdn2/mcp_romfw/Firmware.cmake | 4 +-- product/rdn2/scp_ramfw/Firmware.cmake | 4 +-- product/rdn2/scp_romfw/Firmware.cmake | 4 +-- product/rdv1/mcp_ramfw/Firmware.cmake | 2 +- product/rdv1/mcp_romfw/Firmware.cmake | 2 +- product/rdv1/scp_ramfw/Firmware.cmake | 4 +-- product/rdv1/scp_romfw/Firmware.cmake | 2 +- product/rdv1mc/mcp_ramfw/Firmware.cmake | 2 +- product/rdv1mc/mcp_romfw/Firmware.cmake | 4 +-- product/rdv1mc/scp_ramfw/Firmware.cmake | 4 +-- product/rdv1mc/scp_romfw/Firmware.cmake | 4 +-- product/sgi575/mcp_ramfw/Firmware.cmake | 2 +- product/sgi575/mcp_romfw/Firmware.cmake | 4 +-- product/sgi575/scp_ramfw/Firmware.cmake | 4 +-- product/sgi575/scp_romfw/Firmware.cmake | 4 +-- product/sgm775/scp_ramfw/Firmware.cmake | 4 +-- product/sgm775/scp_romfw/Firmware.cmake | 4 +-- product/sgm776/scp_ramfw/Firmware.cmake | 4 +-- product/sgm776/scp_romfw/Firmware.cmake | 4 +-- product/synquacer/scp_ramfw/Firmware.cmake | 2 +- product/synquacer/scp_romfw/Firmware.cmake | 4 +-- product/tc0/scp_ramfw/Firmware.cmake | 2 +- product/tc0/scp_romfw/Firmware.cmake | 2 +- product/tc1/scp_ramfw/Firmware.cmake | 4 +-- product/tc1/scp_romfw/Firmware.cmake | 2 +- 62 files changed, 151 insertions(+), 132 deletions(-) create mode 100644 .armv8m.cppcheck.cfg create mode 100644 arch/arm/arm-m/Architecture.cmake rename arch/arm/{armv7-m => arm-m}/CMakeLists.txt (72%) rename arch/arm/{armv7-m => arm-m}/include/arch_exceptions.h (90%) rename arch/arm/{armv7-m => arm-m}/include/arch_helpers.h (100%) rename arch/arm/{armv7-m => arm-m}/include/arch_nvic.h (89%) rename arch/arm/{armv7-m => arm-m}/include/arch_scatter.h (90%) rename arch/arm/{armv7-m => arm-m}/src/arch.ld.S (98%) rename arch/arm/{armv7-m => arm-m}/src/arch.scatter.S (96%) rename arch/arm/{armv7-m => arm-m}/src/arch_exceptions.c (90%) rename arch/arm/{armv7-m => arm-m}/src/arch_handlers.c (91%) rename arch/arm/{armv7-m => arm-m}/src/arch_main.c (84%) rename arch/arm/{armv7-m => arm-m}/src/arch_nvic.c (100%) delete mode 100644 arch/arm/armv7-m/Architecture.cmake delete mode 100644 arch/arm/armv7-m/arch.mk diff --git a/.armv8m.cppcheck.cfg b/.armv8m.cppcheck.cfg new file mode 100644 index 000000000..66bd6a6b9 --- /dev/null +++ b/.armv8m.cppcheck.cfg @@ -0,0 +1,6 @@ + + + + + + diff --git a/CMakeLists.txt b/CMakeLists.txt index 4f30068f0..fcded28d1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -181,8 +181,12 @@ if(NOT DISABLE_CPPCHECK) list(APPEND CMAKE_C_CPPCHECK "--enable=all") list(APPEND CMAKE_C_CPPCHECK "--error-exitcode=1") - if(SCP_ARCHITECTURE STREQUAL "armv7-m") - list(APPEND CMAKE_C_CPPCHECK "--library=${CMAKE_CURRENT_SOURCE_DIR}/.armv7m.cppcheck.cfg") + if(SCP_ARCHITECTURE STREQUAL "arm-m") + if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(33|55)") + list(APPEND CMAKE_C_CPPCHECK "--library=${CMAKE_CURRENT_SOURCE_DIR}/.armv8m.cppcheck.cfg") + elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(3|7)") + list(APPEND CMAKE_C_CPPCHECK "--library=${CMAKE_CURRENT_SOURCE_DIR}/.armv7m.cppcheck.cfg") + endif() endif() if(CMAKE_C_COMPILER_ID STREQUAL "ARMClang") diff --git a/arch/CMakeLists.txt b/arch/CMakeLists.txt index 88450ac2f..13a846dfc 100644 --- a/arch/CMakeLists.txt +++ b/arch/CMakeLists.txt @@ -1,11 +1,11 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # -list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/arm/armv7-m") +list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/arm/arm-m") list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/arm/armv8-a") list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/none/host") diff --git a/arch/arm/arm-m/Architecture.cmake b/arch/arm/arm-m/Architecture.cmake new file mode 100644 index 000000000..114b90749 --- /dev/null +++ b/arch/arm/arm-m/Architecture.cmake @@ -0,0 +1,9 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_ARCHITECTURE "arm-m") +set(SCP_ARCHITECTURE_TARGET "arch-arm-m") diff --git a/arch/arm/armv7-m/CMakeLists.txt b/arch/arm/arm-m/CMakeLists.txt similarity index 72% rename from arch/arm/armv7-m/CMakeLists.txt rename to arch/arm/arm-m/CMakeLists.txt index d5be87b5e..b72127fb2 100644 --- a/arch/arm/armv7-m/CMakeLists.txt +++ b/arch/arm/arm-m/CMakeLists.txt @@ -5,22 +5,33 @@ # SPDX-License-Identifier: BSD-3-Clause # -add_library(arch-armv7m) +add_library(arch-arm-m) -target_include_directories(arch-armv7m +# +# Determine which architecture shall be supported according to +# the used CPU +# + +if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(33|55)") + target_compile_definitions(arch-arm-m PUBLIC "ARMV8M") +else() + target_compile_definitions(arch-arm-m PUBLIC "ARMV7M") +endif() + +target_include_directories(arch-arm-m PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") # cmake-lint: disable=E1122 target_sources( - arch-armv7m + arch-arm-m PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_exceptions.c" "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_handlers.c" "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_main.c" "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_nvic.c" PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/../src/arch_mm.c") -target_link_libraries(arch-armv7m PUBLIC cmsis::core-m) +target_link_libraries(arch-arm-m PUBLIC cmsis::core-m) # @@ -36,15 +47,15 @@ cmake_dependent_option( if(SCP_ENABLE_NEWLIB_NANO) if(CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(arch-armv7m PUBLIC "--specs=nano.specs") + target_link_options(arch-arm-m PUBLIC "--specs=nano.specs") elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_libraries(arch-armv7m PUBLIC c_nano) + target_link_libraries(arch-arm-m PUBLIC c_nano) endif() else() if(CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(arch-armv7m PUBLIC "--specs=nosys.specs") + target_link_options(arch-arm-m PUBLIC "--specs=nosys.specs") elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_libraries(arch-armv7m PUBLIC c) + target_link_libraries(arch-arm-m PUBLIC c) endif() endif() @@ -53,15 +64,15 @@ endif() # functions that the standard library relies on. # -target_link_options(arch-armv7m PUBLIC "LINKER:--undefined=arch_exceptions") +target_link_options(arch-arm-m PUBLIC "LINKER:--undefined=arch_exceptions") if(CMAKE_C_COMPILER_ID STREQUAL "ARMClang") - target_link_options(arch-armv7m + target_link_options(arch-arm-m PUBLIC "LINKER:--entry=arch_exception_reset") endif() if(SCP_HAVE_NEWLIB) - target_link_options(arch-armv7m PUBLIC "LINKER:--undefined=posix_memalign" + target_link_options(arch-arm-m PUBLIC "LINKER:--undefined=posix_memalign" "LINKER:--undefined=_sbrk") endif() @@ -89,4 +100,4 @@ else() set(scp_lds "${CMAKE_CURRENT_SOURCE_DIR}/src/arch.ld.S") endif() -scp_target_linker_script(arch-armv7m "${scp_lds}") +scp_target_linker_script(arch-arm-m "${scp_lds}") diff --git a/arch/arm/armv7-m/include/arch_exceptions.h b/arch/arm/arm-m/include/arch_exceptions.h similarity index 90% rename from arch/arm/armv7-m/include/arch_exceptions.h rename to arch/arm/arm-m/include/arch_exceptions.h index e643fe0d1..fe1244ee2 100644 --- a/arch/arm/armv7-m/include/arch_exceptions.h +++ b/arch/arm/arm-m/include/arch_exceptions.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/arch/arm/armv7-m/include/arch_helpers.h b/arch/arm/arm-m/include/arch_helpers.h similarity index 100% rename from arch/arm/armv7-m/include/arch_helpers.h rename to arch/arm/arm-m/include/arch_helpers.h diff --git a/arch/arm/armv7-m/include/arch_nvic.h b/arch/arm/arm-m/include/arch_nvic.h similarity index 89% rename from arch/arm/armv7-m/include/arch_nvic.h rename to arch/arm/arm-m/include/arch_nvic.h index 6bc6b5d7f..cfc4bbaa2 100644 --- a/arch/arm/armv7-m/include/arch_nvic.h +++ b/arch/arm/arm-m/include/arch_nvic.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/arch/arm/armv7-m/include/arch_scatter.h b/arch/arm/arm-m/include/arch_scatter.h similarity index 90% rename from arch/arm/armv7-m/include/arch_scatter.h rename to arch/arm/arm-m/include/arch_scatter.h index bcdfd7e0a..0844f6968 100644 --- a/arch/arm/armv7-m/include/arch_scatter.h +++ b/arch/arm/arm-m/include/arch_scatter.h @@ -1,13 +1,13 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * * Description: * Common linker script configuration options. * - * There are three supported memory layouts for the ARMv7-M architecture: + * There are three supported memory layouts for the ARM-M architectures: * * Layout 1 - Single region: * This layout uses a single read/write/execute memory region for all data. @@ -34,8 +34,8 @@ #ifndef ARCH_SCATTER_H #define ARCH_SCATTER_H -#define ARCH_MEM_MODE_SINGLE_REGION 0 -#define ARCH_MEM_MODE_DUAL_REGION_RELOCATION 1 +#define ARCH_MEM_MODE_SINGLE_REGION 0 +#define ARCH_MEM_MODE_DUAL_REGION_RELOCATION 1 #define ARCH_MEM_MODE_DUAL_REGION_NO_RELOCATION 2 #include diff --git a/arch/arm/armv7-m/src/arch.ld.S b/arch/arm/arm-m/src/arch.ld.S similarity index 98% rename from arch/arm/armv7-m/src/arch.ld.S rename to arch/arm/arm-m/src/arch.ld.S index 5a349ac3b..3b15e36e2 100644 --- a/arch/arm/armv7-m/src/arch.ld.S +++ b/arch/arm/arm-m/src/arch.ld.S @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/arch/arm/armv7-m/src/arch.scatter.S b/arch/arm/arm-m/src/arch.scatter.S similarity index 96% rename from arch/arm/armv7-m/src/arch.scatter.S rename to arch/arm/arm-m/src/arch.scatter.S index c89254df8..c87efe3f8 100644 --- a/arch/arm/armv7-m/src/arch.scatter.S +++ b/arch/arm/arm-m/src/arch.scatter.S @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/arch/arm/armv7-m/src/arch_exceptions.c b/arch/arm/arm-m/src/arch_exceptions.c similarity index 90% rename from arch/arm/armv7-m/src/arch_exceptions.c rename to arch/arm/arm-m/src/arch_exceptions.c index d990c6a5d..e1472f330 100644 --- a/arch/arm/armv7-m/src/arch_exceptions.c +++ b/arch/arm/arm-m/src/arch_exceptions.c @@ -5,12 +5,12 @@ * SPDX-License-Identifier: BSD-3-Clause * * Description: - * ARMv7-M exception handlers. + * ARM-M exception handlers. */ -#include +#include "arch_exceptions.h" -#include +#include #include @@ -49,7 +49,7 @@ extern char __stackheap_end__; #endif /* - * Set up the exception table. The structure below is is added to the + * Set up the exception table. The structure below is added to the * .exceptions section which will be explicitly placed at the beginning of the * binary by the linker script. */ @@ -72,6 +72,10 @@ const struct { (uintptr_t)(arch_exception_invalid), [NVIC_USER_IRQ_OFFSET + UsageFault_IRQn - 1] = (uintptr_t)(arch_exception_invalid), +#ifdef ARMV8M + [NVIC_USER_IRQ_OFFSET + SecureFault_IRQn - 1] = + (uintptr_t)(arch_exception_invalid), +#endif [NVIC_USER_IRQ_OFFSET + DebugMonitor_IRQn - 1] = (uintptr_t)(arch_exception_invalid), diff --git a/arch/arm/armv7-m/src/arch_handlers.c b/arch/arm/arm-m/src/arch_handlers.c similarity index 91% rename from arch/arm/armv7-m/src/arch_handlers.c rename to arch/arm/arm-m/src/arch_handlers.c index 397954989..555358fe3 100644 --- a/arch/arm/armv7-m/src/arch_handlers.c +++ b/arch/arm/arm-m/src/arch_handlers.c @@ -1,11 +1,11 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * * Description: - * ARMv7-M exception handlers. + * ARM-M exception handlers. */ #include diff --git a/arch/arm/armv7-m/src/arch_main.c b/arch/arm/arm-m/src/arch_main.c similarity index 84% rename from arch/arm/armv7-m/src/arch_main.c rename to arch/arm/arm-m/src/arch_main.c index 128d7b2d6..f77c20cd2 100644 --- a/arch/arm/armv7-m/src/arch_main.c +++ b/arch/arm/arm-m/src/arch_main.c @@ -45,18 +45,21 @@ static void arch_init_ccr(void) * Set up the Configuration Control Register (CCR) in the System Control * Block (1) by setting the following flag bits: * - * DIV_0_TRP [4]: Enable trapping on division by zero. + * DIV_0_TRP [4]: Enable trapping on division by zero. (1)(2) * STKALIGN [9]: Enable automatic DWORD stack-alignment on exception - * entry (2). + * entry (3). * * All other bits are left in their default state. * * (1) ARM® v7-M Architecture Reference Manual, section B3.2.8. - * (2) ARM® v7-M Architecture Reference Manual, section B1.5.7. + * (2) Arm® v8-M Architecture Reference Manual, section D1.2.9. + * (3) ARM® v7-M Architecture Reference Manual, section B1.5.7. */ SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; +#ifdef ARMV7M SCB->CCR |= SCB_CCR_STKALIGN_Msk; +#endif } int main(void) diff --git a/arch/arm/armv7-m/src/arch_nvic.c b/arch/arm/arm-m/src/arch_nvic.c similarity index 100% rename from arch/arm/armv7-m/src/arch_nvic.c rename to arch/arm/arm-m/src/arch_nvic.c diff --git a/arch/arm/armv7-m/Architecture.cmake b/arch/arm/armv7-m/Architecture.cmake deleted file mode 100644 index e39a6fb36..000000000 --- a/arch/arm/armv7-m/Architecture.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -set(SCP_ARCHITECTURE "armv7-m") -set(SCP_ARCHITECTURE_TARGET "arch-armv7m") diff --git a/arch/arm/armv7-m/arch.mk b/arch/arm/armv7-m/arch.mk deleted file mode 100644 index 610464a98..000000000 --- a/arch/arm/armv7-m/arch.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_exceptions.c -BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_handlers.c -BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_main.c -BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_nvic.c - -BS_LIB_SOURCES_$(BS_ARCH_ARCH) := $(addprefix $(ARCH_DIR)/$(BS_ARCH_VENDOR)/$(BS_ARCH_ARCH)/src/,$(BS_LIB_SOURCES_$(BS_ARCH_ARCH))) diff --git a/cmake/Toolchain/Clang-Baremetal.cmake b/cmake/Toolchain/Clang-Baremetal.cmake index 1ab74e46a..66b9cf0f4 100644 --- a/cmake/Toolchain/Clang-Baremetal.cmake +++ b/cmake/Toolchain/Clang-Baremetal.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -41,13 +41,17 @@ foreach(language IN ITEMS ASM C CXX) "-I\"${LLVM_SYSROOT_PATH}/include\" ") endif() - if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m[37]") + if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(3|7|33|55)") set(BUILD_TARGET "-mcpu=${CMAKE_SYSTEM_PROCESSOR} -mthumb ") string(APPEND CMAKE_${language}_FLAGS_INIT "${BUILD_TARGET}") if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m7") set(CLANG_BUILTINS_ARCH "armv7em") - else() + elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m33") + set(CLANG_BUILTINS_ARCH "armv8m.main") + elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m3") set(CLANG_BUILTINS_ARCH "armv7m") + elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m55") + set(CLANG_BUILTINS_ARCH "armv8.1m.main") endif() endif() diff --git a/cmake/Toolchain/GNU-Baremetal.cmake b/cmake/Toolchain/GNU-Baremetal.cmake index 457782c1f..3fff1cff8 100644 --- a/cmake/Toolchain/GNU-Baremetal.cmake +++ b/cmake/Toolchain/GNU-Baremetal.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,7 +19,7 @@ foreach(language IN ITEMS ASM C CXX) "-mstrict-align -fno-builtin -DAARCH64 -D__ASSEMBLY__ ") endif() - if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m[37]") + if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(3|7|33|55)") string(APPEND CMAKE_${language}_FLAGS_INIT "-mthumb ") string(APPEND CMAKE_${language}_FLAGS_INIT "-mcpu=${CMAKE_SYSTEM_PROCESSOR} ") diff --git a/product/juno/scp_ramfw/Firmware.cmake b/product/juno/scp_ramfw/Firmware.cmake index 06d998694..12836fec5 100644 --- a/product/juno/scp_ramfw/Firmware.cmake +++ b/product/juno/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -14,7 +14,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) diff --git a/product/juno/scp_romfw/Firmware.cmake b/product/juno/scp_romfw/Firmware.cmake index df01f2863..b157cb339 100644 --- a/product/juno/scp_romfw/Firmware.cmake +++ b/product/juno/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU") set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS TRUE) diff --git a/product/juno/scp_romfw_bypass/Firmware.cmake b/product/juno/scp_romfw_bypass/Firmware.cmake index 9a150d8a4..fd704a379 100644 --- a/product/juno/scp_romfw_bypass/Firmware.cmake +++ b/product/juno/scp_romfw_bypass/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -15,7 +15,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS TRUE) diff --git a/product/morello/mcp_ramfw_fvp/Firmware.cmake b/product/morello/mcp_ramfw_fvp/Firmware.cmake index d97e51e01..1999bf309 100644 --- a/product/morello/mcp_ramfw_fvp/Firmware.cmake +++ b/product/morello/mcp_ramfw_fvp/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -14,7 +14,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) diff --git a/product/morello/mcp_ramfw_soc/Firmware.cmake b/product/morello/mcp_ramfw_soc/Firmware.cmake index af0d0f1b9..976dce2e0 100644 --- a/product/morello/mcp_ramfw_soc/Firmware.cmake +++ b/product/morello/mcp_ramfw_soc/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -14,7 +14,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) diff --git a/product/morello/mcp_romfw/Firmware.cmake b/product/morello/mcp_romfw/Firmware.cmake index d563b099c..1baf48233 100644 --- a/product/morello/mcp_romfw/Firmware.cmake +++ b/product/morello/mcp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_rom") list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip") diff --git a/product/morello/scp_ramfw_fvp/Firmware.cmake b/product/morello/scp_ramfw_fvp/Firmware.cmake index 0774229e9..9ec40f5f4 100644 --- a/product/morello/scp_ramfw_fvp/Firmware.cmake +++ b/product/morello/scp_ramfw_fvp/Firmware.cmake @@ -19,7 +19,7 @@ set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) diff --git a/product/morello/scp_ramfw_soc/Firmware.cmake b/product/morello/scp_ramfw_soc/Firmware.cmake index 663648f7f..fc81c6b03 100644 --- a/product/morello/scp_ramfw_soc/Firmware.cmake +++ b/product/morello/scp_ramfw_soc/Firmware.cmake @@ -19,7 +19,7 @@ set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) diff --git a/product/morello/scp_romfw/Firmware.cmake b/product/morello/scp_romfw/Firmware.cmake index edd30b80f..dc57d5f14 100644 --- a/product/morello/scp_romfw/Firmware.cmake +++ b/product/morello/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_rom") list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip") diff --git a/product/n1sdp/mcp_ramfw/Firmware.cmake b/product/n1sdp/mcp_ramfw/Firmware.cmake index 491e9dd57..1bbedb035 100644 --- a/product/n1sdp/mcp_ramfw/Firmware.cmake +++ b/product/n1sdp/mcp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") diff --git a/product/n1sdp/mcp_romfw/Firmware.cmake b/product/n1sdp/mcp_romfw/Firmware.cmake index e4b304b8b..c12c16ccd 100644 --- a/product/n1sdp/mcp_romfw/Firmware.cmake +++ b/product/n1sdp/mcp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,7 +19,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) diff --git a/product/n1sdp/scp_ramfw/Firmware.cmake b/product/n1sdp/scp_ramfw/Firmware.cmake index f97151f0a..422ae6714 100644 --- a/product/n1sdp/scp_ramfw/Firmware.cmake +++ b/product/n1sdp/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip") diff --git a/product/n1sdp/scp_romfw/Firmware.cmake b/product/n1sdp/scp_romfw/Firmware.cmake index 3c79a9ffd..1c48a22d9 100644 --- a/product/n1sdp/scp_romfw/Firmware.cmake +++ b/product/n1sdp/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/n1sdp_rom") diff --git a/product/rdn1e1/mcp_ramfw/Firmware.cmake b/product/rdn1e1/mcp_ramfw/Firmware.cmake index ba081eb4f..9609e043f 100644 --- a/product/rdn1e1/mcp_ramfw/Firmware.cmake +++ b/product/rdn1e1/mcp_ramfw/Firmware.cmake @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_DEBUGGER_INIT FALSE) diff --git a/product/rdn1e1/mcp_romfw/Firmware.cmake b/product/rdn1e1/mcp_romfw/Firmware.cmake index da8879bdd..e17ffc5ba 100644 --- a/product/rdn1e1/mcp_romfw/Firmware.cmake +++ b/product/rdn1e1/mcp_romfw/Firmware.cmake @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/rdn1e1/scp_ramfw/Firmware.cmake b/product/rdn1e1/scp_ramfw/Firmware.cmake index 88fdd0b47..87861385b 100644 --- a/product/rdn1e1/scp_ramfw/Firmware.cmake +++ b/product/rdn1e1/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,7 +19,7 @@ set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT TRUE) diff --git a/product/rdn1e1/scp_romfw/Firmware.cmake b/product/rdn1e1/scp_romfw/Firmware.cmake index d07c3c2dc..963724bcc 100644 --- a/product/rdn1e1/scp_romfw/Firmware.cmake +++ b/product/rdn1e1/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/rdn2/mcp_ramfw/Firmware.cmake b/product/rdn2/mcp_ramfw/Firmware.cmake index ee27c202d..e865d6d65 100644 --- a/product/rdn2/mcp_ramfw/Firmware.cmake +++ b/product/rdn2/mcp_ramfw/Firmware.cmake @@ -23,7 +23,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_DEBUGGER_INIT FALSE) diff --git a/product/rdn2/mcp_romfw/Firmware.cmake b/product/rdn2/mcp_romfw/Firmware.cmake index 21948ee54..7e76acbca 100644 --- a/product/rdn2/mcp_romfw/Firmware.cmake +++ b/product/rdn2/mcp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NEWLIB_NANO FALSE) diff --git a/product/rdn2/scp_ramfw/Firmware.cmake b/product/rdn2/scp_ramfw/Firmware.cmake index aa6f29051..e54f2349e 100644 --- a/product/rdn2/scp_ramfw/Firmware.cmake +++ b/product/rdn2/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -20,7 +20,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NEWLIB_NANO FALSE) diff --git a/product/rdn2/scp_romfw/Firmware.cmake b/product/rdn2/scp_romfw/Firmware.cmake index a1c52a730..f082efe75 100644 --- a/product/rdn2/scp_romfw/Firmware.cmake +++ b/product/rdn2/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NEWLIB_NANO FALSE) diff --git a/product/rdv1/mcp_ramfw/Firmware.cmake b/product/rdv1/mcp_ramfw/Firmware.cmake index 0aa041612..d14ce26fb 100644 --- a/product/rdv1/mcp_ramfw/Firmware.cmake +++ b/product/rdv1/mcp_ramfw/Firmware.cmake @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_DEBUGGER_INIT FALSE) diff --git a/product/rdv1/mcp_romfw/Firmware.cmake b/product/rdv1/mcp_romfw/Firmware.cmake index c65c557c8..7a01c2b22 100755 --- a/product/rdv1/mcp_romfw/Firmware.cmake +++ b/product/rdv1/mcp_romfw/Firmware.cmake @@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU") set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS TRUE) diff --git a/product/rdv1/scp_ramfw/Firmware.cmake b/product/rdv1/scp_ramfw/Firmware.cmake index c0cf78e18..68e8203b9 100755 --- a/product/rdv1/scp_ramfw/Firmware.cmake +++ b/product/rdv1/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU") set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS TRUE) diff --git a/product/rdv1/scp_romfw/Firmware.cmake b/product/rdv1/scp_romfw/Firmware.cmake index 01b1ec374..8a25b7ecb 100755 --- a/product/rdv1/scp_romfw/Firmware.cmake +++ b/product/rdv1/scp_romfw/Firmware.cmake @@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU") set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(SCP_GENERATE_FLAT_BINARY TRUE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_NOTIFICATIONS TRUE) diff --git a/product/rdv1mc/mcp_ramfw/Firmware.cmake b/product/rdv1mc/mcp_ramfw/Firmware.cmake index 3c7e31d8a..a69fab3de 100644 --- a/product/rdv1mc/mcp_ramfw/Firmware.cmake +++ b/product/rdv1mc/mcp_ramfw/Firmware.cmake @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_DEBUGGER_INIT FALSE) diff --git a/product/rdv1mc/mcp_romfw/Firmware.cmake b/product/rdv1mc/mcp_romfw/Firmware.cmake index a4369a868..4ac81f39c 100755 --- a/product/rdv1mc/mcp_romfw/Firmware.cmake +++ b/product/rdv1mc/mcp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/rdv1mc/scp_ramfw/Firmware.cmake b/product/rdv1mc/scp_ramfw/Firmware.cmake index 0d752a4fb..c0ee89b26 100755 --- a/product/rdv1mc/scp_ramfw/Firmware.cmake +++ b/product/rdv1mc/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/platform_system") diff --git a/product/rdv1mc/scp_romfw/Firmware.cmake b/product/rdv1mc/scp_romfw/Firmware.cmake index 5236b66b2..b76268d1c 100755 --- a/product/rdv1mc/scp_romfw/Firmware.cmake +++ b/product/rdv1mc/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/sgi575/mcp_ramfw/Firmware.cmake b/product/sgi575/mcp_ramfw/Firmware.cmake index ab78a79b1..be1406411 100644 --- a/product/sgi575/mcp_ramfw/Firmware.cmake +++ b/product/sgi575/mcp_ramfw/Firmware.cmake @@ -17,7 +17,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") set(SCP_ENABLE_DEBUGGER_INIT FALSE) diff --git a/product/sgi575/mcp_romfw/Firmware.cmake b/product/sgi575/mcp_romfw/Firmware.cmake index e1d6b0bde..91b215009 100644 --- a/product/sgi575/mcp_romfw/Firmware.cmake +++ b/product/sgi575/mcp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,7 +18,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT FALSE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/sgi575/scp_ramfw/Firmware.cmake b/product/sgi575/scp_ramfw/Firmware.cmake index f451583db..44fc997e5 100644 --- a/product/sgi575/scp_ramfw/Firmware.cmake +++ b/product/sgi575/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,7 +18,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/sgi575_system") diff --git a/product/sgi575/scp_romfw/Firmware.cmake b/product/sgi575/scp_romfw/Firmware.cmake index 43cf29c5c..f2beea8e3 100644 --- a/product/sgi575/scp_romfw/Firmware.cmake +++ b/product/sgi575/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,7 +18,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT FALSE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/sgm775/scp_ramfw/Firmware.cmake b/product/sgm775/scp_ramfw/Firmware.cmake index 6ee056057..ab8c3ff55 100644 --- a/product/sgm775/scp_ramfw/Firmware.cmake +++ b/product/sgm775/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,7 +19,7 @@ set(SCP_ENABLE_NOTIFICATIONS TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/sgm775_ddr_phy500") diff --git a/product/sgm775/scp_romfw/Firmware.cmake b/product/sgm775/scp_romfw/Firmware.cmake index 7abaf93e6..21db9710e 100644 --- a/product/sgm775/scp_romfw/Firmware.cmake +++ b/product/sgm775/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,7 +18,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS FALSE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/sgm776/scp_ramfw/Firmware.cmake b/product/sgm776/scp_ramfw/Firmware.cmake index 7a357a30b..641c7290d 100644 --- a/product/sgm776/scp_ramfw/Firmware.cmake +++ b/product/sgm776/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,7 +18,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/sgm776_system") diff --git a/product/sgm776/scp_romfw/Firmware.cmake b/product/sgm776/scp_romfw/Firmware.cmake index f3ee2b6a3..52f1fbed6 100644 --- a/product/sgm776/scp_romfw/Firmware.cmake +++ b/product/sgm776/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,7 +18,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. diff --git a/product/synquacer/scp_ramfw/Firmware.cmake b/product/synquacer/scp_ramfw/Firmware.cmake index 181b45059..edfecf23f 100644 --- a/product/synquacer/scp_ramfw/Firmware.cmake +++ b/product/synquacer/scp_ramfw/Firmware.cmake @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/scmi_vendor_ext") diff --git a/product/synquacer/scp_romfw/Firmware.cmake b/product/synquacer/scp_romfw/Firmware.cmake index 5a5a0cdce..16a9f4bce 100644 --- a/product/synquacer/scp_romfw/Firmware.cmake +++ b/product/synquacer/scp_romfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/synquacer_pik_clock") diff --git a/product/tc0/scp_ramfw/Firmware.cmake b/product/tc0/scp_ramfw/Firmware.cmake index 11d8eaab0..efc8c3192 100644 --- a/product/tc0/scp_ramfw/Firmware.cmake +++ b/product/tc0/scp_ramfw/Firmware.cmake @@ -29,7 +29,7 @@ set(SCP_ENABLE_PLUGIN_HANDLER_INIT FALSE) set(SCP_PLATFORM_VARIANT_INIT 0) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/tc0_system") diff --git a/product/tc0/scp_romfw/Firmware.cmake b/product/tc0/scp_romfw/Firmware.cmake index ab4468bef..7f6586c2b 100644 --- a/product/tc0/scp_romfw/Firmware.cmake +++ b/product/tc0/scp_romfw/Firmware.cmake @@ -23,7 +23,7 @@ set(SCP_ENABLE_IPO_INIT FALSE) set(SCP_PLATFORM_VARIANT_INIT 0) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/cmn_booker") diff --git a/product/tc1/scp_ramfw/Firmware.cmake b/product/tc1/scp_ramfw/Firmware.cmake index f3a37172c..13d66ed61 100644 --- a/product/tc1/scp_ramfw/Firmware.cmake +++ b/product/tc1/scp_ramfw/Firmware.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -23,7 +23,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/tc1_system") diff --git a/product/tc1/scp_romfw/Firmware.cmake b/product/tc1/scp_romfw/Firmware.cmake index fee95bd73..1a521a609 100644 --- a/product/tc1/scp_romfw/Firmware.cmake +++ b/product/tc1/scp_romfw/Firmware.cmake @@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) set(SCP_ENABLE_IPO_INIT FALSE) -set(SCP_ARCHITECTURE "armv7-m") +set(SCP_ARCHITECTURE "arm-m") list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/cmn_booker") -- GitLab From 6ae01340c331e1e6784e774a3131b0001d33fa66 Mon Sep 17 00:00:00 2001 From: Ahmed Gadallah Date: Fri, 20 Aug 2021 06:58:29 +0100 Subject: [PATCH 3/6] mod_mpu: Add MPU support for ARMv8-M architecture The ARMv8-M architecture comes with a different MPU than the previous ARMv7-M architecture. Hence a new MPU module is added in this change to support it. Signed-off-by: Ahmed Gadallah Change-Id: Ie8d4ff62c05186ec141114ac2508799f0f81a867 --- module/CMakeLists.txt | 1 + module/armv8m_mpu/CMakeLists.txt | 14 ++++ module/armv8m_mpu/Module.cmake | 9 +++ module/armv8m_mpu/include/mod_armv8m_mpu.h | 75 ++++++++++++++++++++++ module/armv8m_mpu/src/mod_armv8m_mpu.c | 54 ++++++++++++++++ 5 files changed, 153 insertions(+) create mode 100644 module/armv8m_mpu/CMakeLists.txt create mode 100644 module/armv8m_mpu/Module.cmake create mode 100644 module/armv8m_mpu/include/mod_armv8m_mpu.h create mode 100644 module/armv8m_mpu/src/mod_armv8m_mpu.c diff --git a/module/CMakeLists.txt b/module/CMakeLists.txt index 916ac7134..1112f6e80 100644 --- a/module/CMakeLists.txt +++ b/module/CMakeLists.txt @@ -18,6 +18,7 @@ list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/apcontext") list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/armv7m_mpu") +list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/armv8m_mpu") list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/bootloader") list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/clock") list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/cmn600") diff --git a/module/armv8m_mpu/CMakeLists.txt b/module/armv8m_mpu/CMakeLists.txt new file mode 100644 index 000000000..7e90682ab --- /dev/null +++ b/module/armv8m_mpu/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_armv8m_mpu.c") diff --git a/module/armv8m_mpu/Module.cmake b/module/armv8m_mpu/Module.cmake new file mode 100644 index 000000000..2c430f0e1 --- /dev/null +++ b/module/armv8m_mpu/Module.cmake @@ -0,0 +1,9 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "armv8m-mpu") +set(SCP_MODULE_TARGET "module-armv8m-mpu") diff --git a/module/armv8m_mpu/include/mod_armv8m_mpu.h b/module/armv8m_mpu/include/mod_armv8m_mpu.h new file mode 100644 index 000000000..ea19d4602 --- /dev/null +++ b/module/armv8m_mpu/include/mod_armv8m_mpu.h @@ -0,0 +1,75 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MOD_ARMV8M_MPU_H +#define MOD_ARMV8M_MPU_H + +#include + +#include + +/*! + * \ingroup GroupModules + * \addtogroup GroupMPUARMv8M MPU (ARMv8-M) + * \{ + */ + +/*! + * \brief MPU_MAIR registers indices. + */ +enum mod_armv8m_mpu_attr_id { + MPU_ATTR_0, + MPU_ATTR_1, + MPU_ATTR_2, + MPU_ATTR_3, + MPU_ATTR_4, + MPU_ATTR_5, + MPU_ATTR_6, + MPU_ATTR_7, + MPU_MAX_ATTR_COUNT, +}; + +/*! + * \brief Module configuration. + */ +struct mod_armv8m_mpu_config { + /*! + * \brief Number of MPU attributes. + */ + uint8_t attributes_count; + + /*! + * \brief Pointer to array of MPU attributes. + */ + const uint8_t *attributes; + + /*! + * \brief First region number. + */ + uint32_t first_region_number; + + /*! + * \brief Number of MPU regions. + */ + uint32_t region_count; + + /*! + * \brief Pointer to array of MPU regions. + * + * \details Documentation for the \c ARM_MPU_Region_t can be found in the + * CMSIS 5 documentation for the ARMv8-M MPU. + * + * \see http://arm-software.github.io/CMSIS_5/General/html/index.html + */ + const ARM_MPU_Region_t *regions; +}; + +/*! + * \} + */ + +#endif /* MOD_ARMV8M_MPU_H */ diff --git a/module/armv8m_mpu/src/mod_armv8m_mpu.c b/module/armv8m_mpu/src/mod_armv8m_mpu.c new file mode 100644 index 000000000..58dbe8221 --- /dev/null +++ b/module/armv8m_mpu/src/mod_armv8m_mpu.c @@ -0,0 +1,54 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mod_armv8m_mpu.h" + +#include +#include +#include +#include + +#include + +static int armv8m_mpu_init( + fwk_id_t module_id, + unsigned int element_count, + const void *data) +{ + const struct mod_armv8m_mpu_config *config; + uint8_t attr_index; + int status; + + fwk_assert(element_count == 0); + fwk_assert(data != NULL); + + config = data; + + if (config->attributes_count <= (uint8_t)MPU_MAX_ATTR_COUNT) { + ARM_MPU_Disable(); + + for (attr_index = 0U; attr_index < config->attributes_count; + attr_index++) { + ARM_MPU_SetMemAttr(attr_index, config->attributes[attr_index]); + } + ARM_MPU_Load( + config->first_region_number, config->regions, config->region_count); + ARM_MPU_Enable(MPU_CTRL_HFNMIENA_Msk); + + status = FWK_SUCCESS; + } else { + status = FWK_E_RANGE; + } + + return status; +} + +/* Module description */ +const struct fwk_module module_armv8m_mpu = { + .type = FWK_MODULE_TYPE_DRIVER, + .init = armv8m_mpu_init, +}; -- GitLab From 2c318deeca559f111f36f7955b4a879108840b92 Mon Sep 17 00:00:00 2001 From: Ahmed Gadallah Date: Fri, 25 Feb 2022 01:14:07 +0000 Subject: [PATCH 4/6] Add new plaform rdfremont Adding rdfremont along with an LCP target consisting of armv8m MPU configuration example. Signed-off-by: Ahmed Gadallah Change-Id: Ibe77e1a62ded74caca6b1bfa04cee51e565127b7 --- product/rdfremont/include/fmw_arch.h | 17 ++++ product/rdfremont/include/fmw_cmsis_lcp.h | 56 ++++++++++++ product/rdfremont/include/lcp_mmap.h | 39 +++++++++ product/rdfremont/lcp_ramfw/CMakeLists.txt | 37 ++++++++ product/rdfremont/lcp_ramfw/Firmware.cmake | 36 ++++++++ .../lcp_ramfw/Toolchain-ArmClang.cmake | 20 +++++ .../rdfremont/lcp_ramfw/Toolchain-Clang.cmake | 17 ++++ .../rdfremont/lcp_ramfw/Toolchain-GNU.cmake | 18 ++++ .../rdfremont/lcp_ramfw/config_armv8m_mpu.c | 86 +++++++++++++++++++ product/rdfremont/lcp_ramfw/fmw_cmsis.h | 15 ++++ product/rdfremont/lcp_ramfw/fmw_memory.h | 30 +++++++ .../rdfremont/lcp_ramfw/fmw_notification.h | 16 ++++ .../module/mod_lcp_platform/CMakeLists.txt | 11 +++ .../module/mod_lcp_platform/Module.cmake | 10 +++ .../mod_lcp_platform/src/mod_lcp_platform.c | 41 +++++++++ product/rdfremont/product.mk | 11 +++ 16 files changed, 460 insertions(+) create mode 100644 product/rdfremont/include/fmw_arch.h create mode 100644 product/rdfremont/include/fmw_cmsis_lcp.h create mode 100644 product/rdfremont/include/lcp_mmap.h create mode 100644 product/rdfremont/lcp_ramfw/CMakeLists.txt create mode 100644 product/rdfremont/lcp_ramfw/Firmware.cmake create mode 100644 product/rdfremont/lcp_ramfw/Toolchain-ArmClang.cmake create mode 100644 product/rdfremont/lcp_ramfw/Toolchain-Clang.cmake create mode 100644 product/rdfremont/lcp_ramfw/Toolchain-GNU.cmake create mode 100644 product/rdfremont/lcp_ramfw/config_armv8m_mpu.c create mode 100644 product/rdfremont/lcp_ramfw/fmw_cmsis.h create mode 100644 product/rdfremont/lcp_ramfw/fmw_memory.h create mode 100644 product/rdfremont/lcp_ramfw/fmw_notification.h create mode 100644 product/rdfremont/module/mod_lcp_platform/CMakeLists.txt create mode 100644 product/rdfremont/module/mod_lcp_platform/Module.cmake create mode 100644 product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c create mode 100644 product/rdfremont/product.mk diff --git a/product/rdfremont/include/fmw_arch.h b/product/rdfremont/include/fmw_arch.h new file mode 100644 index 000000000..cbd92b9e0 --- /dev/null +++ b/product/rdfremont/include/fmw_arch.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_ARCH_H +#define FMW_ARCH_H +/* + * Suspend feature is disabled until the whole system + * ( LCP,MCP and SCPs ) become available to wakeup + * the LCP. + */ +#define FMW_DISABLE_ARCH_SUSPEND 1 + +#endif /* FMW_ARCH_H */ diff --git a/product/rdfremont/include/fmw_cmsis_lcp.h b/product/rdfremont/include/fmw_cmsis_lcp.h new file mode 100644 index 000000000..bced17f75 --- /dev/null +++ b/product/rdfremont/include/fmw_cmsis_lcp.h @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_LCP_H +#define FMW_CMSIS_LCP_H + +#include + +#define __CHECK_DEVICE_DEFINES +#define __CM55_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __VTOR_PRESENT 1U +#define __PMU_PRESENT 0U +#define __DSP_PRESENT 0U +#define __ICACHE_PRESENT 0U +#define __DCACHE_PRESENT 0U +#define __DTCM_PRESENT 0U +#define __NVIC_PRIO_BITS 3U +#define __SAUREGION_PRESENT 0U +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + WDG_RST_RQST_IRQ = 0, /* Watchdog reset request */ + WDG_INT_IRQ = 1, /* Watchdog interrupt */ + RESERVED2_IRQ = 2, /* Reserved */ + TIMER_IRQ = 3, /* Timer */ + RESERVED4_IRQ = 4, /* Reserved */ + RESERVED5_IRQ = 5, /* Reserved */ + RESERVED6_IRQ = 6, /* Reserved */ + RESERVED7_IRQ = 7, /* Reserved */ + RESERVED8_IRQ = 8, /* Reserved */ + RESERVED9_IRQ = 9, /* Reserved */ + + IRQn_MAX = INT16_MAX, +} IRQn_Type; + +#include + +#endif /* FMW_CMSIS_LCP_H */ diff --git a/product/rdfremont/include/lcp_mmap.h b/product/rdfremont/include/lcp_mmap.h new file mode 100644 index 000000000..f5ac28fc0 --- /dev/null +++ b/product/rdfremont/include/lcp_mmap.h @@ -0,0 +1,39 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Software defined memory map for LCP core. + */ + +#ifndef LCP_SOFTWARE_MMAP_H +#define LCP_SOFTWARE_MMAP_H + +#include + +#define LCP_ITCM_SIZE (64 * 1024) +#define LCP_DTCM_SIZE (64 * 1024) + +#define LCP_ITCM_NS_BASE 0x00000000 +#define LCP_ITCM_S_BASE 0x10000000 +#define LCP_DTCM_NS_BASE 0x20000000 +#define LCP_DTCM_S_BASE 0x30000000 + +#define LCP_CORE_ITCM_REGION_START LCP_ITCM_NS_BASE +#define LCP_CORE_ITCM_REGION_END (LCP_ITCM_NS_BASE + LCP_ITCM_SIZE - 1) + +#define LCP_CORE_DTCM_REGION_START LCP_DTCM_NS_BASE +#define LCP_CORE_DTCM_REGION_END (LCP_DTCM_NS_BASE + LCP_DTCM_SIZE - 1) + +#define LCP_CORE_PERIPHERAL_REGION_START 0x30010000 +#define LCP_CORE_PERIPHERAL_REGION_END 0x6FFFFFFF + +#define LCP_SRAM_REGION_START 0x70000000 +#define LCP_SRAM_REGION_END 0xB007FFFF + +#define LCP_DEVICE_REGION_START 0xB0080000 +#define LCP_DEVICE_REGION_END 0xFFFFFFFF + +#endif /* LCP_SOFTWARE_MMAP_H */ diff --git a/product/rdfremont/lcp_ramfw/CMakeLists.txt b/product/rdfremont/lcp_ramfw/CMakeLists.txt new file mode 100644 index 000000000..58e4c9671 --- /dev/null +++ b/product/rdfremont/lcp_ramfw/CMakeLists.txt @@ -0,0 +1,37 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Create the firmware target. +# + +add_executable(rdfremont-lcp) + +target_include_directories( + rdfremont-lcp PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../include" + "${CMAKE_CURRENT_SOURCE_DIR}") + +# cmake-lint: disable=E1122 + +target_sources( + rdfremont-lcp + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv8m_mpu.c") + +# +# Some of our firmware includes require CMSIS. +# + +target_link_libraries(rdfremont-lcp PUBLIC cmsis::core-m) + +# +# We explicitly add the CMSIS include directories to our interface include +# directories. Each module target adds these include directories to their own, +# allowing them to include any firmware includes we expose. +# + +target_include_directories(rdfremont-lcp + PUBLIC $) diff --git a/product/rdfremont/lcp_ramfw/Firmware.cmake b/product/rdfremont/lcp_ramfw/Firmware.cmake new file mode 100644 index 000000000..f103e0f9a --- /dev/null +++ b/product/rdfremont/lcp_ramfw/Firmware.cmake @@ -0,0 +1,36 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Configure the build system. +# + +set(SCP_FIRMWARE "rdfremont-lcp") + +set(SCP_FIRMWARE_TARGET "rdfremont-lcp") + +set(SCP_TOOLCHAIN_INIT "GNU") + +set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +set(SCP_ENABLE_IPO_INIT FALSE) + +set(SCP_ARCHITECTURE "arm-m") + +set(SCP_ENABLE_DEBUGGER_INIT FALSE) + +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/mod_lcp_platform") + +# The order of the modules in the following list is the order in which the +# modules are initialized, bound, started during the pre-runtime phase. +# any change in the order will cause firmware initialization errors. + +list(APPEND SCP_MODULES "armv8m-mpu") +list(APPEND SCP_MODULES "lcp-platform") diff --git a/product/rdfremont/lcp_ramfw/Toolchain-ArmClang.cmake b/product/rdfremont/lcp_ramfw/Toolchain-ArmClang.cmake new file mode 100644 index 000000000..517a0679d --- /dev/null +++ b/product/rdfremont/lcp_ramfw/Toolchain-ArmClang.cmake @@ -0,0 +1,20 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cmake-lint: disable=C0301 + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/ArmClang-Baremetal.cmake" +) diff --git a/product/rdfremont/lcp_ramfw/Toolchain-Clang.cmake b/product/rdfremont/lcp_ramfw/Toolchain-Clang.cmake new file mode 100644 index 000000000..87ffe67a3 --- /dev/null +++ b/product/rdfremont/lcp_ramfw/Toolchain-Clang.cmake @@ -0,0 +1,17 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/Clang-Baremetal.cmake") diff --git a/product/rdfremont/lcp_ramfw/Toolchain-GNU.cmake b/product/rdfremont/lcp_ramfw/Toolchain-GNU.cmake new file mode 100644 index 000000000..2f620ced3 --- /dev/null +++ b/product/rdfremont/lcp_ramfw/Toolchain-GNU.cmake @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") +set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") + +set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/rdfremont/lcp_ramfw/config_armv8m_mpu.c b/product/rdfremont/lcp_ramfw/config_armv8m_mpu.c new file mode 100644 index 000000000..856ca8e3a --- /dev/null +++ b/product/rdfremont/lcp_ramfw/config_armv8m_mpu.c @@ -0,0 +1,86 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "lcp_mmap.h" +#include "mod_armv8m_mpu.h" + +#include +#include + +#include + +static const uint8_t attributes[] = { + /* Device memory, non Gathering, non Re-ordering, non Early Write + Acknowledgement */ + [MPU_ATTR_0] = + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE), + /* Normal memory, non Cacheable */ + [MPU_ATTR_1] = + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE), +}; + +static const ARM_MPU_Region_t regions[] = { + { + /* LCP_CORE_TCM_REGION*/ + .RBAR = ARM_MPU_RBAR( + LCP_CORE_ITCM_REGION_START, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 0 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_CORE_ITCM_REGION_END, MPU_ATTR_1), + }, + { + /* LCP_CORE_DTCM_REGION*/ + .RBAR = ARM_MPU_RBAR( + LCP_CORE_DTCM_REGION_START, /* BASE */ + ARM_MPU_SH_INNER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_CORE_DTCM_REGION_END, MPU_ATTR_1), + }, + { + /* LCP_CORE_PERIPERAL_REGION */ + .RBAR = ARM_MPU_RBAR( + LCP_CORE_PERIPHERAL_REGION_START, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_CORE_PERIPHERAL_REGION_END, MPU_ATTR_0), + }, + { + /* LCP_SRAM_REGION*/ + .RBAR = ARM_MPU_RBAR( + LCP_SRAM_REGION_START, /* BASE */ + ARM_MPU_SH_OUTER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_SRAM_REGION_END, MPU_ATTR_1), + }, + { + /* LCP_DEVICE_REGION */ + .RBAR = ARM_MPU_RBAR( + LCP_DEVICE_REGION_START, /* BASE */ + ARM_MPU_SH_OUTER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_DEVICE_REGION_END, MPU_ATTR_0), + }, +}; + +const struct fwk_module_config config_armv8m_mpu = { + .data = &((struct mod_armv8m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + .attributes_count = FWK_ARRAY_SIZE(attributes), + .attributes = attributes, + }), +}; diff --git a/product/rdfremont/lcp_ramfw/fmw_cmsis.h b/product/rdfremont/lcp_ramfw/fmw_cmsis.h new file mode 100644 index 000000000..77a7ea19e --- /dev/null +++ b/product/rdfremont/lcp_ramfw/fmw_cmsis.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include "fmw_cmsis_lcp.h" + +extern uint32_t SystemCoreClock; + +#endif /* FMW_CMSIS_H */ diff --git a/product/rdfremont/lcp_ramfw/fmw_memory.h b/product/rdfremont/lcp_ramfw/fmw_memory.h new file mode 100644 index 000000000..784f76bc7 --- /dev/null +++ b/product/rdfremont/lcp_ramfw/fmw_memory.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "lcp_mmap.h" + +#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FMW_MEM0_SIZE LCP_ITCM_SIZE +#define FMW_MEM0_BASE LCP_ITCM_NS_BASE + +/* + * RAM data memory + */ +#define FMW_MEM1_SIZE LCP_DTCM_SIZE +#define FMW_MEM1_BASE LCP_DTCM_NS_BASE + +#endif /* FMW_MEMORY_H */ diff --git a/product/rdfremont/lcp_ramfw/fmw_notification.h b/product/rdfremont/lcp_ramfw/fmw_notification.h new file mode 100644 index 000000000..ceffa1787 --- /dev/null +++ b/product/rdfremont/lcp_ramfw/fmw_notification.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware notification configuration. + */ + +#ifndef FMW_NOTIFICATION_H +#define FMW_NOTIFICATION_H + +#define FMW_NOTIFICATION_MAX 128 + +#endif /* FMW_NOTIFICATION_H */ diff --git a/product/rdfremont/module/mod_lcp_platform/CMakeLists.txt b/product/rdfremont/module/mod_lcp_platform/CMakeLists.txt new file mode 100644 index 000000000..f805e7711 --- /dev/null +++ b/product/rdfremont/module/mod_lcp_platform/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_lcp_platform.c") diff --git a/product/rdfremont/module/mod_lcp_platform/Module.cmake b/product/rdfremont/module/mod_lcp_platform/Module.cmake new file mode 100644 index 000000000..2011d81aa --- /dev/null +++ b/product/rdfremont/module/mod_lcp_platform/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "lcp-platform") + +set(SCP_MODULE_TARGET "module-lcp-platform") diff --git a/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c b/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c new file mode 100644 index 000000000..31234f524 --- /dev/null +++ b/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c @@ -0,0 +1,41 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#define MOD_NAME "[LCP_PLATFORM] " + +static int mod_lcp_platform_init( + fwk_id_t module_id, + unsigned int element_count, + const void *unused) +{ + /* No elements support */ + if (element_count > 0) { + return FWK_E_DATA; + } + + return FWK_SUCCESS; +} + +static int mod_lcp_platform_start(fwk_id_t id) +{ + FWK_LOG_INFO(MOD_NAME "LCP RAM firmware initialized\n"); + return FWK_SUCCESS; +} + +const struct fwk_module module_lcp_platform = { + .type = FWK_MODULE_TYPE_SERVICE, + .init = mod_lcp_platform_init, + .start = mod_lcp_platform_start, +}; + +const struct fwk_module_config config_lcp_platform = { 0 }; diff --git a/product/rdfremont/product.mk b/product/rdfremont/product.mk new file mode 100644 index 000000000..346c0361e --- /dev/null +++ b/product/rdfremont/product.mk @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Platforms supported by the rdn1e1 product: RDN1E1. + + +BS_PRODUCT_NAME := rdfremont +BS_FIRMWARE_LIST := lcp_ramfw -- GitLab From 11b2da0b1dc5ed05b82d8bb68ebf89afeb1b3413 Mon Sep 17 00:00:00 2001 From: Ahmed Gadallah Date: Thu, 10 Mar 2022 20:00:39 +0000 Subject: [PATCH 5/6] rdfremont: Add timer configuration Add timer and interrupt configuration to validate interrupt handling in the LCP. Signed-off-by: Ahmed Gadallah Change-Id: I01bbf36890914fb17bab4c6eecb8b1d26b830996 --- product/rdfremont/include/lcp_device.h | 36 +++++++++++++++++++ product/rdfremont/include/lcp_mmap.h | 3 ++ .../mod_lcp_platform/src/mod_lcp_platform.c | 28 +++++++++++++++ 3 files changed, 67 insertions(+) create mode 100644 product/rdfremont/include/lcp_device.h diff --git a/product/rdfremont/include/lcp_device.h b/product/rdfremont/include/lcp_device.h new file mode 100644 index 000000000..5b2331c0e --- /dev/null +++ b/product/rdfremont/include/lcp_device.h @@ -0,0 +1,36 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef LCP_DEVICE_H +#define LCP_DEVICE_H + +#include + +#include + +#include + +#define CTRL_ENABLE_POS 0U +#define CTRL_EXTR_EN_POS 1U +#define CTRL_EXTR_IS_CLK_POS 2U +#define CTRL_INT_EN_POS 3U + +#define CTRL_ENABLE_MASK (1UL << CTRL_ENABLE_POS) +#define CTRL_EXTR_EN_POS_MASK (1UL << CTRL_EXTR_EN_POS) +#define CTRL_EXTR_IS_CLK_MASK (1UL << CTRL_EXTR_IS_CLK_POS) +#define CTRL_INT_EN_MASK (1UL << CTRL_INT_EN_POS) + +struct lcp_timer_reg_str { + FWK_RW uint32_t CTRL; + FWK_RW uint32_t VALUE; + FWK_RW uint32_t RELOAD; + FWK_RW uint32_t INTSTATUS; +}; + +#define LCP_TIMER_REG_S ((struct lcp_timer_reg_str *)LCP_TIMER_BASE_S) + +#endif /* LCP_DEVICE_H */ diff --git a/product/rdfremont/include/lcp_mmap.h b/product/rdfremont/include/lcp_mmap.h index f5ac28fc0..43292f687 100644 --- a/product/rdfremont/include/lcp_mmap.h +++ b/product/rdfremont/include/lcp_mmap.h @@ -36,4 +36,7 @@ #define LCP_DEVICE_REGION_START 0xB0080000 #define LCP_DEVICE_REGION_END 0xFFFFFFFF +#define LCP_TIMER_BASE_NS UINT32_C(0x48000000) +#define LCP_TIMER_BASE_S UINT32_C(0x58000000) + #endif /* LCP_SOFTWARE_MMAP_H */ diff --git a/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c b/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c index 31234f524..df4715d8a 100644 --- a/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c +++ b/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c @@ -4,14 +4,35 @@ * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include +#include #include #include #include #include #define MOD_NAME "[LCP_PLATFORM] " +#define LCP_TIMER_RELOAD 0xFFFFFU + +volatile struct { + uint32_t counter; +} lcp_platform_ctx; + +void timer_isr() +{ + lcp_platform_ctx.counter++; + /* clear interrupt flag */ + LCP_TIMER_REG_S->INTSTATUS = 1U; +} + +void mod_lcp_config_timer() +{ + LCP_TIMER_REG_S->CTRL = CTRL_ENABLE_MASK | CTRL_INT_EN_MASK; + + LCP_TIMER_REG_S->RELOAD = LCP_TIMER_RELOAD; +} static int mod_lcp_platform_init( fwk_id_t module_id, @@ -28,7 +49,14 @@ static int mod_lcp_platform_init( static int mod_lcp_platform_start(fwk_id_t id) { + fwk_interrupt_set_isr(TIMER_IRQ, timer_isr); + + fwk_interrupt_enable(TIMER_IRQ); + + mod_lcp_config_timer(); + FWK_LOG_INFO(MOD_NAME "LCP RAM firmware initialized\n"); + return FWK_SUCCESS; } -- GitLab From 5008c944a484f2218a20c89d939b37bdf0fbedef Mon Sep 17 00:00:00 2001 From: Ahmed Gadallah Date: Fri, 18 Mar 2022 15:17:13 +0000 Subject: [PATCH 6/6] rdfremont: add LCP uart configuration Add uart pl011 configuration to validate uart on LCP. Signed-off-by: Ahmed Gadallah Change-Id: I8707b97d5dde4b427b6a4faf539ab7dbf9a3ab70 --- product/rdfremont/include/fmw_io.h | 17 ++++++++++++ product/rdfremont/include/lcp_mmap.h | 2 ++ product/rdfremont/lcp_ramfw/CMakeLists.txt | 3 ++- product/rdfremont/lcp_ramfw/Firmware.cmake | 1 + product/rdfremont/lcp_ramfw/config_pl011.c | 31 ++++++++++++++++++++++ 5 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 product/rdfremont/include/fmw_io.h create mode 100644 product/rdfremont/lcp_ramfw/config_pl011.c diff --git a/product/rdfremont/include/fmw_io.h b/product/rdfremont/include/fmw_io.h new file mode 100644 index 000000000..57286d4ee --- /dev/null +++ b/product/rdfremont/include/fmw_io.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_IO_H +#define FMW_IO_H + +#include +#include + +#define FMW_IO_STDIN_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) +#define FMW_IO_STDOUT_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) + +#endif /* FMW_IO_H */ diff --git a/product/rdfremont/include/lcp_mmap.h b/product/rdfremont/include/lcp_mmap.h index 43292f687..815243451 100644 --- a/product/rdfremont/include/lcp_mmap.h +++ b/product/rdfremont/include/lcp_mmap.h @@ -39,4 +39,6 @@ #define LCP_TIMER_BASE_NS UINT32_C(0x48000000) #define LCP_TIMER_BASE_S UINT32_C(0x58000000) +#define LCP_UART_BASE 0xB2000000 + #endif /* LCP_SOFTWARE_MMAP_H */ diff --git a/product/rdfremont/lcp_ramfw/CMakeLists.txt b/product/rdfremont/lcp_ramfw/CMakeLists.txt index 58e4c9671..4015892df 100644 --- a/product/rdfremont/lcp_ramfw/CMakeLists.txt +++ b/product/rdfremont/lcp_ramfw/CMakeLists.txt @@ -19,7 +19,8 @@ target_include_directories( target_sources( rdfremont-lcp - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv8m_mpu.c") + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv8m_mpu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c") # # Some of our firmware includes require CMSIS. diff --git a/product/rdfremont/lcp_ramfw/Firmware.cmake b/product/rdfremont/lcp_ramfw/Firmware.cmake index f103e0f9a..32cfe9a0a 100644 --- a/product/rdfremont/lcp_ramfw/Firmware.cmake +++ b/product/rdfremont/lcp_ramfw/Firmware.cmake @@ -34,3 +34,4 @@ list(PREPEND SCP_MODULE_PATHS list(APPEND SCP_MODULES "armv8m-mpu") list(APPEND SCP_MODULES "lcp-platform") +list(APPEND SCP_MODULES "pl011") diff --git a/product/rdfremont/lcp_ramfw/config_pl011.c b/product/rdfremont/lcp_ramfw/config_pl011.c new file mode 100644 index 000000000..b7e020461 --- /dev/null +++ b/product/rdfremont/lcp_ramfw/config_pl011.c @@ -0,0 +1,31 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "lcp_mmap.h" + +#include + +#include +#include +#include +#include + +struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS({ + [0] = { + .name = "lcp-uart", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = LCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + }, + }, + + [1] = { 0 }, + }), +}; -- GitLab