diff --git a/.armv8m.cppcheck.cfg b/.armv8m.cppcheck.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..66bd6a6b91021a500f4d40999b4662d1188bbb37
--- /dev/null
+++ b/.armv8m.cppcheck.cfg
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<!-- At present compiler specific options are not getting passed -->
+<!-- to cpp check, following is a workaround to pass it manually -->
+<!-- GNU specific defines which are not passed to GCC -->
+<def><define name="__ARM_ARCH_8M__" value="1"/>
+</def>
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 4f30068f0e6e99805db44585d3c7104083e3326b..fcded28d1122878354f3151ca74a217941d68aac 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -181,8 +181,12 @@ if(NOT DISABLE_CPPCHECK)
         list(APPEND CMAKE_C_CPPCHECK "--enable=all")
         list(APPEND CMAKE_C_CPPCHECK "--error-exitcode=1")
 
-        if(SCP_ARCHITECTURE STREQUAL "armv7-m")
-            list(APPEND CMAKE_C_CPPCHECK "--library=${CMAKE_CURRENT_SOURCE_DIR}/.armv7m.cppcheck.cfg")
+        if(SCP_ARCHITECTURE STREQUAL "arm-m")
+            if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(33|55)")
+                list(APPEND CMAKE_C_CPPCHECK "--library=${CMAKE_CURRENT_SOURCE_DIR}/.armv8m.cppcheck.cfg")
+            elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(3|7)")
+                list(APPEND CMAKE_C_CPPCHECK "--library=${CMAKE_CURRENT_SOURCE_DIR}/.armv7m.cppcheck.cfg")
+            endif()
         endif()
 
         if(CMAKE_C_COMPILER_ID STREQUAL "ARMClang")
diff --git a/arch/CMakeLists.txt b/arch/CMakeLists.txt
index 88450ac2f8247100c5fe008298240c888dc2a8e9..13a846dfcb4611c9a0214b7fcdb19279d51ee0e2 100644
--- a/arch/CMakeLists.txt
+++ b/arch/CMakeLists.txt
@@ -1,11 +1,11 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/arm/armv7-m")
+list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/arm/arm-m")
 list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/arm/armv8-a")
 list(APPEND SCP_ARCHITECTURE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/none/host")
 
diff --git a/arch/arm/arm-m/Architecture.cmake b/arch/arm/arm-m/Architecture.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..114b90749c9359c6f69274310fea25f7c050ea59
--- /dev/null
+++ b/arch/arm/arm-m/Architecture.cmake
@@ -0,0 +1,9 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set(SCP_ARCHITECTURE "arm-m")
+set(SCP_ARCHITECTURE_TARGET "arch-arm-m")
diff --git a/arch/arm/armv7-m/CMakeLists.txt b/arch/arm/arm-m/CMakeLists.txt
similarity index 72%
rename from arch/arm/armv7-m/CMakeLists.txt
rename to arch/arm/arm-m/CMakeLists.txt
index d5be87b5e9319ec4d6ba1223d39bd7d8283ff549..b72127fb29b9984f857e253dc023d2d3be470965 100644
--- a/arch/arm/armv7-m/CMakeLists.txt
+++ b/arch/arm/arm-m/CMakeLists.txt
@@ -5,22 +5,33 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-add_library(arch-armv7m)
+add_library(arch-arm-m)
 
-target_include_directories(arch-armv7m
+#
+# Determine which architecture shall be supported according to
+# the used CPU
+#
+
+if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(33|55)")
+    target_compile_definitions(arch-arm-m PUBLIC "ARMV8M")
+else()
+    target_compile_definitions(arch-arm-m PUBLIC "ARMV7M")
+endif()
+
+target_include_directories(arch-arm-m
                            PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include")
 
 # cmake-lint: disable=E1122
 
 target_sources(
-    arch-armv7m
+    arch-arm-m
     PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_exceptions.c"
             "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_handlers.c"
             "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_main.c"
             "${CMAKE_CURRENT_SOURCE_DIR}/src/arch_nvic.c"
     PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/../src/arch_mm.c")
 
-target_link_libraries(arch-armv7m PUBLIC cmsis::core-m)
+target_link_libraries(arch-arm-m PUBLIC cmsis::core-m)
 
 
 #
@@ -36,15 +47,15 @@ cmake_dependent_option(
 
 if(SCP_ENABLE_NEWLIB_NANO)
     if(CMAKE_C_COMPILER_ID STREQUAL "GNU")
-        target_link_options(arch-armv7m PUBLIC "--specs=nano.specs")
+        target_link_options(arch-arm-m PUBLIC "--specs=nano.specs")
     elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang")
-        target_link_libraries(arch-armv7m PUBLIC c_nano)
+        target_link_libraries(arch-arm-m PUBLIC c_nano)
     endif()
 else()
     if(CMAKE_C_COMPILER_ID STREQUAL "GNU")
-        target_link_options(arch-armv7m PUBLIC "--specs=nosys.specs")
+        target_link_options(arch-arm-m PUBLIC "--specs=nosys.specs")
     elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang")
-        target_link_libraries(arch-armv7m PUBLIC c)
+        target_link_libraries(arch-arm-m PUBLIC c)
     endif()
 endif()
 
@@ -53,15 +64,15 @@ endif()
 # functions that the standard library relies on.
 #
 
-target_link_options(arch-armv7m PUBLIC "LINKER:--undefined=arch_exceptions")
+target_link_options(arch-arm-m PUBLIC "LINKER:--undefined=arch_exceptions")
 
 if(CMAKE_C_COMPILER_ID STREQUAL "ARMClang")
-    target_link_options(arch-armv7m
+    target_link_options(arch-arm-m
                         PUBLIC "LINKER:--entry=arch_exception_reset")
 endif()
 
 if(SCP_HAVE_NEWLIB)
-    target_link_options(arch-armv7m PUBLIC "LINKER:--undefined=posix_memalign"
+    target_link_options(arch-arm-m PUBLIC "LINKER:--undefined=posix_memalign"
                                            "LINKER:--undefined=_sbrk")
 endif()
 
@@ -89,4 +100,4 @@ else()
     set(scp_lds "${CMAKE_CURRENT_SOURCE_DIR}/src/arch.ld.S")
 endif()
 
-scp_target_linker_script(arch-armv7m "${scp_lds}")
+scp_target_linker_script(arch-arm-m "${scp_lds}")
diff --git a/arch/arm/armv7-m/include/arch_exceptions.h b/arch/arm/arm-m/include/arch_exceptions.h
similarity index 90%
rename from arch/arm/armv7-m/include/arch_exceptions.h
rename to arch/arm/arm-m/include/arch_exceptions.h
index e643fe0d1444233b0be8ec6bc58d97da93047441..fe1244ee20d60ef4c4efd718db23c74ac820459b 100644
--- a/arch/arm/armv7-m/include/arch_exceptions.h
+++ b/arch/arm/arm-m/include/arch_exceptions.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/arch/arm/armv7-m/include/arch_helpers.h b/arch/arm/arm-m/include/arch_helpers.h
similarity index 100%
rename from arch/arm/armv7-m/include/arch_helpers.h
rename to arch/arm/arm-m/include/arch_helpers.h
diff --git a/arch/arm/armv7-m/include/arch_nvic.h b/arch/arm/arm-m/include/arch_nvic.h
similarity index 89%
rename from arch/arm/armv7-m/include/arch_nvic.h
rename to arch/arm/arm-m/include/arch_nvic.h
index 6bc6b5d7f23d55e8b1649db73fa9744f625b968c..cfc4bbaa246d0fbf04df758c2ea33b8ce326d288 100644
--- a/arch/arm/armv7-m/include/arch_nvic.h
+++ b/arch/arm/arm-m/include/arch_nvic.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/arch/arm/armv7-m/include/arch_scatter.h b/arch/arm/arm-m/include/arch_scatter.h
similarity index 90%
rename from arch/arm/armv7-m/include/arch_scatter.h
rename to arch/arm/arm-m/include/arch_scatter.h
index bcdfd7e0ae443796544b18472b843559eaba83b1..0844f696897b400943e3dd4c4759d7fb194670fd 100644
--- a/arch/arm/armv7-m/include/arch_scatter.h
+++ b/arch/arm/arm-m/include/arch_scatter.h
@@ -1,13 +1,13 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
  * Description:
  *      Common linker script configuration options.
  *
- * There are three supported memory layouts for the ARMv7-M architecture:
+ * There are three supported memory layouts for the ARM-M architectures:
  *
  * Layout 1 - Single region:
  *      This layout uses a single read/write/execute memory region for all data.
@@ -34,8 +34,8 @@
 #ifndef ARCH_SCATTER_H
 #define ARCH_SCATTER_H
 
-#define ARCH_MEM_MODE_SINGLE_REGION 0
-#define ARCH_MEM_MODE_DUAL_REGION_RELOCATION 1
+#define ARCH_MEM_MODE_SINGLE_REGION             0
+#define ARCH_MEM_MODE_DUAL_REGION_RELOCATION    1
 #define ARCH_MEM_MODE_DUAL_REGION_NO_RELOCATION 2
 
 #include <fmw_memory.h>
diff --git a/arch/arm/armv7-m/src/arch.ld.S b/arch/arm/arm-m/src/arch.ld.S
similarity index 98%
rename from arch/arm/armv7-m/src/arch.ld.S
rename to arch/arm/arm-m/src/arch.ld.S
index 5a349ac3b49776c9f38f52e17bab2d14d507f0d2..3b15e36e2488366f8af2d259cbadb13c6faf2527 100644
--- a/arch/arm/armv7-m/src/arch.ld.S
+++ b/arch/arm/arm-m/src/arch.ld.S
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
diff --git a/arch/arm/armv7-m/src/arch.scatter.S b/arch/arm/arm-m/src/arch.scatter.S
similarity index 96%
rename from arch/arm/armv7-m/src/arch.scatter.S
rename to arch/arm/arm-m/src/arch.scatter.S
index c89254df8759ace1f20ae9b1d3b1f21bafcc4525..c87efe3f85ee774d4d37266fb1661935b1babf7e 100644
--- a/arch/arm/armv7-m/src/arch.scatter.S
+++ b/arch/arm/arm-m/src/arch.scatter.S
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
diff --git a/arch/arm/armv7-m/src/arch_exceptions.c b/arch/arm/arm-m/src/arch_exceptions.c
similarity index 90%
rename from arch/arm/armv7-m/src/arch_exceptions.c
rename to arch/arm/arm-m/src/arch_exceptions.c
index d990c6a5db02a8e2e2f9947da4fd4aa2c1158e43..e1472f33081a34abc45a50bd8ab06bd1966b7600 100644
--- a/arch/arm/armv7-m/src/arch_exceptions.c
+++ b/arch/arm/arm-m/src/arch_exceptions.c
@@ -5,12 +5,12 @@
  * SPDX-License-Identifier: BSD-3-Clause
  *
  * Description:
- *      ARMv7-M exception handlers.
+ *      ARM-M exception handlers.
  */
 
-#include <fwk_attributes.h>
+#include "arch_exceptions.h"
 
-#include <arch_exceptions.h>
+#include <fwk_attributes.h>
 
 #include <fmw_cmsis.h>
 
@@ -49,7 +49,7 @@ extern char __stackheap_end__;
 #endif
 
 /*
- * Set up the exception table. The structure below is is added to the
+ * Set up the exception table. The structure below is added to the
  * .exceptions section which will be explicitly placed at the beginning of the
  * binary by the linker script.
  */
@@ -72,6 +72,10 @@ const struct {
             (uintptr_t)(arch_exception_invalid),
         [NVIC_USER_IRQ_OFFSET + UsageFault_IRQn - 1] =
             (uintptr_t)(arch_exception_invalid),
+#ifdef ARMV8M
+        [NVIC_USER_IRQ_OFFSET + SecureFault_IRQn - 1] =
+            (uintptr_t)(arch_exception_invalid),
+#endif
         [NVIC_USER_IRQ_OFFSET + DebugMonitor_IRQn - 1] =
             (uintptr_t)(arch_exception_invalid),
 
diff --git a/arch/arm/armv7-m/src/arch_handlers.c b/arch/arm/arm-m/src/arch_handlers.c
similarity index 91%
rename from arch/arm/armv7-m/src/arch_handlers.c
rename to arch/arm/arm-m/src/arch_handlers.c
index 39795498970f948cb0078aa115ed44e038454872..555358fe338248b53329c7b85267720cec4abe76 100644
--- a/arch/arm/armv7-m/src/arch_handlers.c
+++ b/arch/arm/arm-m/src/arch_handlers.c
@@ -1,11 +1,11 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
  * Description:
- *      ARMv7-M exception handlers.
+ *      ARM-M exception handlers.
  */
 
 #include <cmsis_compiler.h>
diff --git a/arch/arm/armv7-m/src/arch_main.c b/arch/arm/arm-m/src/arch_main.c
similarity index 84%
rename from arch/arm/armv7-m/src/arch_main.c
rename to arch/arm/arm-m/src/arch_main.c
index 128d7b2d6a5b2957848634efe1b4c5fa848308a3..f77c20cd2facaae54efeee792369a1a9e5b1a221 100644
--- a/arch/arm/armv7-m/src/arch_main.c
+++ b/arch/arm/arm-m/src/arch_main.c
@@ -45,18 +45,21 @@ static void arch_init_ccr(void)
      * Set up the Configuration Control Register (CCR) in the System Control
      * Block (1) by setting the following flag bits:
      *
-     * DIV_0_TRP   [4]: Enable trapping on division by zero.
+     * DIV_0_TRP   [4]: Enable trapping on division by zero. (1)(2)
      * STKALIGN    [9]: Enable automatic DWORD stack-alignment on exception
-     *                  entry (2).
+     *                  entry (3).
      *
      * All other bits are left in their default state.
      *
      * (1) ARM® v7-M Architecture Reference Manual, section B3.2.8.
-     * (2) ARM® v7-M Architecture Reference Manual, section B1.5.7.
+     * (2) Arm® v8-M Architecture Reference Manual, section D1.2.9.
+     * (3) ARM® v7-M Architecture Reference Manual, section B1.5.7.
      */
 
     SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
+#ifdef ARMV7M
     SCB->CCR |= SCB_CCR_STKALIGN_Msk;
+#endif
 }
 
 int main(void)
diff --git a/arch/arm/armv7-m/src/arch_nvic.c b/arch/arm/arm-m/src/arch_nvic.c
similarity index 100%
rename from arch/arm/armv7-m/src/arch_nvic.c
rename to arch/arm/arm-m/src/arch_nvic.c
diff --git a/arch/arm/armv7-m/Architecture.cmake b/arch/arm/armv7-m/Architecture.cmake
deleted file mode 100644
index e39a6fb3661a828546be46075db299af6f0e1abd..0000000000000000000000000000000000000000
--- a/arch/arm/armv7-m/Architecture.cmake
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-set(SCP_ARCHITECTURE "armv7-m")
-set(SCP_ARCHITECTURE_TARGET "arch-armv7m")
diff --git a/arch/arm/armv7-m/arch.mk b/arch/arm/armv7-m/arch.mk
deleted file mode 100644
index 610464a98dd3aa98b7d5f12dac89737f2568d61e..0000000000000000000000000000000000000000
--- a/arch/arm/armv7-m/arch.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Arm SCP/MCP Software
-# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_exceptions.c
-BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_handlers.c
-BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_main.c
-BS_LIB_SOURCES_$(BS_ARCH_ARCH) += arch_nvic.c
-
-BS_LIB_SOURCES_$(BS_ARCH_ARCH) := $(addprefix $(ARCH_DIR)/$(BS_ARCH_VENDOR)/$(BS_ARCH_ARCH)/src/,$(BS_LIB_SOURCES_$(BS_ARCH_ARCH)))
diff --git a/cmake/Toolchain/Clang-Baremetal.cmake b/cmake/Toolchain/Clang-Baremetal.cmake
index 1ab74e46a19ad5aabec2a29ad6ba624862988cf5..66b9cf0f45e639cc7b32d07bed927ac90c0256a9 100644
--- a/cmake/Toolchain/Clang-Baremetal.cmake
+++ b/cmake/Toolchain/Clang-Baremetal.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -41,13 +41,17 @@ foreach(language IN ITEMS ASM C CXX)
                "-I\"${LLVM_SYSROOT_PATH}/include\" ")
     endif()
 
-    if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m[37]")
+    if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(3|7|33|55)")
         set(BUILD_TARGET "-mcpu=${CMAKE_SYSTEM_PROCESSOR} -mthumb ")
         string(APPEND CMAKE_${language}_FLAGS_INIT "${BUILD_TARGET}")
         if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m7")
             set(CLANG_BUILTINS_ARCH "armv7em")
-        else()
+        elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m33")
+            set(CLANG_BUILTINS_ARCH "armv8m.main")
+        elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m3")
             set(CLANG_BUILTINS_ARCH "armv7m")
+        elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m55")
+            set(CLANG_BUILTINS_ARCH "armv8.1m.main")
         endif()
     endif()
 
diff --git a/cmake/Toolchain/GNU-Baremetal.cmake b/cmake/Toolchain/GNU-Baremetal.cmake
index 457782c1f249fa400f4050375f48818ca2e6a021..3fff1cff8a0d11927629f6be842282748e350057 100644
--- a/cmake/Toolchain/GNU-Baremetal.cmake
+++ b/cmake/Toolchain/GNU-Baremetal.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -19,7 +19,7 @@ foreach(language IN ITEMS ASM C CXX)
             "-mstrict-align -fno-builtin -DAARCH64 -D__ASSEMBLY__ ")
     endif()
 
-    if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m[37]")
+    if(CMAKE_SYSTEM_PROCESSOR MATCHES "cortex-m(3|7|33|55)")
         string(APPEND CMAKE_${language}_FLAGS_INIT "-mthumb ")
         string(APPEND CMAKE_${language}_FLAGS_INIT
             "-mcpu=${CMAKE_SYSTEM_PROCESSOR} ")
diff --git a/contrib/cmsis/git b/contrib/cmsis/git
index 80cc44bba16cb4c8f495b7aa9709d41ac50e9529..13b9f72f212688d2306d0d085d87cbb4bf9e5d3f 160000
--- a/contrib/cmsis/git
+++ b/contrib/cmsis/git
@@ -1 +1 @@
-Subproject commit 80cc44bba16cb4c8f495b7aa9709d41ac50e9529
+Subproject commit 13b9f72f212688d2306d0d085d87cbb4bf9e5d3f
diff --git a/module/CMakeLists.txt b/module/CMakeLists.txt
index 916ac7134bcd964c02b65dab1a3428eb0be52378..1112f6e80fb757099976571701a7d87779d9ea31 100644
--- a/module/CMakeLists.txt
+++ b/module/CMakeLists.txt
@@ -18,6 +18,7 @@
 
 list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/apcontext")
 list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/armv7m_mpu")
+list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/armv8m_mpu")
 list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/bootloader")
 list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/clock")
 list(APPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_SOURCE_DIR}/cmn600")
diff --git a/module/armv8m_mpu/CMakeLists.txt b/module/armv8m_mpu/CMakeLists.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7e90682ab0589bfd28ede63306e277fd552fc508
--- /dev/null
+++ b/module/armv8m_mpu/CMakeLists.txt
@@ -0,0 +1,14 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+add_library(${SCP_MODULE_TARGET} SCP_MODULE)
+
+target_include_directories(${SCP_MODULE_TARGET}
+                           PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+target_sources(${SCP_MODULE_TARGET}
+               PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_armv8m_mpu.c")
diff --git a/module/armv8m_mpu/Module.cmake b/module/armv8m_mpu/Module.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..2c430f0e1328cf48f614a2c7f66e6472bd75182e
--- /dev/null
+++ b/module/armv8m_mpu/Module.cmake
@@ -0,0 +1,9 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set(SCP_MODULE "armv8m-mpu")
+set(SCP_MODULE_TARGET "module-armv8m-mpu")
diff --git a/module/armv8m_mpu/include/mod_armv8m_mpu.h b/module/armv8m_mpu/include/mod_armv8m_mpu.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea19d4602991c56b0769e45213510c7189c861b9
--- /dev/null
+++ b/module/armv8m_mpu/include/mod_armv8m_mpu.h
@@ -0,0 +1,75 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MOD_ARMV8M_MPU_H
+#define MOD_ARMV8M_MPU_H
+
+#include <fmw_cmsis.h>
+
+#include <stddef.h>
+
+/*!
+ * \ingroup GroupModules
+ * \addtogroup GroupMPUARMv8M MPU (ARMv8-M)
+ * \{
+ */
+
+/*!
+ * \brief MPU_MAIR registers indices.
+ */
+enum mod_armv8m_mpu_attr_id {
+    MPU_ATTR_0,
+    MPU_ATTR_1,
+    MPU_ATTR_2,
+    MPU_ATTR_3,
+    MPU_ATTR_4,
+    MPU_ATTR_5,
+    MPU_ATTR_6,
+    MPU_ATTR_7,
+    MPU_MAX_ATTR_COUNT,
+};
+
+/*!
+ * \brief Module configuration.
+ */
+struct mod_armv8m_mpu_config {
+    /*!
+     * \brief Number of MPU attributes.
+     */
+    uint8_t attributes_count;
+
+    /*!
+     * \brief Pointer to array of MPU attributes.
+     */
+    const uint8_t *attributes;
+
+    /*!
+     * \brief First region number.
+     */
+    uint32_t first_region_number;
+
+    /*!
+     * \brief Number of MPU regions.
+     */
+    uint32_t region_count;
+
+    /*!
+     * \brief Pointer to array of MPU regions.
+     *
+     * \details Documentation for the \c ARM_MPU_Region_t can be found in the
+     *      CMSIS 5 documentation for the ARMv8-M MPU.
+     *
+     * \see http://arm-software.github.io/CMSIS_5/General/html/index.html
+     */
+    const ARM_MPU_Region_t *regions;
+};
+
+/*!
+ * \}
+ */
+
+#endif /* MOD_ARMV8M_MPU_H */
diff --git a/module/armv8m_mpu/src/mod_armv8m_mpu.c b/module/armv8m_mpu/src/mod_armv8m_mpu.c
new file mode 100644
index 0000000000000000000000000000000000000000..58dbe822111e12c383a869134cb4d8c900079c63
--- /dev/null
+++ b/module/armv8m_mpu/src/mod_armv8m_mpu.c
@@ -0,0 +1,54 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "mod_armv8m_mpu.h"
+
+#include <fwk_assert.h>
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <fwk_status.h>
+
+#include <fmw_cmsis.h>
+
+static int armv8m_mpu_init(
+    fwk_id_t module_id,
+    unsigned int element_count,
+    const void *data)
+{
+    const struct mod_armv8m_mpu_config *config;
+    uint8_t attr_index;
+    int status;
+
+    fwk_assert(element_count == 0);
+    fwk_assert(data != NULL);
+
+    config = data;
+
+    if (config->attributes_count <= (uint8_t)MPU_MAX_ATTR_COUNT) {
+        ARM_MPU_Disable();
+
+        for (attr_index = 0U; attr_index < config->attributes_count;
+             attr_index++) {
+            ARM_MPU_SetMemAttr(attr_index, config->attributes[attr_index]);
+        }
+        ARM_MPU_Load(
+            config->first_region_number, config->regions, config->region_count);
+        ARM_MPU_Enable(MPU_CTRL_HFNMIENA_Msk);
+
+        status = FWK_SUCCESS;
+    } else {
+        status = FWK_E_RANGE;
+    }
+
+    return status;
+}
+
+/* Module description */
+const struct fwk_module module_armv8m_mpu = {
+    .type = FWK_MODULE_TYPE_DRIVER,
+    .init = armv8m_mpu_init,
+};
diff --git a/product/juno/include/fmw_cmsis.h b/product/juno/include/fmw_cmsis.h
index 94f831858122dc4dbe25b1af870bf50bdbf7ef71..2f85d6b213f8dfd346dd7757b75fcd7d460ab602 100644
--- a/product/juno/include/fmw_cmsis.h
+++ b/product/juno/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,10 +11,11 @@
 #include <stdint.h>
 
 #define __CHECK_DEVICE_DEFINES
-#define __CM3_REV 0x0201
-#define __MPU_PRESENT 1
-#define __NVIC_PRIO_BITS 3
-#define __Vendor_SysTickConfig 0
+#define __CM3_REV              0x0201U
+#define __MPU_PRESENT          1U
+#define __NVIC_PRIO_BITS       3U
+#define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/juno/scp_ramfw/Firmware.cmake b/product/juno/scp_ramfw/Firmware.cmake
index 06d99869469804eb0eea959d67ea6ff2cca28118..12836fec58cee2dbd6f5821b55eee0705ab391d2 100644
--- a/product/juno/scp_ramfw/Firmware.cmake
+++ b/product/juno/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -14,7 +14,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
diff --git a/product/juno/scp_romfw/Firmware.cmake b/product/juno/scp_romfw/Firmware.cmake
index df01f2863e88dff5e495557e68ad472a29ede68b..b157cb33968d863226b629523ce1b3cfc808b037 100644
--- a/product/juno/scp_romfw/Firmware.cmake
+++ b/product/juno/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU")
 set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY TRUE)
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS TRUE)
 
diff --git a/product/juno/scp_romfw_bypass/Firmware.cmake b/product/juno/scp_romfw_bypass/Firmware.cmake
index 9a150d8a47d74d18b03dd7954096c4d734bb0ece..fd704a37978a99d5be44f39b4ffc1caa9313f647 100644
--- a/product/juno/scp_romfw_bypass/Firmware.cmake
+++ b/product/juno/scp_romfw_bypass/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -15,7 +15,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS TRUE)
 
diff --git a/product/morello/include/fmw_cmsis_mcp.h b/product/morello/include/fmw_cmsis_mcp.h
index 469d5456ce3eeff394367a4a258e2da00bcf6e61..18f775a192b080e98efe53d95c5d73324910fd6d 100644
--- a/product/morello/include/fmw_cmsis_mcp.h
+++ b/product/morello/include/fmw_cmsis_mcp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 #define MCP_WDOG_IRQ FWK_INTERRUPT_NMI /* MCP Watchdog (SP805) */
 
diff --git a/product/morello/include/fmw_cmsis_scp.h b/product/morello/include/fmw_cmsis_scp.h
index abd1cd8a0d24cd3cff134b285b4aac7c55988f25..61dd3eb4e03215345a63e3e7ac5d427c06c566da 100644
--- a/product/morello/include/fmw_cmsis_scp.h
+++ b/product/morello/include/fmw_cmsis_scp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 #define SCP_WDOG_IRQ FWK_INTERRUPT_NMI /* SCP Watchdog (SP805) */
 
diff --git a/product/morello/mcp_ramfw_fvp/Firmware.cmake b/product/morello/mcp_ramfw_fvp/Firmware.cmake
index d97e51e01352ee5303ba872bc5a428654c9e65e0..1999bf30947656f130d3c1211330516df3984a7c 100644
--- a/product/morello/mcp_ramfw_fvp/Firmware.cmake
+++ b/product/morello/mcp_ramfw_fvp/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -14,7 +14,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
diff --git a/product/morello/mcp_ramfw_soc/Firmware.cmake b/product/morello/mcp_ramfw_soc/Firmware.cmake
index af0d0f1b9c23276ea8593fe352b901e1bf021416..976dce2e04c06278db4b19d1f34e085a31601135 100644
--- a/product/morello/mcp_ramfw_soc/Firmware.cmake
+++ b/product/morello/mcp_ramfw_soc/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -14,7 +14,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
diff --git a/product/morello/mcp_romfw/Firmware.cmake b/product/morello/mcp_romfw/Firmware.cmake
index d563b099cbe7ab90406ab6d074e3f249eb55656f..1baf4823300c10562b3548deb33c3b81e95165e8 100644
--- a/product/morello/mcp_romfw/Firmware.cmake
+++ b/product/morello/mcp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_rom")
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip")
diff --git a/product/morello/scp_ramfw_fvp/Firmware.cmake b/product/morello/scp_ramfw_fvp/Firmware.cmake
index 0774229e908a1790a54c07ed38986c2b34801e5f..9ec40f5f402d0db98239f705736d550e7fb3e0cf 100644
--- a/product/morello/scp_ramfw_fvp/Firmware.cmake
+++ b/product/morello/scp_ramfw_fvp/Firmware.cmake
@@ -19,7 +19,7 @@ set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
diff --git a/product/morello/scp_ramfw_soc/Firmware.cmake b/product/morello/scp_ramfw_soc/Firmware.cmake
index 663648f7ffe41f5156df1a96e674d7e927b8ecfd..fc81c6b03eb0c54bace360539f77fb47c1994718 100644
--- a/product/morello/scp_ramfw_soc/Firmware.cmake
+++ b/product/morello/scp_ramfw_soc/Firmware.cmake
@@ -19,7 +19,7 @@ set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
diff --git a/product/morello/scp_romfw/Firmware.cmake b/product/morello/scp_romfw/Firmware.cmake
index edd30b80f1478f53dcd1bfd4f5f6bbd8062ad785..dc57d5f14d675f20a33408582aa2fd26f221e328 100644
--- a/product/morello/scp_romfw/Firmware.cmake
+++ b/product/morello/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_rom")
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip")
diff --git a/product/n1sdp/include/fmw_cmsis_mcp.h b/product/n1sdp/include/fmw_cmsis_mcp.h
index acceb6b0180cc902add880f257b114bbf26ee35a..6b32a332aa8b51cd1c5440b44213bf09c5aef4a0 100644
--- a/product/n1sdp/include/fmw_cmsis_mcp.h
+++ b/product/n1sdp/include/fmw_cmsis_mcp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 typedef enum IRQn {
diff --git a/product/n1sdp/include/fmw_cmsis_scp.h b/product/n1sdp/include/fmw_cmsis_scp.h
index 31185689bda0c1a93f7531ca449bcc4b78eff2c7..72c79530b891d2173fa21a05adbb56f687dc6885 100644
--- a/product/n1sdp/include/fmw_cmsis_scp.h
+++ b/product/n1sdp/include/fmw_cmsis_scp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/n1sdp/mcp_ramfw/Firmware.cmake b/product/n1sdp/mcp_ramfw/Firmware.cmake
index 491e9dd5798f1f4783dd68915f7b5626ecfbd38b..1bbedb035fb16051e2d7fa4e9905a196658a9560 100644
--- a/product/n1sdp/mcp_ramfw/Firmware.cmake
+++ b/product/n1sdp/mcp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
diff --git a/product/n1sdp/mcp_romfw/Firmware.cmake b/product/n1sdp/mcp_romfw/Firmware.cmake
index e4b304b8bb9c37ee357a97c0ef199f1c07bf8b0c..c12c16ccd289478d3978f6295b4db2490ad7899f 100644
--- a/product/n1sdp/mcp_romfw/Firmware.cmake
+++ b/product/n1sdp/mcp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -19,7 +19,7 @@ set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
diff --git a/product/n1sdp/scp_ramfw/Firmware.cmake b/product/n1sdp/scp_ramfw/Firmware.cmake
index f97151f0a9142fca94c75751ab927306c34f9399..422ae6714a10f42c48010be2ac18cadedd7666a5 100644
--- a/product/n1sdp/scp_ramfw/Firmware.cmake
+++ b/product/n1sdp/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip")
 
diff --git a/product/n1sdp/scp_romfw/Firmware.cmake b/product/n1sdp/scp_romfw/Firmware.cmake
index 3c79a9ffd5e4561eff60ad1ca8d61d937d7456b2..1c48a22d9720b8763e00076a373459948f3532a7 100644
--- a/product/n1sdp/scp_romfw/Firmware.cmake
+++ b/product/n1sdp/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/fip")
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/n1sdp_rom")
diff --git a/product/rdfremont/include/fmw_arch.h b/product/rdfremont/include/fmw_arch.h
new file mode 100644
index 0000000000000000000000000000000000000000..cbd92b9e0a441776e04b778ec50f59ea4798fd0d
--- /dev/null
+++ b/product/rdfremont/include/fmw_arch.h
@@ -0,0 +1,17 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FMW_ARCH_H
+#define FMW_ARCH_H
+/*
+ * Suspend feature is disabled until the whole system
+ * ( LCP,MCP and SCPs ) become available to wakeup
+ * the LCP.
+ */
+#define FMW_DISABLE_ARCH_SUSPEND 1
+
+#endif /* FMW_ARCH_H */
diff --git a/product/rdfremont/include/fmw_cmsis_lcp.h b/product/rdfremont/include/fmw_cmsis_lcp.h
new file mode 100644
index 0000000000000000000000000000000000000000..bced17f75356775a6ddd6307b43de985c1eb9f72
--- /dev/null
+++ b/product/rdfremont/include/fmw_cmsis_lcp.h
@@ -0,0 +1,56 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FMW_CMSIS_LCP_H
+#define FMW_CMSIS_LCP_H
+
+#include <stdint.h>
+
+#define __CHECK_DEVICE_DEFINES
+#define __CM55_REV             0x0000U
+#define __FPU_PRESENT          0U
+#define __MPU_PRESENT          1U
+#define __VTOR_PRESENT         1U
+#define __PMU_PRESENT          0U
+#define __DSP_PRESENT          0U
+#define __ICACHE_PRESENT       0U
+#define __DCACHE_PRESENT       0U
+#define __DTCM_PRESENT         0U
+#define __NVIC_PRIO_BITS       3U
+#define __SAUREGION_PRESENT    0U
+#define __Vendor_SysTickConfig 0U
+
+typedef enum IRQn {
+    Reset_IRQn = -15,
+    NonMaskableInt_IRQn = -14,
+    HardFault_IRQn = -13,
+    MemoryManagement_IRQn = -12,
+    BusFault_IRQn = -11,
+    UsageFault_IRQn = -10,
+    SecureFault_IRQn = -9,
+    SVCall_IRQn = -5,
+    DebugMonitor_IRQn = -4,
+    PendSV_IRQn = -2,
+    SysTick_IRQn = -1,
+
+    WDG_RST_RQST_IRQ = 0, /* Watchdog reset request */
+    WDG_INT_IRQ = 1, /* Watchdog interrupt */
+    RESERVED2_IRQ = 2, /* Reserved */
+    TIMER_IRQ = 3, /* Timer */
+    RESERVED4_IRQ = 4, /* Reserved */
+    RESERVED5_IRQ = 5, /* Reserved */
+    RESERVED6_IRQ = 6, /* Reserved */
+    RESERVED7_IRQ = 7, /* Reserved */
+    RESERVED8_IRQ = 8, /* Reserved */
+    RESERVED9_IRQ = 9, /* Reserved */
+
+    IRQn_MAX = INT16_MAX,
+} IRQn_Type;
+
+#include <core_cm55.h>
+
+#endif /* FMW_CMSIS_LCP_H */
diff --git a/product/rdfremont/include/fmw_io.h b/product/rdfremont/include/fmw_io.h
new file mode 100644
index 0000000000000000000000000000000000000000..57286d4ee90264174fe84bb88285be8b793c487f
--- /dev/null
+++ b/product/rdfremont/include/fmw_io.h
@@ -0,0 +1,17 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FMW_IO_H
+#define FMW_IO_H
+
+#include <fwk_id.h>
+#include <fwk_module_idx.h>
+
+#define FMW_IO_STDIN_ID  FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0)
+#define FMW_IO_STDOUT_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0)
+
+#endif /* FMW_IO_H */
diff --git a/product/rdfremont/include/lcp_device.h b/product/rdfremont/include/lcp_device.h
new file mode 100644
index 0000000000000000000000000000000000000000..5b2331c0ed6036cea3194cd8c5fdad415447c831
--- /dev/null
+++ b/product/rdfremont/include/lcp_device.h
@@ -0,0 +1,36 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LCP_DEVICE_H
+#define LCP_DEVICE_H
+
+#include <lcp_mmap.h>
+
+#include <fmw_cmsis_lcp.h>
+
+#include <stdint.h>
+
+#define CTRL_ENABLE_POS      0U
+#define CTRL_EXTR_EN_POS     1U
+#define CTRL_EXTR_IS_CLK_POS 2U
+#define CTRL_INT_EN_POS      3U
+
+#define CTRL_ENABLE_MASK      (1UL << CTRL_ENABLE_POS)
+#define CTRL_EXTR_EN_POS_MASK (1UL << CTRL_EXTR_EN_POS)
+#define CTRL_EXTR_IS_CLK_MASK (1UL << CTRL_EXTR_IS_CLK_POS)
+#define CTRL_INT_EN_MASK      (1UL << CTRL_INT_EN_POS)
+
+struct lcp_timer_reg_str {
+    FWK_RW uint32_t CTRL;
+    FWK_RW uint32_t VALUE;
+    FWK_RW uint32_t RELOAD;
+    FWK_RW uint32_t INTSTATUS;
+};
+
+#define LCP_TIMER_REG_S ((struct lcp_timer_reg_str *)LCP_TIMER_BASE_S)
+
+#endif /* LCP_DEVICE_H */
diff --git a/product/rdfremont/include/lcp_mmap.h b/product/rdfremont/include/lcp_mmap.h
new file mode 100644
index 0000000000000000000000000000000000000000..81524345146ed72d95c7387b2295a35aa502087c
--- /dev/null
+++ b/product/rdfremont/include/lcp_mmap.h
@@ -0,0 +1,44 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     Software defined memory map for LCP core.
+ */
+
+#ifndef LCP_SOFTWARE_MMAP_H
+#define LCP_SOFTWARE_MMAP_H
+
+#include <fwk_macros.h>
+
+#define LCP_ITCM_SIZE (64 * 1024)
+#define LCP_DTCM_SIZE (64 * 1024)
+
+#define LCP_ITCM_NS_BASE 0x00000000
+#define LCP_ITCM_S_BASE  0x10000000
+#define LCP_DTCM_NS_BASE 0x20000000
+#define LCP_DTCM_S_BASE  0x30000000
+
+#define LCP_CORE_ITCM_REGION_START LCP_ITCM_NS_BASE
+#define LCP_CORE_ITCM_REGION_END   (LCP_ITCM_NS_BASE + LCP_ITCM_SIZE - 1)
+
+#define LCP_CORE_DTCM_REGION_START LCP_DTCM_NS_BASE
+#define LCP_CORE_DTCM_REGION_END   (LCP_DTCM_NS_BASE + LCP_DTCM_SIZE - 1)
+
+#define LCP_CORE_PERIPHERAL_REGION_START 0x30010000
+#define LCP_CORE_PERIPHERAL_REGION_END   0x6FFFFFFF
+
+#define LCP_SRAM_REGION_START 0x70000000
+#define LCP_SRAM_REGION_END   0xB007FFFF
+
+#define LCP_DEVICE_REGION_START 0xB0080000
+#define LCP_DEVICE_REGION_END   0xFFFFFFFF
+
+#define LCP_TIMER_BASE_NS UINT32_C(0x48000000)
+#define LCP_TIMER_BASE_S  UINT32_C(0x58000000)
+
+#define LCP_UART_BASE 0xB2000000
+
+#endif /* LCP_SOFTWARE_MMAP_H */
diff --git a/product/rdfremont/lcp_ramfw/CMakeLists.txt b/product/rdfremont/lcp_ramfw/CMakeLists.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4015892df09542178461dba05d51489d8b53cdff
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/CMakeLists.txt
@@ -0,0 +1,38 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+#
+# Create the firmware target.
+#
+
+add_executable(rdfremont-lcp)
+
+target_include_directories(
+    rdfremont-lcp PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../include"
+                    "${CMAKE_CURRENT_SOURCE_DIR}")
+
+# cmake-lint: disable=E1122
+
+target_sources(
+    rdfremont-lcp
+    PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv8m_mpu.c"
+            "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c")
+
+#
+# Some of our firmware includes require CMSIS.
+#
+
+target_link_libraries(rdfremont-lcp PUBLIC cmsis::core-m)
+
+#
+# We explicitly add the CMSIS include directories to our interface include
+# directories. Each module target adds these include directories to their own,
+# allowing them to include any firmware includes we expose.
+#
+
+target_include_directories(rdfremont-lcp
+    PUBLIC $<TARGET_PROPERTY:cmsis::core-m,INTERFACE_INCLUDE_DIRECTORIES>)
diff --git a/product/rdfremont/lcp_ramfw/Firmware.cmake b/product/rdfremont/lcp_ramfw/Firmware.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..32cfe9a0ac65becf2f89db9e0084adf53625d8fd
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/Firmware.cmake
@@ -0,0 +1,37 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+#
+# Configure the build system.
+#
+
+set(SCP_FIRMWARE "rdfremont-lcp")
+
+set(SCP_FIRMWARE_TARGET "rdfremont-lcp")
+
+set(SCP_TOOLCHAIN_INIT "GNU")
+
+set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
+
+set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
+
+set(SCP_ENABLE_IPO_INIT FALSE)
+
+set(SCP_ARCHITECTURE "arm-m")
+
+set(SCP_ENABLE_DEBUGGER_INIT FALSE)
+
+list(PREPEND SCP_MODULE_PATHS
+    "${CMAKE_CURRENT_LIST_DIR}/../module/mod_lcp_platform")
+
+# The order of the modules in the following list is the order in which the
+# modules are initialized, bound, started during the pre-runtime phase.
+# any change in the order will cause firmware initialization errors.
+
+list(APPEND SCP_MODULES "armv8m-mpu")
+list(APPEND SCP_MODULES "lcp-platform")
+list(APPEND SCP_MODULES "pl011")
diff --git a/product/rdfremont/lcp_ramfw/Toolchain-ArmClang.cmake b/product/rdfremont/lcp_ramfw/Toolchain-ArmClang.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..517a0679df730652396edabda9a76f6b667261cc
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/Toolchain-ArmClang.cmake
@@ -0,0 +1,20 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# cmake-lint: disable=C0301
+
+include_guard()
+
+set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp")
+
+set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi")
+set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi")
+set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi")
+
+include(
+    "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/ArmClang-Baremetal.cmake"
+)
diff --git a/product/rdfremont/lcp_ramfw/Toolchain-Clang.cmake b/product/rdfremont/lcp_ramfw/Toolchain-Clang.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..87ffe67a392e8fbffd3d6b13f0a1513165f09486
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/Toolchain-Clang.cmake
@@ -0,0 +1,17 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include_guard()
+
+set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp")
+
+set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi")
+set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi")
+set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi")
+
+include(
+    "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/Clang-Baremetal.cmake")
diff --git a/product/rdfremont/lcp_ramfw/Toolchain-GNU.cmake b/product/rdfremont/lcp_ramfw/Toolchain-GNU.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..2f620ced33a993e11993502c0149904df6cf426e
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/Toolchain-GNU.cmake
@@ -0,0 +1,18 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include_guard()
+
+set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp")
+set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-")
+
+set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi")
+set(CMAKE_C_COMPILER_TARGET "arm-none-eabi")
+set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi")
+
+include(
+    "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/GNU-Baremetal.cmake")
diff --git a/product/rdfremont/lcp_ramfw/config_armv8m_mpu.c b/product/rdfremont/lcp_ramfw/config_armv8m_mpu.c
new file mode 100644
index 0000000000000000000000000000000000000000..856ca8e3a38c0fecfb7ebb19a7b64ff60f3bceb8
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/config_armv8m_mpu.c
@@ -0,0 +1,86 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "lcp_mmap.h"
+#include "mod_armv8m_mpu.h"
+
+#include <fwk_macros.h>
+#include <fwk_module.h>
+
+#include <fmw_cmsis.h>
+
+static const uint8_t attributes[] = {
+    /* Device memory, non Gathering, non Re-ordering, non Early Write
+       Acknowledgement */
+    [MPU_ATTR_0] =
+        ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE),
+    /* Normal memory, non Cacheable */
+    [MPU_ATTR_1] =
+        ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE),
+};
+
+static const ARM_MPU_Region_t regions[] = {
+    {
+        /* LCP_CORE_TCM_REGION*/
+        .RBAR = ARM_MPU_RBAR(
+            LCP_CORE_ITCM_REGION_START, /* BASE */
+            ARM_MPU_SH_NON, /* SH */
+            0, /* RO */
+            0, /* NP */
+            0 /* XN */),
+        .RLAR = ARM_MPU_RLAR(LCP_CORE_ITCM_REGION_END, MPU_ATTR_1),
+    },
+    {
+        /* LCP_CORE_DTCM_REGION*/
+        .RBAR = ARM_MPU_RBAR(
+            LCP_CORE_DTCM_REGION_START, /* BASE */
+            ARM_MPU_SH_INNER, /* SH */
+            0, /* RO */
+            0, /* NP */
+            1 /* XN */),
+        .RLAR = ARM_MPU_RLAR(LCP_CORE_DTCM_REGION_END, MPU_ATTR_1),
+    },
+    {
+        /* LCP_CORE_PERIPERAL_REGION */
+        .RBAR = ARM_MPU_RBAR(
+            LCP_CORE_PERIPHERAL_REGION_START, /* BASE */
+            ARM_MPU_SH_NON, /* SH */
+            0, /* RO */
+            0, /* NP */
+            1 /* XN */),
+        .RLAR = ARM_MPU_RLAR(LCP_CORE_PERIPHERAL_REGION_END, MPU_ATTR_0),
+    },
+    {
+        /* LCP_SRAM_REGION*/
+        .RBAR = ARM_MPU_RBAR(
+            LCP_SRAM_REGION_START, /* BASE */
+            ARM_MPU_SH_OUTER, /* SH */
+            0, /* RO */
+            0, /* NP */
+            1 /* XN */),
+        .RLAR = ARM_MPU_RLAR(LCP_SRAM_REGION_END, MPU_ATTR_1),
+    },
+    {
+        /* LCP_DEVICE_REGION */
+        .RBAR = ARM_MPU_RBAR(
+            LCP_DEVICE_REGION_START, /* BASE */
+            ARM_MPU_SH_OUTER, /* SH */
+            0, /* RO */
+            0, /* NP */
+            1 /* XN */),
+        .RLAR = ARM_MPU_RLAR(LCP_DEVICE_REGION_END, MPU_ATTR_0),
+    },
+};
+
+const struct fwk_module_config config_armv8m_mpu = {
+    .data = &((struct mod_armv8m_mpu_config){
+        .region_count = FWK_ARRAY_SIZE(regions),
+        .regions = regions,
+        .attributes_count = FWK_ARRAY_SIZE(attributes),
+        .attributes = attributes,
+    }),
+};
diff --git a/product/rdfremont/lcp_ramfw/config_pl011.c b/product/rdfremont/lcp_ramfw/config_pl011.c
new file mode 100644
index 0000000000000000000000000000000000000000..b7e02046170cda51d782b1b627e108042754c409
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/config_pl011.c
@@ -0,0 +1,31 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "lcp_mmap.h"
+
+#include <mod_pl011.h>
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+
+struct fwk_module_config config_pl011 = {
+    .elements = FWK_MODULE_STATIC_ELEMENTS({
+        [0] = {
+            .name = "lcp-uart",
+            .data =
+                &(struct mod_pl011_element_cfg){
+                    .reg_base = LCP_UART_BASE,
+                    .baud_rate_bps = 115200,
+                    .clock_rate_hz = 24 * FWK_MHZ,
+                },
+        },
+
+        [1] = { 0 },
+    }),
+};
diff --git a/product/rdfremont/lcp_ramfw/fmw_cmsis.h b/product/rdfremont/lcp_ramfw/fmw_cmsis.h
new file mode 100644
index 0000000000000000000000000000000000000000..77a7ea19ef5dab43e5e5892ddcf2ce4593156d6b
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/fmw_cmsis.h
@@ -0,0 +1,15 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FMW_CMSIS_H
+#define FMW_CMSIS_H
+
+#include "fmw_cmsis_lcp.h"
+
+extern uint32_t SystemCoreClock;
+
+#endif /* FMW_CMSIS_H */
diff --git a/product/rdfremont/lcp_ramfw/fmw_memory.h b/product/rdfremont/lcp_ramfw/fmw_memory.h
new file mode 100644
index 0000000000000000000000000000000000000000..784f76bc73d9602618a34cfaea734fa2a5121c95
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/fmw_memory.h
@@ -0,0 +1,30 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     RAM firmware memory layout for the linker script.
+ */
+
+#ifndef FMW_MEMORY_H
+#define FMW_MEMORY_H
+
+#include "lcp_mmap.h"
+
+#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION
+
+/*
+ * RAM instruction memory
+ */
+#define FMW_MEM0_SIZE LCP_ITCM_SIZE
+#define FMW_MEM0_BASE LCP_ITCM_NS_BASE
+
+/*
+ * RAM data memory
+ */
+#define FMW_MEM1_SIZE LCP_DTCM_SIZE
+#define FMW_MEM1_BASE LCP_DTCM_NS_BASE
+
+#endif /* FMW_MEMORY_H */
diff --git a/product/rdfremont/lcp_ramfw/fmw_notification.h b/product/rdfremont/lcp_ramfw/fmw_notification.h
new file mode 100644
index 0000000000000000000000000000000000000000..ceffa17870468484594ca1e996c1ec10fd7c3838
--- /dev/null
+++ b/product/rdfremont/lcp_ramfw/fmw_notification.h
@@ -0,0 +1,16 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     RAM firmware notification configuration.
+ */
+
+#ifndef FMW_NOTIFICATION_H
+#define FMW_NOTIFICATION_H
+
+#define FMW_NOTIFICATION_MAX 128
+
+#endif /* FMW_NOTIFICATION_H */
diff --git a/product/rdfremont/module/mod_lcp_platform/CMakeLists.txt b/product/rdfremont/module/mod_lcp_platform/CMakeLists.txt
new file mode 100644
index 0000000000000000000000000000000000000000..f805e7711653258554e6fe9598a6615129c537b8
--- /dev/null
+++ b/product/rdfremont/module/mod_lcp_platform/CMakeLists.txt
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+add_library(${SCP_MODULE_TARGET} SCP_MODULE)
+
+target_sources(${SCP_MODULE_TARGET}
+               PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_lcp_platform.c")
diff --git a/product/rdfremont/module/mod_lcp_platform/Module.cmake b/product/rdfremont/module/mod_lcp_platform/Module.cmake
new file mode 100644
index 0000000000000000000000000000000000000000..2011d81aa604d2b3714227e35edb7e3695bcda38
--- /dev/null
+++ b/product/rdfremont/module/mod_lcp_platform/Module.cmake
@@ -0,0 +1,10 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set(SCP_MODULE "lcp-platform")
+
+set(SCP_MODULE_TARGET "module-lcp-platform")
diff --git a/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c b/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c
new file mode 100644
index 0000000000000000000000000000000000000000..df4715d8a4142009bbfe98ca4619f23f0a8c6238
--- /dev/null
+++ b/product/rdfremont/module/mod_lcp_platform/src/mod_lcp_platform.c
@@ -0,0 +1,69 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <lcp_device.h>
+
+#include <fwk_id.h>
+#include <fwk_interrupt.h>
+#include <fwk_log.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <fwk_status.h>
+
+#define MOD_NAME "[LCP_PLATFORM] "
+#define LCP_TIMER_RELOAD 0xFFFFFU
+
+volatile struct {
+    uint32_t counter;
+} lcp_platform_ctx;
+
+void timer_isr()
+{
+    lcp_platform_ctx.counter++;
+    /* clear interrupt flag */
+    LCP_TIMER_REG_S->INTSTATUS = 1U;
+}
+
+void mod_lcp_config_timer()
+{
+    LCP_TIMER_REG_S->CTRL = CTRL_ENABLE_MASK | CTRL_INT_EN_MASK;
+
+    LCP_TIMER_REG_S->RELOAD = LCP_TIMER_RELOAD;
+}
+
+static int mod_lcp_platform_init(
+    fwk_id_t module_id,
+    unsigned int element_count,
+    const void *unused)
+{
+    /* No elements support */
+    if (element_count > 0) {
+        return FWK_E_DATA;
+    }
+
+    return FWK_SUCCESS;
+}
+
+static int mod_lcp_platform_start(fwk_id_t id)
+{
+    fwk_interrupt_set_isr(TIMER_IRQ, timer_isr);
+
+    fwk_interrupt_enable(TIMER_IRQ);
+
+    mod_lcp_config_timer();
+
+    FWK_LOG_INFO(MOD_NAME "LCP RAM firmware initialized\n");
+
+    return FWK_SUCCESS;
+}
+
+const struct fwk_module module_lcp_platform = {
+    .type = FWK_MODULE_TYPE_SERVICE,
+    .init = mod_lcp_platform_init,
+    .start = mod_lcp_platform_start,
+};
+
+const struct fwk_module_config config_lcp_platform = { 0 };
diff --git a/product/rdfremont/product.mk b/product/rdfremont/product.mk
new file mode 100644
index 0000000000000000000000000000000000000000..346c0361e7d115a19774bcee4adee8016653f241
--- /dev/null
+++ b/product/rdfremont/product.mk
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platforms supported by the rdn1e1 product: RDN1E1.
+
+
+BS_PRODUCT_NAME := rdfremont
+BS_FIRMWARE_LIST := lcp_ramfw
diff --git a/product/rdn1e1/include/fmw_cmsis_mcp.h b/product/rdn1e1/include/fmw_cmsis_mcp.h
index 06aa786810eaa8331f84c557aecd0db86a92b4fa..5e2c0e358b2afcc9addc0468c8d6e891df22b27f 100644
--- a/product/rdn1e1/include/fmw_cmsis_mcp.h
+++ b/product/rdn1e1/include/fmw_cmsis_mcp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 typedef enum IRQn {
     Reset_IRQn = -15,
diff --git a/product/rdn1e1/include/fmw_cmsis_scp.h b/product/rdn1e1/include/fmw_cmsis_scp.h
index c331225d0612b469b8bdb8a585f6ba13350e8401..90328a9680f2fe7c67fcdf150ca69d13d008ba0e 100644
--- a/product/rdn1e1/include/fmw_cmsis_scp.h
+++ b/product/rdn1e1/include/fmw_cmsis_scp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/rdn1e1/mcp_ramfw/Firmware.cmake b/product/rdn1e1/mcp_ramfw/Firmware.cmake
index ba081eb4f2ad0dcdf23ec331095e672b7a401a8e..9609e043f2924be07820a169a39dd2e6eba8744d 100644
--- a/product/rdn1e1/mcp_ramfw/Firmware.cmake
+++ b/product/rdn1e1/mcp_ramfw/Firmware.cmake
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_DEBUGGER_INIT FALSE)
 
diff --git a/product/rdn1e1/mcp_romfw/Firmware.cmake b/product/rdn1e1/mcp_romfw/Firmware.cmake
index da8879bdd69165c65a7ad4b226ab04239dbce6b4..e17ffc5ba856fc44be301e443a9f91df41547b40 100644
--- a/product/rdn1e1/mcp_romfw/Firmware.cmake
+++ b/product/rdn1e1/mcp_romfw/Firmware.cmake
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/rdn1e1/scp_ramfw/Firmware.cmake b/product/rdn1e1/scp_ramfw/Firmware.cmake
index 88fdd0b472a0d3906aa184b5294860ef226b6c4d..87861385b51390b5703eaf06aaeb1746dd93f88e 100644
--- a/product/rdn1e1/scp_ramfw/Firmware.cmake
+++ b/product/rdn1e1/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -19,7 +19,7 @@ set(SCP_GENERATE_FLAT_BINARY_INIT TRUE)
 
 set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT TRUE)
 
diff --git a/product/rdn1e1/scp_romfw/Firmware.cmake b/product/rdn1e1/scp_romfw/Firmware.cmake
index d07c3c2dc4565bb75af6472613ebd16a5e3f0f27..963724bccc88c149a5b323bd4978635a8ae0965f 100644
--- a/product/rdn1e1/scp_romfw/Firmware.cmake
+++ b/product/rdn1e1/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/rdn2/include/fmw_cmsis.h b/product/rdn2/include/fmw_cmsis.h
index ee386ca273f3646f1e4bb4396858ee765b43cf70..6f8f0ce5f2405c3e544a2ae4fe443187cba4dafc 100644
--- a/product/rdn2/include/fmw_cmsis.h
+++ b/product/rdn2/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT         0U
 #define __NVIC_PRIO_BITS       3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/rdn2/mcp_ramfw/Firmware.cmake b/product/rdn2/mcp_ramfw/Firmware.cmake
index ee27c202dfd94d099a1402fe14fe66adfa93675a..e865d6d65defa7a575bed29aa594662976906f11 100644
--- a/product/rdn2/mcp_ramfw/Firmware.cmake
+++ b/product/rdn2/mcp_ramfw/Firmware.cmake
@@ -23,7 +23,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_DEBUGGER_INIT FALSE)
 
diff --git a/product/rdn2/mcp_romfw/Firmware.cmake b/product/rdn2/mcp_romfw/Firmware.cmake
index 21948ee548d7700fdb89ee09c148a7e916b10a45..7e76acbca3da04188e888507e91d126e7a118ef7 100644
--- a/product/rdn2/mcp_romfw/Firmware.cmake
+++ b/product/rdn2/mcp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NEWLIB_NANO FALSE)
 
diff --git a/product/rdn2/scp_ramfw/Firmware.cmake b/product/rdn2/scp_ramfw/Firmware.cmake
index aa6f29051b3d394abf21e698ddcb32a99a815d8a..e54f2349ecb728fbb77bca31659c18c18d3fa594 100644
--- a/product/rdn2/scp_ramfw/Firmware.cmake
+++ b/product/rdn2/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -20,7 +20,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NEWLIB_NANO FALSE)
 
diff --git a/product/rdn2/scp_romfw/Firmware.cmake b/product/rdn2/scp_romfw/Firmware.cmake
index a1c52a730edf0f038e12d8f34ffaf30b62ef4c1a..f082efe75cc7cf625d66ef8e331cb1b543ede325 100644
--- a/product/rdn2/scp_romfw/Firmware.cmake
+++ b/product/rdn2/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NEWLIB_NANO FALSE)
 
diff --git a/product/rdv1/include/fmw_cmsis.h b/product/rdv1/include/fmw_cmsis.h
index 90168af3b79e789e8ce30055669f9069875b2ae3..fe12b3d0c8f8fdf726d36364fc63eb7d67fa5e18 100644
--- a/product/rdv1/include/fmw_cmsis.h
+++ b/product/rdv1/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT         0U
 #define __NVIC_PRIO_BITS       3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 typedef enum IRQn {
diff --git a/product/rdv1/mcp_ramfw/Firmware.cmake b/product/rdv1/mcp_ramfw/Firmware.cmake
index 0aa041612aa6b16e632c83209c37e06d66ff1c61..d14ce26fb90da939b4949fb507dc103a170953e8 100644
--- a/product/rdv1/mcp_ramfw/Firmware.cmake
+++ b/product/rdv1/mcp_ramfw/Firmware.cmake
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_DEBUGGER_INIT FALSE)
 
diff --git a/product/rdv1/mcp_romfw/Firmware.cmake b/product/rdv1/mcp_romfw/Firmware.cmake
index c65c557c8a872ec8a8afbf1f6d93b3799231af6a..7a01c2b22302c2567b693de2bb4b1ce3553017e9 100755
--- a/product/rdv1/mcp_romfw/Firmware.cmake
+++ b/product/rdv1/mcp_romfw/Firmware.cmake
@@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU")
 set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY TRUE)
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS TRUE)
 
diff --git a/product/rdv1/scp_ramfw/Firmware.cmake b/product/rdv1/scp_ramfw/Firmware.cmake
index c0cf78e1888a33d438e81432571437bcc9d1b712..68e8203b916487f36046b76a6352f882a104be26 100755
--- a/product/rdv1/scp_ramfw/Firmware.cmake
+++ b/product/rdv1/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU")
 set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY TRUE)
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS TRUE)
 
diff --git a/product/rdv1/scp_romfw/Firmware.cmake b/product/rdv1/scp_romfw/Firmware.cmake
index 01b1ec3743fbc9bcede8cc67aa9ca74f4d12d8ea..8a25b7ecb605d3d0489da643eb26c427e047331c 100755
--- a/product/rdv1/scp_romfw/Firmware.cmake
+++ b/product/rdv1/scp_romfw/Firmware.cmake
@@ -13,7 +13,7 @@ set(SCP_TOOLCHAIN_INIT "GNU")
 set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}")
 
 set(SCP_GENERATE_FLAT_BINARY TRUE)
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_NOTIFICATIONS TRUE)
 
diff --git a/product/rdv1mc/include/fmw_cmsis.h b/product/rdv1mc/include/fmw_cmsis.h
index ee386ca273f3646f1e4bb4396858ee765b43cf70..6f8f0ce5f2405c3e544a2ae4fe443187cba4dafc 100644
--- a/product/rdv1mc/include/fmw_cmsis.h
+++ b/product/rdv1mc/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT         0U
 #define __NVIC_PRIO_BITS       3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/rdv1mc/mcp_ramfw/Firmware.cmake b/product/rdv1mc/mcp_ramfw/Firmware.cmake
index 3c7e31d8a4267cd8d53fcd7f95bb6c34a40e92fb..a69fab3de5900761e520491d87e909ba17460007 100644
--- a/product/rdv1mc/mcp_ramfw/Firmware.cmake
+++ b/product/rdv1mc/mcp_ramfw/Firmware.cmake
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_DEBUGGER_INIT FALSE)
 
diff --git a/product/rdv1mc/mcp_romfw/Firmware.cmake b/product/rdv1mc/mcp_romfw/Firmware.cmake
index a4369a86883a33932913c92d403d4be56110a1ab..4ac81f39cea675a1d35a3802ba698d175ce0c44c 100755
--- a/product/rdv1mc/mcp_romfw/Firmware.cmake
+++ b/product/rdv1mc/mcp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/rdv1mc/scp_ramfw/Firmware.cmake b/product/rdv1mc/scp_ramfw/Firmware.cmake
index 0d752a4fbdc397cc8ec22b4274cd47b43427c49a..c0ee89b26defa05d259d8f9e1e4dc99c21675c6a 100755
--- a/product/rdv1mc/scp_ramfw/Firmware.cmake
+++ b/product/rdv1mc/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS
      "${CMAKE_CURRENT_LIST_DIR}/../module/platform_system")
diff --git a/product/rdv1mc/scp_romfw/Firmware.cmake b/product/rdv1mc/scp_romfw/Firmware.cmake
index 5236b66b21c0ccae58cfec27bc01fab3b21a5598..b76268d1c7243a32218e1f9a6f0b4b90722b4267 100755
--- a/product/rdv1mc/scp_romfw/Firmware.cmake
+++ b/product/rdv1mc/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/sgi575/include/fmw_cmsis_mcp.h b/product/sgi575/include/fmw_cmsis_mcp.h
index cf89f6398a7e9841dda23296e1a61b76dfabcd5a..2d212a522c1be5ca914d4b6bb0ced811351aefc7 100644
--- a/product/sgi575/include/fmw_cmsis_mcp.h
+++ b/product/sgi575/include/fmw_cmsis_mcp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 typedef enum IRQn {
     Reset_IRQn = -15,
diff --git a/product/sgi575/include/fmw_cmsis_scp.h b/product/sgi575/include/fmw_cmsis_scp.h
index 180d8430758c1c5e5ae5d6c71e8564006025285b..fc9f3a3049b8f8652af5fe69b0509e2386655ff3 100644
--- a/product/sgi575/include/fmw_cmsis_scp.h
+++ b/product/sgi575/include/fmw_cmsis_scp.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 typedef enum IRQn {
     Reset_IRQn = -15,
diff --git a/product/sgi575/mcp_ramfw/Firmware.cmake b/product/sgi575/mcp_ramfw/Firmware.cmake
index ab78a79b1326b940f39f37a07a842e61171283e7..be14064116ec9babbe962a18e21b51bdbf32a495 100644
--- a/product/sgi575/mcp_ramfw/Firmware.cmake
+++ b/product/sgi575/mcp_ramfw/Firmware.cmake
@@ -17,7 +17,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 set(SCP_ENABLE_DEBUGGER_INIT FALSE)
 
diff --git a/product/sgi575/mcp_romfw/Firmware.cmake b/product/sgi575/mcp_romfw/Firmware.cmake
index e1d6b0bde8c3ad437565173c7082cdeac8351d0d..91b215009c4028e2697e0bf9f897eefe29305922 100644
--- a/product/sgi575/mcp_romfw/Firmware.cmake
+++ b/product/sgi575/mcp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,7 +18,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT FALSE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/sgi575/scp_ramfw/Firmware.cmake b/product/sgi575/scp_ramfw/Firmware.cmake
index f451583db3dbb74db94827c50632750b6d371384..44fc997e5cde724b8ce160ffd138b61a2fe8cf91 100644
--- a/product/sgi575/scp_ramfw/Firmware.cmake
+++ b/product/sgi575/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,7 +18,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS
      "${CMAKE_CURRENT_LIST_DIR}/../module/sgi575_system")
diff --git a/product/sgi575/scp_romfw/Firmware.cmake b/product/sgi575/scp_romfw/Firmware.cmake
index 43cf29c5c1081031cddae89e9fa4a1b83fe87e0e..f2beea8e336c86df3be91b2e65a09bf65f0b6dd8 100644
--- a/product/sgi575/scp_romfw/Firmware.cmake
+++ b/product/sgi575/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,7 +18,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT FALSE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/sgm775/include/fmw_cmsis.h b/product/sgm775/include/fmw_cmsis.h
index 934203779d2ab052d54fd814e75eb23b851616ad..6e0fc77b0600e71bf2273723338fbba73b281288 100644
--- a/product/sgm775/include/fmw_cmsis.h
+++ b/product/sgm775/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,10 +11,11 @@
 #include <stdint.h>
 
 #define __CHECK_DEVICE_DEFINES
-#define __CM3_REV 0x0201
-#define __MPU_PRESENT 1
-#define __NVIC_PRIO_BITS 3
-#define __Vendor_SysTickConfig 0
+#define __CM3_REV              0x0201U
+#define __MPU_PRESENT          1U
+#define __NVIC_PRIO_BITS       3U
+#define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/sgm775/scp_ramfw/Firmware.cmake b/product/sgm775/scp_ramfw/Firmware.cmake
index 6ee05605763055cb3948a4b98a278ef562a5367f..ab8c3ff5594eec1dbaf694862eb643cc1e37628c 100644
--- a/product/sgm775/scp_ramfw/Firmware.cmake
+++ b/product/sgm775/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -19,7 +19,7 @@ set(SCP_ENABLE_NOTIFICATIONS TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS
      "${CMAKE_CURRENT_LIST_DIR}/../module/sgm775_ddr_phy500")
diff --git a/product/sgm775/scp_romfw/Firmware.cmake b/product/sgm775/scp_romfw/Firmware.cmake
index 7abaf93e609f8977fecc69cfebe39302e439f6a9..21db9710ef46702fbfdcc108855cfdf37e7ce914 100644
--- a/product/sgm775/scp_romfw/Firmware.cmake
+++ b/product/sgm775/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,7 +18,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS FALSE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/sgm776/include/fmw_cmsis.h b/product/sgm776/include/fmw_cmsis.h
index 4db3fda901d320de5de39223981e3158837b3656..62f635b1c7b6636c563a08c2a29be08ac43973d1 100644
--- a/product/sgm776/include/fmw_cmsis.h
+++ b/product/sgm776/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,10 +11,11 @@
 #include <stdint.h>
 
 #define __CHECK_DEVICE_DEFINES
-#define __CM3_REV 0x0201
-#define __MPU_PRESENT 1
-#define __NVIC_PRIO_BITS 3
-#define __Vendor_SysTickConfig 0
+#define __CM3_REV              0x0201U
+#define __MPU_PRESENT          1U
+#define __NVIC_PRIO_BITS       3U
+#define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 typedef enum IRQn {
diff --git a/product/sgm776/scp_ramfw/Firmware.cmake b/product/sgm776/scp_ramfw/Firmware.cmake
index 7a357a30be99e52eecf5071c01e1b747fe8c21b2..641c7290d71450b42c65c709ce041438e27f81c4 100644
--- a/product/sgm776/scp_ramfw/Firmware.cmake
+++ b/product/sgm776/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,7 +18,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS
      "${CMAKE_CURRENT_LIST_DIR}/../module/sgm776_system")
diff --git a/product/sgm776/scp_romfw/Firmware.cmake b/product/sgm776/scp_romfw/Firmware.cmake
index f3ee2b6a302f341c9504fbcc8df8abef18cd1c6d..52f1fbed62cfcb51bc81dca50676d9482dabf6e4 100644
--- a/product/sgm776/scp_romfw/Firmware.cmake
+++ b/product/sgm776/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,7 +18,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 # The order of the modules in the following list is the order in which the
 # modules are initialized, bound, started during the pre-runtime phase.
diff --git a/product/synquacer/include/fmw_cmsis.h b/product/synquacer/include/fmw_cmsis.h
index 4ae0dfb30d744f6f7d0106f618adf905a98d2f2c..f530295c1fc7b045b6d8f80b6a8661054e9f2054 100644
--- a/product/synquacer/include/fmw_cmsis.h
+++ b/product/synquacer/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,10 +11,11 @@
 #include <stdint.h>
 
 #define __CHECK_DEVICE_DEFINES
-#define __CM3_REV 0x0201
-#define __MPU_PRESENT 1
-#define __NVIC_PRIO_BITS 3
-#define __Vendor_SysTickConfig 0
+#define __CM3_REV              0x0201U
+#define __MPU_PRESENT          1U
+#define __NVIC_PRIO_BITS       3U
+#define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock;
 
diff --git a/product/synquacer/scp_ramfw/Firmware.cmake b/product/synquacer/scp_ramfw/Firmware.cmake
index 181b45059247bd15234b15808a7c5f90f13494f6..edfecf23f90ccaae9e2be43c8d6910ca032e972d 100644
--- a/product/synquacer/scp_ramfw/Firmware.cmake
+++ b/product/synquacer/scp_ramfw/Firmware.cmake
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS
      "${CMAKE_CURRENT_LIST_DIR}/../module/scmi_vendor_ext")
diff --git a/product/synquacer/scp_romfw/Firmware.cmake b/product/synquacer/scp_romfw/Firmware.cmake
index 5a5a0cdce91b61bc475fae5c06cbe982e644b465..16a9f4bcefaf42d08ebd69e830f1a4c451fca06d 100644
--- a/product/synquacer/scp_romfw/Firmware.cmake
+++ b/product/synquacer/scp_romfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS
      "${CMAKE_CURRENT_LIST_DIR}/../module/synquacer_pik_clock")
diff --git a/product/tc0/include/fmw_cmsis.h b/product/tc0/include/fmw_cmsis.h
index c7add15cbfc0cfeac98a5c44ad6ca57821f0206c..8c4a1320097ed3b1b6d1da1bb43b42d56c8913e6 100644
--- a/product/tc0/include/fmw_cmsis.h
+++ b/product/tc0/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT 0U
 #define __NVIC_PRIO_BITS 3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/tc0/scp_ramfw/Firmware.cmake b/product/tc0/scp_ramfw/Firmware.cmake
index 11d8eaab06317646f0268665d2204db539b682bf..efc8c31929a32b8fa447437d825873cc0dc736e2 100644
--- a/product/tc0/scp_ramfw/Firmware.cmake
+++ b/product/tc0/scp_ramfw/Firmware.cmake
@@ -29,7 +29,7 @@ set(SCP_ENABLE_PLUGIN_HANDLER_INIT FALSE)
 
 set(SCP_PLATFORM_VARIANT_INIT 0)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/tc0_system")
 
diff --git a/product/tc0/scp_romfw/Firmware.cmake b/product/tc0/scp_romfw/Firmware.cmake
index ab4468bef3b25cec74bc8df5139b98820f7e36a7..7f6586c2b62bc05f65a26ed0e8139de99ee39cd4 100644
--- a/product/tc0/scp_romfw/Firmware.cmake
+++ b/product/tc0/scp_romfw/Firmware.cmake
@@ -23,7 +23,7 @@ set(SCP_ENABLE_IPO_INIT FALSE)
 
 set(SCP_PLATFORM_VARIANT_INIT 0)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/cmn_booker")
 
diff --git a/product/tc1/include/fmw_cmsis.h b/product/tc1/include/fmw_cmsis.h
index a1925c7399abac8eb916d0e50316a587f299503d..f2f78fb600e2803dabcd25686ed75af75c7b47a0 100644
--- a/product/tc1/include/fmw_cmsis.h
+++ b/product/tc1/include/fmw_cmsis.h
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 #define __DTCM_PRESENT         0U
 #define __NVIC_PRIO_BITS       3U
 #define __Vendor_SysTickConfig 0U
+#define __VTOR_PRESENT         1U
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
 
diff --git a/product/tc1/scp_ramfw/Firmware.cmake b/product/tc1/scp_ramfw/Firmware.cmake
index f3a37172c5bb70badbe8ab17e575aeb222991a0a..13d66ed61711ac63b168c51acdfd09bff554fb45 100644
--- a/product/tc1/scp_ramfw/Firmware.cmake
+++ b/product/tc1/scp_ramfw/Firmware.cmake
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -23,7 +23,7 @@ set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/tc1_system")
 
diff --git a/product/tc1/scp_romfw/Firmware.cmake b/product/tc1/scp_romfw/Firmware.cmake
index fee95bd73f292cf0d0c84ad6060fdb8a5b1c6af5..1a521a609f8932d00dbf11aeff09e527ad9dde99 100644
--- a/product/tc1/scp_romfw/Firmware.cmake
+++ b/product/tc1/scp_romfw/Firmware.cmake
@@ -21,7 +21,7 @@ set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE)
 
 set(SCP_ENABLE_IPO_INIT FALSE)
 
-set(SCP_ARCHITECTURE "armv7-m")
+set(SCP_ARCHITECTURE "arm-m")
 
 list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/cmn_booker")