From e5d1c78a6a1c67c73311ab33bfbe64170c6b5443 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Wed, 20 Mar 2019 16:38:09 +0530 Subject: [PATCH 1/3] n1sdp: add PCIe/CCIX slave AXI64 I/O space in CMN600 config Change-Id: Iddae693c8d9101e1bff1163a8d2931259fd3897f Signed-off-by: Manoj Kumar --- product/n1sdp/scp_ramfw/config_cmn600.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/product/n1sdp/scp_ramfw/config_cmn600.c b/product/n1sdp/scp_ramfw/config_cmn600.c index 9eec674c0..507dac0cb 100644 --- a/product/n1sdp/scp_ramfw/config_cmn600.c +++ b/product/n1sdp/scp_ramfw/config_cmn600.c @@ -117,6 +117,26 @@ static const struct mod_cmn600_memory_region_map mmap[] = { .type = MOD_CMN600_MEMORY_REGION_TYPE_IO, .node_id = NODE_ID_HND, }, + { + /* + * Peripherals + * Map: 0x20_0000_0000 - 0x3F_FFFF_FFFF (128 GB) + */ + .base = UINT64_C(0x2000000000), + .size = UINT64_C(128) * FWK_GIB, + .type = MOD_CMN600_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x40_0000_0000 - 0x7F_FFFF_FFFF (256 GB) + */ + .base = UINT64_C(0x4000000000), + .size = UINT64_C(256) * FWK_GIB, + .type = MOD_CMN600_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, }; const struct fwk_module_config config_cmn600 = { -- GitLab From 73799d82f560fc02c317f3e4118101cc4a64a7a0 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 1 Apr 2019 15:24:38 +0530 Subject: [PATCH 2/3] n1sdp: tune system clock frequencies for SoC Change-Id: Ib4caadcf8a896ca503cb8847516c97d0fab5db05 Signed-off-by: Manoj Kumar --- product/n1sdp/include/n1sdp_system_clock.h | 2 +- product/n1sdp/scp_ramfw/config_clock.h | 54 +++++++++++----------- product/n1sdp/scp_ramfw/config_pik_clock.c | 12 ++--- 3 files changed, 34 insertions(+), 34 deletions(-) diff --git a/product/n1sdp/include/n1sdp_system_clock.h b/product/n1sdp/include/n1sdp_system_clock.h index 83a5325dd..030293ac7 100644 --- a/product/n1sdp/include/n1sdp_system_clock.h +++ b/product/n1sdp/include/n1sdp_system_clock.h @@ -10,7 +10,7 @@ #include -#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) +#define CLOCK_RATE_REFCLK (50UL * FWK_MHZ) #define CLOCK_RATE_SYSPLLCLK (2400UL * FWK_MHZ) #endif /* N1SDP_SYSTEM_CLOCK_H */ diff --git a/product/n1sdp/scp_ramfw/config_clock.h b/product/n1sdp/scp_ramfw/config_clock.h index 08ef1408a..61111b867 100644 --- a/product/n1sdp/scp_ramfw/config_clock.h +++ b/product/n1sdp/scp_ramfw/config_clock.h @@ -13,74 +13,74 @@ /* * SCC & PIK clock rates. */ -#define SCC_CLK_RATE_IOFPGA_TMIF2XCLK (200 * FWK_MHZ) -#define SCC_CLK_RATE_IOFPGA_TSIF2XCLK (200 * FWK_MHZ) +#define SCC_CLK_RATE_IOFPGA_TMIF2XCLK (120 * FWK_MHZ) +#define SCC_CLK_RATE_IOFPGA_TSIF2XCLK (120 * FWK_MHZ) #define SCC_CLK_RATE_SYSAPBCLK (120 * FWK_MHZ) #define SCC_CLK_RATE_SCPNICCLK (300 * FWK_MHZ) #define SCC_CLK_RATE_SCPI2CCLK (100 * FWK_MHZ) -#define SCC_CLK_RATE_SCPQSPICLK (480 * FWK_MHZ) +#define SCC_CLK_RATE_SCPQSPICLK (50 * FWK_MHZ) #define SCC_CLK_RATE_SENSORCLK (100 * FWK_MHZ) #define SCC_CLK_RATE_MCPNICCLK (300 * FWK_MHZ) #define SCC_CLK_RATE_MCPI2CCLK (100 * FWK_MHZ) -#define SCC_CLK_RATE_MCPQSPICLK (480 * FWK_MHZ) +#define SCC_CLK_RATE_MCPQSPICLK (50 * FWK_MHZ) #define SCC_CLK_RATE_PCIEAXICLK (1200 * FWK_MHZ) #define SCC_CLK_RATE_CCIXAXICLK (1200 * FWK_MHZ) #define SCC_CLK_RATE_PCIEAPBCLK (200 * FWK_MHZ) #define SCC_CLK_RATE_CCIXAPBCLK (200 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0_CPU (3000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1_CPU (3000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0 (2000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1 (2000 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_CPU (1600 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_CPU (1600 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0 (1600 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1 (1600 * FWK_MHZ) #define PIK_CLK_RATE_CLUS0_PPU (300 * FWK_MHZ) #define PIK_CLK_RATE_CLUS1_PPU (300 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0_PCLK (1000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0_ATCLK (1000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0_GIC (1000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS0_AMBACLK (1000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1_PCLK (1000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1_ATCLK (1000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1_GIC (1000 * FWK_MHZ) -#define PIK_CLK_RATE_CLUS1_AMBACLK (1000 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_PCLK (900 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_ATCLK (900 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_GIC (900 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_AMBACLK (900 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_PCLK (900 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_ATCLK (900 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_GIC (900 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_AMBACLK (900 * FWK_MHZ) #define PIK_CLK_RATE_SCP_CORECLK (300 * FWK_MHZ) #define PIK_CLK_RATE_SCP_AXICLK (300 * FWK_MHZ) -#define PIK_CLK_RATE_SYS_PPU (1200 * FWK_MHZ) -#define PIK_CLK_RATE_INTERCONNECT (2000 * FWK_MHZ) +#define PIK_CLK_RATE_SYS_PPU (300 * FWK_MHZ) +#define PIK_CLK_RATE_INTERCONNECT (1600 * FWK_MHZ) #define PIK_CLK_RATE_PCLKSCP (300 * FWK_MHZ) #define PIK_CLK_RATE_SYS_GIC (800 * FWK_MHZ) #define PIK_CLK_RATE_SYSPCLKDBG (300 * FWK_MHZ) #define PIK_CLK_RATE_SYSPERCLK (600 * FWK_MHZ) -#define PIK_CLK_RATE_UART (240 * FWK_MHZ) +#define PIK_CLK_RATE_UART (50 * FWK_MHZ) #define PIK_CLK_RATE_TCU0 (1200 * FWK_MHZ) #define PIK_CLK_RATE_TCU1 (1200 * FWK_MHZ) #define PIK_CLK_RATE_ATCLKDBG (600 * FWK_MHZ) #define PIK_CLK_RATE_PCLKDBG (300 * FWK_MHZ) #define PIK_CLK_RATE_TRACECLK (300 * FWK_MHZ) -#define PIK_CLK_RATE_DMC (1600 * FWK_MHZ) +#define PIK_CLK_RATE_DMC (800 * FWK_MHZ) /* * N1SDP PLL clock rates. */ -#define N1SDP_PLL_RATE_CPU_PLL0 (3000 * FWK_MHZ) -#define N1SDP_PLL_RATE_CPU_PLL1 (3000 * FWK_MHZ) -#define N1SDP_PLL_RATE_CLUSTER_PLL (2000 * FWK_MHZ) -#define N1SDP_PLL_RATE_INTERCONNECT_PLL (2000 * FWK_MHZ) +#define N1SDP_PLL_RATE_CPU_PLL0 (1600 * FWK_MHZ) +#define N1SDP_PLL_RATE_CPU_PLL1 (1600 * FWK_MHZ) +#define N1SDP_PLL_RATE_CLUSTER_PLL (1600 * FWK_MHZ) +#define N1SDP_PLL_RATE_INTERCONNECT_PLL (1600 * FWK_MHZ) #define N1SDP_PLL_RATE_SYSTEM_PLL (2400 * FWK_MHZ) -#define N1SDP_PLL_RATE_DMC_PLL (1600 * FWK_MHZ) +#define N1SDP_PLL_RATE_DMC_PLL (800 * FWK_MHZ) /* * CSS clock rates. */ -#define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (2600 * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (1600 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE (2700 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_NOMINAL (2800 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_OVERDRIVE (2900 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE (3000 * FWK_MHZ) -#define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (2600 * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (1600 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE (2700 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_NOMINAL (2800 * FWK_MHZ) #define CSS_CLK_RATE_CPU_GRP1_OVERDRIVE (2900 * FWK_MHZ) diff --git a/product/n1sdp/scp_ramfw/config_pik_clock.c b/product/n1sdp/scp_ramfw/config_pik_clock.c index e4449ecac..110d252fd 100644 --- a/product/n1sdp/scp_ramfw/config_pik_clock.c +++ b/product/n1sdp/scp_ramfw/config_pik_clock.c @@ -67,9 +67,9 @@ static const struct mod_pik_clock_rate rate_table_scpi2cclk[] = { static const struct mod_pik_clock_rate rate_table_scpqspiclk[] = { { .rate = SCC_CLK_RATE_SCPQSPICLK, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSREFCLK, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_SCPQSPICLK, + .divider = 1, }, }; @@ -103,9 +103,9 @@ static const struct mod_pik_clock_rate rate_table_mcpi2cclk[] = { static const struct mod_pik_clock_rate rate_table_mcpqspiclk[] = { { .rate = SCC_CLK_RATE_MCPQSPICLK, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSREFCLK, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_MCPQSPICLK, + .divider = 1, }, }; @@ -346,9 +346,9 @@ static const struct mod_pik_clock_rate rate_table_sysperclk[] = { static const struct mod_pik_clock_rate rate_table_uart[] = { { .rate = PIK_CLK_RATE_UART, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSREFCLK, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_UART, + .divider = 1, }, }; -- GitLab From 3e7a939d69b997008de612a6889ec87ab22c6adc Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Tue, 26 Mar 2019 16:21:19 +0000 Subject: [PATCH 3/3] n1sdp: pcie increase inbound region size This patch increases the inbound region size from 4GB to 4TB such that PCIe devices can access DDR in 64-bit space. Change-Id: I48c37a2d1c038bf1b313a64ec3c76a5ee9ebe47a Signed-off-by: Manoj Kumar --- product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c | 2 +- product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c index 6a3d6b347..1725e7d0d 100644 --- a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c +++ b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c @@ -276,7 +276,7 @@ static int n1sdp_pcie_setup(struct n1sdp_pcie_dev_ctx *dev_ctx) "[PCIe] Enable inbound region in BAR 2..."); status = axi_inbound_region_setup(dev_ctx->rc_axi_config_apb, AXI_IB_REGION_BASE, - __builtin_ctz(AXI_IB_REGION_SIZE), 2); + AXI_IB_REGION_SIZE_MSB, 2); if (status != FWK_SUCCESS) { pcie_ctx.log_api->log(MOD_LOG_GROUP_INFO, "Error!\n"); return status; diff --git a/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h b/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h index 4616b323e..047fcc54b 100644 --- a/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h +++ b/product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.h @@ -146,7 +146,7 @@ /* AXI inbound region data */ #define AXI_IB_REGION_BASE UINT64_C(0) -#define AXI_IB_REGION_SIZE (4 * FWK_GIB) +#define AXI_IB_REGION_SIZE_MSB 42 /* * PCIe Descriptor Register definitions -- GitLab