diff --git a/product/n1sdp/include/n1sdp_pik_system.h b/product/n1sdp/include/n1sdp_pik_system.h index 7b7c262898a4da2128310aeff96099c61803b639..1f8a17ab70186676d74f59d122cd85675ffdbe40 100644 --- a/product/n1sdp/include/n1sdp_pik_system.h +++ b/product/n1sdp/include/n1sdp_pik_system.h @@ -71,4 +71,8 @@ struct pik_system_reg { FWK_R uint32_t ID3; }; +#define PIK_SYSTEM_DMCCLK_CTRL_DIV2_BYPASS_POS 16 +#define PIK_SYSTEM_DMCCLK_CTRL_DIV2_BYPASS_MASK \ + (UINT32_C(1) << PIK_SYSTEM_DMCCLK_CTRL_DIV2_BYPASS_POS) + #endif /* N1SDP_PIK_SYSTEM_H */ diff --git a/product/n1sdp/module/n1sdp_ddr_phy/include/internal/n1sdp_ddr_phy.h b/product/n1sdp/module/n1sdp_ddr_phy/include/internal/n1sdp_ddr_phy.h new file mode 100644 index 0000000000000000000000000000000000000000..49d143e8e5e7723acb1822570dcd71b1d8fd215b --- /dev/null +++ b/product/n1sdp/module/n1sdp_ddr_phy/include/internal/n1sdp_ddr_phy.h @@ -0,0 +1,2449 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * N1SDP DDR PHY configuration registers. + */ + +#ifndef N1SDP_DDR_PHY_H +#define N1SDP_DDR_PHY_H + +#include +#include + +/* + * N1SDP DDR PHY register definitions. + */ +struct mod_n1sdp_ddr_phy_reg { + FWK_RW uint32_t DENALI_PHY_00_DATA; + FWK_RW uint32_t DENALI_PHY_01_DATA; + FWK_RW uint32_t DENALI_PHY_02_DATA; + FWK_RW uint32_t DENALI_PHY_03_DATA; + FWK_RW uint32_t DENALI_PHY_04_DATA; + FWK_RW uint32_t DENALI_PHY_05_DATA; + FWK_RW uint32_t DENALI_PHY_06_DATA; + FWK_RW uint32_t DENALI_PHY_07_DATA; + FWK_RW uint32_t DENALI_PHY_08_DATA; + FWK_RW uint32_t DENALI_PHY_09_DATA; + FWK_RW uint32_t DENALI_PHY_10_DATA; + FWK_RW uint32_t DENALI_PHY_11_DATA; + FWK_RW uint32_t DENALI_PHY_12_DATA; + FWK_RW uint32_t DENALI_PHY_13_DATA; + FWK_RW uint32_t DENALI_PHY_14_DATA; + FWK_RW uint32_t DENALI_PHY_15_DATA; + FWK_RW uint32_t DENALI_PHY_16_DATA; + FWK_RW uint32_t DENALI_PHY_17_DATA; + FWK_RW uint32_t DENALI_PHY_18_DATA; + FWK_RW uint32_t DENALI_PHY_19_DATA; + FWK_RW uint32_t DENALI_PHY_20_DATA; + FWK_RW uint32_t DENALI_PHY_21_DATA; + FWK_RW uint32_t DENALI_PHY_22_DATA; + FWK_RW uint32_t DENALI_PHY_23_DATA; + FWK_RW uint32_t DENALI_PHY_24_DATA; + FWK_RW uint32_t DENALI_PHY_25_DATA; + FWK_RW uint32_t DENALI_PHY_26_DATA; + FWK_RW uint32_t DENALI_PHY_27_DATA; + FWK_RW uint32_t DENALI_PHY_28_DATA; + FWK_RW uint32_t DENALI_PHY_29_DATA; + FWK_RW uint32_t DENALI_PHY_30_DATA; + FWK_RW uint32_t DENALI_PHY_31_DATA; + FWK_RW uint32_t DENALI_PHY_32_DATA; + FWK_RW uint32_t DENALI_PHY_33_DATA; + FWK_RW uint32_t DENALI_PHY_34_DATA; + FWK_RW uint32_t DENALI_PHY_35_DATA; + FWK_RW uint32_t DENALI_PHY_36_DATA; + FWK_RW uint32_t DENALI_PHY_37_DATA; + FWK_RW uint32_t DENALI_PHY_38_DATA; + FWK_RW uint32_t DENALI_PHY_39_DATA; + FWK_RW uint32_t DENALI_PHY_40_DATA; + FWK_RW uint32_t DENALI_PHY_41_DATA; + FWK_RW uint32_t DENALI_PHY_42_DATA; + FWK_RW uint32_t DENALI_PHY_43_DATA; + FWK_RW uint32_t DENALI_PHY_44_DATA; + FWK_RW uint32_t DENALI_PHY_45_DATA; + FWK_RW uint32_t DENALI_PHY_46_DATA; + FWK_RW uint32_t DENALI_PHY_47_DATA; + FWK_RW uint32_t DENALI_PHY_48_DATA; + FWK_RW uint32_t DENALI_PHY_49_DATA; + FWK_RW uint32_t DENALI_PHY_50_DATA; + FWK_RW uint32_t DENALI_PHY_51_DATA; + FWK_RW uint32_t DENALI_PHY_52_DATA; + FWK_RW uint32_t DENALI_PHY_53_DATA; + FWK_RW uint32_t DENALI_PHY_54_DATA; + FWK_RW uint32_t DENALI_PHY_55_DATA; + FWK_RW uint32_t DENALI_PHY_56_DATA; + FWK_RW uint32_t DENALI_PHY_57_DATA; + FWK_RW uint32_t DENALI_PHY_58_DATA; + FWK_RW uint32_t DENALI_PHY_59_DATA; + FWK_RW uint32_t DENALI_PHY_60_DATA; + FWK_RW uint32_t DENALI_PHY_61_DATA; + FWK_RW uint32_t DENALI_PHY_62_DATA; + FWK_RW uint32_t DENALI_PHY_63_DATA; + FWK_RW uint32_t DENALI_PHY_64_DATA; + FWK_RW uint32_t DENALI_PHY_65_DATA; + FWK_RW uint32_t DENALI_PHY_66_DATA; + FWK_RW uint32_t DENALI_PHY_67_DATA; + FWK_RW uint32_t DENALI_PHY_68_DATA; + FWK_RW uint32_t DENALI_PHY_69_DATA; + FWK_RW uint32_t DENALI_PHY_70_DATA; + FWK_RW uint32_t DENALI_PHY_71_DATA; + FWK_RW uint32_t DENALI_PHY_72_DATA; + FWK_RW uint32_t DENALI_PHY_73_DATA; + FWK_RW uint32_t DENALI_PHY_74_DATA; + FWK_RW uint32_t DENALI_PHY_75_DATA; + FWK_RW uint32_t DENALI_PHY_76_DATA; + FWK_RW uint32_t DENALI_PHY_77_DATA; + FWK_RW uint32_t DENALI_PHY_78_DATA; + FWK_RW uint32_t DENALI_PHY_79_DATA; + FWK_RW uint32_t DENALI_PHY_80_DATA; + FWK_RW uint32_t DENALI_PHY_81_DATA; + FWK_RW uint32_t DENALI_PHY_82_DATA; + FWK_RW uint32_t DENALI_PHY_83_DATA; + FWK_RW uint32_t DENALI_PHY_84_DATA; + FWK_RW uint32_t DENALI_PHY_85_DATA; + FWK_RW uint32_t DENALI_PHY_86_DATA; + FWK_RW uint32_t DENALI_PHY_87_DATA; + FWK_RW uint32_t DENALI_PHY_88_DATA; + FWK_RW uint32_t DENALI_PHY_89_DATA; + FWK_RW uint32_t DENALI_PHY_90_DATA; + FWK_RW uint32_t DENALI_PHY_91_DATA; + FWK_RW uint32_t DENALI_PHY_92_DATA; + FWK_RW uint32_t DENALI_PHY_93_DATA; + FWK_RW uint32_t DENALI_PHY_94_DATA; + FWK_RW uint32_t DENALI_PHY_95_DATA; + FWK_RW uint32_t DENALI_PHY_96_DATA; + FWK_RW uint32_t DENALI_PHY_97_DATA; + FWK_RW uint32_t DENALI_PHY_98_DATA; + FWK_RW uint32_t DENALI_PHY_99_DATA; + FWK_RW uint32_t DENALI_PHY_100_DATA; + FWK_RW uint32_t DENALI_PHY_101_DATA; + FWK_RW uint32_t DENALI_PHY_102_DATA; + FWK_RW uint32_t DENALI_PHY_103_DATA; + FWK_RW uint32_t DENALI_PHY_104_DATA; + FWK_RW uint32_t DENALI_PHY_105_DATA; + FWK_RW uint32_t DENALI_PHY_106_DATA; + FWK_RW uint32_t DENALI_PHY_107_DATA; + FWK_RW uint32_t DENALI_PHY_108_DATA; + FWK_RW uint32_t DENALI_PHY_109_DATA; + FWK_RW uint32_t DENALI_PHY_110_DATA; + FWK_RW uint32_t DENALI_PHY_111_DATA; + FWK_RW uint32_t DENALI_PHY_112_DATA; + FWK_RW uint32_t DENALI_PHY_113_DATA; + FWK_RW uint32_t DENALI_PHY_114_DATA; + FWK_RW uint32_t DENALI_PHY_115_DATA; + FWK_RW uint32_t DENALI_PHY_116_DATA; + FWK_RW uint32_t DENALI_PHY_117_DATA; + FWK_RW uint32_t DENALI_PHY_118_DATA; + FWK_RW uint32_t DENALI_PHY_119_DATA; + FWK_RW uint32_t DENALI_PHY_120_DATA; + FWK_RW uint32_t DENALI_PHY_121_DATA; + FWK_RW uint32_t DENALI_PHY_122_DATA; + FWK_RW uint32_t DENALI_PHY_123_DATA; + FWK_RW uint32_t DENALI_PHY_124_DATA; + FWK_RW uint32_t DENALI_PHY_125_DATA; + FWK_RW uint32_t DENALI_PHY_126_DATA; + FWK_RW uint32_t DENALI_PHY_127_DATA; + FWK_RW uint32_t DENALI_PHY_128_DATA; + FWK_RW uint32_t DENALI_PHY_129_DATA; + FWK_RW uint32_t DENALI_PHY_130_DATA; + FWK_RW uint32_t DENALI_PHY_131_DATA; + FWK_RW uint32_t DENALI_PHY_132_DATA; + FWK_RW uint32_t DENALI_PHY_133_DATA; + FWK_RW uint32_t DENALI_PHY_134_DATA; + FWK_RW uint32_t DENALI_PHY_135_DATA; + FWK_RW uint32_t DENALI_PHY_136_DATA; + FWK_RW uint32_t DENALI_PHY_137_DATA; + FWK_RW uint32_t DENALI_PHY_138_DATA; + FWK_RW uint32_t DENALI_PHY_139_DATA; + FWK_RW uint32_t DENALI_PHY_140_DATA; + FWK_RW uint32_t DENALI_PHY_141_DATA; + FWK_RW uint32_t DENALI_PHY_142_DATA; + FWK_RW uint32_t DENALI_PHY_143_DATA; + FWK_RW uint32_t DENALI_PHY_144_DATA; + FWK_RW uint32_t DENALI_PHY_145_DATA; + FWK_RW uint32_t DENALI_PHY_146_DATA; + FWK_RW uint32_t DENALI_PHY_147_DATA; + FWK_RW uint32_t DENALI_PHY_148_DATA; + FWK_RW uint32_t DENALI_PHY_149_DATA; + FWK_RW uint32_t DENALI_PHY_150_DATA; + FWK_RW uint32_t DENALI_PHY_151_DATA; + FWK_RW uint32_t DENALI_PHY_152_DATA; + FWK_RW uint32_t DENALI_PHY_153_DATA; + FWK_RW uint32_t DENALI_PHY_154_DATA; + FWK_RW uint32_t DENALI_PHY_155_DATA; + FWK_RW uint32_t DENALI_PHY_156_DATA; + FWK_RW uint32_t DENALI_PHY_157_DATA; + FWK_RW uint32_t DENALI_PHY_158_DATA; + FWK_RW uint32_t DENALI_PHY_159_DATA; + FWK_RW uint32_t DENALI_PHY_160_DATA; + FWK_RW uint32_t DENALI_PHY_161_DATA; + FWK_RW uint32_t DENALI_PHY_162_DATA; + FWK_RW uint32_t DENALI_PHY_163_DATA; + FWK_RW uint32_t DENALI_PHY_164_DATA; + FWK_RW uint32_t DENALI_PHY_165_DATA; + FWK_RW uint32_t DENALI_PHY_166_DATA; + FWK_RW uint32_t DENALI_PHY_167_DATA; + FWK_RW uint32_t DENALI_PHY_168_DATA; + FWK_RW uint32_t DENALI_PHY_169_DATA; + FWK_RW uint32_t DENALI_PHY_170_DATA; + FWK_RW uint32_t DENALI_PHY_171_DATA; + FWK_RW uint32_t DENALI_PHY_172_DATA; + FWK_RW uint32_t DENALI_PHY_173_DATA; + FWK_RW uint32_t DENALI_PHY_174_DATA; + FWK_RW uint32_t DENALI_PHY_175_DATA; + FWK_RW uint32_t DENALI_PHY_176_DATA; + FWK_RW uint32_t DENALI_PHY_177_DATA; + FWK_RW uint32_t DENALI_PHY_178_DATA; + FWK_RW uint32_t DENALI_PHY_179_DATA; + FWK_RW uint32_t DENALI_PHY_180_DATA; + FWK_RW uint32_t DENALI_PHY_181_DATA; + FWK_RW uint32_t DENALI_PHY_182_DATA; + FWK_RW uint32_t DENALI_PHY_183_DATA; + FWK_RW uint32_t DENALI_PHY_184_DATA; + FWK_RW uint32_t DENALI_PHY_185_DATA; + FWK_RW uint32_t DENALI_PHY_186_DATA; + FWK_RW uint32_t DENALI_PHY_187_DATA; + FWK_RW uint32_t DENALI_PHY_188_DATA; + FWK_RW uint32_t DENALI_PHY_189_DATA; + FWK_RW uint32_t DENALI_PHY_190_DATA; + FWK_RW uint32_t DENALI_PHY_191_DATA; + FWK_RW uint32_t DENALI_PHY_192_DATA; + FWK_RW uint32_t DENALI_PHY_193_DATA; + FWK_RW uint32_t DENALI_PHY_194_DATA; + FWK_RW uint32_t DENALI_PHY_195_DATA; + FWK_RW uint32_t DENALI_PHY_196_DATA; + FWK_RW uint32_t DENALI_PHY_197_DATA; + FWK_RW uint32_t DENALI_PHY_198_DATA; + FWK_RW uint32_t DENALI_PHY_199_DATA; + FWK_RW uint32_t DENALI_PHY_200_DATA; + FWK_RW uint32_t DENALI_PHY_201_DATA; + FWK_RW uint32_t DENALI_PHY_202_DATA; + FWK_RW uint32_t DENALI_PHY_203_DATA; + FWK_RW uint32_t DENALI_PHY_204_DATA; + FWK_RW uint32_t DENALI_PHY_205_DATA; + FWK_RW uint32_t DENALI_PHY_206_DATA; + FWK_RW uint32_t DENALI_PHY_207_DATA; + FWK_RW uint32_t DENALI_PHY_208_DATA; + FWK_RW uint32_t DENALI_PHY_209_DATA; + FWK_RW uint32_t DENALI_PHY_210_DATA; + FWK_RW uint32_t DENALI_PHY_211_DATA; + FWK_RW uint32_t DENALI_PHY_212_DATA; + FWK_RW uint32_t DENALI_PHY_213_DATA; + FWK_RW uint32_t DENALI_PHY_214_DATA; + FWK_RW uint32_t DENALI_PHY_215_DATA; + FWK_RW uint32_t DENALI_PHY_216_DATA; + FWK_RW uint32_t DENALI_PHY_217_DATA; + FWK_RW uint32_t DENALI_PHY_218_DATA; + FWK_RW uint32_t DENALI_PHY_219_DATA; + FWK_RW uint32_t DENALI_PHY_220_DATA; + FWK_RW uint32_t DENALI_PHY_221_DATA; + FWK_RW uint32_t DENALI_PHY_222_DATA; + FWK_RW uint32_t DENALI_PHY_223_DATA; + FWK_RW uint32_t DENALI_PHY_224_DATA; + FWK_RW uint32_t DENALI_PHY_225_DATA; + FWK_RW uint32_t DENALI_PHY_226_DATA; + FWK_RW uint32_t DENALI_PHY_227_DATA; + FWK_RW uint32_t DENALI_PHY_228_DATA; + FWK_RW uint32_t DENALI_PHY_229_DATA; + FWK_RW uint32_t DENALI_PHY_230_DATA; + FWK_RW uint32_t DENALI_PHY_231_DATA; + FWK_RW uint32_t DENALI_PHY_232_DATA; + FWK_RW uint32_t DENALI_PHY_233_DATA; + FWK_RW uint32_t DENALI_PHY_234_DATA; + FWK_RW uint32_t DENALI_PHY_235_DATA; + FWK_RW uint32_t DENALI_PHY_236_DATA; + FWK_RW uint32_t DENALI_PHY_237_DATA; + FWK_RW uint32_t DENALI_PHY_238_DATA; + FWK_RW uint32_t DENALI_PHY_239_DATA; + FWK_RW uint32_t DENALI_PHY_240_DATA; + FWK_RW uint32_t DENALI_PHY_241_DATA; + FWK_RW uint32_t DENALI_PHY_242_DATA; + FWK_RW uint32_t DENALI_PHY_243_DATA; + FWK_RW uint32_t DENALI_PHY_244_DATA; + FWK_RW uint32_t DENALI_PHY_245_DATA; + FWK_RW uint32_t DENALI_PHY_246_DATA; + FWK_RW uint32_t DENALI_PHY_247_DATA; + FWK_RW uint32_t DENALI_PHY_248_DATA; + FWK_RW uint32_t DENALI_PHY_249_DATA; + FWK_RW uint32_t DENALI_PHY_250_DATA; + FWK_RW uint32_t DENALI_PHY_251_DATA; + FWK_RW uint32_t DENALI_PHY_252_DATA; + FWK_RW uint32_t DENALI_PHY_253_DATA; + FWK_RW uint32_t DENALI_PHY_254_DATA; + FWK_RW uint32_t DENALI_PHY_255_DATA; + FWK_RW uint32_t DENALI_PHY_256_DATA; + FWK_RW uint32_t DENALI_PHY_257_DATA; + FWK_RW uint32_t DENALI_PHY_258_DATA; + FWK_RW uint32_t DENALI_PHY_259_DATA; + FWK_RW uint32_t DENALI_PHY_260_DATA; + FWK_RW uint32_t DENALI_PHY_261_DATA; + FWK_RW uint32_t DENALI_PHY_262_DATA; + FWK_RW uint32_t DENALI_PHY_263_DATA; + FWK_RW uint32_t DENALI_PHY_264_DATA; + FWK_RW uint32_t DENALI_PHY_265_DATA; + FWK_RW uint32_t DENALI_PHY_266_DATA; + FWK_RW uint32_t DENALI_PHY_267_DATA; + FWK_RW uint32_t DENALI_PHY_268_DATA; + FWK_RW uint32_t DENALI_PHY_269_DATA; + FWK_RW uint32_t DENALI_PHY_270_DATA; + FWK_RW uint32_t DENALI_PHY_271_DATA; + FWK_RW uint32_t DENALI_PHY_272_DATA; + FWK_RW uint32_t DENALI_PHY_273_DATA; + FWK_RW uint32_t DENALI_PHY_274_DATA; + FWK_RW uint32_t DENALI_PHY_275_DATA; + FWK_RW uint32_t DENALI_PHY_276_DATA; + FWK_RW uint32_t DENALI_PHY_277_DATA; + FWK_RW uint32_t DENALI_PHY_278_DATA; + FWK_RW uint32_t DENALI_PHY_279_DATA; + FWK_RW uint32_t DENALI_PHY_280_DATA; + FWK_RW uint32_t DENALI_PHY_281_DATA; + FWK_RW uint32_t DENALI_PHY_282_DATA; + FWK_RW uint32_t DENALI_PHY_283_DATA; + FWK_RW uint32_t DENALI_PHY_284_DATA; + FWK_RW uint32_t DENALI_PHY_285_DATA; + FWK_RW uint32_t DENALI_PHY_286_DATA; + FWK_RW uint32_t DENALI_PHY_287_DATA; + FWK_RW uint32_t DENALI_PHY_288_DATA; + FWK_RW uint32_t DENALI_PHY_289_DATA; + FWK_RW uint32_t DENALI_PHY_290_DATA; + FWK_RW uint32_t DENALI_PHY_291_DATA; + FWK_RW uint32_t DENALI_PHY_292_DATA; + FWK_RW uint32_t DENALI_PHY_293_DATA; + FWK_RW uint32_t DENALI_PHY_294_DATA; + FWK_RW uint32_t DENALI_PHY_295_DATA; + FWK_RW uint32_t DENALI_PHY_296_DATA; + FWK_RW uint32_t DENALI_PHY_297_DATA; + FWK_RW uint32_t DENALI_PHY_298_DATA; + FWK_RW uint32_t DENALI_PHY_299_DATA; + FWK_RW uint32_t DENALI_PHY_300_DATA; + FWK_RW uint32_t DENALI_PHY_301_DATA; + FWK_RW uint32_t DENALI_PHY_302_DATA; + FWK_RW uint32_t DENALI_PHY_303_DATA; + FWK_RW uint32_t DENALI_PHY_304_DATA; + FWK_RW uint32_t DENALI_PHY_305_DATA; + FWK_RW uint32_t DENALI_PHY_306_DATA; + FWK_RW uint32_t DENALI_PHY_307_DATA; + FWK_RW uint32_t DENALI_PHY_308_DATA; + FWK_RW uint32_t DENALI_PHY_309_DATA; + FWK_RW uint32_t DENALI_PHY_310_DATA; + FWK_RW uint32_t DENALI_PHY_311_DATA; + FWK_RW uint32_t DENALI_PHY_312_DATA; + FWK_RW uint32_t DENALI_PHY_313_DATA; + FWK_RW uint32_t DENALI_PHY_314_DATA; + FWK_RW uint32_t DENALI_PHY_315_DATA; + FWK_RW uint32_t DENALI_PHY_316_DATA; + FWK_RW uint32_t DENALI_PHY_317_DATA; + FWK_RW uint32_t DENALI_PHY_318_DATA; + FWK_RW uint32_t DENALI_PHY_319_DATA; + FWK_RW uint32_t DENALI_PHY_320_DATA; + FWK_RW uint32_t DENALI_PHY_321_DATA; + FWK_RW uint32_t DENALI_PHY_322_DATA; + FWK_RW uint32_t DENALI_PHY_323_DATA; + FWK_RW uint32_t DENALI_PHY_324_DATA; + FWK_RW uint32_t DENALI_PHY_325_DATA; + FWK_RW uint32_t DENALI_PHY_326_DATA; + FWK_RW uint32_t DENALI_PHY_327_DATA; + FWK_RW uint32_t DENALI_PHY_328_DATA; + FWK_RW uint32_t DENALI_PHY_329_DATA; + FWK_RW uint32_t DENALI_PHY_330_DATA; + FWK_RW uint32_t DENALI_PHY_331_DATA; + FWK_RW uint32_t DENALI_PHY_332_DATA; + FWK_RW uint32_t DENALI_PHY_333_DATA; + FWK_RW uint32_t DENALI_PHY_334_DATA; + FWK_RW uint32_t DENALI_PHY_335_DATA; + FWK_RW uint32_t DENALI_PHY_336_DATA; + FWK_RW uint32_t DENALI_PHY_337_DATA; + FWK_RW uint32_t DENALI_PHY_338_DATA; + FWK_RW uint32_t DENALI_PHY_339_DATA; + FWK_RW uint32_t DENALI_PHY_340_DATA; + FWK_RW uint32_t DENALI_PHY_341_DATA; + FWK_RW uint32_t DENALI_PHY_342_DATA; + FWK_RW uint32_t DENALI_PHY_343_DATA; + FWK_RW uint32_t DENALI_PHY_344_DATA; + FWK_RW uint32_t DENALI_PHY_345_DATA; + FWK_RW uint32_t DENALI_PHY_346_DATA; + FWK_RW uint32_t DENALI_PHY_347_DATA; + FWK_RW uint32_t DENALI_PHY_348_DATA; + FWK_RW uint32_t DENALI_PHY_349_DATA; + FWK_RW uint32_t DENALI_PHY_350_DATA; + FWK_RW uint32_t DENALI_PHY_351_DATA; + FWK_RW uint32_t DENALI_PHY_352_DATA; + FWK_RW uint32_t DENALI_PHY_353_DATA; + FWK_RW uint32_t DENALI_PHY_354_DATA; + FWK_RW uint32_t DENALI_PHY_355_DATA; + FWK_RW uint32_t DENALI_PHY_356_DATA; + FWK_RW uint32_t DENALI_PHY_357_DATA; + FWK_RW uint32_t DENALI_PHY_358_DATA; + FWK_RW uint32_t DENALI_PHY_359_DATA; + FWK_RW uint32_t DENALI_PHY_360_DATA; + FWK_RW uint32_t DENALI_PHY_361_DATA; + FWK_RW uint32_t DENALI_PHY_362_DATA; + FWK_RW uint32_t DENALI_PHY_363_DATA; + FWK_RW uint32_t DENALI_PHY_364_DATA; + FWK_RW uint32_t DENALI_PHY_365_DATA; + FWK_RW uint32_t DENALI_PHY_366_DATA; + FWK_RW uint32_t DENALI_PHY_367_DATA; + FWK_RW uint32_t DENALI_PHY_368_DATA; + FWK_RW uint32_t DENALI_PHY_369_DATA; + FWK_RW uint32_t DENALI_PHY_370_DATA; + FWK_RW uint32_t DENALI_PHY_371_DATA; + FWK_RW uint32_t DENALI_PHY_372_DATA; + FWK_RW uint32_t DENALI_PHY_373_DATA; + FWK_RW uint32_t DENALI_PHY_374_DATA; + FWK_RW uint32_t DENALI_PHY_375_DATA; + FWK_RW uint32_t DENALI_PHY_376_DATA; + FWK_RW uint32_t DENALI_PHY_377_DATA; + FWK_RW uint32_t DENALI_PHY_378_DATA; + FWK_RW uint32_t DENALI_PHY_379_DATA; + FWK_RW uint32_t DENALI_PHY_380_DATA; + FWK_RW uint32_t DENALI_PHY_381_DATA; + FWK_RW uint32_t DENALI_PHY_382_DATA; + FWK_RW uint32_t DENALI_PHY_383_DATA; + FWK_RW uint32_t DENALI_PHY_384_DATA; + FWK_RW uint32_t DENALI_PHY_385_DATA; + FWK_RW uint32_t DENALI_PHY_386_DATA; + FWK_RW uint32_t DENALI_PHY_387_DATA; + FWK_RW uint32_t DENALI_PHY_388_DATA; + FWK_RW uint32_t DENALI_PHY_389_DATA; + FWK_RW uint32_t DENALI_PHY_390_DATA; + FWK_RW uint32_t DENALI_PHY_391_DATA; + FWK_RW uint32_t DENALI_PHY_392_DATA; + FWK_RW uint32_t DENALI_PHY_393_DATA; + FWK_RW uint32_t DENALI_PHY_394_DATA; + FWK_RW uint32_t DENALI_PHY_395_DATA; + FWK_RW uint32_t DENALI_PHY_396_DATA; + FWK_RW uint32_t DENALI_PHY_397_DATA; + FWK_RW uint32_t DENALI_PHY_398_DATA; + FWK_RW uint32_t DENALI_PHY_399_DATA; + FWK_RW uint32_t DENALI_PHY_400_DATA; + FWK_RW uint32_t DENALI_PHY_401_DATA; + FWK_RW uint32_t DENALI_PHY_402_DATA; + FWK_RW uint32_t DENALI_PHY_403_DATA; + FWK_RW uint32_t DENALI_PHY_404_DATA; + FWK_RW uint32_t DENALI_PHY_405_DATA; + FWK_RW uint32_t DENALI_PHY_406_DATA; + FWK_RW uint32_t DENALI_PHY_407_DATA; + FWK_RW uint32_t DENALI_PHY_408_DATA; + FWK_RW uint32_t DENALI_PHY_409_DATA; + FWK_RW uint32_t DENALI_PHY_410_DATA; + FWK_RW uint32_t DENALI_PHY_411_DATA; + FWK_RW uint32_t DENALI_PHY_412_DATA; + FWK_RW uint32_t DENALI_PHY_413_DATA; + FWK_RW uint32_t DENALI_PHY_414_DATA; + FWK_RW uint32_t DENALI_PHY_415_DATA; + FWK_RW uint32_t DENALI_PHY_416_DATA; + FWK_RW uint32_t DENALI_PHY_417_DATA; + FWK_RW uint32_t DENALI_PHY_418_DATA; + FWK_RW uint32_t DENALI_PHY_419_DATA; + FWK_RW uint32_t DENALI_PHY_420_DATA; + FWK_RW uint32_t DENALI_PHY_421_DATA; + FWK_RW uint32_t DENALI_PHY_422_DATA; + FWK_RW uint32_t DENALI_PHY_423_DATA; + FWK_RW uint32_t DENALI_PHY_424_DATA; + FWK_RW uint32_t DENALI_PHY_425_DATA; + FWK_RW uint32_t DENALI_PHY_426_DATA; + FWK_RW uint32_t DENALI_PHY_427_DATA; + FWK_RW uint32_t DENALI_PHY_428_DATA; + FWK_RW uint32_t DENALI_PHY_429_DATA; + FWK_RW uint32_t DENALI_PHY_430_DATA; + FWK_RW uint32_t DENALI_PHY_431_DATA; + FWK_RW uint32_t DENALI_PHY_432_DATA; + FWK_RW uint32_t DENALI_PHY_433_DATA; + FWK_RW uint32_t DENALI_PHY_434_DATA; + FWK_RW uint32_t DENALI_PHY_435_DATA; + FWK_RW uint32_t DENALI_PHY_436_DATA; + FWK_RW uint32_t DENALI_PHY_437_DATA; + FWK_RW uint32_t DENALI_PHY_438_DATA; + FWK_RW uint32_t DENALI_PHY_439_DATA; + FWK_RW uint32_t DENALI_PHY_440_DATA; + FWK_RW uint32_t DENALI_PHY_441_DATA; + FWK_RW uint32_t DENALI_PHY_442_DATA; + FWK_RW uint32_t DENALI_PHY_443_DATA; + FWK_RW uint32_t DENALI_PHY_444_DATA; + FWK_RW uint32_t DENALI_PHY_445_DATA; + FWK_RW uint32_t DENALI_PHY_446_DATA; + FWK_RW uint32_t DENALI_PHY_447_DATA; + FWK_RW uint32_t DENALI_PHY_448_DATA; + FWK_RW uint32_t DENALI_PHY_449_DATA; + FWK_RW uint32_t DENALI_PHY_450_DATA; + FWK_RW uint32_t DENALI_PHY_451_DATA; + FWK_RW uint32_t DENALI_PHY_452_DATA; + FWK_RW uint32_t DENALI_PHY_453_DATA; + FWK_RW uint32_t DENALI_PHY_454_DATA; + FWK_RW uint32_t DENALI_PHY_455_DATA; + FWK_RW uint32_t DENALI_PHY_456_DATA; + FWK_RW uint32_t DENALI_PHY_457_DATA; + FWK_RW uint32_t DENALI_PHY_458_DATA; + FWK_RW uint32_t DENALI_PHY_459_DATA; + FWK_RW uint32_t DENALI_PHY_460_DATA; + FWK_RW uint32_t DENALI_PHY_461_DATA; + FWK_RW uint32_t DENALI_PHY_462_DATA; + FWK_RW uint32_t DENALI_PHY_463_DATA; + FWK_RW uint32_t DENALI_PHY_464_DATA; + FWK_RW uint32_t DENALI_PHY_465_DATA; + FWK_RW uint32_t DENALI_PHY_466_DATA; + FWK_RW uint32_t DENALI_PHY_467_DATA; + FWK_RW uint32_t DENALI_PHY_468_DATA; + FWK_RW uint32_t DENALI_PHY_469_DATA; + FWK_RW uint32_t DENALI_PHY_470_DATA; + FWK_RW uint32_t DENALI_PHY_471_DATA; + FWK_RW uint32_t DENALI_PHY_472_DATA; + FWK_RW uint32_t DENALI_PHY_473_DATA; + FWK_RW uint32_t DENALI_PHY_474_DATA; + FWK_RW uint32_t DENALI_PHY_475_DATA; + FWK_RW uint32_t DENALI_PHY_476_DATA; + FWK_RW uint32_t DENALI_PHY_477_DATA; + FWK_RW uint32_t DENALI_PHY_478_DATA; + FWK_RW uint32_t DENALI_PHY_479_DATA; + FWK_RW uint32_t DENALI_PHY_480_DATA; + FWK_RW uint32_t DENALI_PHY_481_DATA; + FWK_RW uint32_t DENALI_PHY_482_DATA; + FWK_RW uint32_t DENALI_PHY_483_DATA; + FWK_RW uint32_t DENALI_PHY_484_DATA; + FWK_RW uint32_t DENALI_PHY_485_DATA; + FWK_RW uint32_t DENALI_PHY_486_DATA; + FWK_RW uint32_t DENALI_PHY_487_DATA; + FWK_RW uint32_t DENALI_PHY_488_DATA; + FWK_RW uint32_t DENALI_PHY_489_DATA; + FWK_RW uint32_t DENALI_PHY_490_DATA; + FWK_RW uint32_t DENALI_PHY_491_DATA; + FWK_RW uint32_t DENALI_PHY_492_DATA; + FWK_RW uint32_t DENALI_PHY_493_DATA; + FWK_RW uint32_t DENALI_PHY_494_DATA; + FWK_RW uint32_t DENALI_PHY_495_DATA; + FWK_RW uint32_t DENALI_PHY_496_DATA; + FWK_RW uint32_t DENALI_PHY_497_DATA; + FWK_RW uint32_t DENALI_PHY_498_DATA; + FWK_RW uint32_t DENALI_PHY_499_DATA; + FWK_RW uint32_t DENALI_PHY_500_DATA; + FWK_RW uint32_t DENALI_PHY_501_DATA; + FWK_RW uint32_t DENALI_PHY_502_DATA; + FWK_RW uint32_t DENALI_PHY_503_DATA; + FWK_RW uint32_t DENALI_PHY_504_DATA; + FWK_RW uint32_t DENALI_PHY_505_DATA; + FWK_RW uint32_t DENALI_PHY_506_DATA; + FWK_RW uint32_t DENALI_PHY_507_DATA; + FWK_RW uint32_t DENALI_PHY_508_DATA; + FWK_RW uint32_t DENALI_PHY_509_DATA; + FWK_RW uint32_t DENALI_PHY_510_DATA; + FWK_RW uint32_t DENALI_PHY_511_DATA; + FWK_RW uint32_t DENALI_PHY_512_DATA; + FWK_RW uint32_t DENALI_PHY_513_DATA; + FWK_RW uint32_t DENALI_PHY_514_DATA; + FWK_RW uint32_t DENALI_PHY_515_DATA; + FWK_RW uint32_t DENALI_PHY_516_DATA; + FWK_RW uint32_t DENALI_PHY_517_DATA; + FWK_RW uint32_t DENALI_PHY_518_DATA; + FWK_RW uint32_t DENALI_PHY_519_DATA; + FWK_RW uint32_t DENALI_PHY_520_DATA; + FWK_RW uint32_t DENALI_PHY_521_DATA; + FWK_RW uint32_t DENALI_PHY_522_DATA; + FWK_RW uint32_t DENALI_PHY_523_DATA; + FWK_RW uint32_t DENALI_PHY_524_DATA; + FWK_RW uint32_t DENALI_PHY_525_DATA; + FWK_RW uint32_t DENALI_PHY_526_DATA; + FWK_RW uint32_t DENALI_PHY_527_DATA; + FWK_RW uint32_t DENALI_PHY_528_DATA; + FWK_RW uint32_t DENALI_PHY_529_DATA; + FWK_RW uint32_t DENALI_PHY_530_DATA; + FWK_RW uint32_t DENALI_PHY_531_DATA; + FWK_RW uint32_t DENALI_PHY_532_DATA; + FWK_RW uint32_t DENALI_PHY_533_DATA; + FWK_RW uint32_t DENALI_PHY_534_DATA; + FWK_RW uint32_t DENALI_PHY_535_DATA; + FWK_RW uint32_t DENALI_PHY_536_DATA; + FWK_RW uint32_t DENALI_PHY_537_DATA; + FWK_RW uint32_t DENALI_PHY_538_DATA; + FWK_RW uint32_t DENALI_PHY_539_DATA; + FWK_RW uint32_t DENALI_PHY_540_DATA; + FWK_RW uint32_t DENALI_PHY_541_DATA; + FWK_RW uint32_t DENALI_PHY_542_DATA; + FWK_RW uint32_t DENALI_PHY_543_DATA; + FWK_RW uint32_t DENALI_PHY_544_DATA; + FWK_RW uint32_t DENALI_PHY_545_DATA; + FWK_RW uint32_t DENALI_PHY_546_DATA; + FWK_RW uint32_t DENALI_PHY_547_DATA; + FWK_RW uint32_t DENALI_PHY_548_DATA; + FWK_RW uint32_t DENALI_PHY_549_DATA; + FWK_RW uint32_t DENALI_PHY_550_DATA; + FWK_RW uint32_t DENALI_PHY_551_DATA; + FWK_RW uint32_t DENALI_PHY_552_DATA; + FWK_RW uint32_t DENALI_PHY_553_DATA; + FWK_RW uint32_t DENALI_PHY_554_DATA; + FWK_RW uint32_t DENALI_PHY_555_DATA; + FWK_RW uint32_t DENALI_PHY_556_DATA; + FWK_RW uint32_t DENALI_PHY_557_DATA; + FWK_RW uint32_t DENALI_PHY_558_DATA; + FWK_RW uint32_t DENALI_PHY_559_DATA; + FWK_RW uint32_t DENALI_PHY_560_DATA; + FWK_RW uint32_t DENALI_PHY_561_DATA; + FWK_RW uint32_t DENALI_PHY_562_DATA; + FWK_RW uint32_t DENALI_PHY_563_DATA; + FWK_RW uint32_t DENALI_PHY_564_DATA; + FWK_RW uint32_t DENALI_PHY_565_DATA; + FWK_RW uint32_t DENALI_PHY_566_DATA; + FWK_RW uint32_t DENALI_PHY_567_DATA; + FWK_RW uint32_t DENALI_PHY_568_DATA; + FWK_RW uint32_t DENALI_PHY_569_DATA; + FWK_RW uint32_t DENALI_PHY_570_DATA; + FWK_RW uint32_t DENALI_PHY_571_DATA; + FWK_RW uint32_t DENALI_PHY_572_DATA; + FWK_RW uint32_t DENALI_PHY_573_DATA; + FWK_RW uint32_t DENALI_PHY_574_DATA; + FWK_RW uint32_t DENALI_PHY_575_DATA; + FWK_RW uint32_t DENALI_PHY_576_DATA; + FWK_RW uint32_t DENALI_PHY_577_DATA; + FWK_RW uint32_t DENALI_PHY_578_DATA; + FWK_RW uint32_t DENALI_PHY_579_DATA; + FWK_RW uint32_t DENALI_PHY_580_DATA; + FWK_RW uint32_t DENALI_PHY_581_DATA; + FWK_RW uint32_t DENALI_PHY_582_DATA; + FWK_RW uint32_t DENALI_PHY_583_DATA; + FWK_RW uint32_t DENALI_PHY_584_DATA; + FWK_RW uint32_t DENALI_PHY_585_DATA; + FWK_RW uint32_t DENALI_PHY_586_DATA; + FWK_RW uint32_t DENALI_PHY_587_DATA; + FWK_RW uint32_t DENALI_PHY_588_DATA; + FWK_RW uint32_t DENALI_PHY_589_DATA; + FWK_RW uint32_t DENALI_PHY_590_DATA; + FWK_RW uint32_t DENALI_PHY_591_DATA; + FWK_RW uint32_t DENALI_PHY_592_DATA; + FWK_RW uint32_t DENALI_PHY_593_DATA; + FWK_RW uint32_t DENALI_PHY_594_DATA; + FWK_RW uint32_t DENALI_PHY_595_DATA; + FWK_RW uint32_t DENALI_PHY_596_DATA; + FWK_RW uint32_t DENALI_PHY_597_DATA; + FWK_RW uint32_t DENALI_PHY_598_DATA; + FWK_RW uint32_t DENALI_PHY_599_DATA; + FWK_RW uint32_t DENALI_PHY_600_DATA; + FWK_RW uint32_t DENALI_PHY_601_DATA; + FWK_RW uint32_t DENALI_PHY_602_DATA; + FWK_RW uint32_t DENALI_PHY_603_DATA; + FWK_RW uint32_t DENALI_PHY_604_DATA; + FWK_RW uint32_t DENALI_PHY_605_DATA; + FWK_RW uint32_t DENALI_PHY_606_DATA; + FWK_RW uint32_t DENALI_PHY_607_DATA; + FWK_RW uint32_t DENALI_PHY_608_DATA; + FWK_RW uint32_t DENALI_PHY_609_DATA; + FWK_RW uint32_t DENALI_PHY_610_DATA; + FWK_RW uint32_t DENALI_PHY_611_DATA; + FWK_RW uint32_t DENALI_PHY_612_DATA; + FWK_RW uint32_t DENALI_PHY_613_DATA; + FWK_RW uint32_t DENALI_PHY_614_DATA; + FWK_RW uint32_t DENALI_PHY_615_DATA; + FWK_RW uint32_t DENALI_PHY_616_DATA; + FWK_RW uint32_t DENALI_PHY_617_DATA; + FWK_RW uint32_t DENALI_PHY_618_DATA; + FWK_RW uint32_t DENALI_PHY_619_DATA; + FWK_RW uint32_t DENALI_PHY_620_DATA; + FWK_RW uint32_t DENALI_PHY_621_DATA; + FWK_RW uint32_t DENALI_PHY_622_DATA; + FWK_RW uint32_t DENALI_PHY_623_DATA; + FWK_RW uint32_t DENALI_PHY_624_DATA; + FWK_RW uint32_t DENALI_PHY_625_DATA; + FWK_RW uint32_t DENALI_PHY_626_DATA; + FWK_RW uint32_t DENALI_PHY_627_DATA; + FWK_RW uint32_t DENALI_PHY_628_DATA; + FWK_RW uint32_t DENALI_PHY_629_DATA; + FWK_RW uint32_t DENALI_PHY_630_DATA; + FWK_RW uint32_t DENALI_PHY_631_DATA; + FWK_RW uint32_t DENALI_PHY_632_DATA; + FWK_RW uint32_t DENALI_PHY_633_DATA; + FWK_RW uint32_t DENALI_PHY_634_DATA; + FWK_RW uint32_t DENALI_PHY_635_DATA; + FWK_RW uint32_t DENALI_PHY_636_DATA; + FWK_RW uint32_t DENALI_PHY_637_DATA; + FWK_RW uint32_t DENALI_PHY_638_DATA; + FWK_RW uint32_t DENALI_PHY_639_DATA; + FWK_RW uint32_t DENALI_PHY_640_DATA; + FWK_RW uint32_t DENALI_PHY_641_DATA; + FWK_RW uint32_t DENALI_PHY_642_DATA; + FWK_RW uint32_t DENALI_PHY_643_DATA; + FWK_RW uint32_t DENALI_PHY_644_DATA; + FWK_RW uint32_t DENALI_PHY_645_DATA; + FWK_RW uint32_t DENALI_PHY_646_DATA; + FWK_RW uint32_t DENALI_PHY_647_DATA; + FWK_RW uint32_t DENALI_PHY_648_DATA; + FWK_RW uint32_t DENALI_PHY_649_DATA; + FWK_RW uint32_t DENALI_PHY_650_DATA; + FWK_RW uint32_t DENALI_PHY_651_DATA; + FWK_RW uint32_t DENALI_PHY_652_DATA; + FWK_RW uint32_t DENALI_PHY_653_DATA; + FWK_RW uint32_t DENALI_PHY_654_DATA; + FWK_RW uint32_t DENALI_PHY_655_DATA; + FWK_RW uint32_t DENALI_PHY_656_DATA; + FWK_RW uint32_t DENALI_PHY_657_DATA; + FWK_RW uint32_t DENALI_PHY_658_DATA; + FWK_RW uint32_t DENALI_PHY_659_DATA; + FWK_RW uint32_t DENALI_PHY_660_DATA; + FWK_RW uint32_t DENALI_PHY_661_DATA; + FWK_RW uint32_t DENALI_PHY_662_DATA; + FWK_RW uint32_t DENALI_PHY_663_DATA; + FWK_RW uint32_t DENALI_PHY_664_DATA; + FWK_RW uint32_t DENALI_PHY_665_DATA; + FWK_RW uint32_t DENALI_PHY_666_DATA; + FWK_RW uint32_t DENALI_PHY_667_DATA; + FWK_RW uint32_t DENALI_PHY_668_DATA; + FWK_RW uint32_t DENALI_PHY_669_DATA; + FWK_RW uint32_t DENALI_PHY_670_DATA; + FWK_RW uint32_t DENALI_PHY_671_DATA; + FWK_RW uint32_t DENALI_PHY_672_DATA; + FWK_RW uint32_t DENALI_PHY_673_DATA; + FWK_RW uint32_t DENALI_PHY_674_DATA; + FWK_RW uint32_t DENALI_PHY_675_DATA; + FWK_RW uint32_t DENALI_PHY_676_DATA; + FWK_RW uint32_t DENALI_PHY_677_DATA; + FWK_RW uint32_t DENALI_PHY_678_DATA; + FWK_RW uint32_t DENALI_PHY_679_DATA; + FWK_RW uint32_t DENALI_PHY_680_DATA; + FWK_RW uint32_t DENALI_PHY_681_DATA; + FWK_RW uint32_t DENALI_PHY_682_DATA; + FWK_RW uint32_t DENALI_PHY_683_DATA; + FWK_RW uint32_t DENALI_PHY_684_DATA; + FWK_RW uint32_t DENALI_PHY_685_DATA; + FWK_RW uint32_t DENALI_PHY_686_DATA; + FWK_RW uint32_t DENALI_PHY_687_DATA; + FWK_RW uint32_t DENALI_PHY_688_DATA; + FWK_RW uint32_t DENALI_PHY_689_DATA; + FWK_RW uint32_t DENALI_PHY_690_DATA; + FWK_RW uint32_t DENALI_PHY_691_DATA; + FWK_RW uint32_t DENALI_PHY_692_DATA; + FWK_RW uint32_t DENALI_PHY_693_DATA; + FWK_RW uint32_t DENALI_PHY_694_DATA; + FWK_RW uint32_t DENALI_PHY_695_DATA; + FWK_RW uint32_t DENALI_PHY_696_DATA; + FWK_RW uint32_t DENALI_PHY_697_DATA; + FWK_RW uint32_t DENALI_PHY_698_DATA; + FWK_RW uint32_t DENALI_PHY_699_DATA; + FWK_RW uint32_t DENALI_PHY_700_DATA; + FWK_RW uint32_t DENALI_PHY_701_DATA; + FWK_RW uint32_t DENALI_PHY_702_DATA; + FWK_RW uint32_t DENALI_PHY_703_DATA; + FWK_RW uint32_t DENALI_PHY_704_DATA; + FWK_RW uint32_t DENALI_PHY_705_DATA; + FWK_RW uint32_t DENALI_PHY_706_DATA; + FWK_RW uint32_t DENALI_PHY_707_DATA; + FWK_RW uint32_t DENALI_PHY_708_DATA; + FWK_RW uint32_t DENALI_PHY_709_DATA; + FWK_RW uint32_t DENALI_PHY_710_DATA; + FWK_RW uint32_t DENALI_PHY_711_DATA; + FWK_RW uint32_t DENALI_PHY_712_DATA; + FWK_RW uint32_t DENALI_PHY_713_DATA; + FWK_RW uint32_t DENALI_PHY_714_DATA; + FWK_RW uint32_t DENALI_PHY_715_DATA; + FWK_RW uint32_t DENALI_PHY_716_DATA; + FWK_RW uint32_t DENALI_PHY_717_DATA; + FWK_RW uint32_t DENALI_PHY_718_DATA; + FWK_RW uint32_t DENALI_PHY_719_DATA; + FWK_RW uint32_t DENALI_PHY_720_DATA; + FWK_RW uint32_t DENALI_PHY_721_DATA; + FWK_RW uint32_t DENALI_PHY_722_DATA; + FWK_RW uint32_t DENALI_PHY_723_DATA; + FWK_RW uint32_t DENALI_PHY_724_DATA; + FWK_RW uint32_t DENALI_PHY_725_DATA; + FWK_RW uint32_t DENALI_PHY_726_DATA; + FWK_RW uint32_t DENALI_PHY_727_DATA; + FWK_RW uint32_t DENALI_PHY_728_DATA; + FWK_RW uint32_t DENALI_PHY_729_DATA; + FWK_RW uint32_t DENALI_PHY_730_DATA; + FWK_RW uint32_t DENALI_PHY_731_DATA; + FWK_RW uint32_t DENALI_PHY_732_DATA; + FWK_RW uint32_t DENALI_PHY_733_DATA; + FWK_RW uint32_t DENALI_PHY_734_DATA; + FWK_RW uint32_t DENALI_PHY_735_DATA; + FWK_RW uint32_t DENALI_PHY_736_DATA; + FWK_RW uint32_t DENALI_PHY_737_DATA; + FWK_RW uint32_t DENALI_PHY_738_DATA; + FWK_RW uint32_t DENALI_PHY_739_DATA; + FWK_RW uint32_t DENALI_PHY_740_DATA; + FWK_RW uint32_t DENALI_PHY_741_DATA; + FWK_RW uint32_t DENALI_PHY_742_DATA; + FWK_RW uint32_t DENALI_PHY_743_DATA; + FWK_RW uint32_t DENALI_PHY_744_DATA; + FWK_RW uint32_t DENALI_PHY_745_DATA; + FWK_RW uint32_t DENALI_PHY_746_DATA; + FWK_RW uint32_t DENALI_PHY_747_DATA; + FWK_RW uint32_t DENALI_PHY_748_DATA; + FWK_RW uint32_t DENALI_PHY_749_DATA; + FWK_RW uint32_t DENALI_PHY_750_DATA; + FWK_RW uint32_t DENALI_PHY_751_DATA; + FWK_RW uint32_t DENALI_PHY_752_DATA; + FWK_RW uint32_t DENALI_PHY_753_DATA; + FWK_RW uint32_t DENALI_PHY_754_DATA; + FWK_RW uint32_t DENALI_PHY_755_DATA; + FWK_RW uint32_t DENALI_PHY_756_DATA; + FWK_RW uint32_t DENALI_PHY_757_DATA; + FWK_RW uint32_t DENALI_PHY_758_DATA; + FWK_RW uint32_t DENALI_PHY_759_DATA; + FWK_RW uint32_t DENALI_PHY_760_DATA; + FWK_RW uint32_t DENALI_PHY_761_DATA; + FWK_RW uint32_t DENALI_PHY_762_DATA; + FWK_RW uint32_t DENALI_PHY_763_DATA; + FWK_RW uint32_t DENALI_PHY_764_DATA; + FWK_RW uint32_t DENALI_PHY_765_DATA; + FWK_RW uint32_t DENALI_PHY_766_DATA; + FWK_RW uint32_t DENALI_PHY_767_DATA; + FWK_RW uint32_t DENALI_PHY_768_DATA; + FWK_RW uint32_t DENALI_PHY_769_DATA; + FWK_RW uint32_t DENALI_PHY_770_DATA; + FWK_RW uint32_t DENALI_PHY_771_DATA; + FWK_RW uint32_t DENALI_PHY_772_DATA; + FWK_RW uint32_t DENALI_PHY_773_DATA; + FWK_RW uint32_t DENALI_PHY_774_DATA; + FWK_RW uint32_t DENALI_PHY_775_DATA; + FWK_RW uint32_t DENALI_PHY_776_DATA; + FWK_RW uint32_t DENALI_PHY_777_DATA; + FWK_RW uint32_t DENALI_PHY_778_DATA; + FWK_RW uint32_t DENALI_PHY_779_DATA; + FWK_RW uint32_t DENALI_PHY_780_DATA; + FWK_RW uint32_t DENALI_PHY_781_DATA; + FWK_RW uint32_t DENALI_PHY_782_DATA; + FWK_RW uint32_t DENALI_PHY_783_DATA; + FWK_RW uint32_t DENALI_PHY_784_DATA; + FWK_RW uint32_t DENALI_PHY_785_DATA; + FWK_RW uint32_t DENALI_PHY_786_DATA; + FWK_RW uint32_t DENALI_PHY_787_DATA; + FWK_RW uint32_t DENALI_PHY_788_DATA; + FWK_RW uint32_t DENALI_PHY_789_DATA; + FWK_RW uint32_t DENALI_PHY_790_DATA; + FWK_RW uint32_t DENALI_PHY_791_DATA; + FWK_RW uint32_t DENALI_PHY_792_DATA; + FWK_RW uint32_t DENALI_PHY_793_DATA; + FWK_RW uint32_t DENALI_PHY_794_DATA; + FWK_RW uint32_t DENALI_PHY_795_DATA; + FWK_RW uint32_t DENALI_PHY_796_DATA; + FWK_RW uint32_t DENALI_PHY_797_DATA; + FWK_RW uint32_t DENALI_PHY_798_DATA; + FWK_RW uint32_t DENALI_PHY_799_DATA; + FWK_RW uint32_t DENALI_PHY_800_DATA; + FWK_RW uint32_t DENALI_PHY_801_DATA; + FWK_RW uint32_t DENALI_PHY_802_DATA; + FWK_RW uint32_t DENALI_PHY_803_DATA; + FWK_RW uint32_t DENALI_PHY_804_DATA; + FWK_RW uint32_t DENALI_PHY_805_DATA; + FWK_RW uint32_t DENALI_PHY_806_DATA; + FWK_RW uint32_t DENALI_PHY_807_DATA; + FWK_RW uint32_t DENALI_PHY_808_DATA; + FWK_RW uint32_t DENALI_PHY_809_DATA; + FWK_RW uint32_t DENALI_PHY_810_DATA; + FWK_RW uint32_t DENALI_PHY_811_DATA; + FWK_RW uint32_t DENALI_PHY_812_DATA; + FWK_RW uint32_t DENALI_PHY_813_DATA; + FWK_RW uint32_t DENALI_PHY_814_DATA; + FWK_RW uint32_t DENALI_PHY_815_DATA; + FWK_RW uint32_t DENALI_PHY_816_DATA; + FWK_RW uint32_t DENALI_PHY_817_DATA; + FWK_RW uint32_t DENALI_PHY_818_DATA; + FWK_RW uint32_t DENALI_PHY_819_DATA; + FWK_RW uint32_t DENALI_PHY_820_DATA; + FWK_RW uint32_t DENALI_PHY_821_DATA; + FWK_RW uint32_t DENALI_PHY_822_DATA; + FWK_RW uint32_t DENALI_PHY_823_DATA; + FWK_RW uint32_t DENALI_PHY_824_DATA; + FWK_RW uint32_t DENALI_PHY_825_DATA; + FWK_RW uint32_t DENALI_PHY_826_DATA; + FWK_RW uint32_t DENALI_PHY_827_DATA; + FWK_RW uint32_t DENALI_PHY_828_DATA; + FWK_RW uint32_t DENALI_PHY_829_DATA; + FWK_RW uint32_t DENALI_PHY_830_DATA; + FWK_RW uint32_t DENALI_PHY_831_DATA; + FWK_RW uint32_t DENALI_PHY_832_DATA; + FWK_RW uint32_t DENALI_PHY_833_DATA; + FWK_RW uint32_t DENALI_PHY_834_DATA; + FWK_RW uint32_t DENALI_PHY_835_DATA; + FWK_RW uint32_t DENALI_PHY_836_DATA; + FWK_RW uint32_t DENALI_PHY_837_DATA; + FWK_RW uint32_t DENALI_PHY_838_DATA; + FWK_RW uint32_t DENALI_PHY_839_DATA; + FWK_RW uint32_t DENALI_PHY_840_DATA; + FWK_RW uint32_t DENALI_PHY_841_DATA; + FWK_RW uint32_t DENALI_PHY_842_DATA; + FWK_RW uint32_t DENALI_PHY_843_DATA; + FWK_RW uint32_t DENALI_PHY_844_DATA; + FWK_RW uint32_t DENALI_PHY_845_DATA; + FWK_RW uint32_t DENALI_PHY_846_DATA; + FWK_RW uint32_t DENALI_PHY_847_DATA; + FWK_RW uint32_t DENALI_PHY_848_DATA; + FWK_RW uint32_t DENALI_PHY_849_DATA; + FWK_RW uint32_t DENALI_PHY_850_DATA; + FWK_RW uint32_t DENALI_PHY_851_DATA; + FWK_RW uint32_t DENALI_PHY_852_DATA; + FWK_RW uint32_t DENALI_PHY_853_DATA; + FWK_RW uint32_t DENALI_PHY_854_DATA; + FWK_RW uint32_t DENALI_PHY_855_DATA; + FWK_RW uint32_t DENALI_PHY_856_DATA; + FWK_RW uint32_t DENALI_PHY_857_DATA; + FWK_RW uint32_t DENALI_PHY_858_DATA; + FWK_RW uint32_t DENALI_PHY_859_DATA; + FWK_RW uint32_t DENALI_PHY_860_DATA; + FWK_RW uint32_t DENALI_PHY_861_DATA; + FWK_RW uint32_t DENALI_PHY_862_DATA; + FWK_RW uint32_t DENALI_PHY_863_DATA; + FWK_RW uint32_t DENALI_PHY_864_DATA; + FWK_RW uint32_t DENALI_PHY_865_DATA; + FWK_RW uint32_t DENALI_PHY_866_DATA; + FWK_RW uint32_t DENALI_PHY_867_DATA; + FWK_RW uint32_t DENALI_PHY_868_DATA; + FWK_RW uint32_t DENALI_PHY_869_DATA; + FWK_RW uint32_t DENALI_PHY_870_DATA; + FWK_RW uint32_t DENALI_PHY_871_DATA; + FWK_RW uint32_t DENALI_PHY_872_DATA; + FWK_RW uint32_t DENALI_PHY_873_DATA; + FWK_RW uint32_t DENALI_PHY_874_DATA; + FWK_RW uint32_t DENALI_PHY_875_DATA; + FWK_RW uint32_t DENALI_PHY_876_DATA; + FWK_RW uint32_t DENALI_PHY_877_DATA; + FWK_RW uint32_t DENALI_PHY_878_DATA; + FWK_RW uint32_t DENALI_PHY_879_DATA; + FWK_RW uint32_t DENALI_PHY_880_DATA; + FWK_RW uint32_t DENALI_PHY_881_DATA; + FWK_RW uint32_t DENALI_PHY_882_DATA; + FWK_RW uint32_t DENALI_PHY_883_DATA; + FWK_RW uint32_t DENALI_PHY_884_DATA; + FWK_RW uint32_t DENALI_PHY_885_DATA; + FWK_RW uint32_t DENALI_PHY_886_DATA; + FWK_RW uint32_t DENALI_PHY_887_DATA; + FWK_RW uint32_t DENALI_PHY_888_DATA; + FWK_RW uint32_t DENALI_PHY_889_DATA; + FWK_RW uint32_t DENALI_PHY_890_DATA; + FWK_RW uint32_t DENALI_PHY_891_DATA; + FWK_RW uint32_t DENALI_PHY_892_DATA; + FWK_RW uint32_t DENALI_PHY_893_DATA; + FWK_RW uint32_t DENALI_PHY_894_DATA; + FWK_RW uint32_t DENALI_PHY_895_DATA; + FWK_RW uint32_t DENALI_PHY_896_DATA; + FWK_RW uint32_t DENALI_PHY_897_DATA; + FWK_RW uint32_t DENALI_PHY_898_DATA; + FWK_RW uint32_t DENALI_PHY_899_DATA; + FWK_RW uint32_t DENALI_PHY_900_DATA; + FWK_RW uint32_t DENALI_PHY_901_DATA; + FWK_RW uint32_t DENALI_PHY_902_DATA; + FWK_RW uint32_t DENALI_PHY_903_DATA; + FWK_RW uint32_t DENALI_PHY_904_DATA; + FWK_RW uint32_t DENALI_PHY_905_DATA; + FWK_RW uint32_t DENALI_PHY_906_DATA; + FWK_RW uint32_t DENALI_PHY_907_DATA; + FWK_RW uint32_t DENALI_PHY_908_DATA; + FWK_RW uint32_t DENALI_PHY_909_DATA; + FWK_RW uint32_t DENALI_PHY_910_DATA; + FWK_RW uint32_t DENALI_PHY_911_DATA; + FWK_RW uint32_t DENALI_PHY_912_DATA; + FWK_RW uint32_t DENALI_PHY_913_DATA; + FWK_RW uint32_t DENALI_PHY_914_DATA; + FWK_RW uint32_t DENALI_PHY_915_DATA; + FWK_RW uint32_t DENALI_PHY_916_DATA; + FWK_RW uint32_t DENALI_PHY_917_DATA; + FWK_RW uint32_t DENALI_PHY_918_DATA; + FWK_RW uint32_t DENALI_PHY_919_DATA; + FWK_RW uint32_t DENALI_PHY_920_DATA; + FWK_RW uint32_t DENALI_PHY_921_DATA; + FWK_RW uint32_t DENALI_PHY_922_DATA; + FWK_RW uint32_t DENALI_PHY_923_DATA; + FWK_RW uint32_t DENALI_PHY_924_DATA; + FWK_RW uint32_t DENALI_PHY_925_DATA; + FWK_RW uint32_t DENALI_PHY_926_DATA; + FWK_RW uint32_t DENALI_PHY_927_DATA; + FWK_RW uint32_t DENALI_PHY_928_DATA; + FWK_RW uint32_t DENALI_PHY_929_DATA; + FWK_RW uint32_t DENALI_PHY_930_DATA; + FWK_RW uint32_t DENALI_PHY_931_DATA; + FWK_RW uint32_t DENALI_PHY_932_DATA; + FWK_RW uint32_t DENALI_PHY_933_DATA; + FWK_RW uint32_t DENALI_PHY_934_DATA; + FWK_RW uint32_t DENALI_PHY_935_DATA; + FWK_RW uint32_t DENALI_PHY_936_DATA; + FWK_RW uint32_t DENALI_PHY_937_DATA; + FWK_RW uint32_t DENALI_PHY_938_DATA; + FWK_RW uint32_t DENALI_PHY_939_DATA; + FWK_RW uint32_t DENALI_PHY_940_DATA; + FWK_RW uint32_t DENALI_PHY_941_DATA; + FWK_RW uint32_t DENALI_PHY_942_DATA; + FWK_RW uint32_t DENALI_PHY_943_DATA; + FWK_RW uint32_t DENALI_PHY_944_DATA; + FWK_RW uint32_t DENALI_PHY_945_DATA; + FWK_RW uint32_t DENALI_PHY_946_DATA; + FWK_RW uint32_t DENALI_PHY_947_DATA; + FWK_RW uint32_t DENALI_PHY_948_DATA; + FWK_RW uint32_t DENALI_PHY_949_DATA; + FWK_RW uint32_t DENALI_PHY_950_DATA; + FWK_RW uint32_t DENALI_PHY_951_DATA; + FWK_RW uint32_t DENALI_PHY_952_DATA; + FWK_RW uint32_t DENALI_PHY_953_DATA; + FWK_RW uint32_t DENALI_PHY_954_DATA; + FWK_RW uint32_t DENALI_PHY_955_DATA; + FWK_RW uint32_t DENALI_PHY_956_DATA; + FWK_RW uint32_t DENALI_PHY_957_DATA; + FWK_RW uint32_t DENALI_PHY_958_DATA; + FWK_RW uint32_t DENALI_PHY_959_DATA; + FWK_RW uint32_t DENALI_PHY_960_DATA; + FWK_RW uint32_t DENALI_PHY_961_DATA; + FWK_RW uint32_t DENALI_PHY_962_DATA; + FWK_RW uint32_t DENALI_PHY_963_DATA; + FWK_RW uint32_t DENALI_PHY_964_DATA; + FWK_RW uint32_t DENALI_PHY_965_DATA; + FWK_RW uint32_t DENALI_PHY_966_DATA; + FWK_RW uint32_t DENALI_PHY_967_DATA; + FWK_RW uint32_t DENALI_PHY_968_DATA; + FWK_RW uint32_t DENALI_PHY_969_DATA; + FWK_RW uint32_t DENALI_PHY_970_DATA; + FWK_RW uint32_t DENALI_PHY_971_DATA; + FWK_RW uint32_t DENALI_PHY_972_DATA; + FWK_RW uint32_t DENALI_PHY_973_DATA; + FWK_RW uint32_t DENALI_PHY_974_DATA; + FWK_RW uint32_t DENALI_PHY_975_DATA; + FWK_RW uint32_t DENALI_PHY_976_DATA; + FWK_RW uint32_t DENALI_PHY_977_DATA; + FWK_RW uint32_t DENALI_PHY_978_DATA; + FWK_RW uint32_t DENALI_PHY_979_DATA; + FWK_RW uint32_t DENALI_PHY_980_DATA; + FWK_RW uint32_t DENALI_PHY_981_DATA; + FWK_RW uint32_t DENALI_PHY_982_DATA; + FWK_RW uint32_t DENALI_PHY_983_DATA; + FWK_RW uint32_t DENALI_PHY_984_DATA; + FWK_RW uint32_t DENALI_PHY_985_DATA; + FWK_RW uint32_t DENALI_PHY_986_DATA; + FWK_RW uint32_t DENALI_PHY_987_DATA; + FWK_RW uint32_t DENALI_PHY_988_DATA; + FWK_RW uint32_t DENALI_PHY_989_DATA; + FWK_RW uint32_t DENALI_PHY_990_DATA; + FWK_RW uint32_t DENALI_PHY_991_DATA; + FWK_RW uint32_t DENALI_PHY_992_DATA; + FWK_RW uint32_t DENALI_PHY_993_DATA; + FWK_RW uint32_t DENALI_PHY_994_DATA; + FWK_RW uint32_t DENALI_PHY_995_DATA; + FWK_RW uint32_t DENALI_PHY_996_DATA; + FWK_RW uint32_t DENALI_PHY_997_DATA; + FWK_RW uint32_t DENALI_PHY_998_DATA; + FWK_RW uint32_t DENALI_PHY_999_DATA; + FWK_RW uint32_t DENALI_PHY_1000_DATA; + FWK_RW uint32_t DENALI_PHY_1001_DATA; + FWK_RW uint32_t DENALI_PHY_1002_DATA; + FWK_RW uint32_t DENALI_PHY_1003_DATA; + FWK_RW uint32_t DENALI_PHY_1004_DATA; + FWK_RW uint32_t DENALI_PHY_1005_DATA; + FWK_RW uint32_t DENALI_PHY_1006_DATA; + FWK_RW uint32_t DENALI_PHY_1007_DATA; + FWK_RW uint32_t DENALI_PHY_1008_DATA; + FWK_RW uint32_t DENALI_PHY_1009_DATA; + FWK_RW uint32_t DENALI_PHY_1010_DATA; + FWK_RW uint32_t DENALI_PHY_1011_DATA; + FWK_RW uint32_t DENALI_PHY_1012_DATA; + FWK_RW uint32_t DENALI_PHY_1013_DATA; + FWK_RW uint32_t DENALI_PHY_1014_DATA; + FWK_RW uint32_t DENALI_PHY_1015_DATA; + FWK_RW uint32_t DENALI_PHY_1016_DATA; + FWK_RW uint32_t DENALI_PHY_1017_DATA; + FWK_RW uint32_t DENALI_PHY_1018_DATA; + FWK_RW uint32_t DENALI_PHY_1019_DATA; + FWK_RW uint32_t DENALI_PHY_1020_DATA; + FWK_RW uint32_t DENALI_PHY_1021_DATA; + FWK_RW uint32_t DENALI_PHY_1022_DATA; + FWK_RW uint32_t DENALI_PHY_1023_DATA; + FWK_RW uint32_t DENALI_PHY_1024_DATA; + FWK_RW uint32_t DENALI_PHY_1025_DATA; + FWK_RW uint32_t DENALI_PHY_1026_DATA; + FWK_RW uint32_t DENALI_PHY_1027_DATA; + FWK_RW uint32_t DENALI_PHY_1028_DATA; + FWK_RW uint32_t DENALI_PHY_1029_DATA; + FWK_RW uint32_t DENALI_PHY_1030_DATA; + FWK_RW uint32_t DENALI_PHY_1031_DATA; + FWK_RW uint32_t DENALI_PHY_1032_DATA; + FWK_RW uint32_t DENALI_PHY_1033_DATA; + FWK_RW uint32_t DENALI_PHY_1034_DATA; + FWK_RW uint32_t DENALI_PHY_1035_DATA; + FWK_RW uint32_t DENALI_PHY_1036_DATA; + FWK_RW uint32_t DENALI_PHY_1037_DATA; + FWK_RW uint32_t DENALI_PHY_1038_DATA; + FWK_RW uint32_t DENALI_PHY_1039_DATA; + FWK_RW uint32_t DENALI_PHY_1040_DATA; + FWK_RW uint32_t DENALI_PHY_1041_DATA; + FWK_RW uint32_t DENALI_PHY_1042_DATA; + FWK_RW uint32_t DENALI_PHY_1043_DATA; + FWK_RW uint32_t DENALI_PHY_1044_DATA; + FWK_RW uint32_t DENALI_PHY_1045_DATA; + FWK_RW uint32_t DENALI_PHY_1046_DATA; + FWK_RW uint32_t DENALI_PHY_1047_DATA; + FWK_RW uint32_t DENALI_PHY_1048_DATA; + FWK_RW uint32_t DENALI_PHY_1049_DATA; + FWK_RW uint32_t DENALI_PHY_1050_DATA; + FWK_RW uint32_t DENALI_PHY_1051_DATA; + FWK_RW uint32_t DENALI_PHY_1052_DATA; + FWK_RW uint32_t DENALI_PHY_1053_DATA; + FWK_RW uint32_t DENALI_PHY_1054_DATA; + FWK_RW uint32_t DENALI_PHY_1055_DATA; + FWK_RW uint32_t DENALI_PHY_1056_DATA; + FWK_RW uint32_t DENALI_PHY_1057_DATA; + FWK_RW uint32_t DENALI_PHY_1058_DATA; + FWK_RW uint32_t DENALI_PHY_1059_DATA; + FWK_RW uint32_t DENALI_PHY_1060_DATA; + FWK_RW uint32_t DENALI_PHY_1061_DATA; + FWK_RW uint32_t DENALI_PHY_1062_DATA; + FWK_RW uint32_t DENALI_PHY_1063_DATA; + FWK_RW uint32_t DENALI_PHY_1064_DATA; + FWK_RW uint32_t DENALI_PHY_1065_DATA; + FWK_RW uint32_t DENALI_PHY_1066_DATA; + FWK_RW uint32_t DENALI_PHY_1067_DATA; + FWK_RW uint32_t DENALI_PHY_1068_DATA; + FWK_RW uint32_t DENALI_PHY_1069_DATA; + FWK_RW uint32_t DENALI_PHY_1070_DATA; + FWK_RW uint32_t DENALI_PHY_1071_DATA; + FWK_RW uint32_t DENALI_PHY_1072_DATA; + FWK_RW uint32_t DENALI_PHY_1073_DATA; + FWK_RW uint32_t DENALI_PHY_1074_DATA; + FWK_RW uint32_t DENALI_PHY_1075_DATA; + FWK_RW uint32_t DENALI_PHY_1076_DATA; + FWK_RW uint32_t DENALI_PHY_1077_DATA; + FWK_RW uint32_t DENALI_PHY_1078_DATA; + FWK_RW uint32_t DENALI_PHY_1079_DATA; + FWK_RW uint32_t DENALI_PHY_1080_DATA; + FWK_RW uint32_t DENALI_PHY_1081_DATA; + FWK_RW uint32_t DENALI_PHY_1082_DATA; + FWK_RW uint32_t DENALI_PHY_1083_DATA; + FWK_RW uint32_t DENALI_PHY_1084_DATA; + FWK_RW uint32_t DENALI_PHY_1085_DATA; + FWK_RW uint32_t DENALI_PHY_1086_DATA; + FWK_RW uint32_t DENALI_PHY_1087_DATA; + FWK_RW uint32_t DENALI_PHY_1088_DATA; + FWK_RW uint32_t DENALI_PHY_1089_DATA; + FWK_RW uint32_t DENALI_PHY_1090_DATA; + FWK_RW uint32_t DENALI_PHY_1091_DATA; + FWK_RW uint32_t DENALI_PHY_1092_DATA; + FWK_RW uint32_t DENALI_PHY_1093_DATA; + FWK_RW uint32_t DENALI_PHY_1094_DATA; + FWK_RW uint32_t DENALI_PHY_1095_DATA; + FWK_RW uint32_t DENALI_PHY_1096_DATA; + FWK_RW uint32_t DENALI_PHY_1097_DATA; + FWK_RW uint32_t DENALI_PHY_1098_DATA; + FWK_RW uint32_t DENALI_PHY_1099_DATA; + FWK_RW uint32_t DENALI_PHY_1100_DATA; + FWK_RW uint32_t DENALI_PHY_1101_DATA; + FWK_RW uint32_t DENALI_PHY_1102_DATA; + FWK_RW uint32_t DENALI_PHY_1103_DATA; + FWK_RW uint32_t DENALI_PHY_1104_DATA; + FWK_RW uint32_t DENALI_PHY_1105_DATA; + FWK_RW uint32_t DENALI_PHY_1106_DATA; + FWK_RW uint32_t DENALI_PHY_1107_DATA; + FWK_RW uint32_t DENALI_PHY_1108_DATA; + FWK_RW uint32_t DENALI_PHY_1109_DATA; + FWK_RW uint32_t DENALI_PHY_1110_DATA; + FWK_RW uint32_t DENALI_PHY_1111_DATA; + FWK_RW uint32_t DENALI_PHY_1112_DATA; + FWK_RW uint32_t DENALI_PHY_1113_DATA; + FWK_RW uint32_t DENALI_PHY_1114_DATA; + FWK_RW uint32_t DENALI_PHY_1115_DATA; + FWK_RW uint32_t DENALI_PHY_1116_DATA; + FWK_RW uint32_t DENALI_PHY_1117_DATA; + FWK_RW uint32_t DENALI_PHY_1118_DATA; + FWK_RW uint32_t DENALI_PHY_1119_DATA; + FWK_RW uint32_t DENALI_PHY_1120_DATA; + FWK_RW uint32_t DENALI_PHY_1121_DATA; + FWK_RW uint32_t DENALI_PHY_1122_DATA; + FWK_RW uint32_t DENALI_PHY_1123_DATA; + FWK_RW uint32_t DENALI_PHY_1124_DATA; + FWK_RW uint32_t DENALI_PHY_1125_DATA; + FWK_RW uint32_t DENALI_PHY_1126_DATA; + FWK_RW uint32_t DENALI_PHY_1127_DATA; + FWK_RW uint32_t DENALI_PHY_1128_DATA; + FWK_RW uint32_t DENALI_PHY_1129_DATA; + FWK_RW uint32_t DENALI_PHY_1130_DATA; + FWK_RW uint32_t DENALI_PHY_1131_DATA; + FWK_RW uint32_t DENALI_PHY_1132_DATA; + FWK_RW uint32_t DENALI_PHY_1133_DATA; + FWK_RW uint32_t DENALI_PHY_1134_DATA; + FWK_RW uint32_t DENALI_PHY_1135_DATA; + FWK_RW uint32_t DENALI_PHY_1136_DATA; + FWK_RW uint32_t DENALI_PHY_1137_DATA; + FWK_RW uint32_t DENALI_PHY_1138_DATA; + FWK_RW uint32_t DENALI_PHY_1139_DATA; + FWK_RW uint32_t DENALI_PHY_1140_DATA; + FWK_RW uint32_t DENALI_PHY_1141_DATA; + FWK_RW uint32_t DENALI_PHY_1142_DATA; + FWK_RW uint32_t DENALI_PHY_1143_DATA; + FWK_RW uint32_t DENALI_PHY_1144_DATA; + FWK_RW uint32_t DENALI_PHY_1145_DATA; + FWK_RW uint32_t DENALI_PHY_1146_DATA; + FWK_RW uint32_t DENALI_PHY_1147_DATA; + FWK_RW uint32_t DENALI_PHY_1148_DATA; + FWK_RW uint32_t DENALI_PHY_1149_DATA; + FWK_RW uint32_t DENALI_PHY_1150_DATA; + FWK_RW uint32_t DENALI_PHY_1151_DATA; + FWK_RW uint32_t DENALI_PHY_1152_DATA; + FWK_RW uint32_t DENALI_PHY_1153_DATA; + FWK_RW uint32_t DENALI_PHY_1154_DATA; + FWK_RW uint32_t DENALI_PHY_1155_DATA; + FWK_RW uint32_t DENALI_PHY_1156_DATA; + FWK_RW uint32_t DENALI_PHY_1157_DATA; + FWK_RW uint32_t DENALI_PHY_1158_DATA; + FWK_RW uint32_t DENALI_PHY_1159_DATA; + FWK_RW uint32_t DENALI_PHY_1160_DATA; + FWK_RW uint32_t DENALI_PHY_1161_DATA; + FWK_RW uint32_t DENALI_PHY_1162_DATA; + FWK_RW uint32_t DENALI_PHY_1163_DATA; + FWK_RW uint32_t DENALI_PHY_1164_DATA; + FWK_RW uint32_t DENALI_PHY_1165_DATA; + FWK_RW uint32_t DENALI_PHY_1166_DATA; + FWK_RW uint32_t DENALI_PHY_1167_DATA; + FWK_RW uint32_t DENALI_PHY_1168_DATA; + FWK_RW uint32_t DENALI_PHY_1169_DATA; + FWK_RW uint32_t DENALI_PHY_1170_DATA; + FWK_RW uint32_t DENALI_PHY_1171_DATA; + FWK_RW uint32_t DENALI_PHY_1172_DATA; + FWK_RW uint32_t DENALI_PHY_1173_DATA; + FWK_RW uint32_t DENALI_PHY_1174_DATA; + FWK_RW uint32_t DENALI_PHY_1175_DATA; + FWK_RW uint32_t DENALI_PHY_1176_DATA; + FWK_RW uint32_t DENALI_PHY_1177_DATA; + FWK_RW uint32_t DENALI_PHY_1178_DATA; + FWK_RW uint32_t DENALI_PHY_1179_DATA; + FWK_RW uint32_t DENALI_PHY_1180_DATA; + FWK_RW uint32_t DENALI_PHY_1181_DATA; + FWK_RW uint32_t DENALI_PHY_1182_DATA; + FWK_RW uint32_t DENALI_PHY_1183_DATA; + FWK_RW uint32_t DENALI_PHY_1184_DATA; + FWK_RW uint32_t DENALI_PHY_1185_DATA; + FWK_RW uint32_t DENALI_PHY_1186_DATA; + FWK_RW uint32_t DENALI_PHY_1187_DATA; + FWK_RW uint32_t DENALI_PHY_1188_DATA; + FWK_RW uint32_t DENALI_PHY_1189_DATA; + FWK_RW uint32_t DENALI_PHY_1190_DATA; + FWK_RW uint32_t DENALI_PHY_1191_DATA; + FWK_RW uint32_t DENALI_PHY_1192_DATA; + FWK_RW uint32_t DENALI_PHY_1193_DATA; + FWK_RW uint32_t DENALI_PHY_1194_DATA; + FWK_RW uint32_t DENALI_PHY_1195_DATA; + FWK_RW uint32_t DENALI_PHY_1196_DATA; + FWK_RW uint32_t DENALI_PHY_1197_DATA; + FWK_RW uint32_t DENALI_PHY_1198_DATA; + FWK_RW uint32_t DENALI_PHY_1199_DATA; + FWK_RW uint32_t DENALI_PHY_1200_DATA; + FWK_RW uint32_t DENALI_PHY_1201_DATA; + FWK_RW uint32_t DENALI_PHY_1202_DATA; + FWK_RW uint32_t DENALI_PHY_1203_DATA; + FWK_RW uint32_t DENALI_PHY_1204_DATA; + FWK_RW uint32_t DENALI_PHY_1205_DATA; + FWK_RW uint32_t DENALI_PHY_1206_DATA; + FWK_RW uint32_t DENALI_PHY_1207_DATA; + FWK_RW uint32_t DENALI_PHY_1208_DATA; + FWK_RW uint32_t DENALI_PHY_1209_DATA; + FWK_RW uint32_t DENALI_PHY_1210_DATA; + FWK_RW uint32_t DENALI_PHY_1211_DATA; + FWK_RW uint32_t DENALI_PHY_1212_DATA; + FWK_RW uint32_t DENALI_PHY_1213_DATA; + FWK_RW uint32_t DENALI_PHY_1214_DATA; + FWK_RW uint32_t DENALI_PHY_1215_DATA; + FWK_RW uint32_t DENALI_PHY_1216_DATA; + FWK_RW uint32_t DENALI_PHY_1217_DATA; + FWK_RW uint32_t DENALI_PHY_1218_DATA; + FWK_RW uint32_t DENALI_PHY_1219_DATA; + FWK_RW uint32_t DENALI_PHY_1220_DATA; + FWK_RW uint32_t DENALI_PHY_1221_DATA; + FWK_RW uint32_t DENALI_PHY_1222_DATA; + FWK_RW uint32_t DENALI_PHY_1223_DATA; + FWK_RW uint32_t DENALI_PHY_1224_DATA; + FWK_RW uint32_t DENALI_PHY_1225_DATA; + FWK_RW uint32_t DENALI_PHY_1226_DATA; + FWK_RW uint32_t DENALI_PHY_1227_DATA; + FWK_RW uint32_t DENALI_PHY_1228_DATA; + FWK_RW uint32_t DENALI_PHY_1229_DATA; + FWK_RW uint32_t DENALI_PHY_1230_DATA; + FWK_RW uint32_t DENALI_PHY_1231_DATA; + FWK_RW uint32_t DENALI_PHY_1232_DATA; + FWK_RW uint32_t DENALI_PHY_1233_DATA; + FWK_RW uint32_t DENALI_PHY_1234_DATA; + FWK_RW uint32_t DENALI_PHY_1235_DATA; + FWK_RW uint32_t DENALI_PHY_1236_DATA; + FWK_RW uint32_t DENALI_PHY_1237_DATA; + FWK_RW uint32_t DENALI_PHY_1238_DATA; + FWK_RW uint32_t DENALI_PHY_1239_DATA; + FWK_RW uint32_t DENALI_PHY_1240_DATA; + FWK_RW uint32_t DENALI_PHY_1241_DATA; + FWK_RW uint32_t DENALI_PHY_1242_DATA; + FWK_RW uint32_t DENALI_PHY_1243_DATA; + FWK_RW uint32_t DENALI_PHY_1244_DATA; + FWK_RW uint32_t DENALI_PHY_1245_DATA; + FWK_RW uint32_t DENALI_PHY_1246_DATA; + FWK_RW uint32_t DENALI_PHY_1247_DATA; + FWK_RW uint32_t DENALI_PHY_1248_DATA; + FWK_RW uint32_t DENALI_PHY_1249_DATA; + FWK_RW uint32_t DENALI_PHY_1250_DATA; + FWK_RW uint32_t DENALI_PHY_1251_DATA; + FWK_RW uint32_t DENALI_PHY_1252_DATA; + FWK_RW uint32_t DENALI_PHY_1253_DATA; + FWK_RW uint32_t DENALI_PHY_1254_DATA; + FWK_RW uint32_t DENALI_PHY_1255_DATA; + FWK_RW uint32_t DENALI_PHY_1256_DATA; + FWK_RW uint32_t DENALI_PHY_1257_DATA; + FWK_RW uint32_t DENALI_PHY_1258_DATA; + FWK_RW uint32_t DENALI_PHY_1259_DATA; + FWK_RW uint32_t DENALI_PHY_1260_DATA; + FWK_RW uint32_t DENALI_PHY_1261_DATA; + FWK_RW uint32_t DENALI_PHY_1262_DATA; + FWK_RW uint32_t DENALI_PHY_1263_DATA; + FWK_RW uint32_t DENALI_PHY_1264_DATA; + FWK_RW uint32_t DENALI_PHY_1265_DATA; + FWK_RW uint32_t DENALI_PHY_1266_DATA; + FWK_RW uint32_t DENALI_PHY_1267_DATA; + FWK_RW uint32_t DENALI_PHY_1268_DATA; + FWK_RW uint32_t DENALI_PHY_1269_DATA; + FWK_RW uint32_t DENALI_PHY_1270_DATA; + FWK_RW uint32_t DENALI_PHY_1271_DATA; + FWK_RW uint32_t DENALI_PHY_1272_DATA; + FWK_RW uint32_t DENALI_PHY_1273_DATA; + FWK_RW uint32_t DENALI_PHY_1274_DATA; + FWK_RW uint32_t DENALI_PHY_1275_DATA; + FWK_RW uint32_t DENALI_PHY_1276_DATA; + FWK_RW uint32_t DENALI_PHY_1277_DATA; + FWK_RW uint32_t DENALI_PHY_1278_DATA; + FWK_RW uint32_t DENALI_PHY_1279_DATA; + FWK_RW uint32_t DENALI_PHY_1280_DATA; + FWK_RW uint32_t DENALI_PHY_1281_DATA; + FWK_RW uint32_t DENALI_PHY_1282_DATA; + FWK_RW uint32_t DENALI_PHY_1283_DATA; + FWK_RW uint32_t DENALI_PHY_1284_DATA; + FWK_RW uint32_t DENALI_PHY_1285_DATA; + FWK_RW uint32_t DENALI_PHY_1286_DATA; + FWK_RW uint32_t DENALI_PHY_1287_DATA; + FWK_RW uint32_t DENALI_PHY_1288_DATA; + FWK_RW uint32_t DENALI_PHY_1289_DATA; + FWK_RW uint32_t DENALI_PHY_1290_DATA; + FWK_RW uint32_t DENALI_PHY_1291_DATA; + FWK_RW uint32_t DENALI_PHY_1292_DATA; + FWK_RW uint32_t DENALI_PHY_1293_DATA; + FWK_RW uint32_t DENALI_PHY_1294_DATA; + FWK_RW uint32_t DENALI_PHY_1295_DATA; + FWK_RW uint32_t DENALI_PHY_1296_DATA; + FWK_RW uint32_t DENALI_PHY_1297_DATA; + FWK_RW uint32_t DENALI_PHY_1298_DATA; + FWK_RW uint32_t DENALI_PHY_1299_DATA; + FWK_RW uint32_t DENALI_PHY_1300_DATA; + FWK_RW uint32_t DENALI_PHY_1301_DATA; + FWK_RW uint32_t DENALI_PHY_1302_DATA; + FWK_RW uint32_t DENALI_PHY_1303_DATA; + FWK_RW uint32_t DENALI_PHY_1304_DATA; + FWK_RW uint32_t DENALI_PHY_1305_DATA; + FWK_RW uint32_t DENALI_PHY_1306_DATA; + FWK_RW uint32_t DENALI_PHY_1307_DATA; + FWK_RW uint32_t DENALI_PHY_1308_DATA; + FWK_RW uint32_t DENALI_PHY_1309_DATA; + FWK_RW uint32_t DENALI_PHY_1310_DATA; + FWK_RW uint32_t DENALI_PHY_1311_DATA; + FWK_RW uint32_t DENALI_PHY_1312_DATA; + FWK_RW uint32_t DENALI_PHY_1313_DATA; + FWK_RW uint32_t DENALI_PHY_1314_DATA; + FWK_RW uint32_t DENALI_PHY_1315_DATA; + FWK_RW uint32_t DENALI_PHY_1316_DATA; + FWK_RW uint32_t DENALI_PHY_1317_DATA; + FWK_RW uint32_t DENALI_PHY_1318_DATA; + FWK_RW uint32_t DENALI_PHY_1319_DATA; + FWK_RW uint32_t DENALI_PHY_1320_DATA; + FWK_RW uint32_t DENALI_PHY_1321_DATA; + FWK_RW uint32_t DENALI_PHY_1322_DATA; + FWK_RW uint32_t DENALI_PHY_1323_DATA; + FWK_RW uint32_t DENALI_PHY_1324_DATA; + FWK_RW uint32_t DENALI_PHY_1325_DATA; + FWK_RW uint32_t DENALI_PHY_1326_DATA; + FWK_RW uint32_t DENALI_PHY_1327_DATA; + FWK_RW uint32_t DENALI_PHY_1328_DATA; + FWK_RW uint32_t DENALI_PHY_1329_DATA; + FWK_RW uint32_t DENALI_PHY_1330_DATA; + FWK_RW uint32_t DENALI_PHY_1331_DATA; + FWK_RW uint32_t DENALI_PHY_1332_DATA; + FWK_RW uint32_t DENALI_PHY_1333_DATA; + FWK_RW uint32_t DENALI_PHY_1334_DATA; + FWK_RW uint32_t DENALI_PHY_1335_DATA; + FWK_RW uint32_t DENALI_PHY_1336_DATA; + FWK_RW uint32_t DENALI_PHY_1337_DATA; + FWK_RW uint32_t DENALI_PHY_1338_DATA; + FWK_RW uint32_t DENALI_PHY_1339_DATA; + FWK_RW uint32_t DENALI_PHY_1340_DATA; + FWK_RW uint32_t DENALI_PHY_1341_DATA; + FWK_RW uint32_t DENALI_PHY_1342_DATA; + FWK_RW uint32_t DENALI_PHY_1343_DATA; + FWK_RW uint32_t DENALI_PHY_1344_DATA; + FWK_RW uint32_t DENALI_PHY_1345_DATA; + FWK_RW uint32_t DENALI_PHY_1346_DATA; + FWK_RW uint32_t DENALI_PHY_1347_DATA; + FWK_RW uint32_t DENALI_PHY_1348_DATA; + FWK_RW uint32_t DENALI_PHY_1349_DATA; + FWK_RW uint32_t DENALI_PHY_1350_DATA; + FWK_RW uint32_t DENALI_PHY_1351_DATA; + FWK_RW uint32_t DENALI_PHY_1352_DATA; + FWK_RW uint32_t DENALI_PHY_1353_DATA; + FWK_RW uint32_t DENALI_PHY_1354_DATA; + FWK_RW uint32_t DENALI_PHY_1355_DATA; + FWK_RW uint32_t DENALI_PHY_1356_DATA; + FWK_RW uint32_t DENALI_PHY_1357_DATA; + FWK_RW uint32_t DENALI_PHY_1358_DATA; + FWK_RW uint32_t DENALI_PHY_1359_DATA; + FWK_RW uint32_t DENALI_PHY_1360_DATA; + FWK_RW uint32_t DENALI_PHY_1361_DATA; + FWK_RW uint32_t DENALI_PHY_1362_DATA; + FWK_RW uint32_t DENALI_PHY_1363_DATA; + FWK_RW uint32_t DENALI_PHY_1364_DATA; + FWK_RW uint32_t DENALI_PHY_1365_DATA; + FWK_RW uint32_t DENALI_PHY_1366_DATA; + FWK_RW uint32_t DENALI_PHY_1367_DATA; + FWK_RW uint32_t DENALI_PHY_1368_DATA; + FWK_RW uint32_t DENALI_PHY_1369_DATA; + FWK_RW uint32_t DENALI_PHY_1370_DATA; + FWK_RW uint32_t DENALI_PHY_1371_DATA; + FWK_RW uint32_t DENALI_PHY_1372_DATA; + FWK_RW uint32_t DENALI_PHY_1373_DATA; + FWK_RW uint32_t DENALI_PHY_1374_DATA; + FWK_RW uint32_t DENALI_PHY_1375_DATA; + FWK_RW uint32_t DENALI_PHY_1376_DATA; + FWK_RW uint32_t DENALI_PHY_1377_DATA; + FWK_RW uint32_t DENALI_PHY_1378_DATA; + FWK_RW uint32_t DENALI_PHY_1379_DATA; + FWK_RW uint32_t DENALI_PHY_1380_DATA; + FWK_RW uint32_t DENALI_PHY_1381_DATA; + FWK_RW uint32_t DENALI_PHY_1382_DATA; + FWK_RW uint32_t DENALI_PHY_1383_DATA; + FWK_RW uint32_t DENALI_PHY_1384_DATA; + FWK_RW uint32_t DENALI_PHY_1385_DATA; + FWK_RW uint32_t DENALI_PHY_1386_DATA; + FWK_RW uint32_t DENALI_PHY_1387_DATA; + FWK_RW uint32_t DENALI_PHY_1388_DATA; + FWK_RW uint32_t DENALI_PHY_1389_DATA; + FWK_RW uint32_t DENALI_PHY_1390_DATA; + FWK_RW uint32_t DENALI_PHY_1391_DATA; + FWK_RW uint32_t DENALI_PHY_1392_DATA; + FWK_RW uint32_t DENALI_PHY_1393_DATA; + FWK_RW uint32_t DENALI_PHY_1394_DATA; + FWK_RW uint32_t DENALI_PHY_1395_DATA; + FWK_RW uint32_t DENALI_PHY_1396_DATA; + FWK_RW uint32_t DENALI_PHY_1397_DATA; + FWK_RW uint32_t DENALI_PHY_1398_DATA; + FWK_RW uint32_t DENALI_PHY_1399_DATA; + FWK_RW uint32_t DENALI_PHY_1400_DATA; + FWK_RW uint32_t DENALI_PHY_1401_DATA; + FWK_RW uint32_t DENALI_PHY_1402_DATA; + FWK_RW uint32_t DENALI_PHY_1403_DATA; + FWK_RW uint32_t DENALI_PHY_1404_DATA; + FWK_RW uint32_t DENALI_PHY_1405_DATA; + FWK_RW uint32_t DENALI_PHY_1406_DATA; + FWK_RW uint32_t DENALI_PHY_1407_DATA; + FWK_RW uint32_t DENALI_PHY_1408_DATA; + FWK_RW uint32_t DENALI_PHY_1409_DATA; + FWK_RW uint32_t DENALI_PHY_1410_DATA; + FWK_RW uint32_t DENALI_PHY_1411_DATA; + FWK_RW uint32_t DENALI_PHY_1412_DATA; + FWK_RW uint32_t DENALI_PHY_1413_DATA; + FWK_RW uint32_t DENALI_PHY_1414_DATA; + FWK_RW uint32_t DENALI_PHY_1415_DATA; + FWK_RW uint32_t DENALI_PHY_1416_DATA; + FWK_RW uint32_t DENALI_PHY_1417_DATA; + FWK_RW uint32_t DENALI_PHY_1418_DATA; + FWK_RW uint32_t DENALI_PHY_1419_DATA; + FWK_RW uint32_t DENALI_PHY_1420_DATA; + FWK_RW uint32_t DENALI_PHY_1421_DATA; + FWK_RW uint32_t DENALI_PHY_1422_DATA; + FWK_RW uint32_t DENALI_PHY_1423_DATA; + FWK_RW uint32_t DENALI_PHY_1424_DATA; + FWK_RW uint32_t DENALI_PHY_1425_DATA; + FWK_RW uint32_t DENALI_PHY_1426_DATA; + FWK_RW uint32_t DENALI_PHY_1427_DATA; + FWK_RW uint32_t DENALI_PHY_1428_DATA; + FWK_RW uint32_t DENALI_PHY_1429_DATA; + FWK_RW uint32_t DENALI_PHY_1430_DATA; + FWK_RW uint32_t DENALI_PHY_1431_DATA; + FWK_RW uint32_t DENALI_PHY_1432_DATA; + FWK_RW uint32_t DENALI_PHY_1433_DATA; + FWK_RW uint32_t DENALI_PHY_1434_DATA; + FWK_RW uint32_t DENALI_PHY_1435_DATA; + FWK_RW uint32_t DENALI_PHY_1436_DATA; + FWK_RW uint32_t DENALI_PHY_1437_DATA; + FWK_RW uint32_t DENALI_PHY_1438_DATA; + FWK_RW uint32_t DENALI_PHY_1439_DATA; + FWK_RW uint32_t DENALI_PHY_1440_DATA; + FWK_RW uint32_t DENALI_PHY_1441_DATA; + FWK_RW uint32_t DENALI_PHY_1442_DATA; + FWK_RW uint32_t DENALI_PHY_1443_DATA; + FWK_RW uint32_t DENALI_PHY_1444_DATA; + FWK_RW uint32_t DENALI_PHY_1445_DATA; + FWK_RW uint32_t DENALI_PHY_1446_DATA; + FWK_RW uint32_t DENALI_PHY_1447_DATA; + FWK_RW uint32_t DENALI_PHY_1448_DATA; + FWK_RW uint32_t DENALI_PHY_1449_DATA; + FWK_RW uint32_t DENALI_PHY_1450_DATA; + FWK_RW uint32_t DENALI_PHY_1451_DATA; + FWK_RW uint32_t DENALI_PHY_1452_DATA; + FWK_RW uint32_t DENALI_PHY_1453_DATA; + FWK_RW uint32_t DENALI_PHY_1454_DATA; + FWK_RW uint32_t DENALI_PHY_1455_DATA; + FWK_RW uint32_t DENALI_PHY_1456_DATA; + FWK_RW uint32_t DENALI_PHY_1457_DATA; + FWK_RW uint32_t DENALI_PHY_1458_DATA; + FWK_RW uint32_t DENALI_PHY_1459_DATA; + FWK_RW uint32_t DENALI_PHY_1460_DATA; + FWK_RW uint32_t DENALI_PHY_1461_DATA; + FWK_RW uint32_t DENALI_PHY_1462_DATA; + FWK_RW uint32_t DENALI_PHY_1463_DATA; + FWK_RW uint32_t DENALI_PHY_1464_DATA; + FWK_RW uint32_t DENALI_PHY_1465_DATA; + FWK_RW uint32_t DENALI_PHY_1466_DATA; + FWK_RW uint32_t DENALI_PHY_1467_DATA; + FWK_RW uint32_t DENALI_PHY_1468_DATA; + FWK_RW uint32_t DENALI_PHY_1469_DATA; + FWK_RW uint32_t DENALI_PHY_1470_DATA; + FWK_RW uint32_t DENALI_PHY_1471_DATA; + FWK_RW uint32_t DENALI_PHY_1472_DATA; + FWK_RW uint32_t DENALI_PHY_1473_DATA; + FWK_RW uint32_t DENALI_PHY_1474_DATA; + FWK_RW uint32_t DENALI_PHY_1475_DATA; + FWK_RW uint32_t DENALI_PHY_1476_DATA; + FWK_RW uint32_t DENALI_PHY_1477_DATA; + FWK_RW uint32_t DENALI_PHY_1478_DATA; + FWK_RW uint32_t DENALI_PHY_1479_DATA; + FWK_RW uint32_t DENALI_PHY_1480_DATA; + FWK_RW uint32_t DENALI_PHY_1481_DATA; + FWK_RW uint32_t DENALI_PHY_1482_DATA; + FWK_RW uint32_t DENALI_PHY_1483_DATA; + FWK_RW uint32_t DENALI_PHY_1484_DATA; + FWK_RW uint32_t DENALI_PHY_1485_DATA; + FWK_RW uint32_t DENALI_PHY_1486_DATA; + FWK_RW uint32_t DENALI_PHY_1487_DATA; + FWK_RW uint32_t DENALI_PHY_1488_DATA; + FWK_RW uint32_t DENALI_PHY_1489_DATA; + FWK_RW uint32_t DENALI_PHY_1490_DATA; + FWK_RW uint32_t DENALI_PHY_1491_DATA; + FWK_RW uint32_t DENALI_PHY_1492_DATA; + FWK_RW uint32_t DENALI_PHY_1493_DATA; + FWK_RW uint32_t DENALI_PHY_1494_DATA; + FWK_RW uint32_t DENALI_PHY_1495_DATA; + FWK_RW uint32_t DENALI_PHY_1496_DATA; + FWK_RW uint32_t DENALI_PHY_1497_DATA; + FWK_RW uint32_t DENALI_PHY_1498_DATA; + FWK_RW uint32_t DENALI_PHY_1499_DATA; + FWK_RW uint32_t DENALI_PHY_1500_DATA; + FWK_RW uint32_t DENALI_PHY_1501_DATA; + FWK_RW uint32_t DENALI_PHY_1502_DATA; + FWK_RW uint32_t DENALI_PHY_1503_DATA; + FWK_RW uint32_t DENALI_PHY_1504_DATA; + FWK_RW uint32_t DENALI_PHY_1505_DATA; + FWK_RW uint32_t DENALI_PHY_1506_DATA; + FWK_RW uint32_t DENALI_PHY_1507_DATA; + FWK_RW uint32_t DENALI_PHY_1508_DATA; + FWK_RW uint32_t DENALI_PHY_1509_DATA; + FWK_RW uint32_t DENALI_PHY_1510_DATA; + FWK_RW uint32_t DENALI_PHY_1511_DATA; + FWK_RW uint32_t DENALI_PHY_1512_DATA; + FWK_RW uint32_t DENALI_PHY_1513_DATA; + FWK_RW uint32_t DENALI_PHY_1514_DATA; + FWK_RW uint32_t DENALI_PHY_1515_DATA; + FWK_RW uint32_t DENALI_PHY_1516_DATA; + FWK_RW uint32_t DENALI_PHY_1517_DATA; + FWK_RW uint32_t DENALI_PHY_1518_DATA; + FWK_RW uint32_t DENALI_PHY_1519_DATA; + FWK_RW uint32_t DENALI_PHY_1520_DATA; + FWK_RW uint32_t DENALI_PHY_1521_DATA; + FWK_RW uint32_t DENALI_PHY_1522_DATA; + FWK_RW uint32_t DENALI_PHY_1523_DATA; + FWK_RW uint32_t DENALI_PHY_1524_DATA; + FWK_RW uint32_t DENALI_PHY_1525_DATA; + FWK_RW uint32_t DENALI_PHY_1526_DATA; + FWK_RW uint32_t DENALI_PHY_1527_DATA; + FWK_RW uint32_t DENALI_PHY_1528_DATA; + FWK_RW uint32_t DENALI_PHY_1529_DATA; + FWK_RW uint32_t DENALI_PHY_1530_DATA; + FWK_RW uint32_t DENALI_PHY_1531_DATA; + FWK_RW uint32_t DENALI_PHY_1532_DATA; + FWK_RW uint32_t DENALI_PHY_1533_DATA; + FWK_RW uint32_t DENALI_PHY_1534_DATA; + FWK_RW uint32_t DENALI_PHY_1535_DATA; + FWK_RW uint32_t DENALI_PHY_1536_DATA; + FWK_RW uint32_t DENALI_PHY_1537_DATA; + FWK_RW uint32_t DENALI_PHY_1538_DATA; + FWK_RW uint32_t DENALI_PHY_1539_DATA; + FWK_RW uint32_t DENALI_PHY_1540_DATA; + FWK_RW uint32_t DENALI_PHY_1541_DATA; + FWK_RW uint32_t DENALI_PHY_1542_DATA; + FWK_RW uint32_t DENALI_PHY_1543_DATA; + FWK_RW uint32_t DENALI_PHY_1544_DATA; + FWK_RW uint32_t DENALI_PHY_1545_DATA; + FWK_RW uint32_t DENALI_PHY_1546_DATA; + FWK_RW uint32_t DENALI_PHY_1547_DATA; + FWK_RW uint32_t DENALI_PHY_1548_DATA; + FWK_RW uint32_t DENALI_PHY_1549_DATA; + FWK_RW uint32_t DENALI_PHY_1550_DATA; + FWK_RW uint32_t DENALI_PHY_1551_DATA; + FWK_RW uint32_t DENALI_PHY_1552_DATA; + FWK_RW uint32_t DENALI_PHY_1553_DATA; + FWK_RW uint32_t DENALI_PHY_1554_DATA; + FWK_RW uint32_t DENALI_PHY_1555_DATA; + FWK_RW uint32_t DENALI_PHY_1556_DATA; + FWK_RW uint32_t DENALI_PHY_1557_DATA; + FWK_RW uint32_t DENALI_PHY_1558_DATA; + FWK_RW uint32_t DENALI_PHY_1559_DATA; + FWK_RW uint32_t DENALI_PHY_1560_DATA; + FWK_RW uint32_t DENALI_PHY_1561_DATA; + FWK_RW uint32_t DENALI_PHY_1562_DATA; + FWK_RW uint32_t DENALI_PHY_1563_DATA; + FWK_RW uint32_t DENALI_PHY_1564_DATA; + FWK_RW uint32_t DENALI_PHY_1565_DATA; + FWK_RW uint32_t DENALI_PHY_1566_DATA; + FWK_RW uint32_t DENALI_PHY_1567_DATA; + FWK_RW uint32_t DENALI_PHY_1568_DATA; + FWK_RW uint32_t DENALI_PHY_1569_DATA; + FWK_RW uint32_t DENALI_PHY_1570_DATA; + FWK_RW uint32_t DENALI_PHY_1571_DATA; + FWK_RW uint32_t DENALI_PHY_1572_DATA; + FWK_RW uint32_t DENALI_PHY_1573_DATA; + FWK_RW uint32_t DENALI_PHY_1574_DATA; + FWK_RW uint32_t DENALI_PHY_1575_DATA; + FWK_RW uint32_t DENALI_PHY_1576_DATA; + FWK_RW uint32_t DENALI_PHY_1577_DATA; + FWK_RW uint32_t DENALI_PHY_1578_DATA; + FWK_RW uint32_t DENALI_PHY_1579_DATA; + FWK_RW uint32_t DENALI_PHY_1580_DATA; + FWK_RW uint32_t DENALI_PHY_1581_DATA; + FWK_RW uint32_t DENALI_PHY_1582_DATA; + FWK_RW uint32_t DENALI_PHY_1583_DATA; + FWK_RW uint32_t DENALI_PHY_1584_DATA; + FWK_RW uint32_t DENALI_PHY_1585_DATA; + FWK_RW uint32_t DENALI_PHY_1586_DATA; + FWK_RW uint32_t DENALI_PHY_1587_DATA; + FWK_RW uint32_t DENALI_PHY_1588_DATA; + FWK_RW uint32_t DENALI_PHY_1589_DATA; + FWK_RW uint32_t DENALI_PHY_1590_DATA; + FWK_RW uint32_t DENALI_PHY_1591_DATA; + FWK_RW uint32_t DENALI_PHY_1592_DATA; + FWK_RW uint32_t DENALI_PHY_1593_DATA; + FWK_RW uint32_t DENALI_PHY_1594_DATA; + FWK_RW uint32_t DENALI_PHY_1595_DATA; + FWK_RW uint32_t DENALI_PHY_1596_DATA; + FWK_RW uint32_t DENALI_PHY_1597_DATA; + FWK_RW uint32_t DENALI_PHY_1598_DATA; + FWK_RW uint32_t DENALI_PHY_1599_DATA; + FWK_RW uint32_t DENALI_PHY_1600_DATA; + FWK_RW uint32_t DENALI_PHY_1601_DATA; + FWK_RW uint32_t DENALI_PHY_1602_DATA; + FWK_RW uint32_t DENALI_PHY_1603_DATA; + FWK_RW uint32_t DENALI_PHY_1604_DATA; + FWK_RW uint32_t DENALI_PHY_1605_DATA; + FWK_RW uint32_t DENALI_PHY_1606_DATA; + FWK_RW uint32_t DENALI_PHY_1607_DATA; + FWK_RW uint32_t DENALI_PHY_1608_DATA; + FWK_RW uint32_t DENALI_PHY_1609_DATA; + FWK_RW uint32_t DENALI_PHY_1610_DATA; + FWK_RW uint32_t DENALI_PHY_1611_DATA; + FWK_RW uint32_t DENALI_PHY_1612_DATA; + FWK_RW uint32_t DENALI_PHY_1613_DATA; + FWK_RW uint32_t DENALI_PHY_1614_DATA; + FWK_RW uint32_t DENALI_PHY_1615_DATA; + FWK_RW uint32_t DENALI_PHY_1616_DATA; + FWK_RW uint32_t DENALI_PHY_1617_DATA; + FWK_RW uint32_t DENALI_PHY_1618_DATA; + FWK_RW uint32_t DENALI_PHY_1619_DATA; + FWK_RW uint32_t DENALI_PHY_1620_DATA; + FWK_RW uint32_t DENALI_PHY_1621_DATA; + FWK_RW uint32_t DENALI_PHY_1622_DATA; + FWK_RW uint32_t DENALI_PHY_1623_DATA; + FWK_RW uint32_t DENALI_PHY_1624_DATA; + FWK_RW uint32_t DENALI_PHY_1625_DATA; + FWK_RW uint32_t DENALI_PHY_1626_DATA; + FWK_RW uint32_t DENALI_PHY_1627_DATA; + FWK_RW uint32_t DENALI_PHY_1628_DATA; + FWK_RW uint32_t DENALI_PHY_1629_DATA; + FWK_RW uint32_t DENALI_PHY_1630_DATA; + FWK_RW uint32_t DENALI_PHY_1631_DATA; + FWK_RW uint32_t DENALI_PHY_1632_DATA; + FWK_RW uint32_t DENALI_PHY_1633_DATA; + FWK_RW uint32_t DENALI_PHY_1634_DATA; + FWK_RW uint32_t DENALI_PHY_1635_DATA; + FWK_RW uint32_t DENALI_PHY_1636_DATA; + FWK_RW uint32_t DENALI_PHY_1637_DATA; + FWK_RW uint32_t DENALI_PHY_1638_DATA; + FWK_RW uint32_t DENALI_PHY_1639_DATA; + FWK_RW uint32_t DENALI_PHY_1640_DATA; + FWK_RW uint32_t DENALI_PHY_1641_DATA; + FWK_RW uint32_t DENALI_PHY_1642_DATA; + FWK_RW uint32_t DENALI_PHY_1643_DATA; + FWK_RW uint32_t DENALI_PHY_1644_DATA; + FWK_RW uint32_t DENALI_PHY_1645_DATA; + FWK_RW uint32_t DENALI_PHY_1646_DATA; + FWK_RW uint32_t DENALI_PHY_1647_DATA; + FWK_RW uint32_t DENALI_PHY_1648_DATA; + FWK_RW uint32_t DENALI_PHY_1649_DATA; + FWK_RW uint32_t DENALI_PHY_1650_DATA; + FWK_RW uint32_t DENALI_PHY_1651_DATA; + FWK_RW uint32_t DENALI_PHY_1652_DATA; + FWK_RW uint32_t DENALI_PHY_1653_DATA; + FWK_RW uint32_t DENALI_PHY_1654_DATA; + FWK_RW uint32_t DENALI_PHY_1655_DATA; + FWK_RW uint32_t DENALI_PHY_1656_DATA; + FWK_RW uint32_t DENALI_PHY_1657_DATA; + FWK_RW uint32_t DENALI_PHY_1658_DATA; + FWK_RW uint32_t DENALI_PHY_1659_DATA; + FWK_RW uint32_t DENALI_PHY_1660_DATA; + FWK_RW uint32_t DENALI_PHY_1661_DATA; + FWK_RW uint32_t DENALI_PHY_1662_DATA; + FWK_RW uint32_t DENALI_PHY_1663_DATA; + FWK_RW uint32_t DENALI_PHY_1664_DATA; + FWK_RW uint32_t DENALI_PHY_1665_DATA; + FWK_RW uint32_t DENALI_PHY_1666_DATA; + FWK_RW uint32_t DENALI_PHY_1667_DATA; + FWK_RW uint32_t DENALI_PHY_1668_DATA; + FWK_RW uint32_t DENALI_PHY_1669_DATA; + FWK_RW uint32_t DENALI_PHY_1670_DATA; + FWK_RW uint32_t DENALI_PHY_1671_DATA; + FWK_RW uint32_t DENALI_PHY_1672_DATA; + FWK_RW uint32_t DENALI_PHY_1673_DATA; + FWK_RW uint32_t DENALI_PHY_1674_DATA; + FWK_RW uint32_t DENALI_PHY_1675_DATA; + FWK_RW uint32_t DENALI_PHY_1676_DATA; + FWK_RW uint32_t DENALI_PHY_1677_DATA; + FWK_RW uint32_t DENALI_PHY_1678_DATA; + FWK_RW uint32_t DENALI_PHY_1679_DATA; + FWK_RW uint32_t DENALI_PHY_1680_DATA; + FWK_RW uint32_t DENALI_PHY_1681_DATA; + FWK_RW uint32_t DENALI_PHY_1682_DATA; + FWK_RW uint32_t DENALI_PHY_1683_DATA; + FWK_RW uint32_t DENALI_PHY_1684_DATA; + FWK_RW uint32_t DENALI_PHY_1685_DATA; + FWK_RW uint32_t DENALI_PHY_1686_DATA; + FWK_RW uint32_t DENALI_PHY_1687_DATA; + FWK_RW uint32_t DENALI_PHY_1688_DATA; + FWK_RW uint32_t DENALI_PHY_1689_DATA; + FWK_RW uint32_t DENALI_PHY_1690_DATA; + FWK_RW uint32_t DENALI_PHY_1691_DATA; + FWK_RW uint32_t DENALI_PHY_1692_DATA; + FWK_RW uint32_t DENALI_PHY_1693_DATA; + FWK_RW uint32_t DENALI_PHY_1694_DATA; + FWK_RW uint32_t DENALI_PHY_1695_DATA; + FWK_RW uint32_t DENALI_PHY_1696_DATA; + FWK_RW uint32_t DENALI_PHY_1697_DATA; + FWK_RW uint32_t DENALI_PHY_1698_DATA; + FWK_RW uint32_t DENALI_PHY_1699_DATA; + FWK_RW uint32_t DENALI_PHY_1700_DATA; + FWK_RW uint32_t DENALI_PHY_1701_DATA; + FWK_RW uint32_t DENALI_PHY_1702_DATA; + FWK_RW uint32_t DENALI_PHY_1703_DATA; + FWK_RW uint32_t DENALI_PHY_1704_DATA; + FWK_RW uint32_t DENALI_PHY_1705_DATA; + FWK_RW uint32_t DENALI_PHY_1706_DATA; + FWK_RW uint32_t DENALI_PHY_1707_DATA; + FWK_RW uint32_t DENALI_PHY_1708_DATA; + FWK_RW uint32_t DENALI_PHY_1709_DATA; + FWK_RW uint32_t DENALI_PHY_1710_DATA; + FWK_RW uint32_t DENALI_PHY_1711_DATA; + FWK_RW uint32_t DENALI_PHY_1712_DATA; + FWK_RW uint32_t DENALI_PHY_1713_DATA; + FWK_RW uint32_t DENALI_PHY_1714_DATA; + FWK_RW uint32_t DENALI_PHY_1715_DATA; + FWK_RW uint32_t DENALI_PHY_1716_DATA; + FWK_RW uint32_t DENALI_PHY_1717_DATA; + FWK_RW uint32_t DENALI_PHY_1718_DATA; + FWK_RW uint32_t DENALI_PHY_1719_DATA; + FWK_RW uint32_t DENALI_PHY_1720_DATA; + FWK_RW uint32_t DENALI_PHY_1721_DATA; + FWK_RW uint32_t DENALI_PHY_1722_DATA; + FWK_RW uint32_t DENALI_PHY_1723_DATA; + FWK_RW uint32_t DENALI_PHY_1724_DATA; + FWK_RW uint32_t DENALI_PHY_1725_DATA; + FWK_RW uint32_t DENALI_PHY_1726_DATA; + FWK_RW uint32_t DENALI_PHY_1727_DATA; + FWK_RW uint32_t DENALI_PHY_1728_DATA; + FWK_RW uint32_t DENALI_PHY_1729_DATA; + FWK_RW uint32_t DENALI_PHY_1730_DATA; + FWK_RW uint32_t DENALI_PHY_1731_DATA; + FWK_RW uint32_t DENALI_PHY_1732_DATA; + FWK_RW uint32_t DENALI_PHY_1733_DATA; + FWK_RW uint32_t DENALI_PHY_1734_DATA; + FWK_RW uint32_t DENALI_PHY_1735_DATA; + FWK_RW uint32_t DENALI_PHY_1736_DATA; + FWK_RW uint32_t DENALI_PHY_1737_DATA; + FWK_RW uint32_t DENALI_PHY_1738_DATA; + FWK_RW uint32_t DENALI_PHY_1739_DATA; + FWK_RW uint32_t DENALI_PHY_1740_DATA; + FWK_RW uint32_t DENALI_PHY_1741_DATA; + FWK_RW uint32_t DENALI_PHY_1742_DATA; + FWK_RW uint32_t DENALI_PHY_1743_DATA; + FWK_RW uint32_t DENALI_PHY_1744_DATA; + FWK_RW uint32_t DENALI_PHY_1745_DATA; + FWK_RW uint32_t DENALI_PHY_1746_DATA; + FWK_RW uint32_t DENALI_PHY_1747_DATA; + FWK_RW uint32_t DENALI_PHY_1748_DATA; + FWK_RW uint32_t DENALI_PHY_1749_DATA; + FWK_RW uint32_t DENALI_PHY_1750_DATA; + FWK_RW uint32_t DENALI_PHY_1751_DATA; + FWK_RW uint32_t DENALI_PHY_1752_DATA; + FWK_RW uint32_t DENALI_PHY_1753_DATA; + FWK_RW uint32_t DENALI_PHY_1754_DATA; + FWK_RW uint32_t DENALI_PHY_1755_DATA; + FWK_RW uint32_t DENALI_PHY_1756_DATA; + FWK_RW uint32_t DENALI_PHY_1757_DATA; + FWK_RW uint32_t DENALI_PHY_1758_DATA; + FWK_RW uint32_t DENALI_PHY_1759_DATA; + FWK_RW uint32_t DENALI_PHY_1760_DATA; + FWK_RW uint32_t DENALI_PHY_1761_DATA; + FWK_RW uint32_t DENALI_PHY_1762_DATA; + FWK_RW uint32_t DENALI_PHY_1763_DATA; + FWK_RW uint32_t DENALI_PHY_1764_DATA; + FWK_RW uint32_t DENALI_PHY_1765_DATA; + FWK_RW uint32_t DENALI_PHY_1766_DATA; + FWK_RW uint32_t DENALI_PHY_1767_DATA; + FWK_RW uint32_t DENALI_PHY_1768_DATA; + FWK_RW uint32_t DENALI_PHY_1769_DATA; + FWK_RW uint32_t DENALI_PHY_1770_DATA; + FWK_RW uint32_t DENALI_PHY_1771_DATA; + FWK_RW uint32_t DENALI_PHY_1772_DATA; + FWK_RW uint32_t DENALI_PHY_1773_DATA; + FWK_RW uint32_t DENALI_PHY_1774_DATA; + FWK_RW uint32_t DENALI_PHY_1775_DATA; + FWK_RW uint32_t DENALI_PHY_1776_DATA; + FWK_RW uint32_t DENALI_PHY_1777_DATA; + FWK_RW uint32_t DENALI_PHY_1778_DATA; + FWK_RW uint32_t DENALI_PHY_1779_DATA; + FWK_RW uint32_t DENALI_PHY_1780_DATA; + FWK_RW uint32_t DENALI_PHY_1781_DATA; + FWK_RW uint32_t DENALI_PHY_1782_DATA; + FWK_RW uint32_t DENALI_PHY_1783_DATA; + FWK_RW uint32_t DENALI_PHY_1784_DATA; + FWK_RW uint32_t DENALI_PHY_1785_DATA; + FWK_RW uint32_t DENALI_PHY_1786_DATA; + FWK_RW uint32_t DENALI_PHY_1787_DATA; + FWK_RW uint32_t DENALI_PHY_1788_DATA; + FWK_RW uint32_t DENALI_PHY_1789_DATA; + FWK_RW uint32_t DENALI_PHY_1790_DATA; + FWK_RW uint32_t DENALI_PHY_1791_DATA; + FWK_RW uint32_t DENALI_PHY_1792_DATA; + FWK_RW uint32_t DENALI_PHY_1793_DATA; + FWK_RW uint32_t DENALI_PHY_1794_DATA; + FWK_RW uint32_t DENALI_PHY_1795_DATA; + FWK_RW uint32_t DENALI_PHY_1796_DATA; + FWK_RW uint32_t DENALI_PHY_1797_DATA; + FWK_RW uint32_t DENALI_PHY_1798_DATA; + FWK_RW uint32_t DENALI_PHY_1799_DATA; + FWK_RW uint32_t DENALI_PHY_1800_DATA; + FWK_RW uint32_t DENALI_PHY_1801_DATA; + FWK_RW uint32_t DENALI_PHY_1802_DATA; + FWK_RW uint32_t DENALI_PHY_1803_DATA; + FWK_RW uint32_t DENALI_PHY_1804_DATA; + FWK_RW uint32_t DENALI_PHY_1805_DATA; + FWK_RW uint32_t DENALI_PHY_1806_DATA; + FWK_RW uint32_t DENALI_PHY_1807_DATA; + FWK_RW uint32_t DENALI_PHY_1808_DATA; + FWK_RW uint32_t DENALI_PHY_1809_DATA; + FWK_RW uint32_t DENALI_PHY_1810_DATA; + FWK_RW uint32_t DENALI_PHY_1811_DATA; + FWK_RW uint32_t DENALI_PHY_1812_DATA; + FWK_RW uint32_t DENALI_PHY_1813_DATA; + FWK_RW uint32_t DENALI_PHY_1814_DATA; + FWK_RW uint32_t DENALI_PHY_1815_DATA; + FWK_RW uint32_t DENALI_PHY_1816_DATA; + FWK_RW uint32_t DENALI_PHY_1817_DATA; + FWK_RW uint32_t DENALI_PHY_1818_DATA; + FWK_RW uint32_t DENALI_PHY_1819_DATA; + FWK_RW uint32_t DENALI_PHY_1820_DATA; + FWK_RW uint32_t DENALI_PHY_1821_DATA; + FWK_RW uint32_t DENALI_PHY_1822_DATA; + FWK_RW uint32_t DENALI_PHY_1823_DATA; + FWK_RW uint32_t DENALI_PHY_1824_DATA; + FWK_RW uint32_t DENALI_PHY_1825_DATA; + FWK_RW uint32_t DENALI_PHY_1826_DATA; + FWK_RW uint32_t DENALI_PHY_1827_DATA; + FWK_RW uint32_t DENALI_PHY_1828_DATA; + FWK_RW uint32_t DENALI_PHY_1829_DATA; + FWK_RW uint32_t DENALI_PHY_1830_DATA; + FWK_RW uint32_t DENALI_PHY_1831_DATA; + FWK_RW uint32_t DENALI_PHY_1832_DATA; + FWK_RW uint32_t DENALI_PHY_1833_DATA; + FWK_RW uint32_t DENALI_PHY_1834_DATA; + FWK_RW uint32_t DENALI_PHY_1835_DATA; + FWK_RW uint32_t DENALI_PHY_1836_DATA; + FWK_RW uint32_t DENALI_PHY_1837_DATA; + FWK_RW uint32_t DENALI_PHY_1838_DATA; + FWK_RW uint32_t DENALI_PHY_1839_DATA; + FWK_RW uint32_t DENALI_PHY_1840_DATA; + FWK_RW uint32_t DENALI_PHY_1841_DATA; + FWK_RW uint32_t DENALI_PHY_1842_DATA; + FWK_RW uint32_t DENALI_PHY_1843_DATA; + FWK_RW uint32_t DENALI_PHY_1844_DATA; + FWK_RW uint32_t DENALI_PHY_1845_DATA; + FWK_RW uint32_t DENALI_PHY_1846_DATA; + FWK_RW uint32_t DENALI_PHY_1847_DATA; + FWK_RW uint32_t DENALI_PHY_1848_DATA; + FWK_RW uint32_t DENALI_PHY_1849_DATA; + FWK_RW uint32_t DENALI_PHY_1850_DATA; + FWK_RW uint32_t DENALI_PHY_1851_DATA; + FWK_RW uint32_t DENALI_PHY_1852_DATA; + FWK_RW uint32_t DENALI_PHY_1853_DATA; + FWK_RW uint32_t DENALI_PHY_1854_DATA; + FWK_RW uint32_t DENALI_PHY_1855_DATA; + FWK_RW uint32_t DENALI_PHY_1856_DATA; + FWK_RW uint32_t DENALI_PHY_1857_DATA; + FWK_RW uint32_t DENALI_PHY_1858_DATA; + FWK_RW uint32_t DENALI_PHY_1859_DATA; + FWK_RW uint32_t DENALI_PHY_1860_DATA; + FWK_RW uint32_t DENALI_PHY_1861_DATA; + FWK_RW uint32_t DENALI_PHY_1862_DATA; + FWK_RW uint32_t DENALI_PHY_1863_DATA; + FWK_RW uint32_t DENALI_PHY_1864_DATA; + FWK_RW uint32_t DENALI_PHY_1865_DATA; + FWK_RW uint32_t DENALI_PHY_1866_DATA; + FWK_RW uint32_t DENALI_PHY_1867_DATA; + FWK_RW uint32_t DENALI_PHY_1868_DATA; + FWK_RW uint32_t DENALI_PHY_1869_DATA; + FWK_RW uint32_t DENALI_PHY_1870_DATA; + FWK_RW uint32_t DENALI_PHY_1871_DATA; + FWK_RW uint32_t DENALI_PHY_1872_DATA; + FWK_RW uint32_t DENALI_PHY_1873_DATA; + FWK_RW uint32_t DENALI_PHY_1874_DATA; + FWK_RW uint32_t DENALI_PHY_1875_DATA; + FWK_RW uint32_t DENALI_PHY_1876_DATA; + FWK_RW uint32_t DENALI_PHY_1877_DATA; + FWK_RW uint32_t DENALI_PHY_1878_DATA; + FWK_RW uint32_t DENALI_PHY_1879_DATA; + FWK_RW uint32_t DENALI_PHY_1880_DATA; + FWK_RW uint32_t DENALI_PHY_1881_DATA; + FWK_RW uint32_t DENALI_PHY_1882_DATA; + FWK_RW uint32_t DENALI_PHY_1883_DATA; + FWK_RW uint32_t DENALI_PHY_1884_DATA; + FWK_RW uint32_t DENALI_PHY_1885_DATA; + FWK_RW uint32_t DENALI_PHY_1886_DATA; + FWK_RW uint32_t DENALI_PHY_1887_DATA; + FWK_RW uint32_t DENALI_PHY_1888_DATA; + FWK_RW uint32_t DENALI_PHY_1889_DATA; + FWK_RW uint32_t DENALI_PHY_1890_DATA; + FWK_RW uint32_t DENALI_PHY_1891_DATA; + FWK_RW uint32_t DENALI_PHY_1892_DATA; + FWK_RW uint32_t DENALI_PHY_1893_DATA; + FWK_RW uint32_t DENALI_PHY_1894_DATA; + FWK_RW uint32_t DENALI_PHY_1895_DATA; + FWK_RW uint32_t DENALI_PHY_1896_DATA; + FWK_RW uint32_t DENALI_PHY_1897_DATA; + FWK_RW uint32_t DENALI_PHY_1898_DATA; + FWK_RW uint32_t DENALI_PHY_1899_DATA; + FWK_RW uint32_t DENALI_PHY_1900_DATA; + FWK_RW uint32_t DENALI_PHY_1901_DATA; + FWK_RW uint32_t DENALI_PHY_1902_DATA; + FWK_RW uint32_t DENALI_PHY_1903_DATA; + FWK_RW uint32_t DENALI_PHY_1904_DATA; + FWK_RW uint32_t DENALI_PHY_1905_DATA; + FWK_RW uint32_t DENALI_PHY_1906_DATA; + FWK_RW uint32_t DENALI_PHY_1907_DATA; + FWK_RW uint32_t DENALI_PHY_1908_DATA; + FWK_RW uint32_t DENALI_PHY_1909_DATA; + FWK_RW uint32_t DENALI_PHY_1910_DATA; + FWK_RW uint32_t DENALI_PHY_1911_DATA; + FWK_RW uint32_t DENALI_PHY_1912_DATA; + FWK_RW uint32_t DENALI_PHY_1913_DATA; + FWK_RW uint32_t DENALI_PHY_1914_DATA; + FWK_RW uint32_t DENALI_PHY_1915_DATA; + FWK_RW uint32_t DENALI_PHY_1916_DATA; + FWK_RW uint32_t DENALI_PHY_1917_DATA; + FWK_RW uint32_t DENALI_PHY_1918_DATA; + FWK_RW uint32_t DENALI_PHY_1919_DATA; + FWK_RW uint32_t DENALI_PHY_1920_DATA; + FWK_RW uint32_t DENALI_PHY_1921_DATA; + FWK_RW uint32_t DENALI_PHY_1922_DATA; + FWK_RW uint32_t DENALI_PHY_1923_DATA; + FWK_RW uint32_t DENALI_PHY_1924_DATA; + FWK_RW uint32_t DENALI_PHY_1925_DATA; + FWK_RW uint32_t DENALI_PHY_1926_DATA; + FWK_RW uint32_t DENALI_PHY_1927_DATA; + FWK_RW uint32_t DENALI_PHY_1928_DATA; + FWK_RW uint32_t DENALI_PHY_1929_DATA; + FWK_RW uint32_t DENALI_PHY_1930_DATA; + FWK_RW uint32_t DENALI_PHY_1931_DATA; + FWK_RW uint32_t DENALI_PHY_1932_DATA; + FWK_RW uint32_t DENALI_PHY_1933_DATA; + FWK_RW uint32_t DENALI_PHY_1934_DATA; + FWK_RW uint32_t DENALI_PHY_1935_DATA; + FWK_RW uint32_t DENALI_PHY_1936_DATA; + FWK_RW uint32_t DENALI_PHY_1937_DATA; + FWK_RW uint32_t DENALI_PHY_1938_DATA; + FWK_RW uint32_t DENALI_PHY_1939_DATA; + FWK_RW uint32_t DENALI_PHY_1940_DATA; + FWK_RW uint32_t DENALI_PHY_1941_DATA; + FWK_RW uint32_t DENALI_PHY_1942_DATA; + FWK_RW uint32_t DENALI_PHY_1943_DATA; + FWK_RW uint32_t DENALI_PHY_1944_DATA; + FWK_RW uint32_t DENALI_PHY_1945_DATA; + FWK_RW uint32_t DENALI_PHY_1946_DATA; + FWK_RW uint32_t DENALI_PHY_1947_DATA; + FWK_RW uint32_t DENALI_PHY_1948_DATA; + FWK_RW uint32_t DENALI_PHY_1949_DATA; + FWK_RW uint32_t DENALI_PHY_1950_DATA; + FWK_RW uint32_t DENALI_PHY_1951_DATA; + FWK_RW uint32_t DENALI_PHY_1952_DATA; + FWK_RW uint32_t DENALI_PHY_1953_DATA; + FWK_RW uint32_t DENALI_PHY_1954_DATA; + FWK_RW uint32_t DENALI_PHY_1955_DATA; + FWK_RW uint32_t DENALI_PHY_1956_DATA; + FWK_RW uint32_t DENALI_PHY_1957_DATA; + FWK_RW uint32_t DENALI_PHY_1958_DATA; + FWK_RW uint32_t DENALI_PHY_1959_DATA; + FWK_RW uint32_t DENALI_PHY_1960_DATA; + FWK_RW uint32_t DENALI_PHY_1961_DATA; + FWK_RW uint32_t DENALI_PHY_1962_DATA; + FWK_RW uint32_t DENALI_PHY_1963_DATA; + FWK_RW uint32_t DENALI_PHY_1964_DATA; + FWK_RW uint32_t DENALI_PHY_1965_DATA; + FWK_RW uint32_t DENALI_PHY_1966_DATA; + FWK_RW uint32_t DENALI_PHY_1967_DATA; + FWK_RW uint32_t DENALI_PHY_1968_DATA; + FWK_RW uint32_t DENALI_PHY_1969_DATA; + FWK_RW uint32_t DENALI_PHY_1970_DATA; + FWK_RW uint32_t DENALI_PHY_1971_DATA; + FWK_RW uint32_t DENALI_PHY_1972_DATA; + FWK_RW uint32_t DENALI_PHY_1973_DATA; + FWK_RW uint32_t DENALI_PHY_1974_DATA; + FWK_RW uint32_t DENALI_PHY_1975_DATA; + FWK_RW uint32_t DENALI_PHY_1976_DATA; + FWK_RW uint32_t DENALI_PHY_1977_DATA; + FWK_RW uint32_t DENALI_PHY_1978_DATA; + FWK_RW uint32_t DENALI_PHY_1979_DATA; + FWK_RW uint32_t DENALI_PHY_1980_DATA; + FWK_RW uint32_t DENALI_PHY_1981_DATA; + FWK_RW uint32_t DENALI_PHY_1982_DATA; + FWK_RW uint32_t DENALI_PHY_1983_DATA; + FWK_RW uint32_t DENALI_PHY_1984_DATA; + FWK_RW uint32_t DENALI_PHY_1985_DATA; + FWK_RW uint32_t DENALI_PHY_1986_DATA; + FWK_RW uint32_t DENALI_PHY_1987_DATA; + FWK_RW uint32_t DENALI_PHY_1988_DATA; + FWK_RW uint32_t DENALI_PHY_1989_DATA; + FWK_RW uint32_t DENALI_PHY_1990_DATA; + FWK_RW uint32_t DENALI_PHY_1991_DATA; + FWK_RW uint32_t DENALI_PHY_1992_DATA; + FWK_RW uint32_t DENALI_PHY_1993_DATA; + FWK_RW uint32_t DENALI_PHY_1994_DATA; + FWK_RW uint32_t DENALI_PHY_1995_DATA; + FWK_RW uint32_t DENALI_PHY_1996_DATA; + FWK_RW uint32_t DENALI_PHY_1997_DATA; + FWK_RW uint32_t DENALI_PHY_1998_DATA; + FWK_RW uint32_t DENALI_PHY_1999_DATA; + FWK_RW uint32_t DENALI_PHY_2000_DATA; + FWK_RW uint32_t DENALI_PHY_2001_DATA; + FWK_RW uint32_t DENALI_PHY_2002_DATA; + FWK_RW uint32_t DENALI_PHY_2003_DATA; + FWK_RW uint32_t DENALI_PHY_2004_DATA; + FWK_RW uint32_t DENALI_PHY_2005_DATA; + FWK_RW uint32_t DENALI_PHY_2006_DATA; + FWK_RW uint32_t DENALI_PHY_2007_DATA; + FWK_RW uint32_t DENALI_PHY_2008_DATA; + FWK_RW uint32_t DENALI_PHY_2009_DATA; + FWK_RW uint32_t DENALI_PHY_2010_DATA; + FWK_RW uint32_t DENALI_PHY_2011_DATA; + FWK_RW uint32_t DENALI_PHY_2012_DATA; + FWK_RW uint32_t DENALI_PHY_2013_DATA; + FWK_RW uint32_t DENALI_PHY_2014_DATA; + FWK_RW uint32_t DENALI_PHY_2015_DATA; + FWK_RW uint32_t DENALI_PHY_2016_DATA; + FWK_RW uint32_t DENALI_PHY_2017_DATA; + FWK_RW uint32_t DENALI_PHY_2018_DATA; + FWK_RW uint32_t DENALI_PHY_2019_DATA; + FWK_RW uint32_t DENALI_PHY_2020_DATA; + FWK_RW uint32_t DENALI_PHY_2021_DATA; + FWK_RW uint32_t DENALI_PHY_2022_DATA; + FWK_RW uint32_t DENALI_PHY_2023_DATA; + FWK_RW uint32_t DENALI_PHY_2024_DATA; + FWK_RW uint32_t DENALI_PHY_2025_DATA; + FWK_RW uint32_t DENALI_PHY_2026_DATA; + FWK_RW uint32_t DENALI_PHY_2027_DATA; + FWK_RW uint32_t DENALI_PHY_2028_DATA; + FWK_RW uint32_t DENALI_PHY_2029_DATA; + FWK_RW uint32_t DENALI_PHY_2030_DATA; + FWK_RW uint32_t DENALI_PHY_2031_DATA; + FWK_RW uint32_t DENALI_PHY_2032_DATA; + FWK_RW uint32_t DENALI_PHY_2033_DATA; + FWK_RW uint32_t DENALI_PHY_2034_DATA; + FWK_RW uint32_t DENALI_PHY_2035_DATA; + FWK_RW uint32_t DENALI_PHY_2036_DATA; + FWK_RW uint32_t DENALI_PHY_2037_DATA; + FWK_RW uint32_t DENALI_PHY_2038_DATA; + FWK_RW uint32_t DENALI_PHY_2039_DATA; + FWK_RW uint32_t DENALI_PHY_2040_DATA; + FWK_RW uint32_t DENALI_PHY_2041_DATA; + FWK_RW uint32_t DENALI_PHY_2042_DATA; + FWK_RW uint32_t DENALI_PHY_2043_DATA; + FWK_RW uint32_t DENALI_PHY_2044_DATA; + FWK_RW uint32_t DENALI_PHY_2045_DATA; + FWK_RW uint32_t DENALI_PHY_2046_DATA; + FWK_RW uint32_t DENALI_PHY_2047_DATA; + FWK_RW uint32_t DENALI_PHY_2048_DATA; + FWK_RW uint32_t DENALI_PHY_2049_DATA; + FWK_RW uint32_t DENALI_PHY_2050_DATA; + FWK_RW uint32_t DENALI_PHY_2051_DATA; + FWK_RW uint32_t DENALI_PHY_2052_DATA; + FWK_RW uint32_t DENALI_PHY_2053_DATA; + FWK_RW uint32_t DENALI_PHY_2054_DATA; + FWK_RW uint32_t DENALI_PHY_2055_DATA; + FWK_RW uint32_t DENALI_PHY_2056_DATA; + FWK_RW uint32_t DENALI_PHY_2057_DATA; + FWK_RW uint32_t DENALI_PHY_2058_DATA; + FWK_RW uint32_t DENALI_PHY_2059_DATA; + FWK_RW uint32_t DENALI_PHY_2060_DATA; + FWK_RW uint32_t DENALI_PHY_2061_DATA; + FWK_RW uint32_t DENALI_PHY_2062_DATA; + FWK_RW uint32_t DENALI_PHY_2063_DATA; + FWK_RW uint32_t DENALI_PHY_2064_DATA; + FWK_RW uint32_t DENALI_PHY_2065_DATA; + FWK_RW uint32_t DENALI_PHY_2066_DATA; + FWK_RW uint32_t DENALI_PHY_2067_DATA; + FWK_RW uint32_t DENALI_PHY_2068_DATA; + FWK_RW uint32_t DENALI_PHY_2069_DATA; + FWK_RW uint32_t DENALI_PHY_2070_DATA; + FWK_RW uint32_t DENALI_PHY_2071_DATA; + FWK_RW uint32_t DENALI_PHY_2072_DATA; + FWK_RW uint32_t DENALI_PHY_2073_DATA; + FWK_RW uint32_t DENALI_PHY_2074_DATA; + FWK_RW uint32_t DENALI_PHY_2075_DATA; + FWK_RW uint32_t DENALI_PHY_2076_DATA; + FWK_RW uint32_t DENALI_PHY_2077_DATA; + FWK_RW uint32_t DENALI_PHY_2078_DATA; + FWK_RW uint32_t DENALI_PHY_2079_DATA; + FWK_RW uint32_t DENALI_PHY_2080_DATA; + FWK_RW uint32_t DENALI_PHY_2081_DATA; + FWK_RW uint32_t DENALI_PHY_2082_DATA; + FWK_RW uint32_t DENALI_PHY_2083_DATA; + FWK_RW uint32_t DENALI_PHY_2084_DATA; + FWK_RW uint32_t DENALI_PHY_2085_DATA; + FWK_RW uint32_t DENALI_PHY_2086_DATA; + FWK_RW uint32_t DENALI_PHY_2087_DATA; + FWK_RW uint32_t DENALI_PHY_2088_DATA; + FWK_RW uint32_t DENALI_PHY_2089_DATA; + FWK_RW uint32_t DENALI_PHY_2090_DATA; + FWK_RW uint32_t DENALI_PHY_2091_DATA; + FWK_RW uint32_t DENALI_PHY_2092_DATA; + FWK_RW uint32_t DENALI_PHY_2093_DATA; + FWK_RW uint32_t DENALI_PHY_2094_DATA; + FWK_RW uint32_t DENALI_PHY_2095_DATA; + FWK_RW uint32_t DENALI_PHY_2096_DATA; + FWK_RW uint32_t DENALI_PHY_2097_DATA; + FWK_RW uint32_t DENALI_PHY_2098_DATA; + FWK_RW uint32_t DENALI_PHY_2099_DATA; + FWK_RW uint32_t DENALI_PHY_2100_DATA; + FWK_RW uint32_t DENALI_PHY_2101_DATA; + FWK_RW uint32_t DENALI_PHY_2102_DATA; + FWK_RW uint32_t DENALI_PHY_2103_DATA; + FWK_RW uint32_t DENALI_PHY_2104_DATA; + FWK_RW uint32_t DENALI_PHY_2105_DATA; + FWK_RW uint32_t DENALI_PHY_2106_DATA; + FWK_RW uint32_t DENALI_PHY_2107_DATA; + FWK_RW uint32_t DENALI_PHY_2108_DATA; + FWK_RW uint32_t DENALI_PHY_2109_DATA; + FWK_RW uint32_t DENALI_PHY_2110_DATA; + FWK_RW uint32_t DENALI_PHY_2111_DATA; + FWK_RW uint32_t DENALI_PHY_2112_DATA; + FWK_RW uint32_t DENALI_PHY_2113_DATA; + FWK_RW uint32_t DENALI_PHY_2114_DATA; + FWK_RW uint32_t DENALI_PHY_2115_DATA; + FWK_RW uint32_t DENALI_PHY_2116_DATA; + FWK_RW uint32_t DENALI_PHY_2117_DATA; + FWK_RW uint32_t DENALI_PHY_2118_DATA; + FWK_RW uint32_t DENALI_PHY_2119_DATA; + FWK_RW uint32_t DENALI_PHY_2120_DATA; + FWK_RW uint32_t DENALI_PHY_2121_DATA; + FWK_RW uint32_t DENALI_PHY_2122_DATA; + FWK_RW uint32_t DENALI_PHY_2123_DATA; + FWK_RW uint32_t DENALI_PHY_2124_DATA; + FWK_RW uint32_t DENALI_PHY_2125_DATA; + FWK_RW uint32_t DENALI_PHY_2126_DATA; + FWK_RW uint32_t DENALI_PHY_2127_DATA; + FWK_RW uint32_t DENALI_PHY_2128_DATA; + FWK_RW uint32_t DENALI_PHY_2129_DATA; + FWK_RW uint32_t DENALI_PHY_2130_DATA; + FWK_RW uint32_t DENALI_PHY_2131_DATA; + FWK_RW uint32_t DENALI_PHY_2132_DATA; + FWK_RW uint32_t DENALI_PHY_2133_DATA; + FWK_RW uint32_t DENALI_PHY_2134_DATA; + FWK_RW uint32_t DENALI_PHY_2135_DATA; + FWK_RW uint32_t DENALI_PHY_2136_DATA; + FWK_RW uint32_t DENALI_PHY_2137_DATA; + FWK_RW uint32_t DENALI_PHY_2138_DATA; + FWK_RW uint32_t DENALI_PHY_2139_DATA; + FWK_RW uint32_t DENALI_PHY_2140_DATA; + FWK_RW uint32_t DENALI_PHY_2141_DATA; + FWK_RW uint32_t DENALI_PHY_2142_DATA; + FWK_RW uint32_t DENALI_PHY_2143_DATA; + FWK_RW uint32_t DENALI_PHY_2144_DATA; + FWK_RW uint32_t DENALI_PHY_2145_DATA; + FWK_RW uint32_t DENALI_PHY_2146_DATA; + FWK_RW uint32_t DENALI_PHY_2147_DATA; + FWK_RW uint32_t DENALI_PHY_2148_DATA; + FWK_RW uint32_t DENALI_PHY_2149_DATA; + FWK_RW uint32_t DENALI_PHY_2150_DATA; + FWK_RW uint32_t DENALI_PHY_2151_DATA; + FWK_RW uint32_t DENALI_PHY_2152_DATA; + FWK_RW uint32_t DENALI_PHY_2153_DATA; + FWK_RW uint32_t DENALI_PHY_2154_DATA; + FWK_RW uint32_t DENALI_PHY_2155_DATA; + FWK_RW uint32_t DENALI_PHY_2156_DATA; + FWK_RW uint32_t DENALI_PHY_2157_DATA; + FWK_RW uint32_t DENALI_PHY_2158_DATA; + FWK_RW uint32_t DENALI_PHY_2159_DATA; + FWK_RW uint32_t DENALI_PHY_2160_DATA; + FWK_RW uint32_t DENALI_PHY_2161_DATA; + FWK_RW uint32_t DENALI_PHY_2162_DATA; + FWK_RW uint32_t DENALI_PHY_2163_DATA; + FWK_RW uint32_t DENALI_PHY_2164_DATA; + FWK_RW uint32_t DENALI_PHY_2165_DATA; + FWK_RW uint32_t DENALI_PHY_2166_DATA; + FWK_RW uint32_t DENALI_PHY_2167_DATA; + FWK_RW uint32_t DENALI_PHY_2168_DATA; + FWK_RW uint32_t DENALI_PHY_2169_DATA; + FWK_RW uint32_t DENALI_PHY_2170_DATA; + FWK_RW uint32_t DENALI_PHY_2171_DATA; + FWK_RW uint32_t DENALI_PHY_2172_DATA; + FWK_RW uint32_t DENALI_PHY_2173_DATA; + FWK_RW uint32_t DENALI_PHY_2174_DATA; + FWK_RW uint32_t DENALI_PHY_2175_DATA; + FWK_RW uint32_t DENALI_PHY_2176_DATA; + FWK_RW uint32_t DENALI_PHY_2177_DATA; + FWK_RW uint32_t DENALI_PHY_2178_DATA; + FWK_RW uint32_t DENALI_PHY_2179_DATA; + FWK_RW uint32_t DENALI_PHY_2180_DATA; + FWK_RW uint32_t DENALI_PHY_2181_DATA; + FWK_RW uint32_t DENALI_PHY_2182_DATA; + FWK_RW uint32_t DENALI_PHY_2183_DATA; + FWK_RW uint32_t DENALI_PHY_2184_DATA; + FWK_RW uint32_t DENALI_PHY_2185_DATA; + FWK_RW uint32_t DENALI_PHY_2186_DATA; + FWK_RW uint32_t DENALI_PHY_2187_DATA; + FWK_RW uint32_t DENALI_PHY_2188_DATA; + FWK_RW uint32_t DENALI_PHY_2189_DATA; + FWK_RW uint32_t DENALI_PHY_2190_DATA; + FWK_RW uint32_t DENALI_PHY_2191_DATA; + FWK_RW uint32_t DENALI_PHY_2192_DATA; + FWK_RW uint32_t DENALI_PHY_2193_DATA; + FWK_RW uint32_t DENALI_PHY_2194_DATA; + FWK_RW uint32_t DENALI_PHY_2195_DATA; + FWK_RW uint32_t DENALI_PHY_2196_DATA; + FWK_RW uint32_t DENALI_PHY_2197_DATA; + FWK_RW uint32_t DENALI_PHY_2198_DATA; + FWK_RW uint32_t DENALI_PHY_2199_DATA; + FWK_RW uint32_t DENALI_PHY_2200_DATA; + FWK_RW uint32_t DENALI_PHY_2201_DATA; + FWK_RW uint32_t DENALI_PHY_2202_DATA; + FWK_RW uint32_t DENALI_PHY_2203_DATA; + FWK_RW uint32_t DENALI_PHY_2204_DATA; + FWK_RW uint32_t DENALI_PHY_2205_DATA; + FWK_RW uint32_t DENALI_PHY_2206_DATA; + FWK_RW uint32_t DENALI_PHY_2207_DATA; + FWK_RW uint32_t DENALI_PHY_2208_DATA; + FWK_RW uint32_t DENALI_PHY_2209_DATA; + FWK_RW uint32_t DENALI_PHY_2210_DATA; + FWK_RW uint32_t DENALI_PHY_2211_DATA; + FWK_RW uint32_t DENALI_PHY_2212_DATA; + FWK_RW uint32_t DENALI_PHY_2213_DATA; + FWK_RW uint32_t DENALI_PHY_2214_DATA; + FWK_RW uint32_t DENALI_PHY_2215_DATA; + FWK_RW uint32_t DENALI_PHY_2216_DATA; + FWK_RW uint32_t DENALI_PHY_2217_DATA; + FWK_RW uint32_t DENALI_PHY_2218_DATA; + FWK_RW uint32_t DENALI_PHY_2219_DATA; + FWK_RW uint32_t DENALI_PHY_2220_DATA; + FWK_RW uint32_t DENALI_PHY_2221_DATA; + FWK_RW uint32_t DENALI_PHY_2222_DATA; + FWK_RW uint32_t DENALI_PHY_2223_DATA; + FWK_RW uint32_t DENALI_PHY_2224_DATA; + FWK_RW uint32_t DENALI_PHY_2225_DATA; + FWK_RW uint32_t DENALI_PHY_2226_DATA; + FWK_RW uint32_t DENALI_PHY_2227_DATA; + FWK_RW uint32_t DENALI_PHY_2228_DATA; + FWK_RW uint32_t DENALI_PHY_2229_DATA; + FWK_RW uint32_t DENALI_PHY_2230_DATA; + FWK_RW uint32_t DENALI_PHY_2231_DATA; + FWK_RW uint32_t DENALI_PHY_2232_DATA; + FWK_RW uint32_t DENALI_PHY_2233_DATA; + FWK_RW uint32_t DENALI_PHY_2234_DATA; + FWK_RW uint32_t DENALI_PHY_2235_DATA; + FWK_RW uint32_t DENALI_PHY_2236_DATA; + FWK_RW uint32_t DENALI_PHY_2237_DATA; + FWK_RW uint32_t DENALI_PHY_2238_DATA; + FWK_RW uint32_t DENALI_PHY_2239_DATA; + FWK_RW uint32_t DENALI_PHY_2240_DATA; + FWK_RW uint32_t DENALI_PHY_2241_DATA; + FWK_RW uint32_t DENALI_PHY_2242_DATA; + FWK_RW uint32_t DENALI_PHY_2243_DATA; + FWK_RW uint32_t DENALI_PHY_2244_DATA; + FWK_RW uint32_t DENALI_PHY_2245_DATA; + FWK_RW uint32_t DENALI_PHY_2246_DATA; + FWK_RW uint32_t DENALI_PHY_2247_DATA; + FWK_RW uint32_t DENALI_PHY_2248_DATA; + FWK_RW uint32_t DENALI_PHY_2249_DATA; + FWK_RW uint32_t DENALI_PHY_2250_DATA; + FWK_RW uint32_t DENALI_PHY_2251_DATA; + FWK_RW uint32_t DENALI_PHY_2252_DATA; + FWK_RW uint32_t DENALI_PHY_2253_DATA; + FWK_RW uint32_t DENALI_PHY_2254_DATA; + FWK_RW uint32_t DENALI_PHY_2255_DATA; + FWK_RW uint32_t DENALI_PHY_2256_DATA; + FWK_RW uint32_t DENALI_PHY_2257_DATA; + FWK_RW uint32_t DENALI_PHY_2258_DATA; + FWK_RW uint32_t DENALI_PHY_2259_DATA; + FWK_RW uint32_t DENALI_PHY_2260_DATA; + FWK_RW uint32_t DENALI_PHY_2261_DATA; + FWK_RW uint32_t DENALI_PHY_2262_DATA; + FWK_RW uint32_t DENALI_PHY_2263_DATA; + FWK_RW uint32_t DENALI_PHY_2264_DATA; + FWK_RW uint32_t DENALI_PHY_2265_DATA; + FWK_RW uint32_t DENALI_PHY_2266_DATA; + FWK_RW uint32_t DENALI_PHY_2267_DATA; + FWK_RW uint32_t DENALI_PHY_2268_DATA; + FWK_RW uint32_t DENALI_PHY_2269_DATA; + FWK_RW uint32_t DENALI_PHY_2270_DATA; + FWK_RW uint32_t DENALI_PHY_2271_DATA; + FWK_RW uint32_t DENALI_PHY_2272_DATA; + FWK_RW uint32_t DENALI_PHY_2273_DATA; + FWK_RW uint32_t DENALI_PHY_2274_DATA; + FWK_RW uint32_t DENALI_PHY_2275_DATA; + FWK_RW uint32_t DENALI_PHY_2276_DATA; + FWK_RW uint32_t DENALI_PHY_2277_DATA; + FWK_RW uint32_t DENALI_PHY_2278_DATA; + FWK_RW uint32_t DENALI_PHY_2279_DATA; + FWK_RW uint32_t DENALI_PHY_2280_DATA; + FWK_RW uint32_t DENALI_PHY_2281_DATA; + FWK_RW uint32_t DENALI_PHY_2282_DATA; + FWK_RW uint32_t DENALI_PHY_2283_DATA; + FWK_RW uint32_t DENALI_PHY_2284_DATA; + FWK_RW uint32_t DENALI_PHY_2285_DATA; + FWK_RW uint32_t DENALI_PHY_2286_DATA; + FWK_RW uint32_t DENALI_PHY_2287_DATA; + FWK_RW uint32_t DENALI_PHY_2288_DATA; + FWK_RW uint32_t DENALI_PHY_2289_DATA; + FWK_RW uint32_t DENALI_PHY_2290_DATA; + FWK_RW uint32_t DENALI_PHY_2291_DATA; + FWK_RW uint32_t DENALI_PHY_2292_DATA; + FWK_RW uint32_t DENALI_PHY_2293_DATA; + FWK_RW uint32_t DENALI_PHY_2294_DATA; + FWK_RW uint32_t DENALI_PHY_2295_DATA; + FWK_RW uint32_t DENALI_PHY_2296_DATA; + FWK_RW uint32_t DENALI_PHY_2297_DATA; + FWK_RW uint32_t DENALI_PHY_2298_DATA; + FWK_RW uint32_t DENALI_PHY_2299_DATA; + FWK_RW uint32_t DENALI_PHY_2300_DATA; + FWK_RW uint32_t DENALI_PHY_2301_DATA; + FWK_RW uint32_t DENALI_PHY_2302_DATA; + FWK_RW uint32_t DENALI_PHY_2303_DATA; + FWK_RW uint32_t DENALI_PHY_2304_DATA; + FWK_RW uint32_t DENALI_PHY_2305_DATA; + FWK_RW uint32_t DENALI_PHY_2306_DATA; + FWK_RW uint32_t DENALI_PHY_2307_DATA; + FWK_RW uint32_t DENALI_PHY_2308_DATA; + FWK_RW uint32_t DENALI_PHY_2309_DATA; + FWK_RW uint32_t DENALI_PHY_2310_DATA; + FWK_RW uint32_t DENALI_PHY_2311_DATA; + FWK_RW uint32_t DENALI_PHY_2312_DATA; + FWK_RW uint32_t DENALI_PHY_2313_DATA; + FWK_RW uint32_t DENALI_PHY_2314_DATA; + FWK_RW uint32_t DENALI_PHY_2315_DATA; + FWK_RW uint32_t DENALI_PHY_2316_DATA; + FWK_RW uint32_t DENALI_PHY_2317_DATA; + FWK_RW uint32_t DENALI_PHY_2318_DATA; + FWK_RW uint32_t DENALI_PHY_2319_DATA; + FWK_RW uint32_t DENALI_PHY_2320_DATA; + FWK_RW uint32_t DENALI_PHY_2321_DATA; + FWK_RW uint32_t DENALI_PHY_2322_DATA; + FWK_RW uint32_t DENALI_PHY_2323_DATA; + FWK_RW uint32_t DENALI_PHY_2324_DATA; + FWK_RW uint32_t DENALI_PHY_2325_DATA; + FWK_RW uint32_t DENALI_PHY_2326_DATA; + FWK_RW uint32_t DENALI_PHY_2327_DATA; + FWK_RW uint32_t DENALI_PHY_2328_DATA; + FWK_RW uint32_t DENALI_PHY_2329_DATA; + FWK_RW uint32_t DENALI_PHY_2330_DATA; + FWK_RW uint32_t DENALI_PHY_2331_DATA; + FWK_RW uint32_t DENALI_PHY_2332_DATA; + FWK_RW uint32_t DENALI_PHY_2333_DATA; + FWK_RW uint32_t DENALI_PHY_2334_DATA; + FWK_RW uint32_t DENALI_PHY_2335_DATA; + FWK_RW uint32_t DENALI_PHY_2336_DATA; + FWK_RW uint32_t DENALI_PHY_2337_DATA; + FWK_RW uint32_t DENALI_PHY_2338_DATA; + FWK_RW uint32_t DENALI_PHY_2339_DATA; + FWK_RW uint32_t DENALI_PHY_2340_DATA; + FWK_RW uint32_t DENALI_PHY_2341_DATA; + FWK_RW uint32_t DENALI_PHY_2342_DATA; + FWK_RW uint32_t DENALI_PHY_2343_DATA; + FWK_RW uint32_t DENALI_PHY_2344_DATA; + FWK_RW uint32_t DENALI_PHY_2345_DATA; + FWK_RW uint32_t DENALI_PHY_2346_DATA; + FWK_RW uint32_t DENALI_PHY_2347_DATA; + FWK_RW uint32_t DENALI_PHY_2348_DATA; + FWK_RW uint32_t DENALI_PHY_2349_DATA; + FWK_RW uint32_t DENALI_PHY_2350_DATA; + FWK_RW uint32_t DENALI_PHY_2351_DATA; + FWK_RW uint32_t DENALI_PHY_2352_DATA; + FWK_RW uint32_t DENALI_PHY_2353_DATA; + FWK_RW uint32_t DENALI_PHY_2354_DATA; + FWK_RW uint32_t DENALI_PHY_2355_DATA; + FWK_RW uint32_t DENALI_PHY_2356_DATA; + FWK_RW uint32_t DENALI_PHY_2357_DATA; + FWK_RW uint32_t DENALI_PHY_2358_DATA; + FWK_RW uint32_t DENALI_PHY_2359_DATA; + FWK_RW uint32_t DENALI_PHY_2360_DATA; + FWK_RW uint32_t DENALI_PHY_2361_DATA; + FWK_RW uint32_t DENALI_PHY_2362_DATA; + FWK_RW uint32_t DENALI_PHY_2363_DATA; + FWK_RW uint32_t DENALI_PHY_2364_DATA; + FWK_RW uint32_t DENALI_PHY_2365_DATA; + FWK_RW uint32_t DENALI_PHY_2366_DATA; + FWK_RW uint32_t DENALI_PHY_2367_DATA; + FWK_RW uint32_t DENALI_PHY_2368_DATA; + FWK_RW uint32_t DENALI_PHY_2369_DATA; + FWK_RW uint32_t DENALI_PHY_2370_DATA; + FWK_RW uint32_t DENALI_PHY_2371_DATA; + FWK_RW uint32_t DENALI_PHY_2372_DATA; + FWK_RW uint32_t DENALI_PHY_2373_DATA; + FWK_RW uint32_t DENALI_PHY_2374_DATA; + FWK_RW uint32_t DENALI_PHY_2375_DATA; + FWK_RW uint32_t DENALI_PHY_2376_DATA; + FWK_RW uint32_t DENALI_PHY_2377_DATA; + FWK_RW uint32_t DENALI_PHY_2378_DATA; + FWK_RW uint32_t DENALI_PHY_2379_DATA; + FWK_RW uint32_t DENALI_PHY_2380_DATA; + FWK_RW uint32_t DENALI_PHY_2381_DATA; + FWK_RW uint32_t DENALI_PHY_2382_DATA; + FWK_RW uint32_t DENALI_PHY_2383_DATA; + FWK_RW uint32_t DENALI_PHY_2384_DATA; + FWK_RW uint32_t DENALI_PHY_2385_DATA; + FWK_RW uint32_t DENALI_PHY_2386_DATA; + FWK_RW uint32_t DENALI_PHY_2387_DATA; + FWK_RW uint32_t DENALI_PHY_2388_DATA; + FWK_RW uint32_t DENALI_PHY_2389_DATA; + FWK_RW uint32_t DENALI_PHY_2390_DATA; + FWK_RW uint32_t DENALI_PHY_2391_DATA; + FWK_RW uint32_t DENALI_PHY_2392_DATA; + FWK_RW uint32_t DENALI_PHY_2393_DATA; + FWK_RW uint32_t DENALI_PHY_2394_DATA; + FWK_RW uint32_t DENALI_PHY_2395_DATA; + FWK_RW uint32_t DENALI_PHY_2396_DATA; + FWK_RW uint32_t DENALI_PHY_2397_DATA; + FWK_RW uint32_t DENALI_PHY_2398_DATA; + FWK_RW uint32_t DENALI_PHY_2399_DATA; + FWK_RW uint32_t DENALI_PHY_2400_DATA; + FWK_RW uint32_t DENALI_PHY_2401_DATA; + FWK_RW uint32_t DENALI_PHY_2402_DATA; + FWK_RW uint32_t DENALI_PHY_2403_DATA; + FWK_RW uint32_t DENALI_PHY_2404_DATA; + FWK_RW uint32_t DENALI_PHY_2405_DATA; + FWK_RW uint32_t DENALI_PHY_2406_DATA; + FWK_RW uint32_t DENALI_PHY_2407_DATA; + FWK_RW uint32_t DENALI_PHY_2408_DATA; + FWK_RW uint32_t DENALI_PHY_2409_DATA; + FWK_RW uint32_t DENALI_PHY_2410_DATA; + FWK_RW uint32_t DENALI_PHY_2411_DATA; + FWK_RW uint32_t DENALI_PHY_2412_DATA; + FWK_RW uint32_t DENALI_PHY_2413_DATA; + FWK_RW uint32_t DENALI_PHY_2414_DATA; + FWK_RW uint32_t DENALI_PHY_2415_DATA; + FWK_RW uint32_t DENALI_PHY_2416_DATA; + FWK_RW uint32_t DENALI_PHY_2417_DATA; + FWK_RW uint32_t DENALI_PHY_2418_DATA; + FWK_RW uint32_t DENALI_PHY_2419_DATA; + FWK_RW uint32_t DENALI_PHY_2420_DATA; + FWK_RW uint32_t DENALI_PHY_2421_DATA; + FWK_RW uint32_t DENALI_PHY_2422_DATA; + FWK_RW uint32_t DENALI_PHY_2423_DATA; + FWK_RW uint32_t DENALI_PHY_2424_DATA; + FWK_RW uint32_t DENALI_PHY_2425_DATA; +}; + +#endif /* N1SDP_DDR_PHY_H */ diff --git a/product/n1sdp/module/n1sdp_ddr_phy/include/mod_n1sdp_ddr_phy.h b/product/n1sdp/module/n1sdp_ddr_phy/include/mod_n1sdp_ddr_phy.h new file mode 100644 index 0000000000000000000000000000000000000000..48969f49e96e5aede8855011912cbfbe0143e907 --- /dev/null +++ b/product/n1sdp/module/n1sdp_ddr_phy/include/mod_n1sdp_ddr_phy.h @@ -0,0 +1,44 @@ + /* + * Arm SCP/MCP Software + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * N1SDP DDR-PHY driver + */ +#ifndef MOD_N1SDP_DDR_PHY_H +#define MOD_N1SDP_DDR_PHY_H + +#include + +/*! + * \addtogroup GroupN1SDPModule N1SDP Product Modules + * @{ + */ + +/*! + * \defgroup GroupModuleN1SDPDDRPhy N1SDP DDR PHY Driver + * + * \brief Driver support for N1SDP DDR PHY instances. + * + * \{ + */ + +/*! + * \brief Element configuration. + */ +struct mod_n1sdp_ddr_phy_element_config { + /*! Base address of a device configuration register. */ + uintptr_t ddr; +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_N1SDP_DDR_PHY_H */ diff --git a/product/n1sdp/module/n1sdp_ddr_phy/src/Makefile b/product/n1sdp/module/n1sdp_ddr_phy/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..faa550011504e98698bfb327efce3ab7830fdbe0 --- /dev/null +++ b/product/n1sdp/module/n1sdp_ddr_phy/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := N1SDP DDR PHY +BS_LIB_SOURCES += mod_n1sdp_ddr_phy.c + +include $(BS_DIR)/lib.mk diff --git a/product/n1sdp/module/n1sdp_ddr_phy/src/mod_n1sdp_ddr_phy.c b/product/n1sdp/module/n1sdp_ddr_phy/src/mod_n1sdp_ddr_phy.c new file mode 100644 index 0000000000000000000000000000000000000000..42b1f05c51c714074ca9416062d03d73e3ed0289 --- /dev/null +++ b/product/n1sdp/module/n1sdp_ddr_phy/src/mod_n1sdp_ddr_phy.c @@ -0,0 +1,1676 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * N1SDP DDR-PHY driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static uint8_t PHY_WRITE_PATH_LAT_ADD_1600[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static uint16_t PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[9] = { + 0x100, 0x100, 0, 0, 0, 0, 0, 0x100, 0}; +static uint32_t PHY_PAD_VREF_CTRL_DQ_1600 = 0x1234; +static uint32_t VREF_TRAINING_CTRL_1600 = 0x00042520; + +static struct mod_log_api *log_api; + +/* + * Functions fulfilling this module's interface + */ +static int n1sdp_ddr_phy_config(fwk_id_t element_id) +{ + int status; + struct mod_n1sdp_ddr_phy_reg *ddr_phy; + const struct mod_n1sdp_ddr_phy_element_config *element_config; + + status = fwk_module_check_call(element_id); + if (status != FWK_SUCCESS) + return status; + + element_config = fwk_module_get_data(element_id); + + ddr_phy = (struct mod_n1sdp_ddr_phy_reg *)element_config->ddr; + + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR-PHY] Initializing PHY at 0x%x\n", (uintptr_t)ddr_phy); + + ddr_phy->DENALI_PHY_00_DATA = 0x76543210; + ddr_phy->DENALI_PHY_01_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_02_DATA = 0x00000000; + ddr_phy->DENALI_PHY_03_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_04_DATA = 0x00000000; + ddr_phy->DENALI_PHY_05_DATA = 0x00000000; + ddr_phy->DENALI_PHY_06_DATA = 0x00010000; + ddr_phy->DENALI_PHY_07_DATA = 0x00019990; + ddr_phy->DENALI_PHY_08_DATA = 0x00019990; + ddr_phy->DENALI_PHY_09_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_10_DATA = 0x00010000; + ddr_phy->DENALI_PHY_11_DATA = 0x00000000; + ddr_phy->DENALI_PHY_12_DATA = 0x00000000; + ddr_phy->DENALI_PHY_13_DATA = 0x01000100; + ddr_phy->DENALI_PHY_14_DATA = 0x00000000; + ddr_phy->DENALI_PHY_15_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_16_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_17_DATA = 0x00000008; + ddr_phy->DENALI_PHY_18_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_19_DATA = 0x00005555; + ddr_phy->DENALI_PHY_20_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_21_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_22_DATA = 0x00005656; + ddr_phy->DENALI_PHY_23_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_24_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_25_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_26_DATA = 0x00000000; + ddr_phy->DENALI_PHY_27_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_28_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_29_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_30_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_31_DATA = 0x00000000; + ddr_phy->DENALI_PHY_32_DATA = 0x04080000; + ddr_phy->DENALI_PHY_33_DATA = 0x08040400; + ddr_phy->DENALI_PHY_34_DATA = 0x00000004; + ddr_phy->DENALI_PHY_35_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_36_DATA = 0x00000000; + ddr_phy->DENALI_PHY_37_DATA = 0x00000000; + ddr_phy->DENALI_PHY_38_DATA = 0x00000000; + ddr_phy->DENALI_PHY_39_DATA = 0x00000000; + ddr_phy->DENALI_PHY_40_DATA = 0x00000000; + ddr_phy->DENALI_PHY_41_DATA = 0x00000000; + ddr_phy->DENALI_PHY_42_DATA = 0x00000000; + ddr_phy->DENALI_PHY_43_DATA = 0x00000000; + ddr_phy->DENALI_PHY_44_DATA = 0x00000000; + ddr_phy->DENALI_PHY_45_DATA = 0x00000000; + ddr_phy->DENALI_PHY_46_DATA = 0x00000000; + ddr_phy->DENALI_PHY_47_DATA = 0x00000000; + ddr_phy->DENALI_PHY_48_DATA = 0x00000000; + ddr_phy->DENALI_PHY_49_DATA = 0x00000000; + ddr_phy->DENALI_PHY_50_DATA = 0x00010000; + ddr_phy->DENALI_PHY_51_DATA = 0x00000000; + ddr_phy->DENALI_PHY_52_DATA = 0x00000000; + ddr_phy->DENALI_PHY_53_DATA = 0x00000000; + ddr_phy->DENALI_PHY_54_DATA = 0x00000000; + ddr_phy->DENALI_PHY_55_DATA = 0x20000004; + ddr_phy->DENALI_PHY_56_DATA = 0x00000000; + ddr_phy->DENALI_PHY_57_DATA = 0x00000000; + ddr_phy->DENALI_PHY_58_DATA = 0x00000000; + ddr_phy->DENALI_PHY_59_DATA = 0x00000000; + ddr_phy->DENALI_PHY_60_DATA = 0x00000000; + ddr_phy->DENALI_PHY_61_DATA = 0x00000000; + ddr_phy->DENALI_PHY_62_DATA = 0x00000000; + ddr_phy->DENALI_PHY_63_DATA = 0x00000000; + ddr_phy->DENALI_PHY_64_DATA = 0x00000000; + ddr_phy->DENALI_PHY_65_DATA = 0x00000000; + ddr_phy->DENALI_PHY_66_DATA = 0x00000000; + ddr_phy->DENALI_PHY_67_DATA = 0x00000000; + ddr_phy->DENALI_PHY_68_DATA = 0x00000000; + ddr_phy->DENALI_PHY_69_DATA = 0x00000000; + ddr_phy->DENALI_PHY_70_DATA = 0x00000000; + ddr_phy->DENALI_PHY_71_DATA = 0x00000000; + ddr_phy->DENALI_PHY_72_DATA = 0x00000000; + ddr_phy->DENALI_PHY_73_DATA = 0x00000000; + ddr_phy->DENALI_PHY_74_DATA = 0x00000000; + ddr_phy->DENALI_PHY_75_DATA = 0x00000000; + ddr_phy->DENALI_PHY_76_DATA = 0x00000000; + ddr_phy->DENALI_PHY_77_DATA = 0x00000000; + ddr_phy->DENALI_PHY_78_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_79_DATA = 0x00000000; + ddr_phy->DENALI_PHY_80_DATA = 0x00000000; + ddr_phy->DENALI_PHY_81_DATA = 0x04000000; + ddr_phy->DENALI_PHY_82_DATA = 0x02800280; + ddr_phy->DENALI_PHY_83_DATA = 0x02800280; + ddr_phy->DENALI_PHY_84_DATA = 0x02800280; + ddr_phy->DENALI_PHY_85_DATA = 0x02800280; + ddr_phy->DENALI_PHY_86_DATA = 0x00000280; + ddr_phy->DENALI_PHY_87_DATA = 0x00000000; + ddr_phy->DENALI_PHY_88_DATA = 0x00000000; + ddr_phy->DENALI_PHY_89_DATA = 0x00000000; + ddr_phy->DENALI_PHY_90_DATA = 0x00000000; + ddr_phy->DENALI_PHY_91_DATA = 0x00000000; + ddr_phy->DENALI_PHY_92_DATA = 0x00800080; + ddr_phy->DENALI_PHY_93_DATA = 0x00800080; + ddr_phy->DENALI_PHY_94_DATA = 0x00800080; + ddr_phy->DENALI_PHY_95_DATA = 0x00800080; + ddr_phy->DENALI_PHY_96_DATA = 0x00800080; + ddr_phy->DENALI_PHY_97_DATA = 0x00800080; + ddr_phy->DENALI_PHY_98_DATA = 0x00800080; + ddr_phy->DENALI_PHY_99_DATA = 0x00800080; + ddr_phy->DENALI_PHY_100_DATA = 0x00800080; + ddr_phy->DENALI_PHY_101_DATA = 0x00800080; + ddr_phy->DENALI_PHY_102_DATA = 0x00800080; + ddr_phy->DENALI_PHY_103_DATA = 0x00800080; + ddr_phy->DENALI_PHY_104_DATA = 0x00800080; + ddr_phy->DENALI_PHY_105_DATA = 0x00800080; + ddr_phy->DENALI_PHY_106_DATA = 0x00800080; + ddr_phy->DENALI_PHY_107_DATA = 0x00800080; + ddr_phy->DENALI_PHY_108_DATA = 0x00800080; + ddr_phy->DENALI_PHY_109_DATA = 0x00800080; + ddr_phy->DENALI_PHY_110_DATA = 0x10040001; + ddr_phy->DENALI_PHY_111_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_112_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_113_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_114_DATA = 0x01000000; + ddr_phy->DENALI_PHY_115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_116_DATA = 0x00010166; + ddr_phy->DENALI_PHY_117_DATA = 0x00000200; + ddr_phy->DENALI_PHY_118_DATA = 0x00000000; + ddr_phy->DENALI_PHY_119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_120_DATA = 0x00800802; + ddr_phy->DENALI_PHY_121_DATA = 0x00081020; + ddr_phy->DENALI_PHY_122_DATA = 0x04010000; + ddr_phy->DENALI_PHY_123_DATA = 0x61314042; + ddr_phy->DENALI_PHY_124_DATA = 0x00314000; + ddr_phy->DENALI_PHY_125_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_126_DATA = 0x03000080; + ddr_phy->DENALI_PHY_127_DATA = 0x00000200; + ddr_phy->DENALI_PHY_128_DATA = 0x42100010; + ddr_phy->DENALI_PHY_129_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_130_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_131_DATA = 0x40420100; + ddr_phy->DENALI_PHY_132_DATA = 0x40518031; + ddr_phy->DENALI_PHY_133_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_134_DATA = 0x00000233; + ddr_phy->DENALI_PHY_135_DATA = 0x00000203; + ddr_phy->DENALI_PHY_136_DATA = 0x03000100; + ddr_phy->DENALI_PHY_137_DATA = 0x20202000; + ddr_phy->DENALI_PHY_138_DATA = 0x20202020; + ddr_phy->DENALI_PHY_139_DATA = 0x80202020; + ddr_phy->DENALI_PHY_140_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_141_DATA = 0x00000000; + ddr_phy->DENALI_PHY_142_DATA = 0x00000000; + ddr_phy->DENALI_PHY_256_DATA = 0x76543210; + ddr_phy->DENALI_PHY_257_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_258_DATA = 0x00000000; + ddr_phy->DENALI_PHY_259_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_260_DATA = 0x00000000; + ddr_phy->DENALI_PHY_261_DATA = 0x00000000; + ddr_phy->DENALI_PHY_262_DATA = 0x00010000; + ddr_phy->DENALI_PHY_263_DATA = 0x00019990; + ddr_phy->DENALI_PHY_264_DATA = 0x00019990; + ddr_phy->DENALI_PHY_265_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_266_DATA = 0x00010000; + ddr_phy->DENALI_PHY_267_DATA = 0x00000000; + ddr_phy->DENALI_PHY_268_DATA = 0x00000000; + ddr_phy->DENALI_PHY_269_DATA = 0x01000100; + ddr_phy->DENALI_PHY_270_DATA = 0x00000000; + ddr_phy->DENALI_PHY_271_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_272_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_273_DATA = 0x00000008; + ddr_phy->DENALI_PHY_274_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_275_DATA = 0x00005555; + ddr_phy->DENALI_PHY_276_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_277_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_278_DATA = 0x00005656; + ddr_phy->DENALI_PHY_279_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_280_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_281_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_283_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_284_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_285_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_286_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_287_DATA = 0x00000000; + ddr_phy->DENALI_PHY_288_DATA = 0x04080000; + ddr_phy->DENALI_PHY_289_DATA = 0x08040400; + ddr_phy->DENALI_PHY_290_DATA = 0x00000004; + ddr_phy->DENALI_PHY_291_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_293_DATA = 0x00000000; + ddr_phy->DENALI_PHY_294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_295_DATA = 0x00000000; + ddr_phy->DENALI_PHY_296_DATA = 0x00000000; + ddr_phy->DENALI_PHY_297_DATA = 0x00000000; + ddr_phy->DENALI_PHY_298_DATA = 0x00000000; + ddr_phy->DENALI_PHY_299_DATA = 0x00000000; + ddr_phy->DENALI_PHY_300_DATA = 0x00000000; + ddr_phy->DENALI_PHY_301_DATA = 0x00000000; + ddr_phy->DENALI_PHY_302_DATA = 0x00000000; + ddr_phy->DENALI_PHY_303_DATA = 0x00000000; + ddr_phy->DENALI_PHY_304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_305_DATA = 0x00000000; + ddr_phy->DENALI_PHY_306_DATA = 0x00010000; + ddr_phy->DENALI_PHY_307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_309_DATA = 0x00000000; + ddr_phy->DENALI_PHY_310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_311_DATA = 0x20000004; + ddr_phy->DENALI_PHY_312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_313_DATA = 0x00000000; + ddr_phy->DENALI_PHY_314_DATA = 0x00000000; + ddr_phy->DENALI_PHY_315_DATA = 0x00000000; + ddr_phy->DENALI_PHY_316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_329_DATA = 0x00000000; + ddr_phy->DENALI_PHY_330_DATA = 0x00000000; + ddr_phy->DENALI_PHY_331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_334_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_335_DATA = 0x00000000; + ddr_phy->DENALI_PHY_336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_337_DATA = 0x04000000; + ddr_phy->DENALI_PHY_338_DATA = 0x02800280; + ddr_phy->DENALI_PHY_339_DATA = 0x02800280; + ddr_phy->DENALI_PHY_340_DATA = 0x02800280; + ddr_phy->DENALI_PHY_341_DATA = 0x02800280; + ddr_phy->DENALI_PHY_342_DATA = 0x00000280; + ddr_phy->DENALI_PHY_343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_348_DATA = 0x00800080; + ddr_phy->DENALI_PHY_349_DATA = 0x00800080; + ddr_phy->DENALI_PHY_350_DATA = 0x00800080; + ddr_phy->DENALI_PHY_351_DATA = 0x00800080; + ddr_phy->DENALI_PHY_352_DATA = 0x00800080; + ddr_phy->DENALI_PHY_353_DATA = 0x00800080; + ddr_phy->DENALI_PHY_354_DATA = 0x00800080; + ddr_phy->DENALI_PHY_355_DATA = 0x00800080; + ddr_phy->DENALI_PHY_356_DATA = 0x00800080; + ddr_phy->DENALI_PHY_357_DATA = 0x00800080; + ddr_phy->DENALI_PHY_358_DATA = 0x00800080; + ddr_phy->DENALI_PHY_359_DATA = 0x00800080; + ddr_phy->DENALI_PHY_360_DATA = 0x00800080; + ddr_phy->DENALI_PHY_361_DATA = 0x00800080; + ddr_phy->DENALI_PHY_362_DATA = 0x00800080; + ddr_phy->DENALI_PHY_363_DATA = 0x00800080; + ddr_phy->DENALI_PHY_364_DATA = 0x00800080; + ddr_phy->DENALI_PHY_365_DATA = 0x00800080; + ddr_phy->DENALI_PHY_366_DATA = 0x10040001; + ddr_phy->DENALI_PHY_367_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_368_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_369_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_370_DATA = 0x01000000; + ddr_phy->DENALI_PHY_371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_372_DATA = 0x00010166; + ddr_phy->DENALI_PHY_373_DATA = 0x00000200; + ddr_phy->DENALI_PHY_374_DATA = 0x00000000; + ddr_phy->DENALI_PHY_375_DATA = 0x00000000; + ddr_phy->DENALI_PHY_376_DATA = 0x00800802; + ddr_phy->DENALI_PHY_377_DATA = 0x00081020; + ddr_phy->DENALI_PHY_378_DATA = 0x04010000; + ddr_phy->DENALI_PHY_379_DATA = 0x61314042; + ddr_phy->DENALI_PHY_380_DATA = 0x00314000; + ddr_phy->DENALI_PHY_381_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_382_DATA = 0x03000080; + ddr_phy->DENALI_PHY_383_DATA = 0x00000200; + ddr_phy->DENALI_PHY_384_DATA = 0x42100010; + ddr_phy->DENALI_PHY_385_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_386_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_387_DATA = 0x40420100; + ddr_phy->DENALI_PHY_388_DATA = 0x40518031; + ddr_phy->DENALI_PHY_389_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_390_DATA = 0x00000233; + ddr_phy->DENALI_PHY_391_DATA = 0x00000203; + ddr_phy->DENALI_PHY_392_DATA = 0x03000100; + ddr_phy->DENALI_PHY_393_DATA = 0x20202000; + ddr_phy->DENALI_PHY_394_DATA = 0x20202020; + ddr_phy->DENALI_PHY_395_DATA = 0x80202020; + ddr_phy->DENALI_PHY_396_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_397_DATA = 0x00000000; + ddr_phy->DENALI_PHY_398_DATA = 0x00000000; + ddr_phy->DENALI_PHY_512_DATA = 0x76543210; + ddr_phy->DENALI_PHY_513_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_514_DATA = 0x00000000; + ddr_phy->DENALI_PHY_515_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_516_DATA = 0x00000000; + ddr_phy->DENALI_PHY_517_DATA = 0x00000000; + ddr_phy->DENALI_PHY_518_DATA = 0x00010000; + ddr_phy->DENALI_PHY_519_DATA = 0x00019990; + ddr_phy->DENALI_PHY_520_DATA = 0x00019990; + ddr_phy->DENALI_PHY_521_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_522_DATA = 0x00010000; + ddr_phy->DENALI_PHY_523_DATA = 0x00000000; + ddr_phy->DENALI_PHY_524_DATA = 0x00000000; + ddr_phy->DENALI_PHY_525_DATA = 0x01000100; + ddr_phy->DENALI_PHY_526_DATA = 0x00000000; + ddr_phy->DENALI_PHY_527_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_528_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_529_DATA = 0x00000008; + ddr_phy->DENALI_PHY_530_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_531_DATA = 0x00005555; + ddr_phy->DENALI_PHY_532_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_533_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_534_DATA = 0x00005656; + ddr_phy->DENALI_PHY_535_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_536_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_537_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_539_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_540_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_541_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_542_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_543_DATA = 0x00000000; + ddr_phy->DENALI_PHY_544_DATA = 0x04080000; + ddr_phy->DENALI_PHY_545_DATA = 0x08040400; + ddr_phy->DENALI_PHY_546_DATA = 0x00000004; + ddr_phy->DENALI_PHY_547_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_549_DATA = 0x00000000; + ddr_phy->DENALI_PHY_550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_551_DATA = 0x00000000; + ddr_phy->DENALI_PHY_552_DATA = 0x00000000; + ddr_phy->DENALI_PHY_553_DATA = 0x00000000; + ddr_phy->DENALI_PHY_554_DATA = 0x00000000; + ddr_phy->DENALI_PHY_555_DATA = 0x00000000; + ddr_phy->DENALI_PHY_556_DATA = 0x00000000; + ddr_phy->DENALI_PHY_557_DATA = 0x00000000; + ddr_phy->DENALI_PHY_558_DATA = 0x00000000; + ddr_phy->DENALI_PHY_559_DATA = 0x00000000; + ddr_phy->DENALI_PHY_560_DATA = 0x00000000; + ddr_phy->DENALI_PHY_561_DATA = 0x00000000; + ddr_phy->DENALI_PHY_562_DATA = 0x00010000; + ddr_phy->DENALI_PHY_563_DATA = 0x00000000; + ddr_phy->DENALI_PHY_564_DATA = 0x00000000; + ddr_phy->DENALI_PHY_565_DATA = 0x00000000; + ddr_phy->DENALI_PHY_566_DATA = 0x00000000; + ddr_phy->DENALI_PHY_567_DATA = 0x20000004; + ddr_phy->DENALI_PHY_568_DATA = 0x00000000; + ddr_phy->DENALI_PHY_569_DATA = 0x00000000; + ddr_phy->DENALI_PHY_570_DATA = 0x00000000; + ddr_phy->DENALI_PHY_571_DATA = 0x00000000; + ddr_phy->DENALI_PHY_572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_585_DATA = 0x00000000; + ddr_phy->DENALI_PHY_586_DATA = 0x00000000; + ddr_phy->DENALI_PHY_587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_590_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_591_DATA = 0x00000000; + ddr_phy->DENALI_PHY_592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_593_DATA = 0x04000000; + ddr_phy->DENALI_PHY_594_DATA = 0x02800280; + ddr_phy->DENALI_PHY_595_DATA = 0x02800280; + ddr_phy->DENALI_PHY_596_DATA = 0x02800280; + ddr_phy->DENALI_PHY_597_DATA = 0x02800280; + ddr_phy->DENALI_PHY_598_DATA = 0x00000280; + ddr_phy->DENALI_PHY_599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_604_DATA = 0x00800080; + ddr_phy->DENALI_PHY_605_DATA = 0x00800080; + ddr_phy->DENALI_PHY_606_DATA = 0x00800080; + ddr_phy->DENALI_PHY_607_DATA = 0x00800080; + ddr_phy->DENALI_PHY_608_DATA = 0x00800080; + ddr_phy->DENALI_PHY_609_DATA = 0x00800080; + ddr_phy->DENALI_PHY_610_DATA = 0x00800080; + ddr_phy->DENALI_PHY_611_DATA = 0x00800080; + ddr_phy->DENALI_PHY_612_DATA = 0x00800080; + ddr_phy->DENALI_PHY_613_DATA = 0x00800080; + ddr_phy->DENALI_PHY_614_DATA = 0x00800080; + ddr_phy->DENALI_PHY_615_DATA = 0x00800080; + ddr_phy->DENALI_PHY_616_DATA = 0x00800080; + ddr_phy->DENALI_PHY_617_DATA = 0x00800080; + ddr_phy->DENALI_PHY_618_DATA = 0x00800080; + ddr_phy->DENALI_PHY_619_DATA = 0x00800080; + ddr_phy->DENALI_PHY_620_DATA = 0x00800080; + ddr_phy->DENALI_PHY_621_DATA = 0x00800080; + ddr_phy->DENALI_PHY_622_DATA = 0x10040001; + ddr_phy->DENALI_PHY_623_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_624_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_625_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_626_DATA = 0x01000000; + ddr_phy->DENALI_PHY_627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_628_DATA = 0x00010166; + ddr_phy->DENALI_PHY_629_DATA = 0x00000200; + ddr_phy->DENALI_PHY_630_DATA = 0x00000000; + ddr_phy->DENALI_PHY_631_DATA = 0x00000000; + ddr_phy->DENALI_PHY_632_DATA = 0x00800802; + ddr_phy->DENALI_PHY_633_DATA = 0x00081020; + ddr_phy->DENALI_PHY_634_DATA = 0x04010000; + ddr_phy->DENALI_PHY_635_DATA = 0x61314042; + ddr_phy->DENALI_PHY_636_DATA = 0x00314000; + ddr_phy->DENALI_PHY_637_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_638_DATA = 0x03000080; + ddr_phy->DENALI_PHY_639_DATA = 0x00000200; + ddr_phy->DENALI_PHY_640_DATA = 0x42100010; + ddr_phy->DENALI_PHY_641_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_642_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_643_DATA = 0x40420100; + ddr_phy->DENALI_PHY_644_DATA = 0x40518031; + ddr_phy->DENALI_PHY_645_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_646_DATA = 0x00000233; + ddr_phy->DENALI_PHY_647_DATA = 0x00000203; + ddr_phy->DENALI_PHY_648_DATA = 0x03000100; + ddr_phy->DENALI_PHY_649_DATA = 0x20202000; + ddr_phy->DENALI_PHY_650_DATA = 0x20202020; + ddr_phy->DENALI_PHY_651_DATA = 0x80202020; + ddr_phy->DENALI_PHY_652_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_653_DATA = 0x00000000; + ddr_phy->DENALI_PHY_654_DATA = 0x00000000; + ddr_phy->DENALI_PHY_768_DATA = 0x76543210; + ddr_phy->DENALI_PHY_769_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_770_DATA = 0x00000000; + ddr_phy->DENALI_PHY_771_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_772_DATA = 0x00000000; + ddr_phy->DENALI_PHY_773_DATA = 0x00000000; + ddr_phy->DENALI_PHY_774_DATA = 0x00010000; + ddr_phy->DENALI_PHY_775_DATA = 0x00019990; + ddr_phy->DENALI_PHY_776_DATA = 0x00019990; + ddr_phy->DENALI_PHY_777_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_778_DATA = 0x00010000; + ddr_phy->DENALI_PHY_779_DATA = 0x00000000; + ddr_phy->DENALI_PHY_780_DATA = 0x00000000; + ddr_phy->DENALI_PHY_781_DATA = 0x01000100; + ddr_phy->DENALI_PHY_782_DATA = 0x00000000; + ddr_phy->DENALI_PHY_783_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_784_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_785_DATA = 0x00000008; + ddr_phy->DENALI_PHY_786_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_787_DATA = 0x00005555; + ddr_phy->DENALI_PHY_788_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_789_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_790_DATA = 0x00005656; + ddr_phy->DENALI_PHY_791_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_792_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_793_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_795_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_796_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_797_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_798_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_799_DATA = 0x00000000; + ddr_phy->DENALI_PHY_800_DATA = 0x04080000; + ddr_phy->DENALI_PHY_801_DATA = 0x08040400; + ddr_phy->DENALI_PHY_802_DATA = 0x00000004; + ddr_phy->DENALI_PHY_803_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_805_DATA = 0x00000000; + ddr_phy->DENALI_PHY_806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_807_DATA = 0x00000000; + ddr_phy->DENALI_PHY_808_DATA = 0x00000000; + ddr_phy->DENALI_PHY_809_DATA = 0x00000000; + ddr_phy->DENALI_PHY_810_DATA = 0x00000000; + ddr_phy->DENALI_PHY_811_DATA = 0x00000000; + ddr_phy->DENALI_PHY_812_DATA = 0x00000000; + ddr_phy->DENALI_PHY_813_DATA = 0x00000000; + ddr_phy->DENALI_PHY_814_DATA = 0x00000000; + ddr_phy->DENALI_PHY_815_DATA = 0x00000000; + ddr_phy->DENALI_PHY_816_DATA = 0x00000000; + ddr_phy->DENALI_PHY_817_DATA = 0x00000000; + ddr_phy->DENALI_PHY_818_DATA = 0x00010000; + ddr_phy->DENALI_PHY_819_DATA = 0x00000000; + ddr_phy->DENALI_PHY_820_DATA = 0x00000000; + ddr_phy->DENALI_PHY_821_DATA = 0x00000000; + ddr_phy->DENALI_PHY_822_DATA = 0x00000000; + ddr_phy->DENALI_PHY_823_DATA = 0x20000004; + ddr_phy->DENALI_PHY_824_DATA = 0x00000000; + ddr_phy->DENALI_PHY_825_DATA = 0x00000000; + ddr_phy->DENALI_PHY_826_DATA = 0x00000000; + ddr_phy->DENALI_PHY_827_DATA = 0x00000000; + ddr_phy->DENALI_PHY_828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_841_DATA = 0x00000000; + ddr_phy->DENALI_PHY_842_DATA = 0x00000000; + ddr_phy->DENALI_PHY_843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_846_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_847_DATA = 0x00000000; + ddr_phy->DENALI_PHY_848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_849_DATA = 0x04000000; + ddr_phy->DENALI_PHY_850_DATA = 0x02800280; + ddr_phy->DENALI_PHY_851_DATA = 0x02800280; + ddr_phy->DENALI_PHY_852_DATA = 0x02800280; + ddr_phy->DENALI_PHY_853_DATA = 0x02800280; + ddr_phy->DENALI_PHY_854_DATA = 0x00000280; + ddr_phy->DENALI_PHY_855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_860_DATA = 0x00800080; + ddr_phy->DENALI_PHY_861_DATA = 0x00800080; + ddr_phy->DENALI_PHY_862_DATA = 0x00800080; + ddr_phy->DENALI_PHY_863_DATA = 0x00800080; + ddr_phy->DENALI_PHY_864_DATA = 0x00800080; + ddr_phy->DENALI_PHY_865_DATA = 0x00800080; + ddr_phy->DENALI_PHY_866_DATA = 0x00800080; + ddr_phy->DENALI_PHY_867_DATA = 0x00800080; + ddr_phy->DENALI_PHY_868_DATA = 0x00800080; + ddr_phy->DENALI_PHY_869_DATA = 0x00800080; + ddr_phy->DENALI_PHY_870_DATA = 0x00800080; + ddr_phy->DENALI_PHY_871_DATA = 0x00800080; + ddr_phy->DENALI_PHY_872_DATA = 0x00800080; + ddr_phy->DENALI_PHY_873_DATA = 0x00800080; + ddr_phy->DENALI_PHY_874_DATA = 0x00800080; + ddr_phy->DENALI_PHY_875_DATA = 0x00800080; + ddr_phy->DENALI_PHY_876_DATA = 0x00800080; + ddr_phy->DENALI_PHY_877_DATA = 0x00800080; + ddr_phy->DENALI_PHY_878_DATA = 0x10040001; + ddr_phy->DENALI_PHY_879_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_880_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_881_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_882_DATA = 0x01000000; + ddr_phy->DENALI_PHY_883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_884_DATA = 0x00010166; + ddr_phy->DENALI_PHY_885_DATA = 0x00000200; + ddr_phy->DENALI_PHY_886_DATA = 0x00000000; + ddr_phy->DENALI_PHY_887_DATA = 0x00000000; + ddr_phy->DENALI_PHY_888_DATA = 0x00800802; + ddr_phy->DENALI_PHY_889_DATA = 0x00081020; + ddr_phy->DENALI_PHY_890_DATA = 0x04010000; + ddr_phy->DENALI_PHY_891_DATA = 0x61314042; + ddr_phy->DENALI_PHY_892_DATA = 0x00314000; + ddr_phy->DENALI_PHY_893_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_894_DATA = 0x03000080; + ddr_phy->DENALI_PHY_895_DATA = 0x00000200; + ddr_phy->DENALI_PHY_896_DATA = 0x42100010; + ddr_phy->DENALI_PHY_897_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_898_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_899_DATA = 0x40420100; + ddr_phy->DENALI_PHY_900_DATA = 0x40518031; + ddr_phy->DENALI_PHY_901_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_902_DATA = 0x00000233; + ddr_phy->DENALI_PHY_903_DATA = 0x00000203; + ddr_phy->DENALI_PHY_904_DATA = 0x03000100; + ddr_phy->DENALI_PHY_905_DATA = 0x20202000; + ddr_phy->DENALI_PHY_906_DATA = 0x20202020; + ddr_phy->DENALI_PHY_907_DATA = 0x80202020; + ddr_phy->DENALI_PHY_908_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_909_DATA = 0x00000000; + ddr_phy->DENALI_PHY_910_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1024_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1025_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1026_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1027_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1028_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1029_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1030_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1031_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1032_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1033_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1034_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1035_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1036_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1037_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1038_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1039_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1040_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1041_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1042_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1043_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1044_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1045_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1046_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1047_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1048_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1049_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1051_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1052_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1053_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1054_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1055_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1056_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1057_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1058_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1059_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1061_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1063_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1064_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1065_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1066_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1067_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1068_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1069_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1070_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1071_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1072_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1073_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1074_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1075_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1076_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1077_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1078_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1079_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1080_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1081_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1082_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1083_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1097_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1098_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1102_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1103_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1105_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1106_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1107_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1108_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1109_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1110_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1116_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1117_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1118_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1119_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1120_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1121_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1122_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1123_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1124_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1125_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1126_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1127_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1128_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1129_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1130_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1131_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1132_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1133_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1134_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1135_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1136_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1137_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[4] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1138_DATA = 0x01000000; + ddr_phy->DENALI_PHY_1139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1140_DATA = 0x00010166; + ddr_phy->DENALI_PHY_1141_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1142_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1143_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1144_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1145_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1146_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1147_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1148_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1149_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1150_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1151_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1152_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1153_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1154_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1155_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1156_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1157_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1158_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1159_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1160_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1161_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1162_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1163_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1164_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1165_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1166_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1280_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1281_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1283_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1284_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1285_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1286_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1287_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1288_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1289_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1290_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1291_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1293_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1295_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1296_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1297_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1298_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1299_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1300_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1301_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1302_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1303_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1304_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1305_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1307_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1308_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1309_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1310_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1312_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1313_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1314_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1315_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1329_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1330_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1334_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1335_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1337_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1338_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1339_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1340_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1341_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1342_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1348_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1349_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1350_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1351_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1352_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1353_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1354_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1355_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1356_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1357_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1358_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1359_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1360_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1361_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1362_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1363_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1364_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1365_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1366_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1367_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1368_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1369_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1370_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1372_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1373_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1374_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1375_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1376_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1377_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1378_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1379_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1380_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1381_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1382_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1383_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1384_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1385_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1386_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1387_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1388_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1389_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1390_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1391_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1392_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1393_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1394_DATA = 0x01000000; + ddr_phy->DENALI_PHY_1395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1396_DATA = 0x00010166; + ddr_phy->DENALI_PHY_1397_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1398_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1399_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1400_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1401_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1402_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1403_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1404_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1405_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1406_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1407_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1408_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1409_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1410_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1411_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1412_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1413_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1414_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1415_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1416_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1417_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1418_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1419_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1420_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1536_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1537_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1539_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1540_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1541_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1542_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1543_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1544_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1545_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1546_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1547_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1549_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1551_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1552_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1553_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1554_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1555_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1556_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1557_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1558_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1559_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1560_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1561_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1562_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1563_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1564_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1565_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1566_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1567_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1568_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1569_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1570_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1571_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1585_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1586_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1590_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1591_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1593_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1594_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1595_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1596_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1597_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1598_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1604_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1605_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1606_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1607_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1608_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1609_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1610_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1611_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1612_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1613_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1614_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1615_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1616_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1617_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1618_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1619_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1620_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1621_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1622_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1623_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1624_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1625_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1626_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1628_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1629_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1630_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1631_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1632_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1633_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1634_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1635_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1636_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1637_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1638_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1639_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1640_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1641_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1642_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1643_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1644_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1645_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1646_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1647_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1648_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1649_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1650_DATA = 0x01000000; + ddr_phy->DENALI_PHY_1651_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1652_DATA = 0x00010166; + ddr_phy->DENALI_PHY_1653_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1654_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1655_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1656_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1657_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1658_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1659_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1660_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1661_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1662_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1663_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1664_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1665_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1666_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1667_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1668_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1669_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1670_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1671_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1672_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1673_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1674_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1675_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1676_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1677_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1678_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1792_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1793_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1795_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1796_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1797_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1798_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1799_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1800_DATA = 0x00019990; + ddr_phy->DENALI_PHY_1801_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1802_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1803_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1805_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1807_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1808_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1809_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1810_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1811_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1812_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1813_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1814_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1815_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1816_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1817_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1818_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1819_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1820_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1821_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1822_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1823_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1824_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1825_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1826_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1827_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1841_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1842_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1846_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1847_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1849_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1850_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1851_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1852_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1853_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1854_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1860_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1861_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1862_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1863_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1864_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1865_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1866_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1867_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1868_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1869_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1870_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1871_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1872_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1873_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1874_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1875_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1876_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1877_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1878_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1879_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1880_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1881_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1882_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1884_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1885_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1886_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1887_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1888_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1889_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1890_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1891_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1892_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1893_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1894_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1895_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1896_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1897_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1898_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1899_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1900_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1901_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1902_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1903_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1904_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1905_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1906_DATA = 0x01000000; + ddr_phy->DENALI_PHY_1907_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1908_DATA = 0x00010166; + ddr_phy->DENALI_PHY_1909_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1910_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1911_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1912_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1913_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1914_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1915_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1916_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1917_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1918_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1919_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1920_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1921_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1922_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1923_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1924_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1925_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1926_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1927_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1928_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1929_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1930_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1931_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1932_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1933_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1934_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2048_DATA = 0x76543210; + ddr_phy->DENALI_PHY_2049_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_2050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2051_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_2052_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2053_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2054_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2055_DATA = 0x00019990; + ddr_phy->DENALI_PHY_2056_DATA = 0x00019990; + ddr_phy->DENALI_PHY_2057_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_2058_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2059_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2061_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2063_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_2064_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_2065_DATA = 0x00000008; + ddr_phy->DENALI_PHY_2066_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_2067_DATA = 0x00005555; + ddr_phy->DENALI_PHY_2068_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2069_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_2070_DATA = 0x00005656; + ddr_phy->DENALI_PHY_2071_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2072_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2073_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2074_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2075_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_2076_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_2077_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_2078_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_2079_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2080_DATA = 0x04080000; + ddr_phy->DENALI_PHY_2081_DATA = 0x08040400; + ddr_phy->DENALI_PHY_2082_DATA = 0x00000004; + ddr_phy->DENALI_PHY_2083_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_2084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2097_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2098_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2102_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2103_DATA = 0x20000004; + ddr_phy->DENALI_PHY_2104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2105_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2106_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2107_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2108_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2109_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2110_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2116_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2117_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2118_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2120_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2121_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2122_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2123_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2124_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2125_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2126_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_2127_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2128_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2129_DATA = 0x04000000; + ddr_phy->DENALI_PHY_2130_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2131_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2132_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2133_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2134_DATA = 0x00000280; + ddr_phy->DENALI_PHY_2135_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2136_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2137_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2138_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2140_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2141_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2142_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2143_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2144_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2145_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2146_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2147_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2148_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2149_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2150_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2151_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2152_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2153_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2154_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2155_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2156_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2157_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2158_DATA = 0x10040001; + ddr_phy->DENALI_PHY_2159_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_2160_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2161_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2162_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2163_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2164_DATA = 0x00010166; + ddr_phy->DENALI_PHY_2165_DATA = 0x00000200; + ddr_phy->DENALI_PHY_2166_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2167_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2168_DATA = 0x00800802; + ddr_phy->DENALI_PHY_2169_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2170_DATA = 0x04010000; + ddr_phy->DENALI_PHY_2171_DATA = 0x61314042; + ddr_phy->DENALI_PHY_2172_DATA = 0x00314000; + ddr_phy->DENALI_PHY_2173_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_2174_DATA = 0x03000080; + ddr_phy->DENALI_PHY_2175_DATA = 0x00000200; + ddr_phy->DENALI_PHY_2176_DATA = 0x42100010; + ddr_phy->DENALI_PHY_2177_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_2178_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_2179_DATA = 0x40420100; + ddr_phy->DENALI_PHY_2180_DATA = 0x40518031; + ddr_phy->DENALI_PHY_2181_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_2182_DATA = 0x00000233; + ddr_phy->DENALI_PHY_2183_DATA = 0x00000203; + ddr_phy->DENALI_PHY_2184_DATA = 0x03000100; + ddr_phy->DENALI_PHY_2185_DATA = 0x20202000; + ddr_phy->DENALI_PHY_2186_DATA = 0x20202020; + ddr_phy->DENALI_PHY_2187_DATA = 0x80202020; + ddr_phy->DENALI_PHY_2188_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_2189_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2190_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2305_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2309_DATA = 0x00050000; + ddr_phy->DENALI_PHY_2310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2313_DATA = 0x02010000; + ddr_phy->DENALI_PHY_2314_DATA = 0x00008008; + ddr_phy->DENALI_PHY_2315_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2320_DATA = 0x00010100; + ddr_phy->DENALI_PHY_2321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2327_DATA = 0x64000000; + ddr_phy->DENALI_PHY_2328_DATA = 0x00000050; + ddr_phy->DENALI_PHY_2329_DATA = 0x014A114A; + ddr_phy->DENALI_PHY_2330_DATA = 0x0000014A; + ddr_phy->DENALI_PHY_2331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2332_DATA = 0x00163F00; + ddr_phy->DENALI_PHY_2333_DATA = 0x42080010; + ddr_phy->DENALI_PHY_2334_DATA = 0x0100003E; + ddr_phy->DENALI_PHY_2335_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2336_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2337_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2338_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2339_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2340_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2341_DATA = 0x80002020; + ddr_phy->DENALI_PHY_2342_DATA = 0x00124924; + ddr_phy->DENALI_PHY_2343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2347_DATA = 0x070A0707; + ddr_phy->DENALI_PHY_2348_DATA = 0x00005400; + ddr_phy->DENALI_PHY_2349_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2350_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2351_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2352_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2353_DATA = 0x2000073F; + ddr_phy->DENALI_PHY_2354_DATA = 0x0000073F; + ddr_phy->DENALI_PHY_2355_DATA = 0x0006BF00; + ddr_phy->DENALI_PHY_2356_DATA = 0x013200E0; + ddr_phy->DENALI_PHY_2357_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2358_DATA = 0x00007000; + ddr_phy->DENALI_PHY_2359_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2360_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2361_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2362_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2363_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2364_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2365_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2366_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2367_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2368_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2369_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2370_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2371_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2372_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2373_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2374_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2375_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2376_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2377_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2378_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2379_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2380_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2381_DATA = 0x04102089; + ddr_phy->DENALI_PHY_2382_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2383_DATA = 0x00020011; + ddr_phy->DENALI_PHY_2384_DATA = 0x00021000; + ddr_phy->DENALI_PHY_2385_DATA = 0x00000448; + ddr_phy->DENALI_PHY_2386_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2387_DATA = 0x04000408; + ddr_phy->DENALI_PHY_2388_DATA = 0x00000020; + ddr_phy->DENALI_PHY_2389_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2390_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2391_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2392_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2393_DATA = 0x03000000; + ddr_phy->DENALI_PHY_2394_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2396_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2397_DATA = 0x04102035; + ddr_phy->DENALI_PHY_2398_DATA = 0x00041020; + ddr_phy->DENALI_PHY_2399_DATA = 0x01C98C98; + ddr_phy->DENALI_PHY_2400_DATA = 0x3F400000; + ddr_phy->DENALI_PHY_2401_DATA = 0x3F3F1F3F; + ddr_phy->DENALI_PHY_2402_DATA = 0x1F3F3F1F; + ddr_phy->DENALI_PHY_2403_DATA = 0x001F3F3F; + ddr_phy->DENALI_PHY_2404_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2405_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2406_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2407_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2408_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2409_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2410_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2411_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2412_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2413_DATA = 0x00040700; + ddr_phy->DENALI_PHY_2414_DATA = 0x00070000; + ddr_phy->DENALI_PHY_2415_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2416_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2417_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2418_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2419_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2420_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2423_DATA = 0x00000002; + ddr_phy->DENALI_PHY_2424_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2425_DATA = 0x0000000F; + + return FWK_SUCCESS; +} + +static int n1sdp_ddr_phy_post_training_configure(fwk_id_t element_id) +{ + int status; + const struct mod_n1sdp_ddr_phy_element_config *element_config; + uint32_t i; + uint32_t j; + uint32_t phy_base; + uint32_t offset; + + status = fwk_module_check_call(element_id); + if (status != FWK_SUCCESS) + return status; + + element_config = fwk_module_get_data(element_id); + phy_base = (uint32_t)element_config->ddr; + + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR-PHY] Post training PHY setting at 0x%x\n", phy_base); + + for (i = 4; i < 9; i++) { + for (j = 92; j <= 109; j++) { + offset = 4 * (j + (i * 256)); + *(uint32_t *)(phy_base + offset) = 0x00960096; + } + } + + for (i = 4; i < 6; i++) { + offset = 4 * (113 + (i * 256)); + *(uint32_t *)(phy_base + offset) = 0x00400200; + } + + return FWK_SUCCESS; +} + +static int n1sdp_verify_phy_status(fwk_id_t element_id, uint8_t training_type) +{ + int status; + const struct mod_n1sdp_ddr_phy_element_config *element_config; + uint32_t i; + uint32_t j; + uint32_t phy_base; + uint32_t value1; + uint32_t value2; + uint32_t num_slices; + + status = fwk_module_check_call(element_id); + if (status != FWK_SUCCESS) + return status; + + element_config = fwk_module_get_data(element_id); + phy_base = (uint32_t)element_config->ddr; + num_slices = 18; + + switch (training_type) { + case DDR_ADDR_TRAIN_TYPE_WR_LVL: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (41 + (i * 256)))); + value2 = *(uint32_t *)(phy_base + (4 * (42 + (i * 256)))); + if (((value1 >> 16) >= 0x0200) || + ((value2 & 0x0000FFFF) >= 0x200)) { + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR-PHY] PHY 0x%08x : Invalid Hard0/Hard 1 value found " + "for slice %d\n", phy_base, i); + } + } + break; + case DDR_ADDR_TRAIN_TYPE_RD_GATE: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (46 + (i * 256)))); + if (value1 != 0x003C) { + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR-PHY] PHY 0x%08x : Final read gate training " + "status != 0x003C for slice %d\n", phy_base, i); + } + } + break; + case DDR_ADDR_TRAIN_TYPE_RD_EYE: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + for (j = 0; j < num_slices; j++) { + value1 = *(uint32_t *)(phy_base + (4 * (34 + (i * 256)))); + if (j <= 16) + value1 = (value1 & 0xFF00FFFF) | (j << 16); + else + value1 = (value1 & 0xFF00FFFF) | (0x18 << 16); + + value1 = *(uint32_t *)(phy_base + (4 * (47 + (i * 256)))); + if ((value1 & 0x0000FFFF) > 0x0180) { + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR-PHY] PHY 0x%08x : slice %d " + " phy_rdlvl_rddqs_dq_le_dly_obs_%d is > 0x180\n", + phy_base, j, i); + } + if ((value1 >> 16) > 0x0180) { + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR-PHY] PHY 0x%08x : slice %d " + "phy_rdlvl_rddqs_dq_te_dly_obs_%d is > 0x180\n", + phy_base, j, i); + } + value1 = *(uint32_t *)(phy_base + (4 * (49 + (i * 256)))); + if ((value1 >> 16) != 0x0C00) { + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR-PHY] PHY 0x%08x : Final read data eye training " + "status != 0x0C00 for slice %d\n", phy_base, i); + } + } + } + break; + case DDR_ADDR_TRAIN_TYPE_VREF: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + } + break; + default: + return FWK_E_STATE; + break; + } + return FWK_SUCCESS; +} + +static struct mod_dmc_ddr_phy_api n1sdp_ddr_phy_api = { + .configure = n1sdp_ddr_phy_config, + .post_training_configure = n1sdp_ddr_phy_post_training_configure, + .verify_phy_status = n1sdp_verify_phy_status, +}; + +/* + * Functions fulfilling the framework's module interface + */ + +static int n1sdp_ddr_phy_init(fwk_id_t module_id, unsigned int element_count, + const void *config) +{ + return FWK_SUCCESS; +} + +static int n1sdp_ddr_phy_element_init(fwk_id_t element_id, unsigned int unused, + const void *data) +{ + fwk_assert(data != NULL); + + return FWK_SUCCESS; +} + +static int n1sdp_ddr_phy_bind(fwk_id_t id, unsigned int round) +{ + int status; + + /* Skip the second round (rounds are zero-indexed) */ + if (round == 1) + return FWK_SUCCESS; + + /* Nothing to be done for element-level binding */ + if (fwk_module_is_valid_element_id(id)) + return FWK_SUCCESS; + + /* Bind to the log module and get a pointer to its API */ + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG), MOD_LOG_API_ID, + &log_api); + if (status != FWK_SUCCESS) + return FWK_E_HANDLER; + + return FWK_SUCCESS; +} + +static int n1sdp_ddr_phy_process_bind_request(fwk_id_t requester_id, + fwk_id_t id, fwk_id_t api_type, const void **api) +{ + /* Binding to elements is not permitted. */ + if (fwk_module_is_valid_element_id(id)) + return FWK_E_ACCESS; + + *api = &n1sdp_ddr_phy_api; + + return FWK_SUCCESS; +} + +const struct fwk_module module_n1sdp_ddr_phy = { + .name = "N1SDP DDR-PHY", + .type = FWK_MODULE_TYPE_DRIVER, + .init = n1sdp_ddr_phy_init, + .element_init = n1sdp_ddr_phy_element_init, + .bind = n1sdp_ddr_phy_bind, + .process_bind_request = n1sdp_ddr_phy_process_bind_request, + .api_count = 1, +}; diff --git a/product/n1sdp/module/n1sdp_dmc620/include/mod_n1sdp_dmc620.h b/product/n1sdp/module/n1sdp_dmc620/include/mod_n1sdp_dmc620.h new file mode 100644 index 0000000000000000000000000000000000000000..7320cf762128952c346cabcec49e92bbc638dd3d --- /dev/null +++ b/product/n1sdp/module/n1sdp_dmc620/include/mod_n1sdp_dmc620.h @@ -0,0 +1,754 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * N1SDP DMC-620 module. + */ + +#ifndef MOD_N1SDP_DMC620_H +#define MOD_N1SDP_DMC620_H + +#include +#include +#include + +/*! + * \addtogroup GroupN1SDPModule N1SDP Product Modules + * @{ + */ + +/*! + * \defgroup GroupModuleN1SDPDMC-620 N1SDP DMC-620 Driver + * + * \details Please consult the Arm CoreLink DMC-620 Dynamic Memory Controller + * Technical Reference Manual for details on the specific registers that + * are programmed here. + * + * @{ + */ + +/*! + * \brief Number of access addresses + */ +#define MOD_DMC620_ACCESS_ADDRESS_COUNT 8 + +/*! + * \brief Access address next registers + */ +struct mod_dmc620_access_address_next { + /*! + * \cond + * @{ + */ + FWK_RW uint32_t MIN_31_00; + FWK_RW uint32_t MIN_43_32; + FWK_RW uint32_t MAX_31_00; + FWK_RW uint32_t MAX_43_32; + /*! + * \endcond + * @} + */ +}; + +/*! + * \brief Access address next registers + */ +struct mod_dmc620_access_address_now { + /*! + * \cond + * @{ + */ + FWK_R uint32_t MIN_31_00; + FWK_R uint32_t MIN_43_32; + FWK_R uint32_t MAX_31_00; + FWK_R uint32_t MAX_43_32; + /*! + * \endcond + * @} + */ +}; + +/*! + * \brief PMU payload information operation register + */ +struct mod_dmc620_pmu_counter { + /*! + * \cond + * @{ + */ + FWK_RW uint32_t MASK_31_00; + FWK_RW uint32_t MASK_63_32; + FWK_RW uint32_t MATCH_31_00; + FWK_RW uint32_t MATCH_63_32; + FWK_RW uint32_t CONTROL; + uint32_t RESERVED0; + FWK_R uint32_t SNAPSHOT_VALUE_31_00; + uint32_t RESERVED1; + FWK_RW uint32_t VALUE_31_00; + uint32_t RESERVED2; + /*! + * \endcond + * @} + */ +}; + +/*! + * \brief DMC-620 register definitions + */ +struct mod_dmc620_reg { + /*! + * \cond + * @{ + */ + FWK_R uint32_t MEMC_STATUS; + FWK_R uint32_t MEMC_CONFIG; + FWK_W uint32_t MEMC_CMD; + uint32_t RESERVED1; + FWK_RW uint32_t ADDRESS_CONTROL_NEXT; + FWK_RW uint32_t DECODE_CONTROL_NEXT; + FWK_RW uint32_t FORMAT_CONTROL; + FWK_RW uint32_t ADDRESS_MAP_NEXT; + FWK_RW uint32_t LOW_POWER_CONTROL_NEXT; + uint32_t RESERVED2; + FWK_RW uint32_t TURNAROUND_CONTROL_NEXT; + FWK_RW uint32_t HIT_TURNAROUND_CONTROL_NEXT; + FWK_RW uint32_t QOS_CLASS_CONTROL_NEXT; + FWK_RW uint32_t ESCALATION_CONTROL_NEXT; + FWK_RW uint32_t QV_CONTROL_31_00_NEXT; + FWK_RW uint32_t QV_CONTROL_63_32_NEXT; + FWK_RW uint32_t RT_CONTROL_31_00_NEXT; + FWK_RW uint32_t RT_CONTROL_63_32_NEXT; + FWK_RW uint32_t TIMEOUT_CONTROL_NEXT; + FWK_RW uint32_t CREDIT_CONTROL_NEXT; + FWK_RW uint32_t WRITE_PRIORITY_CONTROL_31_00_NEXT; + FWK_RW uint32_t WRITE_PRIORITY_CONTROL_63_32_NEXT; + FWK_RW uint32_t QUEUE_THRESHOLD_CONTROL_31_00_NEXT; + FWK_RW uint32_t QUEUE_THRESHOLD_CONTROL_63_32_NEXT; + FWK_RW uint32_t ADDRESS_SHUTTER_31_00_NEXT; + FWK_RW uint32_t ADDRESS_SHUTTER_63_32_NEXT; + FWK_RW uint32_t ADDRESS_SHUTTER_95_64_NEXT; + FWK_RW uint32_t ADDRESS_SHUTTER_127_96_NEXT; + FWK_RW uint32_t ADDRESS_SHUTTER_159_128_NEXT; + FWK_RW uint32_t ADDRESS_SHUTTER_191_160_NEXT; + FWK_RW uint32_t MEMORY_ADDRESS_MAX_31_00_NEXT; + FWK_RW uint32_t MEMORY_ADDRESS_MAX_43_32_NEXT; + struct mod_dmc620_access_address_next ACCESS_ADDRESS_NEXT + [MOD_DMC620_ACCESS_ADDRESS_COUNT]; + FWK_R uint32_t CHANNEL_STATUS; + FWK_R uint32_t CHANNEL_STATUS_63_32; + FWK_RW uint32_t DIRECT_ADDR; + FWK_W uint32_t DIRECT_CMD; + FWK_RW uint32_t DCI_REPLAY_TYPE_NEXT; + FWK_RW uint32_t DIRECT_CONTROL_NEXT; + FWK_RW uint32_t DCI_STRB; + FWK_RW uint32_t DCI_DATA; + FWK_RW uint32_t REFRESH_CONTROL_NEXT; + uint32_t RESERVED3; + FWK_RW uint32_t MEMORY_TYPE_NEXT; + uint32_t RESERVED4; + FWK_RW uint32_t FEATURE_CONFIG; + uint32_t RESERVED5; + FWK_RW uint32_t NIBBLE_FAILED_031_000; + FWK_RW uint32_t NIBBLE_FAILED_063_032; + FWK_RW uint32_t NIBBLE_FAILED_095_064; + FWK_RW uint32_t NIBBLE_FAILED_127_096; + FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_031_000; + FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_063_032; + FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_095_064; + FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_127_096; + uint8_t RESERVED6[0x16C - 0x158]; + FWK_RW uint32_t LINK_ERR_COUNT; + FWK_RW uint32_t SCRUB_CONTROL0_NEXT; + FWK_RW uint32_t SCRUB_ADDRESS_MIN0_NEXT; + FWK_RW uint32_t SCRUB_ADDRESS_MAX0_NEXT; + FWK_R uint32_t SCRUB_ADDRESS_CURRENT0; + FWK_RW uint32_t SCRUB_CONTROL1_NEXT; + FWK_RW uint32_t SCRUB_ADDRESS_MIN1_NEXT; + FWK_RW uint32_t SCRUB_ADDRESS_MAX1_NEXT; + FWK_R uint32_t SCRUB_ADDRESS_CURRENT1; + uint8_t RESERVED7[0x1A0 - 0x190]; + FWK_RW uint32_t CS_REMAP_CONTROL_31_00_NEXT; + FWK_RW uint32_t CS_REMAP_CONTROL_63_32_NEXT; + FWK_RW uint32_t CS_REMAP_CONTROL_95_64_NEXT; + FWK_RW uint32_t CS_REMAP_CONTROL_127_96_NEXT; + FWK_RW uint32_t CID_REMAP_CONTROL_31_00_NEXT; + FWK_RW uint32_t CID_REMAP_CONTROL_63_32_NEXT; + uint8_t RESERVED8[0x1C0 - 0x1B8]; + FWK_RW uint32_t CKE_REMAP_CONTROL_NEXT; + FWK_RW uint32_t RST_REMAP_CONTROL_NEXT; + FWK_RW uint32_t CK_REMAP_CONTROL_NEXT; + uint32_t RESERVED9; + FWK_RW uint32_t POWER_GROUP_CONTROL_31_00_NEXT; + FWK_RW uint32_t POWER_GROUP_CONTROL_63_32_NEXT; + FWK_RW uint32_t POWER_GROUP_CONTROL_95_64_NEXT; + FWK_RW uint32_t POWER_GROUP_CONTROL_127_96_NEXT; + FWK_RW uint32_t PHY_RDWRDATA_CS_MASK_31_00; + FWK_RW uint32_t PHY_RDWRDATA_CS_MASK_63_32; + FWK_RW uint32_t PHY_REQUEST_CS_REMAP; + uint32_t RESERVED10; + FWK_RW uint32_t FEATURE_CONTROL_NEXT; + FWK_RW uint32_t MUX_CONTROL_NEXT; + FWK_RW uint32_t RANK_REMAP_CONTROL_NEXT; + uint32_t RESERVED11; + FWK_RW uint32_t T_REFI_NEXT; + FWK_RW uint32_t T_RFC_NEXT; + FWK_RW uint32_t T_MRR_NEXT; + FWK_RW uint32_t T_MRW_NEXT; + FWK_RW uint32_t REFRESH_ENABLE_NEXT; + uint32_t RESERVED12; + FWK_RW uint32_t T_RCD_NEXT; + FWK_RW uint32_t T_RAS_NEXT; + FWK_RW uint32_t T_RP_NEXT; + FWK_RW uint32_t T_RPALL_NEXT; + FWK_RW uint32_t T_RRD_NEXT; + FWK_RW uint32_t T_ACT_WINDOW_NEXT; + uint32_t RESERVED13; + FWK_RW uint32_t T_RTR_NEXT; + FWK_RW uint32_t T_RTW_NEXT; + FWK_RW uint32_t T_RTP_NEXT; + uint32_t RESERVED14; + FWK_RW uint32_t T_WR_NEXT; + FWK_RW uint32_t T_WTR_NEXT; + FWK_RW uint32_t T_WTW_NEXT; + uint32_t RESERVED15; + FWK_RW uint32_t T_XMPD_NEXT; + FWK_RW uint32_t T_EP_NEXT; + FWK_RW uint32_t T_XP_NEXT; + FWK_RW uint32_t T_ESR_NEXT; + FWK_RW uint32_t T_XSR_NEXT; + FWK_RW uint32_t T_ESRCK_NEXT; + FWK_RW uint32_t T_CKXSR_NEXT; + FWK_RW uint32_t T_CMD_NEXT; + FWK_RW uint32_t T_PARITY_NEXT; + FWK_RW uint32_t T_ZQCS_NEXT; + FWK_RW uint32_t T_RW_ODT_CLR_NEXT; + uint8_t RESERVED16[0x300 - 0x280]; + FWK_RW uint32_t T_RDDATA_EN_NEXT; + FWK_RW uint32_t T_PHYRDLAT_NEXT; + FWK_RW uint32_t T_PHYWRLAT_NEXT; + uint32_t RESERVED17; + FWK_RW uint32_t RDLVL_CONTROL_NEXT; + FWK_RW uint32_t RDLVL_MRS_NEXT; + FWK_RW uint32_t T_RDLVL_EN_NEXT; + FWK_RW uint32_t T_RDLVL_RR_NEXT; + FWK_RW uint32_t WRLVL_CONTROL_NEXT; + FWK_RW uint32_t WRLVL_MRS_NEXT; + FWK_RW uint32_t T_WRLVL_EN_NEXT; + FWK_RW uint32_t T_WRLVL_WW_NEXT; + uint32_t RESERVED18; + FWK_R uint32_t TRAINING_WRLVL_SLICE_STATUS; + FWK_R uint32_t TRAINING_RDLVL_SLICE_STATUS; + FWK_R uint32_t TRAINING_RDLVL_GATE_SLICE_STATUS; + FWK_R uint32_t TRAINING_WDQLVL_SLICE_STATUS; + FWK_R uint32_t TRAINING_WDQLVL_SLICE_RESULT; + FWK_RW uint32_t PHY_POWER_CONTROL_NEXT; + FWK_RW uint32_t T_LPRESP_NEXT; + FWK_RW uint32_t PHY_UPDATE_CONTROL_NEXT; + FWK_RW uint32_t T_ODTH_NEXT; + FWK_RW uint32_t ODT_TIMING_NEXT; + uint32_t RESERVED19; + FWK_RW uint32_t ODT_WR_CONTROL_31_00_NEXT; + FWK_RW uint32_t ODT_WR_CONTROL_63_32_NEXT; + FWK_RW uint32_t ODT_RD_CONTROL_31_00_NEXT; + FWK_RW uint32_t ODT_RD_CONTROL_63_32_NEXT; + FWK_R uint32_t TEMPERATURE_READOUT; + uint32_t RESERVED20; + FWK_R uint32_t TRAINING_STATUS; + FWK_R uint32_t TRAINING_STATUS_63_32; + FWK_RW uint32_t DQ_MAP_CONTROL_15_00_NEXT; + FWK_RW uint32_t DQ_MAP_CONTROL_31_16_NEXT; + FWK_RW uint32_t DQ_MAP_CONTROL_47_32_NEXT; + FWK_RW uint32_t DQ_MAP_CONTROL_63_48_NEXT; + FWK_RW uint32_t DQ_MAP_CONTROL_71_64_NEXT; + uint32_t RESERVED21; + FWK_R uint32_t RANK_STATUS; + FWK_R uint32_t MODE_CHANGE_STATUS; + uint8_t RESERVED22[0x3B0 - 0x3A0]; + FWK_RW uint32_t ODT_CP_CONTROL_31_00_NEXT; + FWK_RW uint32_t ODT_CP_CONTROL_63_32_NEXT; + uint8_t RESERVED23[0x400 - 0x3B8]; + FWK_R uint32_t USER_STATUS; + uint32_t RESERVED24; + FWK_RW uint32_t USER_CONFIG0_NEXT; + FWK_RW uint32_t USER_CONFIG1_NEXT; + FWK_RW uint32_t USER_CONFIG2; + FWK_RW uint32_t USER_CONFIG3; + uint8_t RESERVED25[0x500 - 0x418]; + FWK_RW uint32_t INTERRUPT_CONTROL; + uint32_t RESERVED26; + FWK_W uint32_t INTERRUPT_CLR; + uint32_t RESERVED27; + FWK_R uint32_t INTERRUPT_STATUS; + uint8_t RESERVED28[0x538 - 0x514]; + FWK_R uint32_t FAILED_ACCESS_INT_INFO_31_00; + FWK_R uint32_t FAILED_ACCESS_INT_INFO_63_32; + FWK_R uint32_t FAILED_PROG_INT_INFO_31_00; + FWK_R uint32_t FAILED_PROG_INT_INFO_63_32; + FWK_R uint32_t LINK_ERR_INT_INFO_31_00; + FWK_R uint32_t LINK_ERR_INT_INFO_63_32; + FWK_R uint32_t ARCH_FSM_INT_INFO_31_00; + FWK_R uint32_t ARCH_FSM_INT_INFO_63_32; + uint8_t RESERVED29[0x610 - 0x558]; + FWK_RW uint32_t T_DB_TRAIN_RESP_NEXT; + FWK_RW uint32_t T_LVL_DISCONNECT_NEXT; + uint8_t RESERVED30[0x620 - 0x618]; + FWK_RW uint32_t WDQLVL_CONTROL_NEXT; + FWK_RW uint32_t WDQLVL_VREFDQ_TRAIN_MRS_NEXT; + FWK_RW uint32_t WDQLVL_ADDRESS_31_00_NEXT; + FWK_RW uint32_t WDQLVL_ADDRESS_63_32_NEXT; + FWK_RW uint32_t T_WDQLVL_EN_NEXT; + FWK_RW uint32_t T_WDQLVL_WW_NEXT; + FWK_RW uint32_t T_WDQLVL_RW_NEXT; + FWK_R uint32_t TRAINING_WDQLVL_SLICE_RESP; + FWK_R uint32_t TRAINING_RDLVL_SLICE_RESP; + uint8_t RESERVED31[0x654 - 0x644]; + FWK_RW uint32_t PHYMSTR_CONTROL_NEXT; + uint8_t RESERVED32[0x700 - 0x658]; + FWK_R uint32_t ERR0FR; + uint32_t RESERVED33; + FWK_RW uint32_t ERR0CTLR0; + FWK_RW uint32_t ERR0CTLR1; + FWK_R uint32_t ERR0STATUS; + uint8_t RESERVED34[0x740 - 0x714]; + FWK_R uint32_t ERR1FR; + uint32_t RESERVED35; + FWK_R uint32_t ERR1CTLR; + uint32_t RESERVED36; + FWK_R uint32_t ERR1STATUS; + uint32_t RESERVED37; + FWK_RW uint32_t ERR1ADDR0; + FWK_RW uint32_t ERR1ADDR1; + FWK_RW uint32_t ERR1MISC0; + FWK_RW uint32_t ERR1MISC1; + FWK_RW uint32_t ERR1MISC2; + FWK_RW uint32_t ERR1MISC3; + FWK_RW uint32_t ERR1MISC4; + FWK_RW uint32_t ERR1MISC5; + uint8_t RESERVED38[0x780 - 0x778]; + FWK_R uint32_t ERR2FR; + uint32_t RESERVED39; + FWK_R uint32_t ERR2CTLR; + uint32_t RESERVED40; + FWK_R uint32_t ERR2STATUS; + uint32_t RESERVED41; + FWK_RW uint32_t ERR2ADDR0; + FWK_RW uint32_t ERR2ADDR1; + FWK_RW uint32_t ERR2MISC0; + FWK_RW uint32_t ERR2MISC1; + FWK_RW uint32_t ERR2MISC2; + FWK_RW uint32_t ERR2MISC3; + FWK_RW uint32_t ERR2MISC4; + FWK_RW uint32_t ERR2MISC5; + uint8_t RESERVED42[0x7C0 - 0x7B8]; + FWK_R uint32_t ERR3FR; + uint32_t RESERVED43; + FWK_R uint32_t ERR3CTLR; + uint32_t RESERVED44; + FWK_R uint32_t ERR3STATUS; + uint32_t RESERVED45; + FWK_RW uint32_t ERR3ADDR0; + FWK_RW uint32_t ERR3ADDR1; + uint8_t RESERVED46[0x800 - 0x7E0]; + FWK_R uint32_t ERR4FR; + uint32_t RESERVED47; + FWK_R uint32_t ERR4CTLR; + uint32_t RESERVED48; + FWK_R uint32_t ERR4STATUS; + uint32_t RESERVED49; + FWK_RW uint32_t ERR4ADDR0; + FWK_RW uint32_t ERR4ADDR1; + FWK_RW uint32_t ERR4MISC0; + FWK_RW uint32_t ERR4MISC1; + FWK_RW uint32_t ERR4MISC2; + uint8_t RESERVED50[0x840 - 0x82C]; + FWK_R uint32_t ERR5FR; + uint32_t RESERVED51; + FWK_R uint32_t ERR5CTLR; + uint32_t RESERVED52; + FWK_R uint32_t ERR5STATUS; + uint32_t RESERVED53; + FWK_RW uint32_t ERR5ADDR0; + FWK_RW uint32_t ERR5ADDR1; + FWK_RW uint32_t ERR5MISC0; + FWK_RW uint32_t ERR5MISC1; + FWK_RW uint32_t ERR5MISC2; + uint8_t RESERVED54[0x880 - 0x86C]; + FWK_R uint32_t ERR6FR; + uint32_t RESERVED55; + FWK_R uint32_t ERR6CTLR; + uint32_t RESERVED56; + FWK_R uint32_t ERR6STATUS; + uint32_t RESERVED57; + FWK_RW uint32_t ERR6ADDR0; + FWK_RW uint32_t ERR6ADDR1; + FWK_RW uint32_t ERR6MISC0; + FWK_RW uint32_t ERR6MISC1; + uint8_t RESERVED58[0x920 - 0x8A8]; + FWK_RW uint32_t ERRGSR; + uint8_t RESERVED59[0xA00 - 0x924]; + FWK_W uint32_t PMU_SNAPSHOT_REQ; + FWK_R uint32_t PMU_SNAPSHOT_ACK; + FWK_RW uint32_t PMU_OVERFLOW_STATUS_CLKDIV2; + FWK_RW uint32_t PMU_OVERFLOW_STATUS_CLK; + struct mod_dmc620_pmu_counter PMC_CLKDIV2_COUNT[8]; + struct mod_dmc620_pmu_counter PMC_CLK_COUNT[2]; + uint8_t RESERVED60[0xE00 - 0xBA0]; + FWK_RW uint32_t INTEG_CFG; + uint32_t RESERVED61; + FWK_W uint32_t INTEG_OUTPUTS; + uint8_t RESERVED62[0x1010 - 0xE0C]; + FWK_R uint32_t ADDRESS_CONTROL_NOW; + FWK_R uint32_t DECODE_CONTROL_NOW; + uint32_t RESERVED63; + FWK_R uint32_t ADDRESS_MAP_NOW; + FWK_R uint32_t LOW_POWER_CONTROL_NOW; + uint32_t RESERVED64; + FWK_R uint32_t TURNAROUND_CONTROL_NOW; + FWK_R uint32_t HIT_TURNAROUND_CONTROL_NOW; + FWK_R uint32_t QOS_CLASS_CONTROL_NOW; + FWK_R uint32_t ESCALATION_CONTROL_NOW; + FWK_R uint32_t QV_CONTROL_31_00_NOW; + FWK_R uint32_t QV_CONTROL_63_32_NOW; + FWK_R uint32_t RT_CONTROL_31_00_NOW; + FWK_R uint32_t RT_CONTROL_63_32_NOW; + FWK_R uint32_t TIMEOUT_CONTROL_NOW; + FWK_R uint32_t CREDIT_CONTROL_NOW; + FWK_R uint32_t WRITE_PRIORITY_CONTROL_31_00_NOW; + FWK_R uint32_t WRITE_PRIORITY_CONTROL_63_32_NOW; + FWK_R uint32_t QUEUE_THRESHOLD_CONTROL_31_00_NOW; + FWK_R uint32_t QUEUE_THRESHOLD_CONTROL_63_32_NOW; + FWK_R uint32_t ADDRESS_SHUTTER_31_00_NOW; + FWK_R uint32_t ADDRESS_SHUTTER_63_32_NOW; + FWK_R uint32_t ADDRESS_SHUTTER_95_64_NOW; + FWK_R uint32_t ADDRESS_SHUTTER_127_96_NOW; + FWK_R uint32_t ADDRESS_SHUTTER_159_128_NOW; + FWK_R uint32_t ADDRESS_SHUTTER_191_160_NOW; + FWK_R uint32_t MEMORY_ADDRESS_MAX_31_00_NOW; + FWK_R uint32_t MEMORY_ADDRESS_MAX_43_32_NOW; + struct mod_dmc620_access_address_now ACCESS_ADDRESS_NOW + [MOD_DMC620_ACCESS_ADDRESS_COUNT]; + uint8_t RESERVED65[0x1110 - 0x1100]; + FWK_R uint32_t DCI_REPLAY_TYPE_NOW; + FWK_R uint32_t DIRECT_CONTROL_NOW; + uint8_t RESERVED66[0x1120 - 0x1118]; + FWK_R uint32_t REFRESH_CONTROL_NOW; + uint32_t RESERVED67; + FWK_R uint32_t MEMORY_TYPE_NOW; + uint8_t RESERVED68[0x1170 - 0x112C]; + FWK_R uint32_t SCRUB_CONTROL0_NOW; + FWK_R uint32_t SCRUB_ADDRESS_MIN0_NOW; + FWK_R uint32_t SCRUB_ADDRESS_MAX0_NOW; + uint32_t RESERVED69; + FWK_R uint32_t SCRUB_CONTROL1_NOW; + FWK_R uint32_t SCRUB_ADDRESS_MIN1_NOW; + FWK_R uint32_t SCRUB_ADDRESS_MAX1_NOW; + uint8_t RESERVED70[0x11A0 - 0x118C]; + FWK_R uint32_t CS_REMAP_CONTROL_31_00_NOW; + FWK_R uint32_t CS_REMAP_CONTROL_63_32_NOW; + FWK_R uint32_t CS_REMAP_CONTROL_95_64_NOW; + FWK_R uint32_t CS_REMAP_CONTROL_127_96_NOW; + FWK_R uint32_t CID_REMAP_CONTROL_31_00_NOW; + FWK_R uint32_t CID_REMAP_CONTROL_63_32_NOW; + uint8_t RESERVED71[0x11C0 - 0x11B8]; + FWK_R uint32_t CKE_REMAP_CONTROL_31_00_NOW; + FWK_R uint32_t RST_REMAP_CONTROL_31_00_NOW; + FWK_R uint32_t CK_REMAP_CONTROL_31_00_NOW; + FWK_R uint32_t POWER_GROUP_CONTROL_31_00_NOW; + FWK_R uint32_t POWER_GROUP_CONTROL_63_32_NOW; + FWK_R uint32_t POWER_GROUP_CONTROL_95_64_NOW; + FWK_R uint32_t POWER_GROUP_CONTROL_127_96_NOW; + uint8_t RESERVED72[0x11F0 - 0x11E0]; + FWK_R uint32_t FEATURE_CONTROL_NOW; + FWK_R uint32_t MUX_CONTROL_NOW; + FWK_R uint32_t RANK_REMAP_CONTROL_NOW; + uint32_t RESERVED73; + FWK_R uint32_t T_REFI_NOW; + FWK_R uint32_t T_RFC_NOW; + FWK_R uint32_t T_MRR_NOW; + FWK_R uint32_t T_MRW_NOW; + uint8_t RESERVED74[0x1218 - 0x1210]; + FWK_R uint32_t T_RCD_NOW; + FWK_R uint32_t T_RAS_NOW; + FWK_R uint32_t T_RP_NOW; + FWK_R uint32_t T_RPALL_NOW; + FWK_R uint32_t T_RRD_NOW; + FWK_R uint32_t T_ACT_WINDOW_NOW; + uint32_t RESERVED75; + FWK_R uint32_t T_RTR_NOW; + FWK_R uint32_t T_RTW_NOW; + FWK_R uint32_t T_RTP_NOW; + uint32_t RESERVED76; + FWK_R uint32_t T_WR_NOW; + FWK_R uint32_t T_WTR_NOW; + FWK_R uint32_t T_WTW_NOW; + uint32_t RESERVED77; + FWK_R uint32_t T_XMPD_NOW; + FWK_R uint32_t T_EP_NOW; + FWK_R uint32_t T_XP_NOW; + FWK_R uint32_t T_ESR_NOW; + FWK_R uint32_t T_XSR_NOW; + FWK_R uint32_t T_ESRCK_NOW; + FWK_R uint32_t T_CKXSR_NOW; + FWK_R uint32_t T_CMD_NOW; + FWK_R uint32_t T_PARITY_NOW; + FWK_R uint32_t T_ZQCS_NOW; + FWK_R uint32_t T_RW_ODT_CLR_NOW; + uint8_t RESERVED78[0x1300 - 0x1280]; + FWK_R uint32_t T_RDDATA_EN_NOW; + FWK_R uint32_t T_PHYRDLAT_NOW; + FWK_R uint32_t T_PHYWRLAT_NOW; + uint32_t RESERVED79; + FWK_R uint32_t RDLVL_CONTROL_NOW; + FWK_R uint32_t RDLVL_MRS_NOW; + FWK_R uint32_t T_RDLVL_EN_NOW; + FWK_R uint32_t T_RDLVL_RR_NOW; + FWK_R uint32_t WRLVL_CONTROL_NOW; + FWK_R uint32_t WRLVL_MRS_NOW; + FWK_R uint32_t T_WRLVL_EN_NOW; + FWK_R uint32_t T_WRLVL_WW_NOW; + uint8_t RESERVED80[0x1348 - 0x1330]; + FWK_R uint32_t PHY_POWER_CONTROL_NOW; + FWK_R uint32_t T_LPRESP_NOW; + FWK_R uint32_t PHY_UPDATE_CONTROL_NOW; + FWK_R uint32_t T_ODTH_NOW; + FWK_R uint32_t ODT_TIMING_NOW; + uint32_t RESERVED81; + FWK_R uint32_t ODT_WR_CONTROL_31_00_NOW; + FWK_R uint32_t ODT_WR_CONTROL_63_32_NOW; + FWK_R uint32_t ODT_RD_CONTROL_31_00_NOW; + FWK_R uint32_t ODT_RD_CONTROL_63_32_NOW; + uint8_t RESERVED82[0x1380 - 0x1370]; + FWK_R uint32_t DQ_MAP_CONTROL_15_00_NOW; + FWK_R uint32_t DQ_MAP_CONTROL_31_16_NOW; + FWK_R uint32_t DQ_MAP_CONTROL_47_32_NOW; + FWK_R uint32_t DQ_MAP_CONTROL_63_48_NOW; + FWK_R uint32_t DQ_MAP_CONTROL_71_64_NOW; + uint8_t RESERVED83[0x13B0 - 0x1394]; + FWK_R uint32_t ODT_CP_CONTROL_31_00_NOW; + FWK_R uint32_t ODT_CP_CONTROL_63_32_NOW; + uint8_t RESERVED84[0x1408 - 0x13B8]; + FWK_R uint32_t USER_CONFIG0_NOW; + FWK_R uint32_t USER_CONFIG1_NOW; + uint8_t RESERVED85[0x1610 - 0x1410]; + FWK_R uint32_t T_DB_TRAIN_RESP_NOW; + FWK_R uint32_t T_LVL_DISCONNECT_NOW; + uint8_t RESERVED86[0x1620 - 0x1618]; + FWK_R uint32_t WDQLVL_CONTROL_NOW; + FWK_R uint32_t WDQLVL_VREFDQ_TRAIN_MRS_NOW; + FWK_R uint32_t WDQLVL_ADDRESS_31_00_NOW; + FWK_R uint32_t WDQLVL_ADDRESS_63_32_NOW; + FWK_R uint32_t T_WDQLVL_EN_NOW; + FWK_R uint32_t T_WDQLVL_WW_NOW; + FWK_R uint32_t T_WDQLVL_RW_NOW; + uint8_t RESERVED87[0x1654 - 0x163C]; + FWK_R uint32_t PHYMSTR_CONTROL_NOW; + uint8_t RESERVED88[0x1FD0 - 0x1658]; + FWK_R uint32_t PERIPH_ID_4; + uint8_t RESERVED89[0x1FE0 - 0x1FD4]; + FWK_R uint32_t PERIPH_ID_0; + FWK_R uint32_t PERIPH_ID_1; + FWK_R uint32_t PERIPH_ID_2; + FWK_R uint32_t PERIPH_ID_3; + FWK_R uint32_t COMPONENT_ID_0; + FWK_R uint32_t COMPONENT_ID_1; + FWK_R uint32_t COMPONENT_ID_2; + FWK_R uint32_t COMPONENT_ID_3; + /*! + * \endcond + * @} + */ +}; + +/*! + * \brief Mask to get the memc_cmd bitfield + */ +#define MOD_DMC620_MEMC_CMD UINT32_C(0x00000007) + +/*! + * \brief Command to enter into the CONFIG architectural state + */ +#define MOD_DMC620_MEMC_CMD_CONFIG UINT32_C(0x00000000) + +/*! + * \brief Command to enter the SLEEP architectural state + */ +#define MOD_DMC620_MEMC_CMD_SLEEP UINT32_C(0x00000001) + +/*! + * \brief Command to enter the READY architectural state + */ +#define MOD_DMC620_MEMC_CMD_GO UINT32_C(0x00000003) + +/*! + * \brief Command to perform any direct_cmd operations + */ +#define MOD_DMC620_MEMC_CMD_EXECUTE UINT32_C(0x00000004) + +/*! + * \brief MEMC command MGR active status bit + */ +#define MOD_DMC620_MEMC_STATUS_MGR_ACTIVE UINT32_C(0x00000100) + +/*! + * \brief DMC channel M0 idle status bit + */ +#define MOD_DMC620_CHANNEL_STATUS_M0_IDLE UINT32_C(0x00000001) + +/*! + * \brief Enable ECC detection on reads + */ +#define DMC_ERR0CTRL0_ED_ENABLE UINT32_C(0x00000001) + +/*! + * \brief Enable defer on reads + */ +#define DMC_ERR0CTRL0_DE_ENABLE UINT32_C(0x00000002) + +/*! + * \brief Enable uncorrectable error recovery interrupt + */ +#define DMC_ERR0CTRL0_UI_ENABLE UINT32_C(0x00000004) + +/*! + * \brief Enable ECC FHI interrupt + */ +#define DMC_ERR0CTRL0_FI_ENABLE UINT32_C(0x00000008) + +/*! + * \brief Enable CFI interrupt + */ +#define DMC_ERR0CTRL0_CFI_ENABLE UINT32_C(0x00000100) + +/*! + * \brief DDR training timeout in microseconds + */ +#define DMC_TRAINING_TIMEOUT UINT32_C(5000) + +/*! + * \brief DDR training command for rank 1 + */ +#define DDR_CMD_TRAIN_RANK_1 UINT32_C(0x0001000A) +/*! + * \brief DDR training command for rank 1 + */ +#define DDR_CMD_TRAIN_RANK_2 UINT32_C(0x0002000A) + +/*! + * \brief DDR training type - Read data eye training + */ +#define DDR_ADDR_TRAIN_TYPE_RD_EYE 1 +/*! + * \brief DDR training type - Read gate training + */ +#define DDR_ADDR_TRAIN_TYPE_RD_GATE 2 +/*! + * \brief DDR training type - Write levelling training + */ +#define DDR_ADDR_TRAIN_TYPE_WR_LVL 3 +/*! + * \brief DDR training type - VREF training + */ +#define DDR_ADDR_TRAIN_TYPE_VREF 4 +/*! + * \brief DDR training data slices position + */ +#define DDR_ADDR_DATA_SLICES_POS 12 + +/*! + * \brief Element configuration. + */ +struct mod_dmc620_element_config { + /*! Base address of the DMC-620 device's registers */ + uintptr_t dmc; + /*! Element identifier of the associated DDR PHY-500 device */ + fwk_id_t ddr_id; + /*! Identifier of the clock that this element depends on */ + fwk_id_t clock_id; +}; + +/*! + * \brief API of the DDR PHY associated to the DMC + */ +struct mod_dmc_ddr_phy_api { + /*! + * \brief Configure a DDR physical device + * + * \param element_id Element identifier corresponding to the device to + * configure. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ + int (*configure)(fwk_id_t element_id); + + /*! + * \brief Post training setting for DDR physical device + * + * \param element_id Element identifier corresponding to the device to + * configure. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ + int (*post_training_configure)(fwk_id_t element_id); + + /*! + * \brief API to verify DDR PHY status at different training stage + * + * \param element_id Element identifier corresponding to the device to + * configure. + * \param training_type Training type for which PHY status to be verified. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ + int (*verify_phy_status)(fwk_id_t element_id, uint8_t training_type); +}; + +/*! + * \brief DMC-620 module configuration. + */ +struct mod_dmc620_module_config { + /*! DDR PHY module ID */ + fwk_id_t ddr_module_id; + /*! DDR PHY API ID */ + fwk_id_t ddr_api_id; +}; + +/*! + * \brief Identifiers of DMC-620 configuration stages. + */ +enum dmc620_config_stage { + /*! DMC-620 DIMM training MGR active stage */ + DMC620_CONFIG_STAGE_TRAINING_MGR_ACTIVE, + + /*! DMC-620 DIMM training channel M0 idle stage */ + DMC620_CONFIG_STAGE_TRAINING_M0_IDLE, + + /*! DMC-620 configuration stages */ + DMC620_CONFIG_STAGE_COUNT, +}; + +/*! + * \brief Structure defining data to be passed to timer API. + */ +struct dmc620_wait_condition_data { + /*! Pointer to DMC-620 module registers */ + void *dmc; + + /*! DMC-620 configuration stage identifier */ + enum dmc620_config_stage stage; +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_DMC620_H */ diff --git a/product/n1sdp/module/n1sdp_dmc620/src/Makefile b/product/n1sdp/module/n1sdp_dmc620/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..ae8d69429f555c6651a97bb2c64e95191cb113f5 --- /dev/null +++ b/product/n1sdp/module/n1sdp_dmc620/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := N1SDP DMC620 +BS_LIB_SOURCES += mod_n1sdp_dmc620.c + +include $(BS_DIR)/lib.mk diff --git a/product/n1sdp/module/n1sdp_dmc620/src/mod_n1sdp_dmc620.c b/product/n1sdp/module/n1sdp_dmc620/src/mod_n1sdp_dmc620.c new file mode 100644 index 0000000000000000000000000000000000000000..6760695690e3d1c1b7968873a432e293f7055705 --- /dev/null +++ b/product/n1sdp/module/n1sdp_dmc620/src/mod_n1sdp_dmc620.c @@ -0,0 +1,859 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * N1SDP DMC-620 driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* DMC-620 register specific definitions */ +#define DDR_TRAIN_TWO_RANKS 0 + +static struct mod_log_api *log_api; +static struct mod_dmc_ddr_phy_api *ddr_phy_api; +static struct mod_timer_api *timer_api; + +static int dmc620_config(struct mod_dmc620_reg *dmc, fwk_id_t ddr_id); +static void direct_ddr_cmd(struct mod_dmc620_reg *dmc); +static int enable_dimm_refresh(struct mod_dmc620_reg *dmc); +static int dmc620_config_interrupt(fwk_id_t ddr_id); + +/* Framework API */ +static int mod_dmc620_init(fwk_id_t module_id, unsigned int element_count, + const void *config) +{ + return FWK_SUCCESS; +} + +static int mod_dmc620_element_init(fwk_id_t element_id, unsigned int unused, + const void *data) +{ + fwk_assert(data != NULL); + + return FWK_SUCCESS; +} + +static int mod_dmc620_bind(fwk_id_t id, unsigned int round) +{ + int status; + const struct mod_dmc620_module_config *module_config; + + /* Nothing to do in the second round of calls. */ + if (round == 1) + return FWK_SUCCESS; + + /* Nothing to do in case of elements. */ + if (fwk_module_is_valid_element_id(id)) + return FWK_SUCCESS; + + module_config = fwk_module_get_data(fwk_module_id_n1sdp_dmc620); + fwk_assert(module_config != NULL); + + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG), + MOD_LOG_API_ID, &log_api); + if (status != FWK_SUCCESS) + return status; + + status = fwk_module_bind(module_config->ddr_module_id, + module_config->ddr_api_id, &ddr_phy_api); + if (status != FWK_SUCCESS) + return status; + + status = fwk_module_bind(FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + FWK_ID_API(FWK_MODULE_IDX_TIMER, MOD_TIMER_API_IDX_TIMER), + &timer_api); + if (status != FWK_SUCCESS) + return status; + + return FWK_SUCCESS; +} + +static int mod_dmc620_start(fwk_id_t id) +{ + const struct mod_dmc620_element_config *element_config; + + if (!fwk_id_is_type(id, FWK_ID_TYPE_ELEMENT)) { + /* Bypass divide by 2 so DMCCLK1X = DMCCLK2X */ + PIK_SYSTEM->DMCCLK_CTRL |= PIK_SYSTEM_DMCCLK_CTRL_DIV2_BYPASS_MASK; + return FWK_SUCCESS; + } + + element_config = fwk_module_get_data(id); + + /* Register elements for clock state notifications */ + return fwk_notification_subscribe( + mod_clock_notification_id_state_changed, + element_config->clock_id, + id); +} + +static int dmc620_notify_system_state_transition_resume(fwk_id_t id) +{ + struct mod_dmc620_reg *dmc; + const struct mod_dmc620_element_config *element_config; + + element_config = fwk_module_get_data(id); + dmc = (struct mod_dmc620_reg *)element_config->dmc; + + return dmc620_config(dmc, element_config->ddr_id); +} + +static int mod_dmc620_process_notification( + const struct fwk_event *event, + struct fwk_event *resp_event) +{ + struct clock_notification_params *params; + + fwk_assert(fwk_id_is_equal(event->id, + mod_clock_notification_id_state_changed)); + fwk_assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_ELEMENT)); + + params = (struct clock_notification_params *)event->params; + + if (params->new_state == MOD_CLOCK_STATE_RUNNING) + return dmc620_notify_system_state_transition_resume(event->target_id); + + return FWK_SUCCESS; +} + +const struct fwk_module module_n1sdp_dmc620 = { + .name = "N1SDP-DMC620", + .type = FWK_MODULE_TYPE_DRIVER, + .init = mod_dmc620_init, + .element_init = mod_dmc620_element_init, + .bind = mod_dmc620_bind, + .start = mod_dmc620_start, + .process_notification = mod_dmc620_process_notification, + .api_count = 0, + .event_count = 0, +}; + +bool dmc620_wait_condition(void *data) +{ + fwk_assert(data != NULL); + + struct dmc620_wait_condition_data *wait_data = + (struct dmc620_wait_condition_data *)data; + struct mod_dmc620_reg *dmc = + (struct mod_dmc620_reg *)(wait_data->dmc); + + switch (wait_data->stage) { + case DMC620_CONFIG_STAGE_TRAINING_MGR_ACTIVE: + return ((dmc->MEMC_STATUS & MOD_DMC620_MEMC_STATUS_MGR_ACTIVE) == 0); + case DMC620_CONFIG_STAGE_TRAINING_M0_IDLE: + return ((dmc->CHANNEL_STATUS & + MOD_DMC620_CHANNEL_STATUS_M0_IDLE) != 0); + default: + fwk_assert(false); + return false; + } +} + +static int ddr_poll_training_status(struct mod_dmc620_reg *dmc) +{ + struct dmc620_wait_condition_data wait_data; + int status; + + wait_data.dmc = dmc; + wait_data.stage = DMC620_CONFIG_STAGE_TRAINING_MGR_ACTIVE; + status = timer_api->wait(FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + DMC_TRAINING_TIMEOUT, + dmc620_wait_condition, + &wait_data); + if (status != FWK_SUCCESS) { + log_api->log(MOD_LOG_GROUP_INFO, "FAIL\n"); + return status; + } + + wait_data.stage = DMC620_CONFIG_STAGE_TRAINING_M0_IDLE; + status = timer_api->wait(FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + DMC_TRAINING_TIMEOUT, + dmc620_wait_condition, + &wait_data); + if (status != FWK_SUCCESS) { + log_api->log(MOD_LOG_GROUP_INFO, "FAIL\n"); + return status; + } + + log_api->log(MOD_LOG_GROUP_INFO, "PASS\n"); + + return FWK_SUCCESS; +} + +static int dmc620_poll_dmc_status(struct mod_dmc620_reg *dmc) +{ + struct dmc620_wait_condition_data wait_data; + + wait_data.dmc = dmc; + wait_data.stage = DMC620_CONFIG_STAGE_TRAINING_MGR_ACTIVE; + return timer_api->wait(FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + DMC_TRAINING_TIMEOUT, + dmc620_wait_condition, + &wait_data); +} + +static int ddr_training(struct mod_dmc620_reg *dmc) +{ + uint32_t value; + int status; + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Training DDR memories...\n"); + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Write leveling... "); + + /* Set training command */ + dmc->DIRECT_ADDR = DDR_ADDR_TRAIN_TYPE_WR_LVL; + dmc->DIRECT_CMD = DDR_CMD_TRAIN_RANK_1; + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) + return status; + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Read gate training\n"); + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] A side..."); + + /* Set write leveling parameters */ + value = dmc->RDLVL_CONTROL_NEXT; + value |= (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + /* Update */ + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = 0x0001000C; + + /* Run training on slices 0-9 */ + dmc->DIRECT_ADDR = (DDR_ADDR_TRAIN_TYPE_RD_GATE | + (0x3FFFF << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = DDR_CMD_TRAIN_RANK_1; + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) + return status; + +#if DDR_TRAIN_TWO_RANKS + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] B side..."); + + /* Set write leveling parameters */ + value = dmc->RDLVL_CONTROL_NEXT; + value |= (0x03 << 9) | (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + /* Update */ + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = 0x0001000C; + + /* Run training on slices 10-17 */ + dmc->DIRECT_ADDR = (DDR_ADDR_TRAIN_TYPE_RD_GATE | + (0x3FFFF << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = DDR_CMD_TRAIN_RANK_1; + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) + return status; +#endif + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Read eye training\n"); + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] A side..."); + + /* Set write leveling parameters */ + value = dmc->RDLVL_CONTROL_NEXT; + value |= (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + /* Update */ + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = 0x0001000C; + + /* Run training on slices 0-9 */ + dmc->DIRECT_ADDR = (DDR_ADDR_TRAIN_TYPE_RD_EYE | + (0x201FF << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = DDR_CMD_TRAIN_RANK_1; + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) + return status; + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] B side..."); + + /* Set write leveling parameters */ + value = dmc->RDLVL_CONTROL_NEXT; + value |= (0x03 << 9) | (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + /* Update */ + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = 0x0001000C; + + /* Run training on slices 10-17 */ + dmc->DIRECT_ADDR = (DDR_ADDR_TRAIN_TYPE_RD_EYE | + (0x1FE00 << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = DDR_CMD_TRAIN_RANK_1; + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) + return status; + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] MC initiated update..."); + + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = 0x0001000A; + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) + return status; + + dmc->DIRECT_CMD = 0x0001000C; + + return FWK_SUCCESS; +} + +static int dmc620_verify_phy_status(struct mod_dmc620_reg *dmc, + fwk_id_t ddr_id) +{ + int status; + uint8_t i; + + for (i = 0; i < 2; i++) { + status = ddr_phy_api->verify_phy_status(ddr_id, + DDR_ADDR_TRAIN_TYPE_WR_LVL); + if (status != FWK_SUCCESS) + return status; + + status = ddr_phy_api->verify_phy_status(ddr_id, + DDR_ADDR_TRAIN_TYPE_RD_GATE); + if (status != FWK_SUCCESS) + return status; + + status = ddr_phy_api->verify_phy_status(ddr_id, + DDR_ADDR_TRAIN_TYPE_RD_EYE); + if (status != FWK_SUCCESS) + return status; + + status = ddr_phy_api->verify_phy_status(ddr_id, + DDR_ADDR_TRAIN_TYPE_VREF); + if (status != FWK_SUCCESS) + return status; + } + return FWK_SUCCESS; +} + +static int dmc620_config(struct mod_dmc620_reg *dmc, fwk_id_t ddr_id) +{ + int status; + + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Initialising DMC620 at 0x%x\n", (uintptr_t)dmc); + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Writing functional settings\n"); + + dmc->ADDRESS_CONTROL_NEXT = 0x00040502; + dmc->DECODE_CONTROL_NEXT = 0x001C2800; + dmc->FORMAT_CONTROL = 0x00000003; + dmc->ADDRESS_MAP_NEXT = 0x00000003; + dmc->ADDRESS_SHUTTER_31_00_NEXT = 0x00000000; + dmc->ADDRESS_SHUTTER_63_32_NEXT = 0x00000000; + dmc->ADDRESS_SHUTTER_95_64_NEXT = 0x00000000; + dmc->ADDRESS_SHUTTER_127_96_NEXT = 0x00000000; + dmc->ADDRESS_SHUTTER_159_128_NEXT = 0x00000000; + dmc->ADDRESS_SHUTTER_191_160_NEXT = 0x00000000; + dmc->LOW_POWER_CONTROL_NEXT = 0x00000010; + dmc->MEMORY_ADDRESS_MAX_31_00_NEXT = 0xffff001f; + dmc->MEMORY_ADDRESS_MAX_43_32_NEXT = 0x0000ffff; + dmc->ACCESS_ADDRESS_NEXT[0].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[1].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[2].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[3].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[4].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[5].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[6].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[7].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[0].MIN_43_32 = 0x00000000; + dmc->ACCESS_ADDRESS_NEXT[1].MIN_43_32 = 0x00000000; + dmc->ACCESS_ADDRESS_NEXT[2].MIN_43_32 = 0x00000000; + dmc->ACCESS_ADDRESS_NEXT[3].MIN_43_32 = 0x00000000; + dmc->ACCESS_ADDRESS_NEXT[4].MIN_43_32 = 0x00000000; + dmc->ACCESS_ADDRESS_NEXT[5].MIN_43_32 = 0x00000000; + dmc->ACCESS_ADDRESS_NEXT[6].MIN_43_32 = 0x00000000; + dmc->ACCESS_ADDRESS_NEXT[7].MIN_43_32 = 0x00000000; + dmc->DCI_REPLAY_TYPE_NEXT = 0x00000000; + dmc->DIRECT_CONTROL_NEXT = 0x00000000; + dmc->DCI_STRB = 0x00000000; + dmc->MEMORY_TYPE_NEXT = 0x00030102; + dmc->FEATURE_CONFIG = 0x00001820; + dmc->T_REFI_NEXT = 0x80000487; + dmc->T_RFC_NEXT = 0x0005D9D2; + dmc->T_MRR_NEXT = 0x00000001; + dmc->T_MRW_NEXT = 0x00000018; + dmc->T_RCD_NEXT = 0x00000014; + dmc->T_RAS_NEXT = 0x00000027; + dmc->T_RP_NEXT = 0x00000014; + dmc->T_RPALL_NEXT = 0x00000013; + dmc->T_RRD_NEXT = 0x04000604; + dmc->T_ACT_WINDOW_NEXT = 0x00001017; + dmc->T_RTR_NEXT = 0x14060604; + dmc->T_RTW_NEXT = 0x001B1B1B; + dmc->T_RTP_NEXT = 0x00000008; + dmc->T_WR_NEXT = 0x00000029; + dmc->T_WTR_NEXT = 0x001B1B1B; + dmc->T_WTW_NEXT = 0x14060604; + dmc->T_XMPD_NEXT = 0x00000480; + dmc->T_EP_NEXT = 0x00000006; + dmc->T_XP_NEXT = 0x000e0007; + dmc->T_ESR_NEXT = 0x00000007; + dmc->T_XSR_NEXT = 0x03000384; + dmc->T_ESRCK_NEXT = 0x0000000a; + dmc->T_CKXSR_NEXT = 0x0000000a; + dmc->T_PARITY_NEXT = 0x00001100; + dmc->T_ZQCS_NEXT = 0x00000090; + dmc->T_RDDATA_EN_NEXT = 0x0000000E; + dmc->T_PHYRDLAT_NEXT = 0x00000046; + dmc->T_PHYWRLAT_NEXT = 0x011f000C; + dmc->RDLVL_CONTROL_NEXT = 0x01000000; + dmc->RDLVL_MRS_NEXT = 0x00000224; + dmc->T_RDLVL_RR_NEXT = 0x0000001E; + dmc->WRLVL_CONTROL_NEXT = 0x00100000; + dmc->WRLVL_MRS_NEXT = 0x00000181; + dmc->T_WRLVL_EN_NEXT = 0x0000001E; + dmc->PHY_UPDATE_CONTROL_NEXT = 0x01401111; + dmc->T_LVL_DISCONNECT_NEXT = 0x00000001; + dmc->WDQLVL_CONTROL_NEXT = 0x00000080; + dmc->T_WDQLVL_EN_NEXT = 0x00000024; + dmc->T_WDQLVL_WW_NEXT = 0x00000006; + dmc->T_WDQLVL_RW_NEXT = 0x00000009; + dmc->ERR0CTLR1 = 0x000000d1; + dmc->RANK_REMAP_CONTROL_NEXT = 0x76543210; + dmc->PHY_REQUEST_CS_REMAP = 0x76543210; + dmc->T_ODTH_NEXT = 0x00000006; + dmc->ODT_TIMING_NEXT = 0x06000600; + dmc->T_RW_ODT_CLR_NEXT = 0x0000000f; + dmc->T_CMD_NEXT = 0x00000000; + dmc->T_RDLVL_EN_NEXT = 0x0000001E; + dmc->T_WRLVL_WW_NEXT = 0x0000001E; + dmc->PHYMSTR_CONTROL_NEXT = 0x00000000; + dmc->T_LPRESP_NEXT = 0x00000005; + dmc->ODT_WR_CONTROL_31_00_NEXT = 0x08040201; + dmc->ODT_WR_CONTROL_63_32_NEXT = 0x08040201; + dmc->ODT_RD_CONTROL_31_00_NEXT = 0x00000000; + dmc->ODT_RD_CONTROL_63_32_NEXT = 0x00000000; + dmc->ODT_CP_CONTROL_31_00_NEXT = 0x08040201; + dmc->ODT_CP_CONTROL_63_32_NEXT = 0x80402010; + dmc->CS_REMAP_CONTROL_31_00_NEXT = 0x00020001; + dmc->CS_REMAP_CONTROL_63_32_NEXT = 0x00080004; + dmc->CS_REMAP_CONTROL_95_64_NEXT = 0x00200010; + dmc->CS_REMAP_CONTROL_127_96_NEXT = 0x00800040; + dmc->CID_REMAP_CONTROL_31_00_NEXT = 0x00000000; + dmc->CID_REMAP_CONTROL_63_32_NEXT = 0x00000000; + dmc->POWER_GROUP_CONTROL_31_00_NEXT = 0x00020001; + dmc->POWER_GROUP_CONTROL_63_32_NEXT = 0x00080004; + dmc->POWER_GROUP_CONTROL_95_64_NEXT = 0x00200010; + dmc->POWER_GROUP_CONTROL_127_96_NEXT = 0x00800040; + dmc->REFRESH_CONTROL_NEXT = 0x00000000; + dmc->T_RTR_NEXT = 0x14060604; + dmc->T_DB_TRAIN_RESP_NEXT = 0x00000004; + dmc->FEATURE_CONTROL_NEXT = 0x0aa30000; + dmc->MUX_CONTROL_NEXT = 0x00000000; + dmc->LOW_POWER_CONTROL_NEXT = 0x00000010; + dmc->MEMORY_ADDRESS_MAX_31_00_NEXT = 0xffff001f; + dmc->INTERRUPT_CONTROL = 0x00000070; + + dmc->DIRECT_CMD = 0x0001000C; + + dmc->USER_CONFIG0_NEXT = 0x1; + dmc->MEMC_CMD = MOD_DMC620_MEMC_CMD_GO; + while ((dmc->MEMC_STATUS & MOD_DMC620_MEMC_CMD) != MOD_DMC620_MEMC_CMD_GO) + continue; + + status = ddr_phy_api->configure(ddr_id); + if (status != FWK_SUCCESS) + return status; + + dmc->MEMC_CMD = MOD_DMC620_MEMC_CMD_CONFIG; + while ((dmc->MEMC_STATUS & MOD_DMC620_MEMC_CMD) != + MOD_DMC620_MEMC_CMD_CONFIG) + continue; + dmc->USER_CONFIG0_NEXT = 0x3; + dmc->MEMC_CMD = MOD_DMC620_MEMC_CMD_GO; + while ((dmc->MEMC_STATUS & MOD_DMC620_MEMC_CMD) != MOD_DMC620_MEMC_CMD_GO) + continue; + dmc->MEMC_CMD = MOD_DMC620_MEMC_CMD_CONFIG; + while ((dmc->MEMC_STATUS & MOD_DMC620_MEMC_CMD) != + MOD_DMC620_MEMC_CMD_CONFIG) + continue; + + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Sending direct DDR commands\n"); + + direct_ddr_cmd(dmc); + + dmc620_config_interrupt(ddr_id); + + status = ddr_training(dmc); + if (status != FWK_SUCCESS) + return status; + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Enable DIMM refresh..."); + status = enable_dimm_refresh(dmc); + if (status != FWK_SUCCESS) + return status; + + /* Switch to READY */ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Setting DMC to READY mode\n"); + + dmc->MEMC_CMD = MOD_DMC620_MEMC_CMD_GO; + + while ((dmc->MEMC_STATUS & MOD_DMC620_MEMC_CMD) != MOD_DMC620_MEMC_CMD_GO) + continue; + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] DMC init done.\n"); + + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Verifying PHY status..."); + status = dmc620_verify_phy_status(dmc, ddr_id); + if (status != FWK_SUCCESS) + return status; + log_api->log(MOD_LOG_GROUP_INFO, "Done\n"); + + return FWK_SUCCESS; +} + +static void execute_ddr_cmd(struct mod_dmc620_reg *dmc, + uint32_t addr, uint32_t cmd) +{ + int status; + + dmc->DIRECT_ADDR = addr; + dmc->DIRECT_CMD = cmd; + status = dmc620_poll_dmc_status(dmc); + if (status != FWK_SUCCESS) { + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Execute command failed! ADDR: 0x%08x CMD: 0x%08x\n", + addr, cmd); + } +} + +static void direct_ddr_cmd(struct mod_dmc620_reg *dmc) +{ + int count; + + execute_ddr_cmd(dmc, 0x00000004, 0x0001000A); + execute_ddr_cmd(dmc, 0x00000006, 0x00010004); + execute_ddr_cmd(dmc, 0x00000000, 0x0001000B); + execute_ddr_cmd(dmc, 0x00000001, 0x0001000B); + execute_ddr_cmd(dmc, 0x000003E8, 0x0001000D); + execute_ddr_cmd(dmc, 0x00000258, 0x0001000D); + execute_ddr_cmd(dmc, 0x00010001, 0x0001000B); + execute_ddr_cmd(dmc, 0x0000002A, 0x0001000D); + + for (count = 0; count < 12; count++) + execute_ddr_cmd(dmc, 0x00000200, 0x0001000D); + + execute_ddr_cmd(dmc, 0x000000A0, 0x0001070F); + execute_ddr_cmd(dmc, 0x00000311, 0x0001070F); + execute_ddr_cmd(dmc, 0x000000DC, 0x0001070F); + execute_ddr_cmd(dmc, 0x000000EC, 0x0001070F); + execute_ddr_cmd(dmc, 0x00000000, 0x00010000); + + /* MRS3 */ + execute_ddr_cmd(dmc, 0x00000220, 0x00010301); + + /* MRS6 */ + execute_ddr_cmd(dmc, 0x00000C97, 0x00010601); + + /* MRS5 */ + execute_ddr_cmd(dmc, 0x00000180, 0x00010501); + + /* MRS4 */ + execute_ddr_cmd(dmc, 0x00000000, 0x00010401); + + /* MRS2 */ + execute_ddr_cmd(dmc, 0x00000818, 0x00010201); + + /* MRS1 */ + execute_ddr_cmd(dmc, 0x00000003, 0x00010101); + + /* MRS0 */ + execute_ddr_cmd(dmc, 0x00000B40, 0x00010001); + + for (count = 0; count < 12; count++) + execute_ddr_cmd(dmc, 0x00000200, 0x0001000D); + + execute_ddr_cmd(dmc, 0x00000400, 0x00010005); + + for (count = 0; count < 12; count++) + execute_ddr_cmd(dmc, 0x00000200, 0x0001000D); +} + +static int enable_dimm_refresh(struct mod_dmc620_reg *dmc) +{ + dmc->REFRESH_ENABLE_NEXT = 0x00000001; + dmc->DIRECT_CMD = 0x0001000C; + + return ddr_poll_training_status(dmc); +} + +void dmc620_abort_recover(struct mod_dmc620_reg *dmc) +{ + uint32_t current_state; + volatile uint32_t *dmc_abort = 0; + + current_state = dmc->MEMC_STATUS & 0x00000007; + /* Make sure we don't run this from ABORT or RECOVERY states */ + if (current_state > 3) { + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC generated abortable error from abort/recovery state\n"); + return; + } + + /* Abort register is at offset 0x10000 */ + dmc_abort = (uint32_t *)((uint32_t)dmc + 0x10000); + + /* Assert abort request */ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Asserting abort request\n"); + *dmc_abort = 0x1; + + /* Wait for DMC to enter aborted state */ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Waiting for DMC to enter abort state..."); + while ((dmc->MEMC_STATUS & 0x00000007) != 0x4) + continue; + + log_api->log(MOD_LOG_GROUP_INFO, "DONE\n"); + + /* Deassert abort request */ + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Deasserting abort request\n"); + *dmc_abort = 0x0; + + /* Send ABORT_CLR command to change to recovery mode. */ + log_api->log(MOD_LOG_GROUP_INFO, "[DDR] Sending abort clear\n"); + dmc->MEMC_CMD = 0x00000006; + + /* Wait for state transition to complete */ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Waiting for DMC state transition..."); + while ((dmc->MEMC_STATUS & 0x00000007) != 0x5) + continue; + + log_api->log(MOD_LOG_GROUP_INFO, "DONE\n"); + + /* Go back to pre-error state */ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Initiating state transition back to normal world\n"); + dmc->MEMC_CMD = current_state; + + /* Wait for state transition to complete */ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Waiting for DMC state transition..."); + while ((dmc->MEMC_STATUS & 0x00000007) != current_state) + continue; + + log_api->log(MOD_LOG_GROUP_INFO, "DONE\n"); + + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Resuming operation in state %d\n", current_state); +} + +void dmc620_handle_interrupt(int dmc_num) +{ + struct mod_dmc620_reg *dmc; + const struct mod_dmc620_element_config *element_config; + + element_config = fwk_module_get_data( + FWK_ID_ELEMENT(FWK_MODULE_IDX_N1SDP_DMC620, dmc_num)); + dmc = (struct mod_dmc620_reg *)element_config->dmc; + + dmc620_abort_recover(dmc); + dmc->INTERRUPT_CLR = 0x3FF; +} + +void dmc0_misc_oflow_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC0 MISC overflow interrupt!\n"); + dmc620_handle_interrupt(0); + fwk_interrupt_clear_pending(DMCS0_MISC_OFLOW_IRQ); +} + +void dmc0_err_oflow_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC0 error overflow interrupt!\n"); + dmc620_handle_interrupt(0); + fwk_interrupt_clear_pending(DMCS0_ERR_OFLOW_IRQ); +} + +void dmc0_ecc_err_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC0 ECC error interrupt!\n"); + dmc620_handle_interrupt(0); + fwk_interrupt_clear_pending(DMCS0_ECC_ERR_INT_IRQ); +} + +void dmc0_misc_access_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC0 misc access interrupt!\n"); + dmc620_handle_interrupt(0); + fwk_interrupt_clear_pending(DMCS0_MISC_ACCESS_INT_IRQ); +} + +void dmc0_temp_event_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC0 temperature event interrupt!\n"); + dmc620_handle_interrupt(0); + fwk_interrupt_clear_pending(DMCS0_TEMPERATURE_EVENT_INT_IRQ); +} + +void dmc0_failed_access_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC0 failed access interrupt!\n"); + dmc620_handle_interrupt(0); + fwk_interrupt_clear_pending(DMCS0_FAILED_ACCESS_INT_IRQ); +} + +void dmc0_mgr_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC0 mgr interrupt!\n"); + dmc620_handle_interrupt(0); + fwk_interrupt_clear_pending(DMCS0_MGR_INT_IRQ); +} + +void dmc1_misc_oflow_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC1 MISC overflow interrupt!\n"); + dmc620_handle_interrupt(1); + fwk_interrupt_clear_pending(DMCS1_MISC_OFLOW_IRQ); +} + +void dmc1_err_oflow_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC1 error overflow interrupt!\n"); + dmc620_handle_interrupt(1); + fwk_interrupt_clear_pending(DMCS1_ERR_OFLOW_IRQ); +} + +void dmc1_ecc_err_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC1 ECC error interrupt!\n"); + dmc620_handle_interrupt(1); + fwk_interrupt_clear_pending(DMCS1_ECC_ERR_INT_IRQ); +} + +void dmc1_misc_access_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC1 misc access interrupt!\n"); + dmc620_handle_interrupt(1); + fwk_interrupt_clear_pending(DMCS1_MISC_ACCESS_INT_IRQ); +} + +void dmc1_temp_event_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC1 temperature event interrupt!\n"); + dmc620_handle_interrupt(1); + fwk_interrupt_clear_pending(DMCS1_TEMPERATURE_EVENT_INT_IRQ); +} + +void dmc1_failed_access_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC1 failed access interrupt!\n"); + dmc620_handle_interrupt(1); + fwk_interrupt_clear_pending(DMCS1_FAILED_ACCESS_INT_IRQ); +} + +void dmc1_mgr_handler(void) +{ + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] DMC1 mgr interrupt!\n"); + dmc620_handle_interrupt(1); + fwk_interrupt_clear_pending(DMCS1_MGR_INT_IRQ); +} + +static int dmc620_config_interrupt(fwk_id_t ddr_id) +{ + int id; + + id = fwk_id_get_element_idx(ddr_id); + log_api->log(MOD_LOG_GROUP_INFO, + "[DDR] Configuring interrupts for DMC%d\n", id); + + if (id == 0) { + fwk_interrupt_set_isr(DMCS0_MISC_OFLOW_IRQ, dmc0_misc_oflow_handler); + fwk_interrupt_set_isr(DMCS0_ERR_OFLOW_IRQ, dmc0_err_oflow_handler); + fwk_interrupt_set_isr(DMCS0_ECC_ERR_INT_IRQ, dmc0_ecc_err_handler); + fwk_interrupt_set_isr(DMCS0_MISC_ACCESS_INT_IRQ, + dmc0_misc_access_handler); + fwk_interrupt_set_isr(DMCS0_TEMPERATURE_EVENT_INT_IRQ, + dmc0_temp_event_handler); + fwk_interrupt_set_isr(DMCS0_FAILED_ACCESS_INT_IRQ, + dmc0_failed_access_handler); + fwk_interrupt_set_isr(DMCS0_MGR_INT_IRQ, dmc0_mgr_handler); + fwk_interrupt_clear_pending(DMCS0_MISC_OFLOW_IRQ); + fwk_interrupt_clear_pending(DMCS0_ERR_OFLOW_IRQ); + fwk_interrupt_clear_pending(DMCS0_ECC_ERR_INT_IRQ); + fwk_interrupt_clear_pending(DMCS0_MISC_ACCESS_INT_IRQ); + fwk_interrupt_clear_pending(DMCS0_TEMPERATURE_EVENT_INT_IRQ); + fwk_interrupt_clear_pending(DMCS0_FAILED_ACCESS_INT_IRQ); + fwk_interrupt_clear_pending(DMCS0_MGR_INT_IRQ); + fwk_interrupt_enable(DMCS0_MISC_OFLOW_IRQ); + fwk_interrupt_enable(DMCS0_ERR_OFLOW_IRQ); + fwk_interrupt_enable(DMCS0_ECC_ERR_INT_IRQ); + fwk_interrupt_enable(DMCS0_MISC_ACCESS_INT_IRQ); + fwk_interrupt_enable(DMCS0_TEMPERATURE_EVENT_INT_IRQ); + fwk_interrupt_enable(DMCS0_FAILED_ACCESS_INT_IRQ); + fwk_interrupt_enable(DMCS0_MGR_INT_IRQ); + } else if (id == 1) { + fwk_interrupt_set_isr(DMCS1_MISC_OFLOW_IRQ, dmc1_misc_oflow_handler); + fwk_interrupt_set_isr(DMCS1_ERR_OFLOW_IRQ, dmc1_err_oflow_handler); + fwk_interrupt_set_isr(DMCS1_ECC_ERR_INT_IRQ, dmc1_ecc_err_handler); + fwk_interrupt_set_isr(DMCS1_MISC_ACCESS_INT_IRQ, + dmc1_misc_access_handler); + fwk_interrupt_set_isr(DMCS1_TEMPERATURE_EVENT_INT_IRQ, + dmc1_temp_event_handler); + fwk_interrupt_set_isr(DMCS1_FAILED_ACCESS_INT_IRQ, + dmc1_failed_access_handler); + fwk_interrupt_set_isr(DMCS1_MGR_INT_IRQ, dmc1_mgr_handler); + fwk_interrupt_clear_pending(DMCS1_MISC_OFLOW_IRQ); + fwk_interrupt_clear_pending(DMCS1_ERR_OFLOW_IRQ); + fwk_interrupt_clear_pending(DMCS1_ECC_ERR_INT_IRQ); + fwk_interrupt_clear_pending(DMCS1_MISC_ACCESS_INT_IRQ); + fwk_interrupt_clear_pending(DMCS1_TEMPERATURE_EVENT_INT_IRQ); + fwk_interrupt_clear_pending(DMCS1_FAILED_ACCESS_INT_IRQ); + fwk_interrupt_clear_pending(DMCS1_MGR_INT_IRQ); + fwk_interrupt_enable(DMCS1_MISC_OFLOW_IRQ); + fwk_interrupt_enable(DMCS1_ERR_OFLOW_IRQ); + fwk_interrupt_enable(DMCS1_ECC_ERR_INT_IRQ); + fwk_interrupt_enable(DMCS1_MISC_ACCESS_INT_IRQ); + fwk_interrupt_enable(DMCS1_TEMPERATURE_EVENT_INT_IRQ); + fwk_interrupt_enable(DMCS1_FAILED_ACCESS_INT_IRQ); + fwk_interrupt_enable(DMCS1_MGR_INT_IRQ); + } else { + return FWK_E_PARAM; + } + return FWK_SUCCESS; +} diff --git a/product/n1sdp/scp_ramfw/config_ddr_phy500.c b/product/n1sdp/scp_ramfw/config_ddr_phy500.c deleted file mode 100644 index 07d94dc45e0ed4007c2d21df6d3f4ae62b78870d..0000000000000000000000000000000000000000 --- a/product/n1sdp/scp_ramfw/config_ddr_phy500.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include -#include -#include -#include - -/* Default configuration values for DDR PHY500 devices. */ -static struct mod_ddr_phy500_reg ddr_reg_val = { - .INIT_COMPLETE = 0x00000001, - .READ_DELAY = 0x00000001, - .CAPTURE_MASK = 0x00000002, - .T_CTRL_DELAY = 0x0C000000, - .T_WRLAT = 0x00000001, - .T_RDDATA_EN = 0x00001600, - .T_RDLAT = 0x00000011, - .DFI_LP_ACK = 0x00030000, - .DFI_WR_PREMBL = 0x00000001, - .DELAY_SEL = 0x0000000D, - .REF_EN = 0x00000000, - .T_CTRL_UPD_MIN = 0x00000000, -}; - -/* Table of DDR PHY500 element descriptions. */ -static struct fwk_element ddr_phy500_element_table[] = { - [0] = { .name = "DDR_PHY500-0", - .data = &((struct mod_ddr_phy500_element_config) { - .ddr = SCP_DDR_PHY0, - }), - }, - [1] = { .name = "DDR_PHY500-1", - .data = &((struct mod_ddr_phy500_element_config) { - .ddr = SCP_DDR_PHY1, - }), - }, - [2] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *ddr_phy500_get_element_table - (fwk_id_t module_id) -{ - return ddr_phy500_element_table; -} - -/* Configuration of the DDR PHY500 module. */ -const struct fwk_module_config config_ddr_phy500 = { - .get_element_table = ddr_phy500_get_element_table, - .data = &((struct mod_ddr_phy500_module_config) { - .ddr_reg_val = &ddr_reg_val, - }), -}; diff --git a/product/n1sdp/scp_ramfw/config_dmc620.c b/product/n1sdp/scp_ramfw/config_dmc620.c deleted file mode 100644 index 9a0db87275b129b671bf333c1d3024093eb57f07..0000000000000000000000000000000000000000 --- a/product/n1sdp/scp_ramfw/config_dmc620.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -#define COL_BITS 2 -#define BANK_BITS 4 -#define RANK_BITS 1 -#define ROW_BITS 5 -#define BANK_HASH_ENABLE 1 -#define MEM_TYPE 2 -#define ADDR_DEC 0x68C -#define STRIPE_DEC 1 -#define MEM_DEVICE_WIDTH 0 -#define BANK_GROUP 3 -#define MEM_CHANNEL 2 -#define ADDRESS_CONTROL_NEXT_VAL ((BANK_HASH_ENABLE << 28) | \ - (RANK_BITS << 24) | (BANK_BITS << 16) | \ - (ROW_BITS << 8) | (COL_BITS)) -#define DECODE_CONTROL_NEXT_VAL ((ADDR_DEC << 10) | (STRIPE_DEC << 4)) -#define MEMORY_TYPE_NEXT_VAL ((BANK_GROUP << 16) | \ - (MEM_DEVICE_WIDTH << 8) | \ - (MEM_TYPE)) - -struct mod_dmc620_reg dmc_val = { - .ADDRESS_CONTROL_NEXT = ADDRESS_CONTROL_NEXT_VAL, - .DECODE_CONTROL_NEXT = DECODE_CONTROL_NEXT_VAL, - .FORMAT_CONTROL = 0x00000003, - .ADDRESS_MAP_NEXT = 0x00000002, - .LOW_POWER_CONTROL_NEXT = 0x00000010, - .TURNAROUND_CONTROL_NEXT = 0x1F0F0F0F, - .HIT_TURNAROUND_CONTROL_NEXT = 0x08909FBF, - .QOS_CLASS_CONTROL_NEXT = 0x00000FC8, - .ESCALATION_CONTROL_NEXT = 0x00080F00, - .QV_CONTROL_31_00_NEXT = 0x76543210, - .QV_CONTROL_63_32_NEXT = 0xFEDCBA98, - .RT_CONTROL_31_00_NEXT = 0x00000000, - .RT_CONTROL_63_32_NEXT = 0x00000000, - .TIMEOUT_CONTROL_NEXT = 0x00000001, - .CREDIT_CONTROL_NEXT = 0x00000F03, - .WRITE_PRIORITY_CONTROL_31_00_NEXT = 0x00000000, - .WRITE_PRIORITY_CONTROL_63_32_NEXT = 0xECA86421, - .QUEUE_THRESHOLD_CONTROL_31_00_NEXT = 0x00000008, - .QUEUE_THRESHOLD_CONTROL_63_32_NEXT = 0x00000000, - .ADDRESS_SHUTTER_31_00_NEXT = 0x11111110, - .ADDRESS_SHUTTER_63_32_NEXT = 0x11111111, - .ADDRESS_SHUTTER_95_64_NEXT = 0x11111111, - .ADDRESS_SHUTTER_127_96_NEXT = 0x11111111, - .ADDRESS_SHUTTER_159_128_NEXT = 0x11111111, - .ADDRESS_SHUTTER_191_160_NEXT = 0x11111111, - .MEMORY_ADDRESS_MAX_31_00_NEXT = 0xFFFF001F, - .MEMORY_ADDRESS_MAX_43_32_NEXT = 0x00000FFF, - .ACCESS_ADDRESS_NEXT = { - [0] = {.MIN_31_00 = 0x0000000F, .MIN_43_32 = 0x00000000}, - [1] = {.MIN_31_00 = 0x0000000F, .MIN_43_32 = 0x00000000}, - [2] = {.MIN_31_00 = 0x0000000F}, - [3] = {.MIN_31_00 = 0x0000000F}, - [4] = {.MIN_31_00 = 0x0000000F}, - [5] = {.MIN_31_00 = 0x0000000F}, - [6] = {.MIN_31_00 = 0x0000000F}, - [7] = {.MIN_31_00 = 0x0000000F}, - }, - .DCI_REPLAY_TYPE_NEXT = 0x00000000, - .DCI_STRB = 0x00000007, - .DCI_DATA = 0x00000000, - .REFRESH_CONTROL_NEXT = 0x00000000, - .MEMORY_TYPE_NEXT = MEMORY_TYPE_NEXT_VAL, - .FEATURE_CONFIG = 0x00001800, - .FEATURE_CONTROL_NEXT = 0x00000000, - .MUX_CONTROL_NEXT = 0x00000000, - .T_REFI_NEXT = 0x90000618, - .T_RFC_NEXT = 0x06A8C230, - .T_MRR_NEXT = 0x00000001, - .T_MRW_NEXT = 0x00010018, - .T_RCD_NEXT = 0x00000014, - .T_RAS_NEXT = 0x00000034, - .T_RP_NEXT = 0x00000014, - .T_RPALL_NEXT = 0x00000014, - .T_RRD_NEXT = 0x04000805, - .T_ACT_WINDOW_NEXT = 0x00001010, - .T_RTR_NEXT = 0x14060804, - .T_RTW_NEXT = 0x000A0A0A, - .T_RTP_NEXT = 0x0000000C, - .T_WR_NEXT = 0x0000002C, - .T_WTR_NEXT = 0x00022019, - .T_WTW_NEXT = 0x14060804, - .T_XMPD_NEXT = 0x00000510, - .T_EP_NEXT = 0x00000008, - .T_XP_NEXT = 0x0014000A, - .T_ESR_NEXT = 0x00000009, - .T_XSR_NEXT = 0x04000110, - .T_ESRCK_NEXT = 0x00000010, - .T_CKXSR_NEXT = 0x00000010, - .T_CMD_NEXT = 0x00000000, - .T_PARITY_NEXT = 0x00001600, - .T_ZQCS_NEXT = 0x00000090, - .T_RW_ODT_CLR_NEXT = 0x0000005E, - .T_RDDATA_EN_NEXT = 0x00000000, - .T_PHYWRLAT_NEXT = 0x001F000E, - .T_PHYRDLAT_NEXT = 0x0000002E, - .RDLVL_CONTROL_NEXT = 0x00000000, - .RDLVL_MRS_NEXT = 0x00000424, - .T_RDLVL_EN_NEXT = 0x00000001, - .T_RDLVL_RR_NEXT = 0x0000001A, - .WRLVL_CONTROL_NEXT = 0x00100000, - .WRLVL_MRS_NEXT = 0x00000181, - .T_WRLVL_EN_NEXT = 0x00000018, - .T_WRLVL_WW_NEXT = 0x00000001, - .PHY_POWER_CONTROL_NEXT = 0x00000000, - .T_LPRESP_NEXT = 0x00000000, - .PHY_UPDATE_CONTROL_NEXT = 0x00000000, - .T_ODTH_NEXT = 0x00000006, - .ODT_TIMING_NEXT = 0x07003900, - .ODT_WR_CONTROL_31_00_NEXT = 0x08040201, - .ODT_WR_CONTROL_63_32_NEXT = 0x80402010, - .ODT_RD_CONTROL_31_00_NEXT = 0x00000000, - .ODT_RD_CONTROL_63_32_NEXT = 0x00000000, - .ERR0CTLR0 = DMC_ERR0CTRL0_ED_ENABLE | - DMC_ERR0CTRL0_DE_ENABLE | - DMC_ERR0CTRL0_UI_ENABLE | - DMC_ERR0CTRL0_FI_ENABLE | - DMC_ERR0CTRL0_CFI_ENABLE, -}; - -/* Table of DMC620 elements descriptions. */ -static struct fwk_element dmc620_element_table[] = { - [0] = { .name = "DMC620-0", - .data = &((struct mod_dmc620_element_config) { - .dmc = SCP_DMC0, - .ddr_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DDR_PHY500, 0), - .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_INTERCONNECT), - }), - }, - [1] = { .name = "DMC620-1", - .data = &((struct mod_dmc620_element_config) { - .dmc = SCP_DMC1, - .ddr_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DDR_PHY500, 1), - .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_INTERCONNECT), - }), - }, - [2] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *dmc620_get_element_table(fwk_id_t module_id) -{ - return dmc620_element_table; -} - -static void direct_ddr_cmd(struct mod_dmc620_reg *dmc) -{ - dmc->DIRECT_ADDR = 0x00000004; - dmc->DIRECT_CMD = 0x0001000A; - dmc->DIRECT_ADDR = 0x00000006; - dmc->DIRECT_CMD = 0x00030004; - dmc->DIRECT_ADDR = 0x00000000; - dmc->DIRECT_CMD = 0x0001000B; - dmc->DIRECT_ADDR = 0x00000001; - dmc->DIRECT_CMD = 0x0003000B; - dmc->DIRECT_ADDR = 0x000003E8; - dmc->DIRECT_CMD = 0x0001000D; - dmc->DIRECT_ADDR = 0x00000258; - dmc->DIRECT_CMD = 0x0001000D; - dmc->DIRECT_ADDR = 0x00010001; - dmc->DIRECT_CMD = 0x0003000B; - dmc->DIRECT_ADDR = 0x0000003C; - dmc->DIRECT_CMD = 0x0001000D; - dmc->DIRECT_ADDR = 0x00000000; - dmc->DIRECT_CMD = 0x00030000; - dmc->DIRECT_ADDR = 0x0000003C; - dmc->DIRECT_ADDR = 0x00000420; - dmc->DIRECT_CMD = 0x00030301; - dmc->DIRECT_ADDR = 0x00001000; - dmc->DIRECT_CMD = 0x00030601; - dmc->DIRECT_ADDR = 0x00000600; - dmc->DIRECT_CMD = 0x00030501; - dmc->DIRECT_ADDR = 0x00000000; - dmc->DIRECT_CMD = 0x30030401; - dmc->DIRECT_ADDR = 0x00000028; - dmc->DIRECT_CMD = 0x00030201; - dmc->DIRECT_ADDR = 0x00000001; - dmc->DIRECT_CMD = 0x00030101; - dmc->DIRECT_ADDR = 0x00000D50; - dmc->DIRECT_CMD = 0x00030001; - dmc->DIRECT_ADDR = 0x000003F6; - dmc->DIRECT_CMD = 0x0001000D; - dmc->DIRECT_ADDR = 0x0000000A; - dmc->DIRECT_CMD = 0x0001000D; - dmc->DIRECT_ADDR = 0x00000400; - dmc->DIRECT_CMD = 0x00030005; - dmc->DIRECT_ADDR = 0x000003FF; - dmc->DIRECT_CMD = 0x0001000D; - -} - -/* Configuration of the DMC620 module. */ -const struct fwk_module_config config_dmc620 = { - .get_element_table = dmc620_get_element_table, - .data = &((struct mod_dmc620_module_config) { - .dmc_val = &dmc_val, - .ddr_module_id = FWK_ID_MODULE_INIT( - FWK_MODULE_IDX_DDR_PHY500), - .ddr_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_DDR_PHY500, - 0), - .direct_ddr_cmd = direct_ddr_cmd, - }), -}; diff --git a/product/n1sdp/scp_ramfw/config_n1sdp_ddr_phy.c b/product/n1sdp/scp_ramfw/config_n1sdp_ddr_phy.c new file mode 100644 index 0000000000000000000000000000000000000000..e323a35e5a11a707e3ae2fa714ac2de98880435d --- /dev/null +++ b/product/n1sdp/scp_ramfw/config_n1sdp_ddr_phy.c @@ -0,0 +1,38 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#include + +/* Table of N1SDP DDR PHY element descriptions. */ +static struct fwk_element n1sdp_ddr_phy_element_table[] = { + [0] = { .name = "DDR_PHY-0", + .data = &((struct mod_n1sdp_ddr_phy_element_config) { + .ddr = SCP_DDR_PHY0, + }), + }, + [1] = { .name = "DDR_PHY-1", + .data = &((struct mod_n1sdp_ddr_phy_element_config) { + .ddr = SCP_DDR_PHY1, + }), + }, + [2] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *n1sdp_ddr_phy_get_element_table + (fwk_id_t module_id) +{ + return n1sdp_ddr_phy_element_table; +} + +/* Configuration of the N1SDP DDR PHY module. */ +const struct fwk_module_config config_n1sdp_ddr_phy = { + .get_element_table = n1sdp_ddr_phy_get_element_table, +}; diff --git a/product/n1sdp/scp_ramfw/config_n1sdp_dmc620.c b/product/n1sdp/scp_ramfw/config_n1sdp_dmc620.c new file mode 100644 index 0000000000000000000000000000000000000000..a85fc7237bb013539c7f126c11cbaf989f60d9d4 --- /dev/null +++ b/product/n1sdp/scp_ramfw/config_n1sdp_dmc620.c @@ -0,0 +1,52 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Table of DMC620 elements descriptions. */ +static struct fwk_element dmc620_element_table[] = { + [0] = { .name = "DMC620-0", + .data = &((struct mod_dmc620_element_config) { + .dmc = SCP_DMC0, + .ddr_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_N1SDP_DDR_PHY, 0), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + }), + }, + [1] = { .name = "DMC620-1", + .data = &((struct mod_dmc620_element_config) { + .dmc = SCP_DMC1, + .ddr_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_N1SDP_DDR_PHY, 1), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + }), + }, + [2] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *dmc620_get_element_table(fwk_id_t module_id) +{ + return dmc620_element_table; +} + +/* Configuration of the DMC620 module. */ +const struct fwk_module_config config_n1sdp_dmc620 = { + .get_element_table = dmc620_get_element_table, + .data = &((struct mod_dmc620_module_config) { + .ddr_module_id = FWK_ID_MODULE_INIT( + FWK_MODULE_IDX_N1SDP_DDR_PHY), + .ddr_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_N1SDP_DDR_PHY, + 0), + }), +}; diff --git a/product/n1sdp/scp_ramfw/firmware.mk b/product/n1sdp/scp_ramfw/firmware.mk index e395547e2808656a53a66c572c99aba992599f8b..25b7b1fef4423c12b43931e4f30a4312e35970d0 100644 --- a/product/n1sdp/scp_ramfw/firmware.mk +++ b/product/n1sdp/scp_ramfw/firmware.mk @@ -24,8 +24,8 @@ BS_FIRMWARE_MODULES := \ ppu_v0 \ system_power \ n1sdp_pll \ - dmc620 \ - ddr_phy500 \ + n1sdp_dmc620 \ + n1sdp_ddr_phy \ mhu \ smt \ scmi \ @@ -54,8 +54,8 @@ BS_FIRMWARE_SOURCES := \ config_power_domain.c \ config_ppu_v0.c \ config_ppu_v1.c \ - config_dmc620.c \ - config_ddr_phy500.c \ + config_n1sdp_dmc620.c \ + config_n1sdp_ddr_phy.c \ config_mhu.c \ config_smt.c \ config_scmi.c \