From a72498dc26a0b830fed45e59a3eb8861a285079e Mon Sep 17 00:00:00 2001 From: sah01 Date: Tue, 28 Sep 2021 06:45:13 +0000 Subject: [PATCH 01/41] morello: Introduce trusted board boot In current boot flow, the SCP RAM firmware copies TF-BL31 from SCP QSPI memory to SRAM, and the AP core starts the execution from it. With TBBR boot flow enabled SCP RAM firmware will point the AP RVBAR to 0x0 and AP core starts execution from AP ROM code instead. This patch sets AP RVBAR to the address pointed to by SCC BOOT_GPR2 and BOOT_GPR3 registers. The default value of BOOT_GPR2 & BOOT_GPR3 registers is 0 making AP cores to boot from on-chip AP ROM firmware. BOOT_GPR2/3 registers can be modified in motherboard configuration files to let AP cores boot custom firmware images loaded in any valid memory region. This patch also removes BL33 info SDS structure as it is no longer needed with the TBBR based boot. Signed-off-by: sahil Change-Id: If151aa0e867b7e8b7b54b61d0e73b431b9fde31c --- product/morello/include/morello_sds.h | 3 - .../include/mod_morello_system.h | 21 --- .../morello_system/src/mod_morello_system.c | 140 ++---------------- product/morello/scp_ramfw_fvp/config_sds.c | 9 -- 4 files changed, 13 insertions(+), 160 deletions(-) diff --git a/product/morello/include/morello_sds.h b/product/morello/include/morello_sds.h index 04b4aabf2..f025f705f 100644 --- a/product/morello/include/morello_sds.h +++ b/product/morello/include/morello_sds.h @@ -24,7 +24,6 @@ enum morello_sds_struct_id { MORELLO_SDS_CPU_BOOTCTR = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), MORELLO_SDS_CPU_FLAGS = 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), MORELLO_SDS_PLATFORM_INFO = 8 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), - MORELLO_SDS_BL33_INFO = 9 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), }; enum morello_sds_region_idx { @@ -46,7 +45,6 @@ enum morello_sds_region_idx { #define MORELLO_SDS_CPU_BOOTCTR_SIZE 256 #define MORELLO_SDS_CPU_FLAGS_SIZE 256 #define MORELLO_SDS_PLATFORM_INFO_SIZE 18 -#define MORELLO_SDS_BL33_INFO_SIZE 12 /* * Field masks and offsets for the MORELLO_SDS_AP_CPU_INFO structure. @@ -80,5 +78,4 @@ struct morello_sds_platid { */ #define SDS_ELEMENT_IDX_FEATURE_AVAILABILITY 3 #define SDS_ELEMENT_IDX_PLATFORM_INFO 4 -#define SDS_ELEMENT_IDX_BL33_INFO 5 #endif /* MORELLO_SDS_H */ diff --git a/product/morello/module/morello_system/include/mod_morello_system.h b/product/morello/module/morello_system/include/mod_morello_system.h index fab9e7338..50160d44f 100644 --- a/product/morello/module/morello_system/include/mod_morello_system.h +++ b/product/morello/module/morello_system/include/mod_morello_system.h @@ -25,33 +25,12 @@ * \brief MORELLO system macro definitions. */ -/*! - * MORELLO AP cores do not have internal ROM memory to boot code once they are - * released from reset. It is the responsibility of SCP to copy the AP - * firmware to internal/external memory and set the RVBAR register of the - * AP cores to corresponding memory's base address and then switch ON - * the PPU of primary core to release from reset. This macro specifies the - * base address of the Trusted AP SRAM to which AP firmware will be copied - * to and therefore the value to set in the RVBAR of all AP cores. - */ - /*! Offset of the Trusted SRAM between AP and SCP Address Space*/ #define AP_SCP_SRAM_OFFSET UINT32_C(0xA0000000) -/*! AP Cores Reset Address in SCP Address Space */ -#define AP_CORE_RESET_ADDR UINT32_C(0xA4040000) - /*! Address translation enable bit */ #define ADDR_TRANS_EN UINT32_C(0x1) -/*! Source address of BL33 image to be used by BL31 */ -#define BL33_SRC_BASE_ADDR UINT32_C(0x14200000) - -/*! Destination address of BL33 image to be used by BL31 */ -#define BL33_DST_BASE_ADDR UINT32_C(0xE0000000) - -/*! Size of BL33 image to be used by BL31 */ -#define BL33_SIZE UINT32_C(0x00200000) /*! * Offset of NIC-400 security 0 register for diff --git a/product/morello/module/morello_system/src/mod_morello_system.c b/product/morello/module/morello_system/src/mod_morello_system.c index e9845cc72..b974f0ad8 100644 --- a/product/morello/module/morello_system/src/mod_morello_system.c +++ b/product/morello/module/morello_system/src/mod_morello_system.c @@ -21,7 +21,6 @@ #include #include -#include #include #include #include @@ -62,18 +61,6 @@ struct FWK_PACKED morello_platform_info { bool multichip_mode; }; -/* - * BL33 image information structure used by BL31 - */ -struct morello_bl33_info { - /* Source address of BL33 image */ - uint32_t bl33_src_addr; - /* Load address of BL33 image */ - uint32_t bl33_dst_addr; - /* BL33 image size */ - uint32_t bl33_size; -}; - /* MultiChip information */ struct morello_multichip_info { /* If multichip mode */ @@ -113,11 +100,6 @@ static struct morello_platform_info sds_platform_info; static fwk_id_t sds_platform_info_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, SDS_ELEMENT_IDX_PLATFORM_INFO); -/* SDS BL33 image information */ -static struct morello_bl33_info sds_bl33_info; -static fwk_id_t sds_bl33_info_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, SDS_ELEMENT_IDX_BL33_INFO); - /* Module context */ struct morello_system_ctx { /* Pointer to the Interrupt Service Routine API of the PPU_V1 module */ @@ -126,9 +108,6 @@ struct morello_system_ctx { /* Power domain module restricted API pointer */ struct mod_pd_restricted_api *mod_pd_restricted_api; - /* Pointer to FIP APIs */ - const struct mod_fip_api *fip_api; - /* Pointer to DMC Bing memory information API */ const struct mod_dmc_bing_mem_info_api *dmc_bing_api; @@ -241,28 +220,6 @@ struct mod_morello_system_ap_memory_access_api .disable_ap_memory_access = morello_system_disable_ap_memory_access, }; -/* - * Function to copy into AP SRAM. - */ -static int morello_system_copy_to_ap_sram( - uint32_t sram_address, - const void *spi_address, - uint32_t size) -{ - memcpy((void *)sram_address, spi_address, size); - - if (memcmp((void *)sram_address, spi_address, size) != 0) { - FWK_LOG_INFO( - "[MORELLO SYSTEM] Copy failed at destination address: 0x%" PRIX32, - sram_address); - return FWK_E_DATA; - } - FWK_LOG_INFO( - "[MORELLO SYSTEM] Copied binary to SRAM address: 0x%08" PRIX32, - sram_address); - return FWK_SUCCESS; -} - void cdbg_pwrupreq_handler(void) { FWK_LOG_INFO("[MORELLO SYSTEM] Received debug power up request interrupt"); @@ -318,21 +275,6 @@ static int morello_system_fill_platform_info(void) sds_structure_desc->size); } -static int morello_system_fill_bl33_info(void) -{ - const struct mod_sds_structure_desc *sds_structure_desc = - fwk_module_get_data(sds_bl33_info_id); - - sds_bl33_info.bl33_src_addr = BL33_SRC_BASE_ADDR; - sds_bl33_info.bl33_dst_addr = BL33_DST_BASE_ADDR; - sds_bl33_info.bl33_size = BL33_SIZE; - return morello_system_ctx.sds_api->struct_write( - sds_structure_desc->id, - 0, - (void *)(&sds_bl33_info), - sds_structure_desc->size); -} - /* * Initialize primary core during system initialization */ @@ -343,29 +285,12 @@ static int morello_system_init_primary_core(void) unsigned int core_idx; unsigned int cluster_idx; unsigned int cluster_count; - uint32_t rvbar_low; - uint32_t rvbar_high; - uintptr_t fip_base; - size_t fip_size; - - /* - * SCC BOOT_GPR2 & BOOT_GPR3 registers are used to set user specific - * RVBAR addresses. If both registers are set to 0 then a fixed trusted - * SRAM based is used. - */ - if ((SCC->BOOT_GPR2 == 0) && (SCC->BOOT_GPR3 == 0)) { - rvbar_low = (AP_CORE_RESET_ADDR - AP_SCP_SRAM_OFFSET); - rvbar_high = 0; - } else { - rvbar_low = SCC->BOOT_GPR2; - rvbar_high = SCC->BOOT_GPR3; - } FWK_LOG_INFO( "[MORELLO SYSTEM] Setting AP Reset Address to 0x%08" PRIX32 "%08" PRIX32, - rvbar_high, - rvbar_low); + SCC->BOOT_GPR3, + SCC->BOOT_GPR2); cluster_count = morello_core_get_cluster_count(); for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { @@ -373,60 +298,28 @@ static int morello_system_init_primary_core(void) core_idx < morello_core_get_core_per_cluster_count(cluster_idx); core_idx++) { PIK_CLUSTER(cluster_idx)->STATIC_CONFIG[core_idx].RVBARADDR_LW = - rvbar_low; + SCC->BOOT_GPR2; PIK_CLUSTER(cluster_idx)->STATIC_CONFIG[core_idx].RVBARADDR_UP = - rvbar_high; + SCC->BOOT_GPR3; } } if (morello_get_chipid() == 0x0) { - struct mod_fip_entry_data entry; - if (SCC->BOOT_GPR0 != 0x0) { - fip_base = SCC->BOOT_GPR0; - /* Assume maximum size limit */ - fip_size = 0xFFFFFFFF; - } else { - fip_base = SCP_QSPI_FLASH_BASE_ADDR; - fip_size = SCP_QSPI_FLASH_SIZE; - } - - status = morello_system_ctx.fip_api->get_entry( - MOD_FIP_TOC_ENTRY_TFA_BL31, &entry, fip_base, fip_size); - if (status != FWK_SUCCESS) { - FWK_LOG_INFO( - "[MORELLO SYSTEM] Failed to locate AP TF_BL31, error: %d\n", - status); - return FWK_E_PANIC; - } - - FWK_LOG_INFO("[MORELLO SYSTEM] Located AP TF_BL31:\n"); - FWK_LOG_INFO("[MORELLO SYSTEM] address: %p\n", entry.base); - FWK_LOG_INFO("[MORELLO SYSTEM] size : %u\n", entry.size); - FWK_LOG_INFO( - "[MORELLO SYSTEM] flags : 0x%08" PRIX32 "%08" PRIX32 "\n", - (uint32_t)(entry.flags >> 32), - (uint32_t)entry.flags); - FWK_LOG_INFO( - "[MORELLO SYSTEM] Copying AP TF_BL31 to address 0x%" PRIX32 "...\n", - AP_CORE_RESET_ADDR); - - status = morello_system_copy_to_ap_sram( - AP_CORE_RESET_ADDR, entry.base, entry.size); - if (status != FWK_SUCCESS) - return FWK_E_PANIC; - - /* Fill BL33 image information structure */ - FWK_LOG_INFO("[MORELLO SYSTEM] Filling BL33 information..."); - status = morello_system_fill_bl33_info(); - if (status != FWK_SUCCESS) - return status; - /* Fill Platform information structure */ FWK_LOG_INFO("[MORELLO SYSTEM] Collecting Platform information..."); status = morello_system_fill_platform_info(); if (status != FWK_SUCCESS) return status; + /* + * At the moment, DPU ACLK is not hooked to SCMI Clock protocol due to + * an issue with clock dividier configuration. + * As such, hard-coding the dividers here until SCMI Clock comms + * is fixed to work with DPU ALCK. + */ + PIK_DPU->ACLKDP_DIV1 = 0; + PIK_DPU->ACLKDP_DIV2 = 0; + /* Enable non-secure CoreSight debug access */ FWK_LOG_INFO( "[MORELLO SYSTEM] Enabling CoreSight debug non-secure access"); @@ -501,13 +394,6 @@ static int morello_system_bind(fwk_id_t id, unsigned int round) if (round > 0) return FWK_SUCCESS; - status = fwk_module_bind( - FWK_ID_MODULE(FWK_MODULE_IDX_FIP), - FWK_ID_API(FWK_MODULE_IDX_FIP, 0), - &morello_system_ctx.fip_api); - if (status != FWK_SUCCESS) - return status; - status = fwk_module_bind( FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), diff --git a/product/morello/scp_ramfw_fvp/config_sds.c b/product/morello/scp_ramfw_fvp/config_sds.c index 2511227a8..ebb7aa2fb 100644 --- a/product/morello/scp_ramfw_fvp/config_sds.c +++ b/product/morello/scp_ramfw_fvp/config_sds.c @@ -102,15 +102,6 @@ static struct fwk_element sds_element_table[] = { .finalize = true, }), }, - { - .name = "BL33 Image Info", - .data = &((struct mod_sds_structure_desc){ - .id = MORELLO_SDS_BL33_INFO, - .size = MORELLO_SDS_BL33_INFO_SIZE, - .region_id = MORELLO_SDS_REGION_SECURE, - .finalize = true, - }), - }, #ifdef BUILD_MODE_DEBUG { .name = "Boot Counters", -- GitLab From 8c10a7af3bc24e1a64edfdacff0dbb2c89aca729 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 15:59:50 +0100 Subject: [PATCH 02/41] morello: fix MCP alternate boot base address The alternate base address of MCP QSPI Flash was incorrectly specified to be 0x80_0000. Change it to reflect the correct address, which is 0x84_0000. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: If5460cc929ca83a512889613d26470d65f7b981f --- product/morello/include/morello_mcp_system_mmap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/product/morello/include/morello_mcp_system_mmap.h b/product/morello/include/morello_mcp_system_mmap.h index 7501075e7..fb8c1c5e2 100644 --- a/product/morello/include/morello_mcp_system_mmap.h +++ b/product/morello/include/morello_mcp_system_mmap.h @@ -11,8 +11,8 @@ /* * External QSPI flash memory - mapped address */ -#define MCP_QSPI_FLASH_BASE_ADDR 0x30000000 -#define MCP_QSPI_FLASH_BASE_ADDR_ALT 0x00800000 +#define MCP_QSPI_FLASH_BASE_ADDR 0x30000000 +#define MCP_QSPI_FLASH_BASE_ADDR_ALT 0x00840000 #define MCP_QSPI_FLASH_SIZE 0x02000000 /* -- GitLab From 9bdc1554761b914aa4dca44cf021a808af24b19c Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 03/41] morello: add PLAT_FVP build macro Introduce PLAT_FVP build macro in order to conditionally compile either the FVP-specific or the forthcoming SoC-specific code within the product modules common to both. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I64bccb03968116502ab75290b6b8cabf1cafb6fb --- product/morello/scp_ramfw_fvp/Firmware.cmake | 4 +++- product/morello/scp_ramfw_fvp/firmware.mk | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/product/morello/scp_ramfw_fvp/Firmware.cmake b/product/morello/scp_ramfw_fvp/Firmware.cmake index aec39a32e..9570e85f3 100644 --- a/product/morello/scp_ramfw_fvp/Firmware.cmake +++ b/product/morello/scp_ramfw_fvp/Firmware.cmake @@ -27,11 +27,13 @@ set(SCP_ENABLE_IPO_INIT FALSE) set(SCP_ENABLE_DEBUGGER_INIT FALSE) +set(SCP_ENABLE_PLAT_FVP TRUE) + list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../../../module/fip") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_pll") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/dmc_bing") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_system") -list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/dmc_bing") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/scmi_management") diff --git a/product/morello/scp_ramfw_fvp/firmware.mk b/product/morello/scp_ramfw_fvp/firmware.mk index dec24a0c4..c89998117 100644 --- a/product/morello/scp_ramfw_fvp/firmware.mk +++ b/product/morello/scp_ramfw_fvp/firmware.mk @@ -14,6 +14,9 @@ BS_FIRMWARE_USE_NEWLIB_NANO_SPECS := yes BS_FIRMWARE_MODULE_HEADERS_ONLY := \ +DEFINES += PLAT_FVP=1 +export PLAT_FVP=1 + BS_FIRMWARE_MODULES := \ armv7m_mpu \ pl011 \ -- GitLab From 78ef299735f2db3692b0a053cff763b3bd9e04ca Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 04/41] morello: add morello_pcie module This patch adds the PCIe module required for PCIe/CCIX controller programming in Morello. Co-authored-by: Jagadeesh Ujja Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I840827e8fa319d0be811f1d1ad51eca81545c873 --- .../module/morello_pcie/CMakeLists.txt | 20 + .../morello/module/morello_pcie/Module.cmake | 10 + .../include/internal/pcie_ctrl_apb_reg.h | 178 +++++ .../morello_pcie/include/mod_morello_pcie.h | 230 ++++++ .../morello/module/morello_pcie/src/Makefile | 11 + .../morello_pcie/src/mod_morello_pcie.c | 754 ++++++++++++++++++ .../module/morello_pcie/src/morello_pcie.c | 532 ++++++++++++ .../module/morello_pcie/src/morello_pcie.h | 639 +++++++++++++++ tools/cppcheck_suppress_list.txt | 1 + 9 files changed, 2375 insertions(+) create mode 100644 product/morello/module/morello_pcie/CMakeLists.txt create mode 100644 product/morello/module/morello_pcie/Module.cmake create mode 100644 product/morello/module/morello_pcie/include/internal/pcie_ctrl_apb_reg.h create mode 100644 product/morello/module/morello_pcie/include/mod_morello_pcie.h create mode 100644 product/morello/module/morello_pcie/src/Makefile create mode 100644 product/morello/module/morello_pcie/src/mod_morello_pcie.c create mode 100644 product/morello/module/morello_pcie/src/morello_pcie.c create mode 100644 product/morello/module/morello_pcie/src/morello_pcie.h diff --git a/product/morello/module/morello_pcie/CMakeLists.txt b/product/morello/module/morello_pcie/CMakeLists.txt new file mode 100644 index 000000000..d9880815b --- /dev/null +++ b/product/morello/module/morello_pcie/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_include_directories( + ${SCP_MODULE_TARGET} PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/include/internal" + "${CMAKE_CURRENT_SOURCE_DIR}/src") + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_morello_pcie.c" + "${CMAKE_CURRENT_SOURCE_DIR}/src/morello_pcie.c") + +target_link_libraries(${SCP_MODULE_TARGET} PRIVATE module-timer module-clock) diff --git a/product/morello/module/morello_pcie/Module.cmake b/product/morello/module/morello_pcie/Module.cmake new file mode 100644 index 000000000..81a935965 --- /dev/null +++ b/product/morello/module/morello_pcie/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "morello-pcie") + +set(SCP_MODULE_TARGET "module-morello-pcie") diff --git a/product/morello/module/morello_pcie/include/internal/pcie_ctrl_apb_reg.h b/product/morello/module/morello_pcie/include/internal/pcie_ctrl_apb_reg.h new file mode 100644 index 000000000..193983686 --- /dev/null +++ b/product/morello/module/morello_pcie/include/internal/pcie_ctrl_apb_reg.h @@ -0,0 +1,178 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * PCIe controller configuration registers. + */ + +#ifndef INTERNAL_PCIE_CTRL_APB_REG_H +#define INTERNAL_PCIE_CTRL_APB_REG_H + +#include + +#include + +/*! + * \brief PCIe APB register definitions + */ +struct pcie_ctrl_apb_reg { + FWK_W uint32_t RESET_CTRL; + FWK_R uint32_t RESET_STATUS; + uint8_t RESERVED0[0x1000 - 0x8]; + FWK_RW uint32_t INT_CTRL; + uint32_t RESERVED1; + uint32_t RESERVED2; + uint32_t RESERVED3; + FWK_RW uint32_t RP_CONFIG_IN; + FWK_R uint32_t RP_CONFIG_OUT; + uint32_t RESERVED4; + FWK_RW uint32_t RP_ERROR_CTRL; + FWK_R uint32_t RP_DEBUG; + FWK_RW uint32_t RP_L1_EXIT_CTRL; + FWK_R uint32_t RP_LTSSM_STATE; + FWK_R uint32_t PIPE_STATUS; + FWK_R uint32_t PM_STATUS; + uint32_t RESERVED5; + uint32_t RESERVED6; + uint32_t RESERVED7; + FWK_R uint32_t PMA_COMMON_STATUS; + FWK_R uint32_t PMA_LANE_STATUS; + uint8_t RESERVED8[0x3000 - 0x1048]; + FWK_RW uint32_t MODE_CTRL; + FWK_RW uint32_t PWR_STATE_CHANGE_CTRL; + FWK_R uint32_t VF_PWR_STATE; + FWK_RW uint32_t HOT_RESET_INT_CTRL; + FWK_RW uint32_t FLR_RESET_INT_CTRL; + FWK_RW uint32_t EP_MISC_CTRL; + FWK_R uint32_t EP_MISC_STATUS; + FWK_R uint32_t PF_TPH_STATUS; + FWK_R uint32_t VF_TPH_STATUS; + FWK_RW uint32_t CCIX_CTRL; + uint8_t RESERVED9[0xFFD0 - 0x3028]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t CID0; + FWK_R uint32_t CID1; + FWK_R uint32_t CID2; + FWK_R uint32_t CID3; +}; + +#define RESET_CTRL_PHY_REL_POS UINT32_C(0) +#define RESET_CTRL_RC_REL_POS UINT32_C(1) +#define RESET_CTRL_HOT_RESET_POS UINT32_C(3) + +#define RESET_CTRL_PHY_REL_MASK (1 << RESET_CTRL_PHY_REL_POS) +#define RESET_CTRL_RC_REL_MASK (1 << RESET_CTRL_RC_REL_POS) +#define RESET_CTRL_HOT_RESET_MASK (1 << RESET_CTRL_HOT_RESET_POS) + +#define RESET_STATUS_PLL_ST_POS UINT32_C(0) +#define RESET_STATUS_PHY_REL_ST_POS UINT32_C(1) +#define RESET_STATUS_RC_ST_POS UINT32_C(2) +#define RESET_STATUS_RC_REL_ST_POS UINT32_C(4) +#define RESET_STATUS_HOT_RESET_ST_POS UINT32_C(5) +#define RESET_STATUS_PM_ST_POS UINT32_C(6) + +#define RESET_STATUS_PLL_ST_MASK (1 << RESET_STATUS_PLL_ST_POS) +#define RESET_STATUS_PHY_REL_ST_MASK (1 << RESET_STATUS_PHY_REL_ST_POS) +#define RESET_STATUS_RC_ST_MASK (1 << RESET_STATUS_RC_ST_POS) +#define RESET_STATUS_RC_REL_ST_MASK (1 << RESET_STATUS_RC_REL_ST_POS) +#define RESET_STATUS_HOT_RESET_ST_MASK (1 << RESET_STATUS_HOT_RESET_ST_POS) +#define RESET_STATUS_PM_ST_MASK (1 << RESET_STATUS_PM_ST_POS) + +#define INT_CTRL_NEGOTIATED_SPD_IRQ_EN_POS UINT32_C(0) +#define INT_CTRL_LINK_TRNG_DONE_IRQ_EN_POS UINT32_C(1) +#define INT_CTRL_PLL_STATUS_IRQ_EN_POS UINT32_C(2) + +#define INT_CTRL_NEGOTIATED_SPD_IRQ_EN_MASK \ + (1 << INT_CTRL_NEGOTIATED_SPD_IRQ_EN_POS) +#define INT_CTRL_LINK_TRNG_DONE_IRQ_EN_MASK \ + (1 << INT_CTRL_LINK_TRNG_DONE_IRQ_EN_POS) +#define INT_CTRL_PLL_STATUS_IRQ_EN_MASK (1 << INT_CTRL_PLL_STATUS_IRQ_EN_POS) + +#define RP_CONFIG_IN_CLIENT_REQ_EXIT_L2_POS UINT32_C(0) +#define RP_CONFIG_IN_LINK_TRNG_EN_POS UINT32_C(1) +#define RP_CONFIG_IN_ARI_EN_POS UINT32_C(2) +#define RP_CONFIG_IN_LANE_CNT_IN_POS UINT32_C(3) +#define RP_CONFIG_IN_PCIE_GEN_SEL_POS UINT32_C(6) +#define RP_CONFIG_IN_SR_IOV_EN_POS UINT32_C(8) +#define RP_CONFIG_IN_GEN3_DC_BAL_DIS_POS UINT32_C(9) +#define RP_CONFIG_IN_SRIS_EN_POS UINT32_C(10) +#define RP_CONFIG_IN_PMA_CMN_EXT_REFCLK_DET_POS UINT32_C(11) +#define RP_CONFIG_IN_PMA_CMN_EXT_REFCLK_TERMEN_POS UINT32_C(12) +#define RP_CONFIG_IN_NON_POSTED_REJ_POS UINT32_C(13) + +#define RP_CONFIG_IN_CLIENT_REQ_EXIT_L2_MASK \ + (1 << RP_CONFIG_IN_CLIENT_REQ_EXIT_L2_POS) +#define RP_CONFIG_IN_LINK_TRNG_EN_MASK (1 << RP_CONFIG_IN_LINK_TRNG_EN_POS) +#define RP_CONFIG_IN_ARI_EN_MASK (1 << RP_CONFIG_IN_ARI_EN_POS) +#define RP_CONFIG_IN_LANE_CNT_IN_MASK (0x7 << RP_CONFIG_IN_LANE_CNT_IN_POS) +#define RP_CONFIG_IN_PCIE_GEN_SEL_MASK (0x3 << RP_CONFIG_IN_PCIE_GEN_SEL_POS) +#define RP_CONFIG_IN_SR_IOV_EN_MASK (1 << RP_CONFIG_IN_SR_IOV_EN_POS) +#define RP_CONFIG_IN_GEN3_DC_BAL_DIS_MASK \ + (1 << RP_CONFIG_IN_GEN3_DC_BAL_DIS_POS) +#define RP_CONFIG_IN_SRIS_EN_MASK (1 << RP_CONFIG_IN_SRIS_EN_POS) +#define RP_CONFIG_IN_PMA_CMN_EXT_REFCLK_DET_MASK \ + (1 << RP_CONFIG_IN_PMA_CMN_EXT_REFCLK_DET_POS) +#define RP_CONFIG_IN_PMA_CMN_EXT_REFCLK_TERMEN_MASK \ + (1 << RP_CONFIG_IN_PMA_CMN_EXT_REFCLK_TERMEN_POS) +#define RP_CONFIG_IN_NON_POSTED_REJ_MASK (1 << RP_CONFIG_IN_NON_POSTED_REJ_POS) + +#define RP_CONFIG_OUT_OBFF_EN_POS UINT32_C(0) +#define RP_CONFIG_OUT_RCB_STATUS_POS UINT32_C(2) +#define RP_CONFIG_OUT_MAX_PAYLOAD_SIZE_POS UINT32_C(3) +#define RP_CONFIG_OUT_MAX_READREQ_SIZE_POS UINT32_C(6) +#define RP_CONFIG_OUT_LINK_PWR_STATE_POS UINT32_C(9) +#define RP_CONFIG_OUT_FN_PWR_STATE_POS UINT32_C(16) +#define RP_CONFIG_OUT_NEGOTIATED_SPD_POS UINT32_C(20) +#define RP_CONFIG_OUT_NEGOTIATED_LINK_WIDTH_POS UINT32_C(22) +#define RP_CONFIG_OUT_LINK_STATUS_POS UINT32_C(25) + +#define RP_CONFIG_OUT_OBFF_EN_MASK (0x3 << RP_CONFIG_OUT_OBFF_EN_POS) +#define RP_CONFIG_OUT_RCB_STATUS_MASK (1 << RP_CONFIG_OUT_RCB_STATUS_POS) +#define RP_CONFIG_OUT_MAX_PAYLOAD_SIZE_MASK \ + (0x7 << RP_CONFIG_OUT_MAX_PAYLOAD_SIZE_POS) +#define RP_CONFIG_OUT_MAX_READREQ_SIZE_MASK \ + (0x7 << RP_CONFIG_OUT_MAX_READREQ_SIZE_POS) +#define RP_CONFIG_OUT_LINK_PWR_STATE_MASK \ + (0xF << RP_CONFIG_OUT_LINK_PWR_STATE_POS) +#define RP_CONFIG_OUT_FN_PWR_STATE_MASK (0x7 << RP_CONFIG_OUT_FN_PWR_STATE_POS) +#define RP_CONFIG_OUT_NEGOTIATED_SPD_MASK \ + (0x3 << RP_CONFIG_OUT_NEGOTIATED_SPD_POS) +#define RP_CONFIG_OUT_NEGOTIATED_LINK_WIDTH_MASK \ + (0x7 << RP_CONFIG_OUT_NEGOTIATED_LINK_WIDTH_POS) +#define RP_CONFIG_OUT_LINK_STATUS_MASK (0x3 << RP_CONFIG_OUT_LINK_STATUS_POS) + +#define RP_ERROR_CTRL_UNCORRECTABLE_ERROR_IN_POS UINT32_C(0) +#define RP_ERROR_CTRL_CORRECTABLE_ERROR_IN_POS UINT32_C(1) + +#define RP_ERROR_CTRL_UNCORRECTABLE_ERROR_IN_MASK \ + (1 << RP_ERROR_CTRL_UNCORRECTABLE_ERROR_IN_POS) +#define RP_ERROR_CTRL_CORRECTABLE_ERROR_IN_MASK \ + (1 << RP_ERROR_CTRL_CORRECTABLE_ERROR_IN_POS) + +#define RP_LTSSM_STATE_POS UINT32_C(0) +#define RP_LTSSM_STATE_MASK (0x3F << RP_LTSSM_STATE_POS) + +#define PIPE_STATUS_PIPE_RATE_POS UINT32_C(0) +#define PIPE_STATUS_PIPE_RATE_MASK (0x3 << PIPE_STATUS_PIPE_RATE_POS) + +#define PM_STATUS_L1_PM_SUBSTATE_POS UINT32_C(0) +#define PM_STATUS_L1_PM_SUBSTATE_MASK (0x7 << PM_STATUS_L1_PM_SUBSTATE_POS) + +#define MODE_CTRL_MODE_SELECT_EP UINT32_C(0) +#define MODE_CTRL_MODE_SELECT_RP UINT32_C(1) + +#define EP_MISC_CTRL_REQ_PM_L23_READY_POS UINT32_C(0) +#define EP_MISC_CTRL_CONFIG_EN_POS UINT32_C(8) + +#define EP_MISC_CTRL_REQ_PM_L23_READY_MASK \ + (0x1 << EP_MISC_CTRL_REQ_PM_L23_READY_POS) +#define EP_MISC_CTRL_CONFIG_EN_MASK (0x1 << EP_MISC_CTRL_CONFIG_EN_POS) + +#endif /* INTERNAL_PCIE_CTRL_APB_REG_H */ diff --git a/product/morello/module/morello_pcie/include/mod_morello_pcie.h b/product/morello/module/morello_pcie/include/mod_morello_pcie.h new file mode 100644 index 000000000..865b7f836 --- /dev/null +++ b/product/morello/module/morello_pcie/include/mod_morello_pcie.h @@ -0,0 +1,230 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MOD_MORELLO_PCIE_H +#define MOD_MORELLO_PCIE_H + +#include + +#include +#include + +/*! + * \addtogroup GroupMorelloModule Morello Product Modules + * @{ + */ + +/*! + * \defgroup GroupModuleMorelloPcie Morello PCIe Driver + * + * \brief Driver support for Morello PCIe Root Complex & End Point devices. + * + * \details This module provides driver support for enabling and configuring + * the PCIe peripheral either in root complex mode or in end point mode. + * + * \{ + */ + +/*! + * \brief PCIe AXI outbound region types + */ +enum ob_region_type { + PCIE_AXI_OB_REGION_TYPE_MMIO = 0x2, + PCIE_AXI_OB_REGION_TYPE_IO = 0x6, + PCIE_AXI_OB_REGION_TYPE_ECAM = 0xA, + PCIE_AXI_OB_REGION_TYPE_MSG = 0xC, + PCIE_AXI_OB_REGION_TYPE_VDM = 0xD, +}; + +/*! + * \brief PCIe AXI outbound region map descriptor + */ +struct morello_pcie_axi_ob_region_map { + /*! Base address */ + uint64_t base; + + /*! Region size in bytes */ + uint64_t size; + + /*! Region type */ + enum ob_region_type type; +}; + +/*! + * \brief Morello PCIe instance configuration + */ +struct morello_pcie_dev_config { + /*! + * Base address of the PCIe Controller. This includes the PHY configuration + * and PCIe IP level configuration registers. + */ + uintptr_t ctrl_base; + + /*! + * Base address of the PCIe functional configuration registers. This + * region includes registers for configuring the IP in both RC and + * EP modes. + */ + uintptr_t global_config_base; + + /*! Base address of the PCIe message registers. */ + uintptr_t msg_base; + + /*! + * Base address of the PCIe AXI subordinate memory region (within 32-bit + * address space). This region holds the ECAM space, MMIO32 & IO space. + */ + uint32_t axi_subordinate_base32; + + /*! + * Base address of the PCIe AXI subordinate memory region (in 64-bit address + * space). This region holds the MMIO64 space. + */ + uint64_t axi_subordinate_base64; + + /*! Identifier to indicate if the PCIe controller is CCIX capable */ + bool ccix_capable; + + /*! Table of AXI outbound region entries */ + struct morello_pcie_axi_ob_region_map *axi_ob_table; + + /*! Number of entries in the \ref axi_ob_table */ + unsigned int axi_ob_count; + + /*! Primary bus number for the RP */ + uint8_t pri_bus_num; +}; + +/*! + * \brief Module API indices + */ +enum morello_pcie_api_idx { + /*! Index of the PCIe initialization API */ + MORELLO_PCIE_API_IDX_PCIE_INIT, + + /*! Index of the CCIX config API */ + MORELLO_PCIE_API_IDX_CCIX_CONFIG, + + /*! Number of APIs */ + MORELLO_PCIE_API_COUNT +}; + +/*! + * \brief Morello PCIe initialization api + */ +struct morello_pcie_init_api { + /*! + * \brief API to power ON the PCIe controller + * + * \param id Identifier of the PCIe instance + * + * \retval ::FWK_SUCCESS The operation succeeded + * \retval ::FWK_E_PARAM Element data is NULL + * \retval ::FWK_E_TIMEOUT PCIe power on timed out + * \return One of the standard error codes for implementation-defined + * errors + */ + int (*power_on)(fwk_id_t id); + + /*! + * \brief API to initialize the PHY layer + * + * \param id Identifier of the PCIe instance + * + * \retval ::FWK_SUCCESS The operation succeeded + * \retval ::FWK_E_PARAM Element data is NULL + * \retval ::FWK_E_TIMEOUT PCIe initialisation timed out + * \return One of the standard error codes for implementation-defined + * errors + */ + int (*phy_init)(fwk_id_t id); + + /*! + * \brief API to initialize the PCIe controller + * + * \param id Identifier of the PCIe instance + * \param ep_mode Identifier to configure the controller + * in root port or endpoint mode + * + * \retval ::FWK_SUCCESS The operation succeeded + * \retval ::FWK_E_PARAM Element data is NULL + * \retval ::FWK_E_TIMEOUT PCIe Controller initialisation timed out + * \return One of the standard error codes for implementation-defined + * errors + */ + int (*controller_init)(fwk_id_t id, bool ep_mode); + + /*! + * \brief API to perform the link training process + * + * \param id Identifier of the PCIe instance + * + * \retval ::FWK_SUCCESS The operation succeeded + * \retval ::FWK_E_PARAM Element data is NULL + * \retval ::FWK_E_TIMEOUT PCIe Link training timed out + * \return One of the standard error codes for implementation-defined + * errors + */ + int (*link_training)(fwk_id_t id, bool ep_mode); + + /*! + * \brief API to setup the root complex + * + * \param id Identifier of the PCIe instance + * + * \retval ::FWK_SUCCESS The operation succeeded + * \retval ::FWK_E_PARAM Element data is NULL + * \retval ::FWK_E_DATA AXI region base not aligned with region size + * \retval ::FWK_E_RANGE Invalid AXI region + * \return One of the standard error codes for implementation-defined + * errors + */ + int (*rc_setup)(fwk_id_t id); + + /*! + * \brief API to enable Virtual Channel 1 and map to + * specified Traffic class. This API is used in multichip mode. + * + * \param id Identifier of the PCIe instance + * \param vc1_tc Traffic class to be mapped to VC1 + * + * \retval ::FWK_SUCCESS The operation succeeded + * \retval ::FWK_E_PARAM Element data is NULL or PCIe VC setup failed + * \return One of the standard error codes for implementation-defined + * errors + */ + int (*vc1_setup)(fwk_id_t id, uint8_t vc1_tc); +}; + +/*! + * \brief Morello PCIe ccix configuration api + */ +struct morello_pcie_ccix_config_api { + /*! + * \brief Enable the optimized tlp (Transaction Layer Packet) + * for the ccix root complex + * + * \param enable Enable optimized tlp (true) or disable it (false) + * and thus enable pcie compatible header + * + * \retval ::FWK_SUCCESS The operation succeeded + * \retval ::FWK_E_DATA PCIe/CCIX config data is NULL + * \return One of the standard error codes for implementation-defined + * errors + */ + int (*enable_opt_tlp)(bool enable); +}; + +/*! + * \} + */ + +/*! + * \} + */ + +#endif /* MOD_MORELLO_PCIE_H */ diff --git a/product/morello/module/morello_pcie/src/Makefile b/product/morello/module/morello_pcie/src/Makefile new file mode 100644 index 000000000..3b010f71a --- /dev/null +++ b/product/morello/module/morello_pcie/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := "Morello PCIe" +BS_LIB_SOURCES = morello_pcie.c mod_morello_pcie.c + +include $(BS_DIR)/lib.mk diff --git a/product/morello/module/morello_pcie/src/mod_morello_pcie.c b/product/morello/module/morello_pcie/src/mod_morello_pcie.c new file mode 100644 index 000000000..478dafbd7 --- /dev/null +++ b/product/morello/module/morello_pcie/src/mod_morello_pcie.c @@ -0,0 +1,754 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_core.h" +#include "morello_scc_reg.h" +#include "morello_scp_pik.h" + +#include + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * Device context + */ +struct morello_pcie_dev_ctx { + /* Pointer to PCIe device configuration */ + struct morello_pcie_dev_config *config; + + /* + * Pointer to PCIe Controller IP configuration APB registers. + * Accessible in both RC & EP modes. + */ + struct pcie_ctrl_apb_reg *ctrl_apb; + + /* + * Base address of the PCIe PHY APB registers. + * Accessible in both RC & EP modes. + */ + uintptr_t phy_apb; + + /* + * Base address of the PCIe configuration APB registers. + * Accessible in both RP & EP mode. + */ + uintptr_t rp_ep_config_apb; + + /* + * Base address of the PCIe Local Management (LM) registers. + * Accessible in both RC & EP modes. + */ + uintptr_t lm_apb; + + /* + * Base address of the AXI configuration registers for RC. + * Accessible in RC mode. + */ + uintptr_t rc_axi_config_apb; + + /* + * Base address of the AXI configuration registers for EP. + * Accessible in EP mode. + */ + uintptr_t ep_axi_config_apb; +}; + +/* + * Module context + */ +struct morello_pcie_ctx { + /* Timer module API */ + struct mod_timer_api *timer_api; + + /* Table of PCIe device contexts */ + struct morello_pcie_dev_ctx *device_ctx_table; + + /* Number of PCIe root complexes/endpoints in the system */ + unsigned int pcie_instance_count; +}; + +static struct morello_pcie_ctx pcie_ctx; + +#if FWK_LOG_LEVEL <= FWK_LOG_LEVEL_ERROR +static const char *const pcie_type[2] = { "PCIe", "CCIX" }; +#endif + +#if FWK_LOG_LEVEL <= FWK_LOG_LEVEL_INFO +static const char *const axi_ob_mmap_type_name[] = { + [PCIE_AXI_OB_REGION_TYPE_MMIO] = "MMIO", + [PCIE_AXI_OB_REGION_TYPE_IO] = "IO", + [PCIE_AXI_OB_REGION_TYPE_ECAM] = "ECAM", + [PCIE_AXI_OB_REGION_TYPE_MSG] = "MSG", + [PCIE_AXI_OB_REGION_TYPE_VDM] = "VDM", +}; +#endif + +/* + * CCIX configuration API + */ +static int morello_pcie_ccix_enable_opt_tlp(bool enable) +{ + uint32_t value; + unsigned int i; + struct morello_pcie_dev_ctx *dev_ctx = NULL; + struct morello_pcie_dev_config *config = NULL; + + for (i = 0; i <= pcie_ctx.pcie_instance_count; i++) { + dev_ctx = &pcie_ctx.device_ctx_table[i]; + if (dev_ctx->config->ccix_capable) { + config = dev_ctx->config; + break; + } + } + + if (config == NULL) { + return FWK_E_DATA; + } + + /* Configure for the optimized header or pcie compatible header*/ + if (enable) { + value = + (CCIX_CTRL_CAW | CCIX_CTRL_EN_OPT_TLP | CCIX_CTRL_CSTT_V0_V1 | + CCIX_VENDOR_ID); + } else { + value = (CCIX_CTRL_CAW | CCIX_VENDOR_ID); + } + + FWK_LOG_INFO("[CCIX] CCIX_CONTROL: 0x%" PRIX32, value); + + *(uint32_t *)(dev_ctx->lm_apb + PCIE_LM_RC_CCIX_CTRL_REG) = value; + + if (enable) { + dev_ctx->ctrl_apb->CCIX_CTRL = 0x1; + } + + return FWK_SUCCESS; +} + +static const struct morello_pcie_ccix_config_api pcie_ccix_config_api = { + .enable_opt_tlp = morello_pcie_ccix_enable_opt_tlp, +}; + +/* + * PCIe initialization APIs + */ +static int morello_pcie_power_on(fwk_id_t id) +{ + struct pcie_wait_condition_data wait_data; + struct morello_pcie_dev_ctx *dev_ctx; + int status; + unsigned int did; + + did = fwk_id_get_element_idx(id); + dev_ctx = &pcie_ctx.device_ctx_table[did]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + FWK_LOG_INFO("[%s] Powering ON controller...", pcie_type[did]); + wait_data.ctrl_apb = NULL; + if (dev_ctx->config->ccix_capable) { + SCC->AXI_OVRD_CCIX = AXI_OVRD_VAL_CCIX; + SCC->CCIX_PM_CTRL = SCC_CCIX_PM_CTRL_PWR_REQ_POS; + wait_data.stage = PCIE_INIT_STAGE_CCIX_POWER_ON; + status = pcie_ctx.timer_api->wait( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + PCIE_POWER_ON_TIMEOUT, + pcie_wait_condition, + &wait_data); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[%s] Timeout!", pcie_type[did]); + return status; + } + SCC->SYS_MAN_RESET &= ~(1 << SCC_SYS_MAN_RESET_CCIX_POS); + } else { + SCC->AXI_OVRD_PCIE = AXI_OVRD_VAL_PCIE; + SCC->PCIE_PM_CTRL = SCC_PCIE_PM_CTRL_PWR_REQ_POS; + wait_data.stage = PCIE_INIT_STAGE_PCIE_POWER_ON; + status = pcie_ctx.timer_api->wait( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + PCIE_POWER_ON_TIMEOUT, + pcie_wait_condition, + &wait_data); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[%s] Timeout!", pcie_type[did]); + return status; + } + SCC->SYS_MAN_RESET &= ~(1 << SCC_SYS_MAN_RESET_PCIE_POS); + } + FWK_LOG_INFO("[%s] Done", pcie_type[did]); + + return FWK_SUCCESS; +} + +static int morello_pcie_phy_init(fwk_id_t id) +{ + struct morello_pcie_dev_ctx *dev_ctx; + enum pcie_gen gen_speed; + int status; + unsigned int did; + enum pcie_lane_count lane_count; + + did = fwk_id_get_element_idx(id); + dev_ctx = &pcie_ctx.device_ctx_table[did]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + if (dev_ctx->config->ccix_capable) { + gen_speed = PCIE_GEN_4; + } else { + gen_speed = PCIE_GEN_3; + } + + lane_count = LAN_COUNT_IN_X_16; + + FWK_LOG_INFO("[%s] Initializing PHY...", pcie_type[did]); + + pcie_phy_init(dev_ctx->phy_apb, lane_count); + + status = pcie_init( + dev_ctx->ctrl_apb, + pcie_ctx.timer_api, + PCIE_INIT_STAGE_PHY, + gen_speed, + lane_count); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[%s] Timeout!", pcie_type[did]); + return status; + } + FWK_LOG_INFO("[%s] Done", pcie_type[did]); + + return FWK_SUCCESS; +} + +static int morello_pcie_controller_init(fwk_id_t id, bool ep_mode) +{ + struct morello_pcie_dev_ctx *dev_ctx; + enum pcie_gen gen_speed; + int status; + int did; + enum pcie_lane_count lane_count; + + did = fwk_id_get_element_idx(id); + dev_ctx = &pcie_ctx.device_ctx_table[did]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + if (dev_ctx->config->ccix_capable) { + gen_speed = PCIE_GEN_4; + } else { + gen_speed = PCIE_GEN_3; + } + + lane_count = LAN_COUNT_IN_X_16; + + if (ep_mode) { + dev_ctx->ctrl_apb->MODE_CTRL = 0x0; + dev_ctx->ctrl_apb->EP_MISC_CTRL |= 0x100; + } + + FWK_LOG_INFO( + "[%s] Initializing controller in %s mode...", + pcie_type[did], + (ep_mode ? "endpoint" : "root port")); + status = pcie_init( + dev_ctx->ctrl_apb, + pcie_ctx.timer_api, + PCIE_INIT_STAGE_CTRL, + gen_speed, + lane_count); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[%s] Timeout!", pcie_type[did]); + return status; + } + FWK_LOG_INFO("[%s] Done", pcie_type[did]); + + return FWK_SUCCESS; +} + +static int morello_pcie_link_training(fwk_id_t id, bool ep_mode) +{ + struct morello_pcie_dev_ctx *dev_ctx; + enum pcie_gen gen_speed; + uint8_t neg_config; + uint32_t reg_val; + int status; + unsigned int did; + enum pcie_lane_count lane_count; + uint32_t down_stream_tx_preset = 0; + uint32_t up_stream_tx_preset = 0; + + did = fwk_id_get_element_idx(id); + dev_ctx = &pcie_ctx.device_ctx_table[did]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + if (dev_ctx->config->ccix_capable) { + gen_speed = PCIE_GEN_4; + down_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE; + up_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE; + } else { + gen_speed = PCIE_GEN_3; + down_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE; + up_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE; + } + + lane_count = LAN_COUNT_IN_X_16; + + if (gen_speed >= PCIE_GEN_3 && !ep_mode) { + FWK_LOG_INFO( + "[%s] Setting TX Preset for GEN%d...", + pcie_type[did], + PCIE_GEN_3 + 1); + status = pcie_set_gen_tx_preset( + dev_ctx->rp_ep_config_apb, + down_stream_tx_preset, + up_stream_tx_preset, + PCIE_GEN_3); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[%s] Error!", pcie_type[did]); + return status; + } + if (gen_speed == PCIE_GEN_4) { + FWK_LOG_INFO( + "[%s] Setting TX Preset for GEN%d...", + pcie_type[did], + PCIE_GEN_4 + 1); + status = pcie_set_gen_tx_preset( + dev_ctx->rp_ep_config_apb, + down_stream_tx_preset, + up_stream_tx_preset, + PCIE_GEN_4); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[%s] Error!", pcie_type[did]); + return status; + } + } + FWK_LOG_INFO("[%s] Done", pcie_type[did]); + } + + /* Link training */ + FWK_LOG_INFO("[%s] Starting link training...", pcie_type[did]); + status = pcie_init( + dev_ctx->ctrl_apb, + pcie_ctx.timer_api, + PCIE_INIT_STAGE_LINK_TRNG, + gen_speed, + lane_count); + if (status != FWK_SUCCESS) { + FWK_LOG_INFO("[%s] Timeout!", pcie_type[did]); + return FWK_E_TIMEOUT; + } + FWK_LOG_INFO("[%s] Done", pcie_type[did]); + + (void)neg_config; + neg_config = (dev_ctx->ctrl_apb->RP_CONFIG_OUT & + RP_CONFIG_OUT_NEGOTIATED_SPD_MASK) >> + RP_CONFIG_OUT_NEGOTIATED_SPD_POS; + FWK_LOG_INFO( + "[%s] Negotiated speed: GEN%d", pcie_type[did], neg_config + 1); + + neg_config = (dev_ctx->ctrl_apb->RP_CONFIG_OUT & + RP_CONFIG_OUT_NEGOTIATED_LINK_WIDTH_MASK) >> + RP_CONFIG_OUT_NEGOTIATED_LINK_WIDTH_POS; + FWK_LOG_INFO( + "[%s] Negotiated link width: x%d", + pcie_type[did], + fwk_math_pow2(neg_config)); + + if (gen_speed == PCIE_GEN_4) { + FWK_LOG_INFO("[%s] Re-training link to GEN4 speed...", pcie_type[did]); + /* Set GEN4 as target speed */ + pcie_rp_ep_config_read_word( + dev_ctx->rp_ep_config_apb, + PCIE_LINK_CTRL_STATUS_2_OFFSET, + ®_val); + reg_val &= ~PCIE_LINK_CTRL_2_TARGET_SPEED_MASK; + reg_val |= PCIE_LINK_CTRL_2_TARGET_SPEED_GEN4; + pcie_rp_ep_config_write_word( + dev_ctx->rp_ep_config_apb, PCIE_LINK_CTRL_STATUS_2_OFFSET, reg_val); + + /* Start link retraining */ + status = pcie_link_retrain( + dev_ctx->ctrl_apb, dev_ctx->rp_ep_config_apb, pcie_ctx.timer_api); + if (status != FWK_SUCCESS) { + FWK_LOG_INFO("[%s] TIMEOUT", pcie_type[did]); + return FWK_E_TIMEOUT; + } + FWK_LOG_INFO("[%s] Done", pcie_type[did]); + + pcie_rp_ep_config_read_word( + dev_ctx->rp_ep_config_apb, PCIE_LINK_CTRL_STATUS_OFFSET, ®_val); + neg_config = (reg_val >> PCIE_LINK_CTRL_NEG_SPEED_POS) & + PCIE_LINK_CTRL_NEG_SPEED_MASK; + FWK_LOG_INFO( + "[%s] Re-negotiated speed: GEN%d", pcie_type[did], neg_config); + + neg_config = (reg_val >> PCIE_LINK_CTRL_NEG_WIDTH_POS) & + PCIE_LINK_CTRL_NEG_WIDTH_MASK; + FWK_LOG_INFO( + "[%s] Re-negotiated link width: x%d", pcie_type[did], neg_config); + } + + return FWK_SUCCESS; +} + +static int morello_pcie_rc_setup(fwk_id_t id) +{ + struct morello_pcie_axi_ob_region_map *region; + struct morello_pcie_dev_ctx *dev_ctx; + unsigned int region_idx; + int status; + unsigned int did; + + did = fwk_id_get_element_idx(id); + dev_ctx = &pcie_ctx.device_ctx_table[did]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + FWK_LOG_INFO("[%s] AXI Outbound Region Setup:", pcie_type[did]); + + for (region_idx = 0; region_idx < dev_ctx->config->axi_ob_count; + region_idx++) { + region = &dev_ctx->config->axi_ob_table[region_idx]; + FWK_LOG_INFO( + "[%s] [0x%08" PRIX32 "%08" PRIX32 " - 0x%08" PRIX32 "%08" PRIX32 + "] %s", + pcie_type[did], + (uint32_t)(region->base >> 32), + (uint32_t)region->base, + (uint32_t)((region->base + region->size - 1) >> 32), + (uint32_t)(region->base + region->size - 1), + axi_ob_mmap_type_name[region->type]); + + if ((region->base % region->size) != 0) { + FWK_LOG_ERR( + "[%s] Region base not aligned with size!", pcie_type[did]); + return FWK_E_DATA; + } + + status = axi_outbound_region_setup( + dev_ctx->rc_axi_config_apb, + region->base, + __builtin_ctz(region->size), + region_idx, + (uint8_t)region->type); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR( + "[%s] Error during region setup: %d", pcie_type[did], status); + return status; + } + } + + FWK_LOG_INFO("[%s] Setup RP classcode...", pcie_type[did]); + status = pcie_rp_ep_config_write_word( + dev_ctx->rp_ep_config_apb, + PCIE_CLASS_CODE_OFFSET, + PCIE_CLASS_CODE_PCI_BRIDGE); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("Error!"); + return status; + } + FWK_LOG_INFO("Done"); + + FWK_LOG_INFO("[%s] Setup Primary bus number...", pcie_type[did]); + *(uint32_t *)(dev_ctx->lm_apb + PCIE_LM_AXI_FEATURE_CONFIG) |= + (dev_ctx->config->pri_bus_num << 8); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("Error!"); + return status; + } + FWK_LOG_INFO("Done"); + + FWK_LOG_INFO("[%s] Enable inbound region in BAR 2...", pcie_type[did]); + status = axi_inbound_region_setup( + dev_ctx->rc_axi_config_apb, + AXI_IB_REGION_BASE, + AXI_IB_REGION_SIZE_MSB, + 2); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[%s] Error!", pcie_type[did]); + return status; + } + FWK_LOG_INFO("[%s] Done", pcie_type[did]); + + FWK_LOG_INFO("[%s] Enable Type 1 I/O configuration", pcie_type[did]); + *(uint32_t *)(dev_ctx->lm_apb + PCIE_LM_RC_BAR_CONFIG_REG) = + (TYPE1_PREF_MEM_BAR_ENABLE_MASK | TYPE1_PREF_MEM_BAR_SIZE_64BIT_MASK | + TYPE1_PREF_IO_BAR_ENABLE_MASK | TYPE1_PREF_IO_BAR_SIZE_32BIT_MASK); + + /* + * Wait until devices connected in downstream ports + * finish link training before doing bus enumeration + */ + return pcie_ctx.timer_api->delay( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), PCIE_LINK_TRAINING_TIMEOUT); +} + +static int morello_pcie_vc1_setup(fwk_id_t id, uint8_t vc1_tc) +{ + struct morello_pcie_dev_ctx *dev_ctx; + uint32_t config_base_addr; + int status; + + dev_ctx = &pcie_ctx.device_ctx_table[fwk_id_get_element_idx(id)]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + if (!dev_ctx->config->ccix_capable || (vc1_tc > 7) || (vc1_tc == 0)) { + return FWK_E_PARAM; + } + + config_base_addr = dev_ctx->rp_ep_config_apb; + + FWK_LOG_INFO( + "[CCIX] Enabling VC1 in RP 0x%" PRIX32 "...", config_base_addr); + + status = pcie_vc_setup(config_base_addr, vc1_tc); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[CCIX] Error!"); + return status; + } + FWK_LOG_INFO("[CCIX] Done"); + + /* Set max payload size to 512 */ + *(volatile uint32_t *)(config_base_addr + PCIE_DEV_CTRL_STATUS_OFFSET) |= + (0x2 << PCIE_DEV_CTRL_MAX_PAYLOAD_SHIFT); + + config_base_addr = dev_ctx->config->axi_subordinate_base32 + 0x100000; + + FWK_LOG_INFO( + "[CCIX] Enabling VC1 in EP 0x%" PRIX32 "...", config_base_addr); + + status = pcie_vc_setup(config_base_addr, vc1_tc); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[CCIX] Error!"); + return status; + } + FWK_LOG_INFO("[CCIX] Done"); + + *(volatile uint32_t *)(config_base_addr + PCIE_DEV_CTRL_STATUS_OFFSET) |= + (0x2 << PCIE_DEV_CTRL_MAX_PAYLOAD_SHIFT); + + return FWK_SUCCESS; +} + +static const struct morello_pcie_init_api pcie_init_api = { + .power_on = morello_pcie_power_on, + .phy_init = morello_pcie_phy_init, + .controller_init = morello_pcie_controller_init, + .link_training = morello_pcie_link_training, + .rc_setup = morello_pcie_rc_setup, + .vc1_setup = morello_pcie_vc1_setup, +}; + +/* + * Module functions + */ +static int morello_pcie_setup(fwk_id_t id) +{ + struct morello_pcie_dev_ctx *dev_ctx; + int status; + + dev_ctx = &pcie_ctx.device_ctx_table[fwk_id_get_element_idx(id)]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + /* PCIe controller power ON */ + status = morello_pcie_power_on(id); + if (status != FWK_SUCCESS) { + return status; + } + + /* PCIe PHY initialization */ + status = morello_pcie_phy_init(id); + if (status != FWK_SUCCESS) { + return status; + } + + /* PCIe controller initialization */ + status = morello_pcie_controller_init(id, false); + if (status != FWK_SUCCESS) { + return status; + } + + /* Link training */ + status = morello_pcie_link_training(id, false); + if (status != FWK_SUCCESS && !dev_ctx->config->ccix_capable) { + return status; + } + + /* Root Complex setup */ + status = morello_pcie_rc_setup(id); + if (status != FWK_SUCCESS) { + return status; + } + + return FWK_SUCCESS; +} + +/* + * Framework handlers + */ +static int morello_pcie_init( + fwk_id_t module_id, + unsigned int element_count, + const void *data) +{ + if (element_count == 0) { + return FWK_E_DATA; + } + + pcie_ctx.device_ctx_table = + fwk_mm_calloc(element_count, sizeof(pcie_ctx.device_ctx_table[0])); + + pcie_ctx.pcie_instance_count = element_count; + + return FWK_SUCCESS; +} + +static int morello_pcie_element_init( + fwk_id_t element_id, + unsigned int unused, + const void *data) +{ + struct morello_pcie_dev_ctx *dev_ctx; + struct morello_pcie_dev_config *config; + + if (data == NULL) { + return FWK_E_PARAM; + } + + config = (struct morello_pcie_dev_config *)data; + + dev_ctx = &pcie_ctx.device_ctx_table[fwk_id_get_element_idx(element_id)]; + if (dev_ctx == NULL) { + return FWK_E_DATA; + } + + dev_ctx->config = config; + + dev_ctx->ctrl_apb = + (struct pcie_ctrl_apb_reg *)(config->ctrl_base + APB_OFFSET_CTRL_REGS); + dev_ctx->phy_apb = config->ctrl_base + APB_OFFSET_PHY_REGS; + dev_ctx->rp_ep_config_apb = + config->global_config_base + APB_OFFSET_RP_EP_CONFIG_REGS; + dev_ctx->lm_apb = config->global_config_base + APB_OFFSET_LM_REGS; + dev_ctx->rc_axi_config_apb = + config->global_config_base + APB_OFFSET_RC_AXI_CONFIG_REGS; + dev_ctx->ep_axi_config_apb = + config->global_config_base + APB_OFFSET_EP_AXI_CONFIG_REGS; + + return FWK_SUCCESS; +} + +static int morello_pcie_bind(fwk_id_t id, unsigned int round) +{ + if ((round == 0) && fwk_id_is_type(id, FWK_ID_TYPE_MODULE)) { + return fwk_module_bind( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + FWK_ID_API(FWK_MODULE_IDX_TIMER, MOD_TIMER_API_IDX_TIMER), + &pcie_ctx.timer_api); + } + + return FWK_SUCCESS; +} + +static int morello_pcie_start(fwk_id_t id) +{ + struct morello_pcie_dev_ctx *dev_ctx; + + if (fwk_id_is_type(id, FWK_ID_TYPE_MODULE)) { + /* + * Enable AP core to access PCIe root port's + * configuration space + */ + *(volatile uint32_t *)(NIC400_SOC_GPV_BASE + 0x0C) = 0x7F; + return FWK_SUCCESS; + } + + dev_ctx = &pcie_ctx.device_ctx_table[fwk_id_get_element_idx(id)]; + if (dev_ctx == NULL) { + return FWK_E_PARAM; + } + + /* Do not initialize PCIe RP in remote chip */ + if ((!dev_ctx->config->ccix_capable) && (morello_get_chipid() != 0)) { + return FWK_SUCCESS; + } + + return fwk_notification_subscribe( + mod_clock_notification_id_state_changed, + FWK_ID_ELEMENT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT), + id); +} + +static int morello_pcie_process_bind_request( + fwk_id_t requester_id, + fwk_id_t target_id, + fwk_id_t api_id, + const void **api) +{ + int status = FWK_E_PARAM; + + switch (fwk_id_get_api_idx(api_id)) { + case MORELLO_PCIE_API_IDX_PCIE_INIT: + *api = &pcie_init_api; + status = FWK_SUCCESS; + break; + case MORELLO_PCIE_API_IDX_CCIX_CONFIG: + *api = &pcie_ccix_config_api; + status = FWK_SUCCESS; + break; + default: + break; + } + + return status; +} + +static int morello_pcie_process_notification( + const struct fwk_event *event, + struct fwk_event *resp) +{ + return morello_pcie_setup(event->target_id); +} + +const struct fwk_module module_morello_pcie = { + .type = FWK_MODULE_TYPE_DRIVER, + .api_count = (unsigned int)MORELLO_PCIE_API_COUNT, + .init = morello_pcie_init, + .element_init = morello_pcie_element_init, + .bind = morello_pcie_bind, + .start = morello_pcie_start, + .process_bind_request = morello_pcie_process_bind_request, + .process_notification = morello_pcie_process_notification, +}; diff --git a/product/morello/module/morello_pcie/src/morello_pcie.c b/product/morello/module/morello_pcie/src/morello_pcie.c new file mode 100644 index 000000000..40440e4a3 --- /dev/null +++ b/product/morello/module/morello_pcie/src/morello_pcie.c @@ -0,0 +1,532 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_scc_reg.h" +#include "morello_scp_pik.h" + +#include + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +void pcie_phy_init(uint32_t phy_apb_base, uint32_t pcie_lane_count) +{ + *((unsigned int *)(0x3000c | phy_apb_base)) = 0x00000144; + *((unsigned int *)(0x38000 | phy_apb_base)) = 0x00000040; + *((unsigned int *)(0x38014 | phy_apb_base)) = 0x00000100; + + if (pcie_lane_count == LAN_COUNT_IN_X_1) { + *((unsigned int *)(0x38038 | phy_apb_base)) = 0x0000FFFE; + *((unsigned int *)(0x3803C | phy_apb_base)) = 0x00009000; + } else if (pcie_lane_count == LAN_COUNT_IN_X_2) { + *((unsigned int *)(0x38038 | phy_apb_base)) = 0x0000FFFC; + *((unsigned int *)(0x3803C | phy_apb_base)) = 0x00009000; + } else if (pcie_lane_count == LAN_COUNT_IN_X_4) { + *((unsigned int *)(0x38038 | phy_apb_base)) = 0x0000FFF0; + *((unsigned int *)(0x3803C | phy_apb_base)) = 0x00009000; + } else if (pcie_lane_count == LAN_COUNT_IN_X_8) { + *((unsigned int *)(0x38038 | phy_apb_base)) = 0x0000FF00; + *((unsigned int *)(0x3803C | phy_apb_base)) = 0x00009000; + } else { /* LAN_COUNT_IN_X_16 */ + *((unsigned int *)(0x38038 | phy_apb_base)) = 0x00000000; + *((unsigned int *)(0x3803C | phy_apb_base)) = 0x00000000; + } + + *((unsigned int *)(0x00140 | phy_apb_base)) = 0x00008804; + *((unsigned int *)(0x00188 | phy_apb_base)) = 0x00001219; + + *((unsigned int *)(0x18008 | phy_apb_base)) = 0x000055A0; + *((unsigned int *)(0x1800c | phy_apb_base)) = 0x00006910; + *((unsigned int *)(0x18030 | phy_apb_base)) = 0x0000001D; + *((unsigned int *)(0x1812C | phy_apb_base)) = 0x00000143; + *((unsigned int *)(0x18204 | phy_apb_base)) = 0x0000813E; + *((unsigned int *)(0x18214 | phy_apb_base)) = 0x00001978; + *((unsigned int *)(0x18218 | phy_apb_base)) = 0x00000389; + *((unsigned int *)(0x18220 | phy_apb_base)) = 0x0000038C; + *((unsigned int *)(0x18238 | phy_apb_base)) = 0x00003A7A; + *((unsigned int *)(0x18244 | phy_apb_base)) = 0x0000033C; + *((unsigned int *)(0x1824C | phy_apb_base)) = 0x00000000; + *((unsigned int *)(0x18258 | phy_apb_base)) = 0x00000003; + *((unsigned int *)(0x1825C | phy_apb_base)) = 0x000022CC; + *((unsigned int *)(0x182A8 | phy_apb_base)) = 0x00007FF6; + *((unsigned int *)(0x182AC | phy_apb_base)) = 0x00007FF6; + *((unsigned int *)(0x182C0 | phy_apb_base)) = 0x00007FBF; + *((unsigned int *)(0x182C4 | phy_apb_base)) = 0x00007FBF; + *((unsigned int *)(0x182C8 | phy_apb_base)) = 0x00007FD8; + *((unsigned int *)(0x18350 | phy_apb_base)) = 0x00008C67; + *((unsigned int *)(0x18354 | phy_apb_base)) = 0x00008C67; + *((unsigned int *)(0x18378 | phy_apb_base)) = 0x00002437; + *((unsigned int *)(0x18388 | phy_apb_base)) = 0x00003C2C; + + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000000; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000203; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000001; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000403; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000002; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000603; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000003; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000803; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000004; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000A03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000005; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000C03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000006; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000E03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000007; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00000F03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000008; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001003; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000009; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001103; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000000A; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00001E06; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001203; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000000B; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001303; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000000C; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001403; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000000D; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001503; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000000E; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00002A06; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001603; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000000F; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00002D06; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001703; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000010; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00002E06; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001803; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000011; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001903; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000012; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003006; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001A03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000013; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003106; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001B03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000014; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003106; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001C03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000015; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003106; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001D03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000016; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003106; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001E03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000017; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003106; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00001F03; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000018; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003206; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002003; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x00000019; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003306; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002103; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000001A; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003606; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002203; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000001B; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003906; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002303; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000001C; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003B06; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002403; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000001D; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00003F06; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002603; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000001E; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00004306; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002803; + *((unsigned int *)(0x183A0 | phy_apb_base)) = 0x0000001F; + *((unsigned int *)(0x183A4 | phy_apb_base)) = 0x00004706; + *((unsigned int *)(0x183A8 | phy_apb_base)) = 0x00002A03; + + *((unsigned int *)(0x183D4 | phy_apb_base)) = 0x00001560; + *((unsigned int *)(0x183E0 | phy_apb_base)) = 0x00001560; + *((unsigned int *)(0x183E8 | phy_apb_base)) = 0x000000BC; + *((unsigned int *)(0x183EC | phy_apb_base)) = 0x000000A6; + *((unsigned int *)(0x183F0 | phy_apb_base)) = 0x000001B6; + *((unsigned int *)(0x183FC | phy_apb_base)) = 0x00000333; + *((unsigned int *)(0x18400 | phy_apb_base)) = 0x00000738; + *((unsigned int *)(0x18404 | phy_apb_base)) = 0x00000665; + *((unsigned int *)(0x18408 | phy_apb_base)) = 0x000009AC; + *((unsigned int *)(0x1840C | phy_apb_base)) = 0x00000888; + *((unsigned int *)(0x18410 | phy_apb_base)) = 0x00000CDD; + *((unsigned int *)(0x18414 | phy_apb_base)) = 0x00000888; + *((unsigned int *)(0x18418 | phy_apb_base)) = 0x00000CDD; + *((unsigned int *)(0x1841C | phy_apb_base)) = 0x00000888; + *((unsigned int *)(0x18420 | phy_apb_base)) = 0x00000CDD; + *((unsigned int *)(0x18424 | phy_apb_base)) = 0x00000888; + *((unsigned int *)(0x18428 | phy_apb_base)) = 0x00000CDD; + *((unsigned int *)(0x1842C | phy_apb_base)) = 0x00000599; + *((unsigned int *)(0x18430 | phy_apb_base)) = 0x00000DFE; + *((unsigned int *)(0x18438 | phy_apb_base)) = 0x00000599; + *((unsigned int *)(0x1843C | phy_apb_base)) = 0x00000DEE; + *((unsigned int *)(0x18444 | phy_apb_base)) = 0x000028FF; + *((unsigned int *)(0x1845C | phy_apb_base)) = 0x00001D3A; + *((unsigned int *)(0x18460 | phy_apb_base)) = 0x00001B36; + *((unsigned int *)(0x1846C | phy_apb_base)) = 0x0000000F; + *((unsigned int *)(0x18470 | phy_apb_base)) = 0x00000002; + *((unsigned int *)(0x18474 | phy_apb_base)) = 0x00000002; + *((unsigned int *)(0x18478 | phy_apb_base)) = 0x0000003C; + *((unsigned int *)(0x18484 | phy_apb_base)) = 0x0000001F; + *((unsigned int *)(0x18488 | phy_apb_base)) = 0x00001CE7; + *((unsigned int *)(0x1848C | phy_apb_base)) = 0x00001D67; + *((unsigned int *)(0x184A0 | phy_apb_base)) = 0x000003F4; + *((unsigned int *)(0x18530 | phy_apb_base)) = 0x00000E04; + *((unsigned int *)(0x18534 | phy_apb_base)) = 0x00000101; + *((unsigned int *)(0x18540 | phy_apb_base)) = 0x0000005A; + *((unsigned int *)(0x1854C | phy_apb_base)) = 0x00006A10; + *((unsigned int *)(0x18550 | phy_apb_base)) = 0x00000080; + *((unsigned int *)(0x18554 | phy_apb_base)) = 0x00000002; + *((unsigned int *)(0x18558 | phy_apb_base)) = 0x00000F21; + *((unsigned int *)(0x1855C | phy_apb_base)) = 0x00001F21; + *((unsigned int *)(0x18584 | phy_apb_base)) = 0x00000023; + *((unsigned int *)(0x185F8 | phy_apb_base)) = 0x00000B24; + *((unsigned int *)(0x18640 | phy_apb_base)) = 0x0000003F; + *((unsigned int *)(0x187E0 | phy_apb_base)) = 0x00000551; + *((unsigned int *)(0x187E4 | phy_apb_base)) = 0x00000022; + *((unsigned int *)(0x187E8 | phy_apb_base)) = 0x00000010; + *((unsigned int *)(0x187EC | phy_apb_base)) = 0x00000010; + *((unsigned int *)(0x187F0 | phy_apb_base)) = 0x00000008; + *((unsigned int *)(0x187F8 | phy_apb_base)) = 0x0000795B; +} + +bool pcie_wait_condition(void *data) +{ + bool completed; + fwk_assert(data != NULL); + + struct pcie_wait_condition_data *wait_data = + (struct pcie_wait_condition_data *)data; + struct pcie_ctrl_apb_reg *ctrl_apb = + (struct pcie_ctrl_apb_reg *)(wait_data->ctrl_apb); + + switch (wait_data->stage) { + case PCIE_INIT_STAGE_PCIE_POWER_ON: + completed = ((SCC->PCIE_PM_CTRL & SCC_PCIE_PM_CTRL_PWR_ACK_MASK) != 0); + break; + + case PCIE_INIT_STAGE_CCIX_POWER_ON: + completed = ((SCC->CCIX_PM_CTRL & SCC_CCIX_PM_CTRL_PWR_ACK_MASK) != 0); + break; + + case PCIE_INIT_STAGE_PHY: + completed = + ((ctrl_apb->RESET_STATUS & RESET_STATUS_PHY_REL_ST_MASK) != 0); + break; + + case PCIE_INIT_STAGE_CTRL: + completed = + (((ctrl_apb->RESET_STATUS & RESET_STATUS_PHY_REL_ST_MASK) != 0) && + ((ctrl_apb->RESET_STATUS & RESET_STATUS_PLL_ST_MASK) != 0)); + break; + + case PCIE_INIT_STAGE_LINK_TRNG: + + case PCIE_INIT_STAGE_LINK_RE_TRNG: + completed = ((ctrl_apb->RP_LTSSM_STATE & RP_LTSSM_STATE_MASK) == 0x10); + break; + + default: + fwk_unexpected(); + completed = false; + break; + } + + return completed; +} + +int pcie_init( + struct pcie_ctrl_apb_reg *ctrl_apb, + struct mod_timer_api *timer_api, + enum pcie_init_stage stage, + enum pcie_gen gen, + enum pcie_lane_count lane_count) +{ + struct pcie_wait_condition_data wait_data; + int status; + + fwk_assert(ctrl_apb != NULL); + fwk_assert(timer_api != NULL); + fwk_assert(stage < PCIE_INIT_STAGE_COUNT); + + wait_data.ctrl_apb = ctrl_apb; + wait_data.stage = stage; + + switch (stage) { + /* PCIe PHY reset request */ + case PCIE_INIT_STAGE_PHY: + ctrl_apb->RESET_CTRL = RESET_CTRL_PHY_REL_MASK; + status = timer_api->wait( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + PCIE_PHY_PLL_LOCK_TIMEOUT, + pcie_wait_condition, + &wait_data); + break; + + /* PCIe RC reset request */ + case PCIE_INIT_STAGE_CTRL: + /* Clear ARI & SR_IOV bits */ + ctrl_apb->RP_CONFIG_IN &= ~RP_CONFIG_IN_ARI_EN_MASK; + // ctrl_apb->RP_CONFIG_IN |= RP_CONFIG_IN_ARI_EN_MASK; + ctrl_apb->RP_CONFIG_IN &= ~RP_CONFIG_IN_SR_IOV_EN_MASK; + + /* Clear the bits before writing to it */ + ctrl_apb->RP_CONFIG_IN &= ~RP_CONFIG_IN_PCIE_GEN_SEL_MASK; + ctrl_apb->RP_CONFIG_IN &= ~RP_CONFIG_IN_LANE_CNT_IN_MASK; + + ctrl_apb->RP_CONFIG_IN |= (lane_count << RP_CONFIG_IN_LANE_CNT_IN_POS) | + (gen << RP_CONFIG_IN_PCIE_GEN_SEL_POS); + ctrl_apb->RESET_CTRL = RESET_CTRL_RC_REL_MASK; + status = timer_api->wait( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + PCIE_CTRL_RC_RESET_TIMEOUT, + pcie_wait_condition, + &wait_data); + break; + + /* PCIe link training request */ + case PCIE_INIT_STAGE_LINK_TRNG: + ctrl_apb->RP_CONFIG_IN |= RP_CONFIG_IN_LINK_TRNG_EN_MASK; + status = timer_api->wait( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + PCIE_LINK_TRAINING_TIMEOUT, + pcie_wait_condition, + &wait_data); + break; + + default: + fwk_unexpected(); + status = FWK_E_PARAM; + break; + } + return status; +} + +int pcie_link_retrain( + struct pcie_ctrl_apb_reg *ctrl_apb, + uint32_t rp_ep_config_base, + struct mod_timer_api *timer_api) +{ + uint32_t reg_val = 0; + struct pcie_wait_condition_data wait_data; + + fwk_assert(ctrl_apb != NULL); + fwk_assert(rp_ep_config_base != 0x0); + fwk_assert(timer_api != NULL); + + wait_data.ctrl_apb = ctrl_apb; + wait_data.stage = PCIE_INIT_STAGE_LINK_RE_TRNG; + + pcie_rp_ep_config_read_word( + rp_ep_config_base, PCIE_LINK_CTRL_STATUS_OFFSET, ®_val); + reg_val |= PCIE_LINK_CTRL_LINK_RETRAIN_MASK; + pcie_rp_ep_config_write_word( + rp_ep_config_base, PCIE_LINK_CTRL_STATUS_OFFSET, reg_val); + + return timer_api->wait( + FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + PCIE_LINK_RE_TRAINING_TIMEOUT, + pcie_wait_condition, + &wait_data); +} + +int axi_outbound_region_setup( + uint32_t axi_config_base_addr, + uint64_t axi_base_addr, + uint32_t region_size, + uint8_t region_idx, + uint8_t trans_type) +{ + volatile struct axi_ob_config ob_config = { 0 }; + volatile uint32_t *region_address = NULL; + volatile uint32_t *ptr; + int count; + + if (region_idx >= AXI_OB_REGIONS_MAX) { + return FWK_E_RANGE; + } + + (void)memset((void *)&ob_config, 0, sizeof(struct axi_ob_config)); + + ob_config.addr0.num_bits = region_size - 1; + if ((trans_type == TRANS_TYPE_MEM_IO) || (trans_type == TRANS_TYPE_IO)) { + ob_config.addr0.address_bits = + ((uint32_t)axi_base_addr >> AXI_LOW_ADDR_BIT_POS); + ob_config.addr1.address_bits = + (uint32_t)(axi_base_addr >> AXI_HIGH_ADDR_BIT_POS); + } else { + ob_config.addr0.address_bits = 0; + } + ob_config.desc0.bus_dev_num_from_addr_desc = 1; + ob_config.desc0.trans_type = trans_type; + ob_config.axi_base_addr0.region_sz = region_size - 1; + ob_config.axi_base_addr0.axi_base_address = + ((uint32_t)axi_base_addr >> AXI_LOW_ADDR_BIT_POS); + ob_config.axi_base_addr1.axi_base_address = + (uint32_t)(axi_base_addr >> AXI_HIGH_ADDR_BIT_POS); + region_address = + (volatile uint32_t + *)(axi_config_base_addr + (region_idx * AXI_OB_REGISTER_SET_SIZE)); + + ptr = (volatile uint32_t *)&ob_config; + + for (count = 0; count < AXI_OB_REGISTER_COUNT; count++) { + region_address[count] = ptr[count]; + } + + return FWK_SUCCESS; +} + +int axi_inbound_region_setup( + uint32_t axi_config_base_addr, + uint64_t axi_base_addr, + uint32_t region_size, + uint8_t bar) +{ + uint32_t offset; + + if ((bar >= AXI_IB_REGIONS_MAX) || (region_size > AXI_ADDR_NUM_BITS_MAX) || + (__builtin_ctz(axi_base_addr) < AXI_LOW_ADDR_BIT_POS)) { + return FWK_E_PARAM; + } + + offset = AXI_IB_REGION_REGS_OFFSET + (bar * AXI_IB_REGISTER_SET_SIZE); + *(uint32_t *)(axi_config_base_addr + offset) = + (uint32_t)axi_base_addr | (region_size - 1); + *(uint32_t *)(axi_config_base_addr + offset + 4) = + (uint32_t)(axi_base_addr >> AXI_HIGH_ADDR_BIT_POS); + return FWK_SUCCESS; +} + +int pcie_rp_ep_config_write_word(uint32_t base, uint32_t offset, uint32_t value) +{ + if ((offset % 4)) { + return FWK_E_PARAM; + } + + base |= ROOT_PORT_WRITE_ENABLE; + *(volatile uint32_t *)(base + offset) = value; + + return FWK_SUCCESS; +} + +int pcie_rp_ep_config_read_word(uint32_t base, uint32_t offset, uint32_t *value) +{ + if ((offset % 4) || (value == NULL)) { + return FWK_E_PARAM; + } + + *value = *(volatile uint32_t *)(base + offset); + + return FWK_SUCCESS; +} + +int pcie_set_gen_tx_preset( + uint32_t rp_ep_config_apb_base, + uint32_t down_stream_tx_preset, + uint32_t up_stream_tx_preset, + enum pcie_gen gen) +{ + uint32_t i; + uint32_t j; + uint32_t offset; + uint32_t reg_value; + uint32_t preset_value = 0; + uint32_t offset_min; + uint32_t offset_max; + uint32_t nibble; + + fwk_assert((gen == PCIE_GEN_3) || (gen == PCIE_GEN_4)); + + offset_min = (gen == PCIE_GEN_3) ? GEN3_OFFSET_MIN : GEN4_OFFSET_MIN; + offset_max = (gen == PCIE_GEN_3) ? GEN3_OFFSET_MAX : GEN4_OFFSET_MAX; + nibble = (gen == PCIE_GEN_3) ? GEN3_PRESET : GEN4_PRESET; + + for (i = 0, j = 0; i < 32; i += nibble, j++) { + if (j % 2 == 0) { + preset_value |= (down_stream_tx_preset << i); + } else { + preset_value |= (up_stream_tx_preset << i); + } + } + + for (offset = offset_min; offset < offset_max; offset += 0x4) { + pcie_rp_ep_config_write_word( + rp_ep_config_apb_base, offset, preset_value); + pcie_rp_ep_config_read_word(rp_ep_config_apb_base, offset, ®_value); + + if (reg_value != preset_value) { + return FWK_E_DATA; + } + } + return FWK_SUCCESS; +} + +int pcie_skip_ext_cap(uint32_t base, uint16_t ext_cap_id) +{ + uint32_t cap_hdr_now; + uint32_t cap_hdr_next; + uint32_t offset; + uint32_t offset_next; + uint32_t offset_target; + + offset = EXT_CAP_START_OFFSET; + cap_hdr_now = 0; + cap_hdr_next = 0; + + do { + pcie_rp_ep_config_read_word(base, offset, &cap_hdr_now); + offset_next = (cap_hdr_now >> EXT_CAP_NEXT_CAP_POS); + pcie_rp_ep_config_read_word(base, offset_next, &cap_hdr_next); + if (((uint16_t)(cap_hdr_next & EXT_CAP_ID_MASK)) == ext_cap_id) { + offset_target = + (cap_hdr_next & + (EXT_CAP_NEXT_CAP_MASK << EXT_CAP_NEXT_CAP_POS)); + cap_hdr_now = (cap_hdr_now & + ~(EXT_CAP_NEXT_CAP_MASK << EXT_CAP_NEXT_CAP_POS)) | + offset_target; + + pcie_rp_ep_config_write_word(base, offset, cap_hdr_now); + return FWK_SUCCESS; + } + offset = offset_next; + } while ((offset != 0)); + + return FWK_E_SUPPORT; +} + +int pcie_vc_setup(uint32_t base, uint8_t vc1_tc) +{ + /* VC1 Traffic class cannot be greater than 7 or equal to 0 */ + if ((vc1_tc > 7) || (vc1_tc == 0)) { + return FWK_E_PARAM; + } + + /* Map all other TCs to VC0 */ + *(volatile uint32_t *)(base + PCIE_VC_RESOURCE_CTRL_0_OFFSET) = + PCIE_VC_CTRL_VCEN_MASK | (0 << PCIE_VC_VCID_SHIFT) | + (~(1 << vc1_tc) & 0xFF); + + /* Enable VC1 & map VC1 to TC7 */ + *(volatile uint32_t *)(base + PCIE_VC_RESOURCE_CTRL_1_OFFSET) = + PCIE_VC_CTRL_VCEN_MASK | (1 << PCIE_VC_VCID_SHIFT) | + ((1 << vc1_tc) & 0xFF); + + return FWK_SUCCESS; +} diff --git a/product/morello/module/morello_pcie/src/morello_pcie.h b/product/morello/module/morello_pcie/src/morello_pcie.h new file mode 100644 index 000000000..27821b648 --- /dev/null +++ b/product/morello/module/morello_pcie/src/morello_pcie.h @@ -0,0 +1,639 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MORELLO_PCIE_H +#define MORELLO_PCIE_H + +#include + +#include + +#include + +#include +#include + +/* + * Definitions of PCIe APB register offsets from global configuration + * base address. + */ + +/* + * Offset from ctrl_base implementing PCIe controller + * configuration registers. + */ +#define APB_OFFSET_CTRL_REGS 0x00040000U +/* + * Offset from ctrl_base implementing PCIe physical layer + * configuration registers. + */ +#define APB_OFFSET_PHY_REGS 0x00000000U +/* + * Offset from global_config_base implementing Root Port/End Point's + * PCIe configuration space registers. + */ +#define APB_OFFSET_RP_EP_CONFIG_REGS 0x00000000U +/* + * Offset from global_config_base implementing PCIe controller's + * local management configuration registers. + */ +#define APB_OFFSET_LM_REGS 0x00100000U +/* + * Offset from global_config_base implementing Root Complex's + * AXI address translation registers. + */ +#define APB_OFFSET_RC_AXI_CONFIG_REGS 0x00400000U +/* + * Offset from global_config_base implementing End Point's + * AXI address translation registers. + */ +#define APB_OFFSET_EP_AXI_CONFIG_REGS 0x00400840U +/* + * Offset between SCP and AP's view of memory space in System Access Port. + * AP's view : 0x40000000 - 0x7FFFFFFF + * SCP's view : 0x60000000 - 0x9FFFFFFF + */ +#define SCP_AP_AXI_OFFSET 0x20000000U + +/* NIC400 base address definition */ +#define NIC400_SOC_GPV_BASE UINT32_C(0xC2000000) + +/* PCIe Vendor ID and Device ID definition */ +#define MORELLO_PCIE_VENDOR_ID_ARM 0x13B5U +#define MORELLO_PCIE_VENDOR_ID_ARM_MASK 0xFFFFU + +#define MORELLO_PCIE_DEVICE_ID_ARM 0x100U +#define MORELLO_PCIE_DEVICE_ID_ARM_MASK 0xFFFF0000U + +/* + * PCIe timeout values for PHY, controller & link training. + * Timeout values specified in microseconds. + * Note: Execution will block for the specified timeout. If the timeout + * is too long switch to alarm API instead of blocking. + */ +#define PCIE_PHY_PLL_LOCK_TIMEOUT UINT32_C(500) +#define PCIE_CTRL_RC_RESET_TIMEOUT UINT32_C(100) +#define PCIE_LINK_TRAINING_TIMEOUT UINT32_C(200000) +#define PCIE_LINK_RE_TRAINING_TIMEOUT UINT32_C(2000000) + +/* PCIe controller power on timeout (in microseconds) */ +#define PCIE_POWER_ON_TIMEOUT UINT32_C(10) + +/* PCIe configuration space offset definitions */ +#define PCIE_CLASS_CODE_OFFSET 0x8 +#define PCIE_LINK_CTRL_STATUS_OFFSET 0xD0 +#define PCIE_LINK_CTRL_STATUS_2_OFFSET 0xF0 +#define PCIE_DEV_CTRL_STATUS_OFFSET 0xC8 +#define PCIE_VC_RESOURCE_CTRL_0_OFFSET 0x4D4 +#define PCIE_VC_RESOURCE_CTRL_1_OFFSET 0x4E0 + +/* PCIe configuration space link control status register definitions */ +#define PCIE_LINK_CTRL_LINK_RETRAIN_MASK 0x20 +#define PCIE_LINK_CTRL_NEG_SPEED_MASK 0xF +#define PCIE_LINK_CTRL_NEG_WIDTH_MASK 0x3F +#define PCIE_LINK_CTRL_NEG_SPEED_POS 16 +#define PCIE_LINK_CTRL_NEG_WIDTH_POS 20 + +/* PCIe configuration space link control status register 2 definitions */ +#define PCIE_LINK_CTRL_2_TARGET_SPEED_MASK 0xF +#define PCIE_LINK_CTRL_2_TARGET_SPEED_GEN4 0x4 + +/* PCIe device control & status register definitions */ +#define PCIE_DEV_CTRL_MAX_PAYLOAD_SHIFT 5 + +/* PCIe virtual channel register definitions */ +#define PCIE_VC_CTRL_VCEN_MASK (1U << 31) +#define PCIE_VC_VCID_SHIFT 24 + +/* PCIe class code for PCI bridge */ +#define PCIE_CLASS_CODE_PCI_BRIDGE UINT32_C(0x06040000) + +/* PCIe controller local management (LM) register offsets */ +#define PCIE_LM_RC_BAR_CONFIG_REG UINT32_C(0x300) +#define PCIE_LM_RC_CCIX_CTRL_REG UINT32_C(0xCA4) +#define PCIE_LM_AXI_FEATURE_CONFIG UINT32_C(0xE5C) + +/* CCIX CONTROL Values */ +#define CCIX_CTRL_EN_OPT_TLP (1U << 16) +#define CCIX_CTRL_CSTT_V0_V1 (1U << 17) +#define CCIX_CTRL_CAW (8U << 24) + +/* + * CCIX Consortium defined Vendor ID. This vendor id is embedded in + * the tlp packets. + * Non Compliance to this value would cause the CCIX capable PCIe + * controllers to drop the incoming packet. + * This value is same as what Xilinx Hood FPGA expects. + * To be revisited after consortium finalizes the value. + */ +#define CCIX_VENDOR_ID (0x1E2C) + +/* PCIe LM root complex bar configuration register bit masks */ +#define TYPE1_PREF_MEM_BAR_ENABLE_MASK (1U << 17) +#define TYPE1_PREF_MEM_BAR_SIZE_32BIT_MASK (0U << 18) +#define TYPE1_PREF_MEM_BAR_SIZE_64BIT_MASK (1U << 18) +#define TYPE1_PREF_IO_BAR_ENABLE_MASK (1U << 19) +#define TYPE1_PREF_IO_BAR_SIZE_32BIT_MASK (0U << 20) +#define TYPE1_PREF_IO_BAR_SIZE_64BIT_MASK (1U << 20) + +/* + * Root port's config space cannot be written directly with its base address. + * Bit 21 has to be set in the base address to enable writing to root port's + * config register. This macro defines the mask with bit 21 set to be used + * with root port write function + */ +#define ROOT_PORT_WRITE_ENABLE UINT32_C(0x00200000) + +/* + * ECAM space per bus + * 32 devices * 8 functions * 4kB config space = 1MB + */ +#define MAX_ECAM_SPACE_PER_BUS (1 * FWK_MIB) + +/* Maximum bus levels for type 0 and type 1 transactions */ +#define MAX_BUS_LEVELS 128 + +/* Maximum AXI space for type 0 and type 1 transactions */ +#define AXI_ECAM_SIZE (MAX_BUS_LEVELS * MAX_ECAM_SPACE_PER_BUS) + +/* Maximum AXI space for MMIO64, MMIO32 & IO transactions */ +#define AXI_MMIO64_SIZE (63 * FWK_GIB) +#define AXI_MMIO32_SIZE (240 * FWK_MIB) +#define AXI_IO_SIZE (16 * FWK_MIB) + +/* + * PCIe AXI subordinate ECAM memory mapping + */ +#define PCIE_AXI_ECAM_OFFSET UINT64_C(0) + +/* + * CCIX AXI subordinate ECAM memory mapping + */ +#define CCIX_AXI_ECAM_OFFSET UINT64_C(0) + +/* + * PCIe AXI subordinate MMIO64 memory mapping + */ +#define PCIE_AXI_MMIO64_OFFSET UINT64_C(0x40000000) + +/* + * CCIX AXI subordinate MMIO64 memory mapping + */ +#define CCIX_AXI_MMIO64_OFFSET UINT64_C(0x40000000) + +/* PCIe AXI subordinate IO offset addresses */ +#define PCIE_AXI_IO_OFFSET (0x0F000000) + +/* CCIX AXI subordinate IO offset addresses */ +#define CCIX_AXI_IO_OFFSET (0x0F000000) + +/* AXI inbound region data */ +#define AXI_IB_REGION_BASE UINT64_C(0) +#define AXI_IB_REGION_SIZE_MSB 48 + +/* + * PCIe Descriptor Register definitions + */ +#define TRANS_TYPE_MEM_IO 0x2 +#define TRANS_TYPE_IO 0x6 +#define TRANS_TYPE_0_CFG 0xA +#define TRANS_TYPE_1_CFG 0xB +#define TRANS_TYPE_NORMAL 0xC +#define TRANS_TYPE_VDM 0xD + +#define PCIE_ATTR_ID_BASED_ORDERING 0x4 +#define PCIE_ATTR_RELAXED_ORDERING 0x2 +#define PCIE_ATTR_NO_SNOOP 0x1 + +#define ATS_UNTRANSLATED 0 +#define ATS_TRANSLATION_REQUEST 1 +#define ATS_TRANSLATED 2 + +#define TRAFFIC_CLASS_0 0 +#define TRAFFIC_CLASS_1 1 +#define TRAFFIC_CLASS_2 2 +#define TRAFFIC_CLASS_3 3 +#define TRAFFIC_CLASS_4 4 +#define TRAFFIC_CLASS_5 5 +#define TRAFFIC_CLASS_6 6 +#define TRAFFIC_CLASS_7 7 + +#define FORCE_ECRC 1 +#define DISABLE_ECRC 0 + +#define INPUT_REQ_ID_FROM_ADDR 1 + +#define PASID_PRESENT 1 +#define PASID_NOT_PRESENT 0 + +#define PRIV_MODE_ACCESS_REQUEST 1 +#define NO_PRIV_MODE_ACCESS 0 + +#define EXEC_MODE_ACCESS_REQUEST 1 +#define NO_EXEC_MODE_ACCESS_REQUEST 0 + +/* + * Maximum AXI outbound regions that can be configured + */ +#define AXI_OB_REGIONS_MAX 32 + +/* + * Total register size of each outbound region + */ +#define AXI_OB_REGISTER_SET_SIZE (8 * 4) + +/* + * Total register count of each outbound region + */ +#define AXI_OB_REGISTER_COUNT 8 + +/* + * Maximum AXI inbound regions that can be configured + */ +#define AXI_IB_REGIONS_MAX 3 + +/* + * Offset from AXI region configuration base where inbound region + * configuration register starts + */ +#define AXI_IB_REGION_REGS_OFFSET (0x800) + +/* + * Total register size of each inbound region + */ +#define AXI_IB_REGISTER_SET_SIZE (2 * 4) + +/* + * AXI address translation register definitions + */ +#define AXI_LOW_ADDR_BIT_POS 8 +#define AXI_HIGH_ADDR_BIT_POS 32 +#define AXI_ADDR_NUM_BITS_MAX ((1 << 6) - 1) + +#define PCIE_RC_TX_PRESET_VALUE 0x4 +#define CCIX_RC_TX_PRESET_VALUE 0x6 + +#define GEN3_OFFSET_MIN 0x30C +#define GEN3_OFFSET_MAX 0x32C +#define GEN3_PRESET 0x8 + +#define GEN4_OFFSET_MIN 0x9E0 +#define GEN4_OFFSET_MAX 0x9F0 +#define GEN4_PRESET 0x4 + +/* + * PCI express extended capability header definitions + */ +#define EXT_CAP_ID_MASK UINT32_C(0xFFFF) +#define EXT_CAP_ID_POS UINT32_C(0) +#define EXT_CAP_NEXT_CAP_MASK UINT32_C(0xFFF) +#define EXT_CAP_NEXT_CAP_POS UINT32_C(20) +#define EXT_CAP_START_OFFSET UINT32_C(0x100) + +#define EXT_CAP_ID_ATS UINT16_C(0x0F) +#define EXT_CAP_ID_PRI UINT16_C(0x13) + +/* + * AXI override values for PCIe & CCIX root ports + */ +#define AXI_OVRD_VAL_PCIE UINT32_C(0x00303F3B) +#define AXI_OVRD_VAL_CCIX UINT32_C(0x00303F3B) + +/* + * AXI outbound region register set definitions + */ + +/* + * Input AXI to outbound PCIe Address translation registers + */ +struct axi_ob_addr0 { + /* Number of bits passed through from AXI address to PCIe address */ + uint32_t num_bits : 6; + uint32_t reserved : 2; + /* Bits [31:8] of PCIe address */ + uint32_t address_bits : 24; +}; + +struct axi_ob_addr1 { + /* Bits [63:32] of PCIe address */ + uint32_t address_bits; +}; + +/* + * Outbound PCIe descriptor registers + */ +struct axi_ob_desc0 { + /* Outbound transaction type */ + uint32_t trans_type : 4; + /* Outbound PCIe attributes */ + uint32_t attr : 3; + /* + * Address Translation Service + * Config TLP - reserved + * Mem/IO TLP - one of the address transalation types + */ + uint32_t ats : 2; + uint32_t reserved1 : 8; + uint32_t traffic_class : 3; + /* Poison mem write for memory TLP, reserved for other TLPs */ + uint32_t poison_mem_write : 1; + /* Force generation of ECRC for every TLP */ + uint32_t force_ecrc : 1; + uint32_t reserved2 : 1; + /* Use bus/dev number from addrx for config TLP & descx for mem TLP */ + uint32_t bus_dev_num_from_addr_desc : 1; + /* Function number in ARI mode or Dev+Function number in non-ARI mode */ + uint32_t dev_func_num : 8; +}; + +struct axi_ob_desc1 { + /* Bus number if bus_dev_num_from_addr_desc in desc0 is set */ + uint32_t bus_number : 8; + uint32_t reserved : 24; +}; + +struct axi_ob_desc2 { + /* Steering tag for the hint */ + uint32_t steering_tag : 8; + /* Index bit */ + uint32_t index_bit : 1; + /* PH value associated with the hint */ + uint32_t ph_value : 2; + /* Transaction Processing Hint length */ + uint32_t tph_length : 1; + /* TPH request */ + uint32_t tph_req : 1; + uint32_t reserved : 19; +}; + +struct axi_ob_desc3 { + /* Process Address Space ID present identifier */ + uint32_t pasid_present_bit : 1; + /* PASID value */ + uint32_t pasid_value : 20; + /* Privilege mode access request */ + uint32_t priv_mode_access_req : 1; + /* Execute mode access request */ + uint32_t exec_mode_access_req : 1; + uint32_t reserved : 9; +}; + +/* + * Input AXI base address registers + */ +struct axi_ob_axi_base_addr0 { + /* Region size = 2 ^ (region_sz + 1) */ + uint32_t region_sz : 6; + uint32_t reserved : 2; + /* Bits [31:8] of AXI base address */ + uint32_t axi_base_address : 24; +}; + +struct axi_ob_axi_base_addr1 { + /* Bits [63:32] of AXI base address */ + uint32_t axi_base_address; +}; + +/* + * AXI outbound region register set + */ +struct axi_ob_config { + struct axi_ob_addr0 addr0; + struct axi_ob_addr1 addr1; + struct axi_ob_desc0 desc0; + struct axi_ob_desc1 desc1; + struct axi_ob_desc2 desc2; + struct axi_ob_desc3 desc3; + struct axi_ob_axi_base_addr0 axi_base_addr0; + struct axi_ob_axi_base_addr1 axi_base_addr1; +}; + +/* + * Identifiers of PCIe initialization stages + */ +enum pcie_init_stage { + /* PCIe controller power ON stage */ + PCIE_INIT_STAGE_PCIE_POWER_ON, + + /* CCIX controller power ON stage */ + PCIE_INIT_STAGE_CCIX_POWER_ON, + + /* PHY initialization stage */ + PCIE_INIT_STAGE_PHY, + + /* Controller initialization stage */ + PCIE_INIT_STAGE_CTRL, + + /* Link training stage */ + PCIE_INIT_STAGE_LINK_TRNG, + + /* Link re-training stage for GEN4 speed */ + PCIE_INIT_STAGE_LINK_RE_TRNG, + + /* PCIe initialization stages */ + PCIE_INIT_STAGE_COUNT, +}; + +/* + * Identifiers of PCIe Generation + */ +enum pcie_gen { + PCIE_GEN_1, + PCIE_GEN_2, + PCIE_GEN_3, + PCIE_GEN_4, +}; + +/* + * Identifiers of PCIe LANE COUNT + */ +enum pcie_lane_count { + LAN_COUNT_IN_X_1, + LAN_COUNT_IN_X_2, + LAN_COUNT_IN_X_4, + LAN_COUNT_IN_X_8, + LAN_COUNT_IN_X_16, +}; + +/* + * Structure defining data to be passed to timer API + */ +struct pcie_wait_condition_data { + void *ctrl_apb; + enum pcie_init_stage stage; +}; + +/* + * Driver function prototypes + */ + +/* + * Brief - Function to setup an outbound region for translating + * incoming AXI address to outgoing PCIe address. + * + * param - axi_config_base_addr - APB address of AXI configuration space + * param - axi_base_addr - AXI incoming base address + * param - region_size - Region size of the outbound region + * param - region_idx - Region identifier of the outbound region + * param - trans_type - Transaction type this region will generate when + * accessed + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_RANGE - if the maximum outbound region is exceeded + */ +int axi_outbound_region_setup( + uint32_t axi_config_base_addr, + uint64_t axi_base_addr, + uint32_t region_size, + uint8_t region_idx, + uint8_t trans_type); + +/* + * Brief - Function to setup an inbound region for translating + * incoming PCIe address to AXI address. + * + * param - axi_config_base_addr - APB address of AXI configuration space + * param - axi_base_addr - AXI base address + * param - region_size - Region size of the inbound region + * param - bar - BAR number to which this inbound region will be setup + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_PARAM - if the passed parameters are invalid + */ +int axi_inbound_region_setup( + uint32_t axi_config_base_addr, + uint64_t axi_base_addr, + uint32_t region_size, + uint8_t bar); + +/* + * Brief - Function to check PCIe status in various initialization stages. + * + * param - data - Pointer to wait condition data + * + * retval - true - if the condition is met + * false - if the condition is not met + */ +bool pcie_wait_condition(void *data); + +/* + * Brief - Function to initialize different stages of PCIe module. + * + * param - ctrl_apb - Pointer to APB controller register space + * param - timer_api - Pointer to timer API used for timeout detection + * param - stage - Identifier of current PCIe initialization stage + * param - gen - PCIe Generation + * param - lane_count - PCIe Lane Count + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_TIMEOUT - if initialization times out + */ +int pcie_init( + struct pcie_ctrl_apb_reg *ctrl_apb, + struct mod_timer_api *timer_api, + enum pcie_init_stage stage, + enum pcie_gen gen, + enum pcie_lane_count lane_count); + +/* + * Brief - Function to re-train PCIe link to GEN4 speed. + * + * param - ctrl_apb - Pointer to APB controller register space + * param - rp_ep_config_base - Root port configuration space base address + * param - timer_api - Pointer to timer API used for timeout detection + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_TIMEOUT - if initialization times out + */ +int pcie_link_retrain( + struct pcie_ctrl_apb_reg *ctrl_apb, + uint32_t rp_ep_config_base, + struct mod_timer_api *timer_api); + +/* + * Brief - Function to initialize PCIe PHY layer. + * + * param - pcie_phy_base - Base address of the PHY layer registers + * param - lane_count - PCIe Lane Count + */ +void pcie_phy_init(uint32_t phy_apb_base, uint32_t lane_count); + +/* + * Brief - Function to write to Root Port's/End Point's configuration space. + * + * param - base - Base address of RP/EP's configuration memory + * param - offset - Register offset from base (must be word aligned) + * param - value - Value to write to the configuration space register + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_PARAM - if offset is not word aligned + */ +int pcie_rp_ep_config_write_word( + uint32_t base, + uint32_t offset, + uint32_t value); + +/* + * Brief - Function to read from Root Port's/End Point's configuration space. + * + * param - base - Base address of RP/EP's configuration memory + * param - offset - Register offset from base (must be word aligned) + * param - value - Pointer to hold the read value + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_PARAM - if offset is not word aligned or value is NULL + */ +int pcie_rp_ep_config_read_word( + uint32_t base, + uint32_t offset, + uint32_t *value); + +/* + * Brief - TX Equalization Preset function. + * + * param - rp_ep_config_apb_base - Base address of the PCIe configuration + * APB registers. + * param - down_stream_tx_preset - downstream Preset Value + * param - up_stream_tx_preset - upstream Preset Value + * param - gen - PCIe generation + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DATA - if there is a mismatch between value written + * to and read from the register. + */ +int pcie_set_gen_tx_preset( + uint32_t rp_ep_config_apb_base, + uint32_t down_stream_tx_preset, + uint32_t up_stream_tx_preset, + enum pcie_gen gen); + +/* + * Brief - Function to skip an extended capability from capability + * linked list. + * + * param - base - Base address of RP/EP's configuration memory + * param - ext_cap_id - Extended capability ID to be skipped + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_SUPPORT - if the specified capability is not present in the + * linked list + */ +int pcie_skip_ext_cap(uint32_t base, uint16_t ext_cap_id); + +/* + * Brief - Function to setup PCIe virtual channels and map to + * specified traffic class. + * + * param - base - Base address of RP/EP's configuration memory + * param - vc1_tc - Traffic class value for virtual channel 1 + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_PARAM - if the passed parameters are inconsistent + */ +int pcie_vc_setup(uint32_t base, uint8_t vc1_tc); + +#endif /* MORELLO_PCIE_H */ diff --git a/tools/cppcheck_suppress_list.txt b/tools/cppcheck_suppress_list.txt index f29b12a7b..2d19d53fa 100755 --- a/tools/cppcheck_suppress_list.txt +++ b/tools/cppcheck_suppress_list.txt @@ -178,6 +178,7 @@ arrayIndexOutOfBounds:*product/rdv1mc/module/platform_system/src/mod_platform_sy arrayIndexOutOfBounds:*product/rdv1mc/module/platform_system/src/mod_platform_system.c:135 arrayIndexOutOfBounds:*product/rdv1mc/module/platform_system/src/mod_platform_system.c:141 objectIndex:*product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.c:438 +objectIndex:*product/morello/module/morello_pcie/src/morello_pcie.c:390 knownConditionTrueFalse:*product/n1sdp/module/n1sdp_dmc620/src/mod_n1sdp_dmc620.c:85 // Suppress CMSIS errors -- GitLab From 8bb8bca14bf9e0c98853d51cfe395c421c4ed897 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 05/41] morello/scp_ramfw_soc: add MPU configuration Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I322061c8117a02e9bd8776ff113e019828b8add0 --- .../morello/scp_ramfw_soc/config_armv7m_mpu.c | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_armv7m_mpu.c diff --git a/product/morello/scp_ramfw_soc/config_armv7m_mpu.c b/product/morello/scp_ramfw_soc/config_armv7m_mpu.c new file mode 100644 index 000000000..3f373b809 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_armv7m_mpu.c @@ -0,0 +1,102 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include + +static const ARM_MPU_Region_t regions[] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 0, + 1, + 0, + ARM_MPU_REGION_SIZE_4GB), + }, + { + /* 0x0080_0000 - 0x0088_0000 */ + .RBAR = ARM_MPU_RBAR(1, SCP_RAM0_BASE), + .RASR = ARM_MPU_RASR( + 0, + ARM_MPU_AP_PRO, + 0, + 0, + 1, + 0, + 0, + ARM_MPU_REGION_SIZE_512KB), + }, + { + /* 0x2000_0000 - 0x2003_FFFF */ + .RBAR = ARM_MPU_RBAR(2, SCP_RAM1_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 0, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, + { + /* 0xA400_0000 - 0xA407_FFFF*/ + .RBAR = ARM_MPU_RBAR(3, SCP_TRUSTED_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_512KB), + }, + { + /* 0x6540_0000 - 0x6540_00FF */ + .RBAR = ARM_MPU_RBAR(4, SCP_AP_SHARED_SECURE_RAM), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256B), + }, + { + /* 0x6520_0000 - 0x6520_FFFF */ + .RBAR = ARM_MPU_RBAR(5, SCP_AP_SHARED_NONSECURE_RAM), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_64KB), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; -- GitLab From 2a0d0926b3f8c59a3d4e4108ccb58c2873f254d2 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 06/41] morello/scp_ramfw_soc: add apcontext config data Supply the base addres and the size of shared memory region b/w AP and SCP, which the AP context module zero's out upon initialisation and subsequent resets. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I9bbe77a65915b3247709d8ced67f0d974b4b6700 --- .../morello/scp_ramfw_soc/config_apcontext.c | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_apcontext.c diff --git a/product/morello/scp_ramfw_soc/config_apcontext.c b/product/morello/scp_ramfw_soc/config_apcontext.c new file mode 100644 index 000000000..83e8a594d --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_apcontext.c @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include + +/* + * AP Context module configuration + */ +static const struct mod_apcontext_config apcontext_data = { + .base = SCP_AP_CONTEXT_BASE, + .size = SCP_AP_CONTEXT_SIZE, + .clock_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT), +}; + +struct fwk_module_config config_apcontext = { + .data = &apcontext_data, +}; -- GitLab From 2b0313ce51583afc07e75f56c5f72de97ac957a3 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 07/41] morello/scp_ramfw_soc: add config data for Morello clocks Add configuration data for PLLs, CSS, and PIK clocks. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I8da959b6d3d8e8a0db040691912c68480360d72a --- product/morello/scp_ramfw_soc/config_clock.c | 107 ++ product/morello/scp_ramfw_soc/config_clock.h | 247 ++++ .../morello/scp_ramfw_soc/config_css_clock.c | 271 +++++ .../scp_ramfw_soc/config_morello_pll.c | 126 ++ .../morello/scp_ramfw_soc/config_pik_clock.c | 1065 +++++++++++++++++ 5 files changed, 1816 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_clock.c create mode 100644 product/morello/scp_ramfw_soc/config_clock.h create mode 100644 product/morello/scp_ramfw_soc/config_css_clock.c create mode 100644 product/morello/scp_ramfw_soc/config_morello_pll.c create mode 100644 product/morello/scp_ramfw_soc/config_pik_clock.c diff --git a/product/morello/scp_ramfw_soc/config_clock.c b/product/morello/scp_ramfw_soc/config_clock.c new file mode 100644 index 000000000..7fd02a08e --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_clock.c @@ -0,0 +1,107 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { + [CLOCK_IDX_INTERCONNECT] = { + .name = "Interconnect", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, + CLOCK_PIK_IDX_INTERCONNECT), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP0] = { + .name = "CPU_GROUP0", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP1] = { + .name = "CPU_GROUP1", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP1), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_GPU] = { + .name = "GPU", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_GPU), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_DPU] = { + .name = "DPU", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_DPU), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_PIXEL_0] = { + .name = "PIXEL_0", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MORELLO_PLL, + CLOCK_PLL_IDX_PXL), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MORELLO_PLL, + MOD_MORELLO_PLL_API_TYPE_DEFAULT), + }), + }, + { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id) +{ + unsigned int i; + struct mod_clock_dev_config *dev_config; + + for (i = 0; i < CLOCK_IDX_COUNT; i++) { + dev_config = + (struct mod_clock_dev_config *)clock_dev_desc_table[i].data; + dev_config->pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, PD_SINGLE_CHIP_IDX_SYSTOP0); + } + + return clock_dev_desc_table; +} + +const struct fwk_module_config config_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(clock_get_dev_desc_table), + .data = &((struct mod_clock_config){ + .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), + .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION), + }), + +}; diff --git a/product/morello/scp_ramfw_soc/config_clock.h b/product/morello/scp_ramfw_soc/config_clock.h new file mode 100644 index 000000000..8480cd3af --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_clock.h @@ -0,0 +1,247 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_CLOCK_H +#define CONFIG_CLOCK_H + +#include + +/* + * DDR Subsystem clock in MHz + */ +#define DDR_CLOCK_MHZ 1333UL + +#define CPU_CLOCK_SUD 2100UL +#define CPU_CLOCK_UD 2200UL +#define CPU_CLOCK_NOM 2300UL +#define CPU_CLOCK_OD 2400UL +#define CPU_CLOCK_SOD 2500UL + +#define CLUS_CLOCK_MHZ 2000UL +#define INT_CLOCK_MHZ 1850UL + +/* + * SCC & PIK clock rates. + */ +/* 200MHz Nominal */ +#define SCC_CLK_RATE_IOFPGA_TMIF2XCLK (150 * FWK_MHZ) +/* 200MHz Nominal */ +#define SCC_CLK_RATE_IOFPGA_TSIF2XCLK (150 * FWK_MHZ) +/* verification value */ +#define SCC_CLK_RATE_SYSAPBCLK (120 * FWK_MHZ) +#define SCC_CLK_RATE_SCPNICCLK (300 * FWK_MHZ) +#define SCC_CLK_RATE_SCPI2CCLK (100 * FWK_MHZ) +/* 480MHz Nominal */ +#define SCC_CLK_RATE_SCPQSPICLK (50 * FWK_MHZ) +#define SCC_CLK_RATE_SENSORCLK (100 * FWK_MHZ) +#define SCC_CLK_RATE_MCPNICCLK (300 * FWK_MHZ) +#define SCC_CLK_RATE_MCPI2CCLK (100 * FWK_MHZ) +/* 480MHz Nominal */ +#define SCC_CLK_RATE_MCPQSPICLK (50 * FWK_MHZ) +#define SCC_CLK_RATE_PCIEAXICLK (1200 * FWK_MHZ) +#define SCC_CLK_RATE_CCIXAXICLK (1200 * FWK_MHZ) +#define SCC_CLK_RATE_PCIEAPBCLK (200 * FWK_MHZ) +#define SCC_CLK_RATE_CCIXAPBCLK (200 * FWK_MHZ) + +/* 2500MHz Nom */ +#define PIK_CLK_RATE_CLUS0_CPU (CPU_CLOCK_SOD * FWK_MHZ) +/* 2500MHz Nom */ +#define PIK_CLK_RATE_CLUS1_CPU (CPU_CLOCK_SOD * FWK_MHZ) +/* 2000MHz Nom */ +#define PIK_CLK_RATE_CLUS0 (CLUS_CLOCK_MHZ * FWK_MHZ) +/* 2000MHz Nom */ +#define PIK_CLK_RATE_CLUS1 (CLUS_CLOCK_MHZ * FWK_MHZ) +#define PIK_CLK_RATE_CLUS0_PPU (300 * FWK_MHZ) +#define PIK_CLK_RATE_CLUS1_PPU (300 * FWK_MHZ) +/* 1000MHz Nom */ +#define PIK_CLK_RATE_CLUS0_PCLK (800 * FWK_MHZ) +/* 1000MHz Nom */ +#define PIK_CLK_RATE_CLUS0_ATCLK (800 * FWK_MHZ) +/* 1000MHz Nom */ +#define PIK_CLK_RATE_CLUS0_GIC (800 * FWK_MHZ) +/* 2000MHz Nom */ +#define PIK_CLK_RATE_CLUS0_AMBACLK (1200 * FWK_MHZ) +/* 1000MHz Nom */ +#define PIK_CLK_RATE_CLUS1_PCLK (800 * FWK_MHZ) +/* 1000MHz Nom */ +#define PIK_CLK_RATE_CLUS1_ATCLK (800 * FWK_MHZ) +/* 1000MHz Nom */ +#define PIK_CLK_RATE_CLUS1_GIC (800 * FWK_MHZ) +/* 2000MHz Nom */ +#define PIK_CLK_RATE_CLUS1_AMBACLK (1200 * FWK_MHZ) + +#define PIK_CLK_RATE_GPU (650 * FWK_MHZ) +/* 365MHz Nom */ +#define PIK_CLK_RATE_DPU (350 * FWK_MHZ) + +#define PIK_CLK_RATE_SCP_CORECLK (300 * FWK_MHZ) +#define PIK_CLK_RATE_SCP_AXICLK (300 * FWK_MHZ) +#define PIK_CLK_RATE_SCP_SYNCCLK (150 * FWK_MHZ) + +#define PIK_CLK_RATE_SYS_PPU (300 * FWK_MHZ) +/* 1852MHz Nom */ +#define PIK_CLK_RATE_INTERCONNECT (INT_CLOCK_MHZ * FWK_MHZ) +#define PIK_CLK_RATE_PCLKSCP (300 * FWK_MHZ) +#define PIK_CLK_RATE_SYS_GIC (800 * FWK_MHZ) +#define PIK_CLK_RATE_SYSPCLKDBG (300 * FWK_MHZ) +#define PIK_CLK_RATE_SYSPERCLK (600 * FWK_MHZ) +#define PIK_CLK_RATE_UART (50 * FWK_MHZ) +#define PIK_CLK_RATE_TCU0 (1200 * FWK_MHZ) +#define PIK_CLK_RATE_TCU1 (1200 * FWK_MHZ) +#define PIK_CLK_RATE_TCU2 (1200 * FWK_MHZ) +#define PIK_CLK_RATE_TCU3 (1200 * FWK_MHZ) + +#define PIK_CLK_RATE_ATCLKDBG (600 * FWK_MHZ) +#define PIK_CLK_RATE_PCLKDBG (300 * FWK_MHZ) +#define PIK_CLK_RATE_TRACECLK (300 * FWK_MHZ) +#define PIK_CLK_RATE_DMC (DDR_CLOCK_MHZ * FWK_MHZ) + +/* + * MORELLO PLL clock rates. + */ +#define MORELLO_PLL_RATE_CPU_PLL0 (CPU_CLOCK_SOD * FWK_MHZ) +#define MORELLO_PLL_RATE_CPU_PLL1 (CPU_CLOCK_SOD * FWK_MHZ) +#define MORELLO_PLL_RATE_CLUSTER_PLL (CLUS_CLOCK_MHZ * FWK_MHZ) +#define MORELLO_PLL_RATE_INTERCONNECT_PLL (INT_CLOCK_MHZ * FWK_MHZ) +#define MORELLO_PLL_RATE_SYSTEM_PLL (2400 * FWK_MHZ) +#define MORELLO_PLL_RATE_DMC_PLL (DDR_CLOCK_MHZ * FWK_MHZ) +#define MORELLO_PLL_RATE_GPU_PLL (650 * FWK_MHZ) +#define MORELLO_PLL_RATE_DPU_PLL (350 * FWK_MHZ) +/* 1920x1080 @60Hz */ +#define MORELLO_PLL_RATE_PIXEL_PLL (148500000UL) + +/* + * CSS clock rates. + */ +#define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (CPU_CLOCK_SUD * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE (CPU_CLOCK_UD * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP0_NOMINAL (CPU_CLOCK_NOM * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP0_OVERDRIVE (CPU_CLOCK_OD * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE (CPU_CLOCK_SOD * FWK_MHZ) + +#define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (CPU_CLOCK_SUD * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE (CPU_CLOCK_UD * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP1_NOMINAL (CPU_CLOCK_NOM * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP1_OVERDRIVE (CPU_CLOCK_OD * FWK_MHZ) +#define CSS_CLK_RATE_CPU_GRP1_SUPER_OVERDRIVE (CPU_CLOCK_SOD * FWK_MHZ) + +#define CSS_CLK_RATE_GPU_SUPER_UNDERDRIVE (450 * FWK_MHZ) +#define CSS_CLK_RATE_GPU_UNDERDRIVE (500 * FWK_MHZ) +#define CSS_CLK_RATE_GPU_NOMINAL (550 * FWK_MHZ) +#define CSS_CLK_RATE_GPU_OVERDRIVE (600 * FWK_MHZ) +#define CSS_CLK_RATE_GPU_SUPER_OVERDRIVE (650 * FWK_MHZ) + +#define OSC_FREQ_HZ (24 * FWK_MHZ) +/* + * Clock indexes. + */ +enum clock_idx { + CLOCK_IDX_INTERCONNECT, + CLOCK_IDX_CPU_GROUP0, + CLOCK_IDX_CPU_GROUP1, + CLOCK_IDX_GPU, + CLOCK_IDX_DPU, + CLOCK_IDX_PIXEL_0, + CLOCK_IDX_COUNT +}; + +/* + * SCC & PIK clock indexes. + */ +enum clock_pik_idx { + /* SCC Clocks */ + CLOCK_SCC_IDX_IOFPGA_TMIF2XCLK, + CLOCK_SCC_IDX_IOFPGA_TSIF2XCLK, + CLOCK_SCC_IDX_SYSAPBCLK, + CLOCK_SCC_IDX_SCPNICCLK, + CLOCK_SCC_IDX_SCPI2CCLK, + CLOCK_SCC_IDX_SCPQSPICLK, + CLOCK_SCC_IDX_SENSORCLK, + CLOCK_SCC_IDX_MCPNICCLK, + CLOCK_SCC_IDX_MCPI2CCLK, + CLOCK_SCC_IDX_MCPQSPICLK, + CLOCK_SCC_IDX_PCIEAXICLK, + CLOCK_SCC_IDX_CCIXAXICLK, + CLOCK_SCC_IDX_PCIEAPBCLK, + CLOCK_SCC_IDX_CCIXAPBCLK, + + /* PIK Clocks */ + + /* CPU element clocks */ + CLOCK_PIK_IDX_CLUS0_CPU0, + CLOCK_PIK_IDX_CLUS0_CPU1, + CLOCK_PIK_IDX_CLUS1_CPU0, + CLOCK_PIK_IDX_CLUS1_CPU1, + CLOCK_PIK_IDX_CLUS0, + CLOCK_PIK_IDX_CLUS1, + CLOCK_PIK_IDX_CLUS0_PPU, + CLOCK_PIK_IDX_CLUS1_PPU, + CLOCK_PIK_IDX_CLUS0_PCLK, + CLOCK_PIK_IDX_CLUS0_ATCLK, + CLOCK_PIK_IDX_CLUS0_GIC, + CLOCK_PIK_IDX_CLUS0_AMBACLK, + CLOCK_PIK_IDX_CLUS1_PCLK, + CLOCK_PIK_IDX_CLUS1_ATCLK, + CLOCK_PIK_IDX_CLUS1_GIC, + CLOCK_PIK_IDX_CLUS1_AMBACLK, + /* Multimedia element clocks */ + CLOCK_PIK_IDX_GPU, + CLOCK_PIK_IDX_DPU, + /* SCP element clocks */ + CLOCK_PIK_IDX_SCP_CORECLK, + CLOCK_PIK_IDX_SCP_AXICLK, + CLOCK_PIK_IDX_SCP_SYNCCLK, + /* Top element clocks */ + CLOCK_PIK_IDX_SYS_PPU, + CLOCK_PIK_IDX_INTERCONNECT, + CLOCK_PIK_IDX_PCLKSCP, + CLOCK_PIK_IDX_SYS_GIC, + CLOCK_PIK_IDX_SYSPCLKDBG, + CLOCK_PIK_IDX_SYSPERCLK, + CLOCK_PIK_IDX_UART, + CLOCK_PIK_IDX_TCU0, + CLOCK_PIK_IDX_TCU1, + CLOCK_PIK_IDX_TCU2, + CLOCK_PIK_IDX_TCU3, + /* Debug element clocks */ + CLOCK_PIK_IDX_ATCLKDBG, + CLOCK_PIK_IDX_PCLKDBG, + CLOCK_PIK_IDX_TRACECLK, + /* DMC element clock */ + CLOCK_PIK_IDX_DMC, + /* Number of generated clocks */ + CLOCK_PIK_IDX_COUNT +}; + +/* + * CSS clock indexes. + */ +enum clock_css_idx { + CLOCK_CSS_IDX_CPU_GROUP0, + CLOCK_CSS_IDX_CPU_GROUP1, + CLOCK_CSS_IDX_GPU, + CLOCK_CSS_IDX_DPU, + CLOCK_CSS_IDX_COUNT +}; + +/* + * SoC PLL indexes. + */ +enum clock_pll_idx { + CLOCK_PLL_IDX_CPU0, + CLOCK_PLL_IDX_CPU1, + CLOCK_PLL_IDX_CLUS, + CLOCK_PLL_IDX_INTERCONNECT, + CLOCK_PLL_IDX_SYS, + CLOCK_PLL_IDX_DMC, + CLOCK_PLL_IDX_GPU, + CLOCK_PLL_IDX_DPU, + CLOCK_PLL_IDX_PXL, + CLOCK_PLL_IDX_COUNT +}; + +#endif /* CONFIG_CLOCK_H */ diff --git a/product/morello/scp_ramfw_soc/config_css_clock.c b/product/morello/scp_ramfw_soc/config_css_clock.c new file mode 100644 index 000000000..c8186e79e --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_css_clock.c @@ -0,0 +1,271 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +static const struct mod_css_clock_rate rate_table_cpu_group_0[5] = { + { + /* Super Underdrive */ + .rate = CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = CSS_CLK_RATE_CPU_GRP0_NOMINAL, + .pll_rate = CSS_CLK_RATE_CPU_GRP0_NOMINAL, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = CSS_CLK_RATE_CPU_GRP0_OVERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP0_OVERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_1[5] = { + { + /* Super Underdrive */ + .rate = CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = CSS_CLK_RATE_CPU_GRP1_NOMINAL, + .pll_rate = CSS_CLK_RATE_CPU_GRP1_NOMINAL, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = CSS_CLK_RATE_CPU_GRP1_OVERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP1_OVERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = CSS_CLK_RATE_CPU_GRP1_SUPER_OVERDRIVE, + .pll_rate = CSS_CLK_RATE_CPU_GRP1_SUPER_OVERDRIVE, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_gpu[5] = { + { + .rate = CSS_CLK_RATE_GPU_SUPER_UNDERDRIVE, + .pll_rate = CSS_CLK_RATE_GPU_SUPER_UNDERDRIVE, + .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + }, + { + .rate = CSS_CLK_RATE_GPU_UNDERDRIVE, + .pll_rate = CSS_CLK_RATE_GPU_UNDERDRIVE, + .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + }, + { + .rate = CSS_CLK_RATE_GPU_NOMINAL, + .pll_rate = CSS_CLK_RATE_GPU_NOMINAL, + .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + }, + { + .rate = CSS_CLK_RATE_GPU_OVERDRIVE, + .pll_rate = CSS_CLK_RATE_GPU_OVERDRIVE, + .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + }, + { + /* Nominal */ + .rate = CSS_CLK_RATE_GPU_SUPER_OVERDRIVE, + .pll_rate = CSS_CLK_RATE_GPU_SUPER_OVERDRIVE, + .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + }, +}; + +static const fwk_id_t member_table_cpu_group_0[2] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), +}; + +static const fwk_id_t member_table_cpu_group_1[2] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU0), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU1), +}; + +static const fwk_id_t member_table_gpu[1] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_GPU), +}; + +static const fwk_id_t member_table_dpu[1] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_DPU), +}; + +static const struct fwk_element + css_clock_element_table[CLOCK_CSS_IDX_COUNT + 1] = { + [CLOCK_CSS_IDX_CPU_GROUP0] = { + .name = "CPU_GROUP_0", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_0, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MORELLO_PLL, + CLOCK_PLL_IDX_CPU0), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MORELLO_PLL, + MOD_MORELLO_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_0, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP1] = { + .name = "CPU_GROUP_1", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_1, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MORELLO_PLL, + CLOCK_PLL_IDX_CPU1), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MORELLO_PLL, + MOD_MORELLO_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_1, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_1), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = CSS_CLK_RATE_CPU_GRP1_SUPER_OVERDRIVE, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_GPU] = { + .name = "GPU", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_gpu, + .rate_count = FWK_ARRAY_SIZE(rate_table_gpu), + .clock_switching_source = MOD_PIK_CLOCK_GPUCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MORELLO_PLL, + CLOCK_PLL_IDX_GPU), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MORELLO_PLL, + MOD_MORELLO_PLL_API_TYPE_DEFAULT), + .member_table = member_table_gpu, + .member_count = FWK_ARRAY_SIZE(member_table_gpu), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = CSS_CLK_RATE_GPU_SUPER_OVERDRIVE, + .modulation_supported = false, + }), + }, + [CLOCK_CSS_IDX_DPU] = { + .name = "DPU", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_NON_INDEXED, + .clock_default_source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, + .clock_switching_source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MORELLO_PLL, + CLOCK_PLL_IDX_DPU), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MORELLO_PLL, + MOD_MORELLO_PLL_API_TYPE_DEFAULT), + .member_table = member_table_dpu, + .member_count = FWK_ARRAY_SIZE(member_table_dpu), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = PIK_CLK_RATE_DPU, + .modulation_supported = false, + }), + }, + [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) +{ + return css_clock_element_table; +} + +const struct fwk_module_config config_css_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(css_clock_get_element_table), +}; diff --git a/product/morello/scp_ramfw_soc/config_morello_pll.c b/product/morello/scp_ramfw_soc/config_morello_pll.c new file mode 100644 index 000000000..ef1f95fd3 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_morello_pll.c @@ -0,0 +1,126 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +static struct morello_pll_custom_freq_param_entry freq_table[1] = { + { + .freq_value_mhz = 1333, + .fbdiv = 160, + .refdiv = 3, + .postdiv = 2, + }, +}; + +static const struct fwk_element + morello_pll_element_table[CLOCK_PLL_IDX_COUNT + 1] = { + [CLOCK_PLL_IDX_CPU0] = { + .name = "CPU_PLL_0", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_CPU0_CTRL, + .control_reg1 = (void *)SCP_PLL_CPU0_STAT, + .initial_rate = MORELLO_PLL_RATE_CPU_PLL0, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_CPU1] = { + .name = "CPU_PLL_1", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_CPU1_CTRL, + .control_reg1 = (void *)SCP_PLL_CPU1_STAT, + .initial_rate = MORELLO_PLL_RATE_CPU_PLL1, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_CLUS] = { + .name = "CLUSTER_PLL", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_CLUS_CTRL, + .control_reg1 = (void *)SCP_PLL_CLUS_STAT, + .initial_rate = MORELLO_PLL_RATE_CLUSTER_PLL, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_INTERCONNECT] = { + .name = "INT_PLL", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_INTERCONNECT_CTRL, + .control_reg1 = (void *)SCP_PLL_INTERCONNECT_STAT, + .initial_rate = MORELLO_PLL_RATE_INTERCONNECT_PLL, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_SYS] = { + .name = "SYS_PLL", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_SYSPLL_CTRL, + .control_reg1 = (void *)SCP_PLL_SYSPLL_STAT, + .initial_rate = MORELLO_PLL_RATE_SYSTEM_PLL, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_DMC] = { + .name = "DMC_PLL", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_DMC_CTRL, + .control_reg1 = (void *)SCP_PLL_DMC_STAT, + .initial_rate = MORELLO_PLL_RATE_DMC_PLL, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_GPU] = { + .name = "GPU_PLL", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_GPU_CTRL, + .control_reg1 = (void *)SCP_PLL_GPU_STAT, + .initial_rate = MORELLO_PLL_RATE_GPU_PLL, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_DPU] = { + .name = "DPU_PLL", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_DPU_CTRL, + .control_reg1 = (void *)SCP_PLL_DPU_STAT, + .initial_rate = MORELLO_PLL_RATE_DPU_PLL, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_PXL] = { + .name = "PXL_PLL", + .data = &((struct mod_morello_pll_dev_config) { + .control_reg0 = (void *)SCP_PLL_PIXEL_CTRL, + .control_reg1 = (void *)SCP_PLL_PIXEL_STAT, + .initial_rate = MORELLO_PLL_RATE_PIXEL_PLL, + .ref_rate = CLOCK_RATE_REFCLK, + }), + }, + [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *morello_pll_get_element_table( + fwk_id_t module_id) +{ + return morello_pll_element_table; +} + +const struct fwk_module_config config_morello_pll = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(morello_pll_get_element_table), + .data = &((struct morello_pll_module_config){ + .custom_freq_table = freq_table, + .custom_freq_table_size = FWK_ARRAY_SIZE(freq_table), + }), +}; diff --git a/product/morello/scp_ramfw_soc/config_pik_clock.c b/product/morello/scp_ramfw_soc/config_pik_clock.c new file mode 100644 index 000000000..2527fd6e9 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_pik_clock.c @@ -0,0 +1,1065 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +/* + * Rate lookup tables + */ + +static const struct mod_pik_clock_rate rate_table_iofpga_tmif2xclk[1] = { + { + .rate = SCC_CLK_RATE_IOFPGA_TMIF2XCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_IOFPGA_TMIF2XCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_iofpga_tsif2xclk[1] = { + { + .rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_IOFPGA_TSIF2XCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sysapbclk[1] = { + { + .rate = SCC_CLK_RATE_SYSAPBCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_SYSAPBCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scpnicclk[1] = { + { + .rate = SCC_CLK_RATE_SCPNICCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_SCPNICCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scpi2cclk[1] = { + { + .rate = SCC_CLK_RATE_SCPI2CCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_SCPI2CCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scpqspiclk[1] = { + { + .rate = SCC_CLK_RATE_SCPQSPICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSREFCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sensorclk[1] = { + { + .rate = SCC_CLK_RATE_SENSORCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_SENSORCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_mcpnicclk[1] = { + { + .rate = SCC_CLK_RATE_MCPNICCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_MCPNICCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_mcpi2cclk[1] = { + { + .rate = SCC_CLK_RATE_MCPI2CCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_MCPI2CCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_mcpqspiclk[1] = { + { + .rate = SCC_CLK_RATE_MCPQSPICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSREFCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_pcieaxiclk[1] = { + { + .rate = SCC_CLK_RATE_PCIEAXICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_PCIEAXICLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_ccixaxiclk[1] = { + { + .rate = SCC_CLK_RATE_CCIXAXICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_CCIXAXICLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_pcieapbclk[1] = { + { + .rate = SCC_CLK_RATE_PCIEAPBCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_PCIEAPBCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_ccixapbclk[1] = { + { + .rate = SCC_CLK_RATE_CCIXAPBCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_CCIXAPBCLK, + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_0[1] = { + { + .rate = PIK_CLK_RATE_CLUS0_CPU, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_1[1] = { + { + .rate = PIK_CLK_RATE_CLUS1_CPU, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus_0[1] = { + { + .rate = PIK_CLK_RATE_CLUS0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus_1[1] = { + { + .rate = PIK_CLK_RATE_CLUS1, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus_0_ppu[1] = { + { + .rate = PIK_CLK_RATE_CLUS0_PPU, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_CLUS0_PPU, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus_1_ppu[1] = { + { + .rate = PIK_CLK_RATE_CLUS1_PPU, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_CLUS1_PPU, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus0_pclk[1] = { + { + .rate = PIK_CLK_RATE_CLUS0_PCLK, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS0 / PIK_CLK_RATE_CLUS0_PCLK, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus0_atclk[1] = { + { + .rate = PIK_CLK_RATE_CLUS0_ATCLK, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS0 / PIK_CLK_RATE_CLUS0_ATCLK, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus0_gic[1] = { + { + .rate = PIK_CLK_RATE_CLUS0_GIC, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS0 / PIK_CLK_RATE_CLUS0_GIC, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus0_ambaclk[1] = { + { + .rate = PIK_CLK_RATE_CLUS0_AMBACLK, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS0 / PIK_CLK_RATE_CLUS0_AMBACLK, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus1_pclk[1] = { + { + .rate = PIK_CLK_RATE_CLUS1_PCLK, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS1 / PIK_CLK_RATE_CLUS1_PCLK, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus1_atclk[1] = { + { + .rate = PIK_CLK_RATE_CLUS1_ATCLK, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS1 / PIK_CLK_RATE_CLUS1_ATCLK, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus1_gic[1] = { + { + .rate = PIK_CLK_RATE_CLUS1_GIC, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS1 / PIK_CLK_RATE_CLUS1_GIC, + }, +}; + +static struct mod_pik_clock_rate rate_table_clus1_ambaclk[1] = { + { + .rate = PIK_CLK_RATE_CLUS1_AMBACLK, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = PIK_CLK_RATE_CLUS1 / PIK_CLK_RATE_CLUS1_AMBACLK, + }, +}; + +static struct mod_pik_clock_rate rate_table_gpu[1] = { + { + .rate = PIK_CLK_RATE_GPU, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static struct mod_pik_clock_rate rate_table_dpu[1] = { + { + .rate = PIK_CLK_RATE_DPU, + .source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scp_coreclk[1] = { + { + .rate = PIK_CLK_RATE_SCP_CORECLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_SCP_CORECLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scp_aclk[1] = { + { + .rate = PIK_CLK_RATE_SCP_AXICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_SCP_AXICLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scp_syncclk[1] = { + { + .rate = PIK_CLK_RATE_SCP_SYNCCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_SCP_SYNCCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sys_ppu[1] = { + { + .rate = PIK_CLK_RATE_SYS_PPU, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_SYS_PPU, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sys_intclk[1] = { + { + .rate = PIK_CLK_RATE_INTERCONNECT, + .source = MOD_PIK_CLOCK_INTCLK_SOURCE_INTPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_pclkscp[1] = { + { + .rate = PIK_CLK_RATE_PCLKSCP, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_PCLKSCP, + }, +}; + +static const struct mod_pik_clock_rate rate_table_gicclk[1] = { + { + .rate = PIK_CLK_RATE_SYS_GIC, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_SYS_GIC, + }, +}; + +static const struct mod_pik_clock_rate rate_table_syspclkdbg[1] = { + { + .rate = PIK_CLK_RATE_SYSPCLKDBG, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_SYSPCLKDBG, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sysperclk[1] = { + { + .rate = PIK_CLK_RATE_SYSPERCLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_SYSPERCLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_uart[1] = { + { + .rate = PIK_CLK_RATE_UART, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSREFCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_tcu0[1] = { + { + .rate = PIK_CLK_RATE_TCU0, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_TCU0, + }, +}; + +static const struct mod_pik_clock_rate rate_table_tcu1[1] = { + { + .rate = PIK_CLK_RATE_TCU1, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_TCU1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_tcu2[1] = { + { + .rate = PIK_CLK_RATE_TCU2, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_TCU2, + }, +}; + +static const struct mod_pik_clock_rate rate_table_tcu3[1] = { + { + .rate = PIK_CLK_RATE_TCU3, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_TCU3, + }, +}; + +static const struct mod_pik_clock_rate rate_table_atclkdbg[1] = { + { + .rate = PIK_CLK_RATE_ATCLKDBG, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_ATCLKDBG, + }, +}; + +static const struct mod_pik_clock_rate rate_table_pclkdbg[1] = { + { + .rate = PIK_CLK_RATE_PCLKDBG, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = PIK_CLK_RATE_ATCLKDBG / PIK_CLK_RATE_PCLKDBG, + }, +}; + +static const struct mod_pik_clock_rate rate_table_traceclk[1] = { + { + .rate = PIK_CLK_RATE_TRACECLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_TRACECLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sys_dmcclk[1] = { + { + .rate = PIK_CLK_RATE_DMC, + .source = MOD_PIK_CLOCK_DMCCLK_SOURCE_DDRPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static const struct fwk_element + pik_clock_element_table[CLOCK_PIK_IDX_COUNT + 1] = { + [CLOCK_SCC_IDX_IOFPGA_TMIF2XCLK] = { + .name = "IOFPGA TMIF2XCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->IOFPGA_TMIF2XCLK_CTRL, + .divsys_reg = &SCC->IOFPGA_TMIF2XCLK_DIV, + .rate_table = rate_table_iofpga_tmif2xclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_iofpga_tmif2xclk), + .initial_rate = SCC_CLK_RATE_IOFPGA_TMIF2XCLK, + }), + }, + [CLOCK_SCC_IDX_IOFPGA_TSIF2XCLK] = { + .name = "IOFPGA TSIF2XCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->IOFPGA_TSIF2XCLK_CTRL, + .divsys_reg = &SCC->IOFPGA_TSIF2XCLK_DIV, + .rate_table = rate_table_iofpga_tsif2xclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_iofpga_tsif2xclk), + .initial_rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK, + }), + }, + [CLOCK_SCC_IDX_SYSAPBCLK] = { + .name = "SYSAPBCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->SYSAPBCLK_CTRL, + .divsys_reg = &SCC->SYSAPBCLK_DIV, + .rate_table = rate_table_sysapbclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sysapbclk), + .initial_rate = SCC_CLK_RATE_SYSAPBCLK, + }), + }, + [CLOCK_SCC_IDX_SCPNICCLK] = { + .name = "SCPNICCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->SCPNICCLK_CTRL, + .divsys_reg = &SCC->SCPNICCLK_DIV, + .rate_table = rate_table_scpnicclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scpnicclk), + .initial_rate = SCC_CLK_RATE_SCPNICCLK, + }), + }, + [CLOCK_SCC_IDX_SCPI2CCLK] = { + .name = "SCPI2CCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->SCPI2CCLK_CTRL, + .divsys_reg = &SCC->SCPI2CCLK_DIV, + .rate_table = rate_table_scpi2cclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scpi2cclk), + .initial_rate = SCC_CLK_RATE_SCPI2CCLK, + }), + }, + [CLOCK_SCC_IDX_SCPQSPICLK] = { + .name = "SCPQSPICLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->SCPQSPICLK_CTRL, + .divsys_reg = &SCC->SCPQSPICLK_DIV, + .rate_table = rate_table_scpqspiclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scpqspiclk), + .initial_rate = SCC_CLK_RATE_SCPQSPICLK, + }), + }, + [CLOCK_SCC_IDX_SENSORCLK] = { + .name = "SENSORCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->SENSORCLK_CTRL, + .divsys_reg = &SCC->SENSORCLK_DIV, + .rate_table = rate_table_sensorclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sensorclk), + .initial_rate = SCC_CLK_RATE_SENSORCLK, + }), + }, + [CLOCK_SCC_IDX_MCPNICCLK] = { + .name = "MCPNICCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->MCPNICCLK_CTRL, + .divsys_reg = &SCC->MCPNICCLK_DIV, + .rate_table = rate_table_mcpnicclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcpnicclk), + .initial_rate = SCC_CLK_RATE_MCPNICCLK, + }), + }, + [CLOCK_SCC_IDX_MCPI2CCLK] = { + .name = "MCPI2CCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->MCPI2CCLK_CTRL, + .divsys_reg = &SCC->MCPI2CCLK_DIV, + .rate_table = rate_table_mcpi2cclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcpi2cclk), + .initial_rate = SCC_CLK_RATE_MCPI2CCLK, + }), + }, + [CLOCK_SCC_IDX_MCPQSPICLK] = { + .name = "MCPQSPICLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->MCPQSPICLK_CTRL, + .divsys_reg = &SCC->MCPQSPICLK_DIV, + .rate_table = rate_table_mcpqspiclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcpqspiclk), + .initial_rate = SCC_CLK_RATE_MCPQSPICLK, + }), + }, + [CLOCK_SCC_IDX_PCIEAXICLK] = { + .name = "PCIEAXICLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->PCIEAXICLK_CTRL, + .divsys_reg = &SCC->PCIEAXICLK_DIV, + .rate_table = rate_table_pcieaxiclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_pcieaxiclk), + .initial_rate = SCC_CLK_RATE_PCIEAXICLK, + }), + }, + [CLOCK_SCC_IDX_CCIXAXICLK] = { + .name = "CCIXAXICLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->CCIXAXICLK_CTRL, + .divsys_reg = &SCC->CCIXAXICLK_DIV, + .rate_table = rate_table_ccixaxiclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_ccixaxiclk), + .initial_rate = SCC_CLK_RATE_CCIXAXICLK, + }), + }, + [CLOCK_SCC_IDX_PCIEAPBCLK] = { + .name = "PCIEAPBCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->PCIEAPBCLK_CTRL, + .divsys_reg = &SCC->PCIEAPBCLK_DIV, + .rate_table = rate_table_pcieapbclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_pcieapbclk), + .initial_rate = SCC_CLK_RATE_PCIEAPBCLK, + }), + }, + [CLOCK_SCC_IDX_CCIXAPBCLK] = { + .name = "CCIXAPBCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCC->CCIXAPBCLK_CTRL, + .divsys_reg = &SCC->CCIXAPBCLK_DIV, + .rate_table = rate_table_ccixapbclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_ccixapbclk), + .initial_rate = SCC_CLK_RATE_CCIXAPBCLK, + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU0] = { + .name = "CLUS0_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(0)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(0)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_0, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0), + .initial_rate = PIK_CLK_RATE_CLUS0_CPU, + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU1] = { + .name = "CLUS0_CPU1", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(0)->CORECLK[1].CTRL, + .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV, + .modulator_reg = &PIK_CLUSTER(0)->CORECLK[1].MOD, + .rate_table = rate_table_cpu_group_0, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0), + .initial_rate = PIK_CLK_RATE_CLUS0_CPU, + }), + }, + [CLOCK_PIK_IDX_CLUS1_CPU0] = { + .name = "CLUS1_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(1)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(1)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_1, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1), + .initial_rate = PIK_CLK_RATE_CLUS1_CPU, + }), + }, + [CLOCK_PIK_IDX_CLUS1_CPU1] = { + .name = "CLUS1_CPU1", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(1)->CORECLK[1].CTRL, + .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV, + .modulator_reg = &PIK_CLUSTER(1)->CORECLK[1].MOD, + .rate_table = rate_table_cpu_group_1, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1), + .initial_rate = PIK_CLK_RATE_CLUS1_CPU, + }), + }, + [CLOCK_PIK_IDX_CLUS0] = { + .name = "CLUS0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(0)->CLUSCLK_CTRL, + .divext_reg = &PIK_CLUSTER(0)->CLUSCLK_DIV1, + .rate_table = rate_table_clus_0, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus_0), + .initial_rate = PIK_CLK_RATE_CLUS0, + }), + }, + [CLOCK_PIK_IDX_CLUS1] = { + .name = "CLUS1", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(1)->CLUSCLK_CTRL, + .divext_reg = &PIK_CLUSTER(1)->CLUSCLK_DIV1, + .rate_table = rate_table_clus_1, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus_1), + .initial_rate = PIK_CLK_RATE_CLUS1, + }), + }, + [CLOCK_PIK_IDX_CLUS0_PPU] = { + .name = "CLUS0 PPU", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(0)->PPUCLK_CTRL, + .divsys_reg = &PIK_CLUSTER(0)->PPUCLK_DIV1, + .rate_table = rate_table_clus_0_ppu, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus_0_ppu), + .initial_rate = PIK_CLK_RATE_CLUS0_PPU, + }), + }, + [CLOCK_PIK_IDX_CLUS1_PPU] = { + .name = "CLUS1 PPU", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(1)->PPUCLK_CTRL, + .divsys_reg = &PIK_CLUSTER(1)->PPUCLK_DIV1, + .rate_table = rate_table_clus_1_ppu, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus_1_ppu), + .initial_rate = PIK_CLK_RATE_CLUS1_PPU, + }), + }, + [CLOCK_PIK_IDX_CLUS0_PCLK] = { + .name = "CLUS0 PCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(0)->PCLK_CTRL, + .rate_table = rate_table_clus0_pclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus0_pclk), + .initial_rate = PIK_CLK_RATE_CLUS0_PCLK, + }), + }, + [CLOCK_PIK_IDX_CLUS0_ATCLK] = { + .name = "CLUS0 ATCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(0)->ATCLK_CTRL, + .rate_table = rate_table_clus0_atclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus0_atclk), + .initial_rate = PIK_CLK_RATE_CLUS0_ATCLK, + }), + }, + [CLOCK_PIK_IDX_CLUS0_GIC] = { + .name = "CLUS0 GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(0)->GICCLK_CTRL, + .rate_table = rate_table_clus0_gic, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus0_gic), + .initial_rate = PIK_CLK_RATE_CLUS0_GIC, + }), + }, + [CLOCK_PIK_IDX_CLUS0_AMBACLK] = { + .name = "CLUS0 AMBACLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(0)->AMBACLK_CTRL, + .rate_table = rate_table_clus0_ambaclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus0_ambaclk), + .initial_rate = PIK_CLK_RATE_CLUS0_AMBACLK, + }), + }, + [CLOCK_PIK_IDX_CLUS1_PCLK] = { + .name = "CLUS1 PCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(1)->PCLK_CTRL, + .rate_table = rate_table_clus1_pclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus1_pclk), + .initial_rate = PIK_CLK_RATE_CLUS1_PCLK, + }), + }, + [CLOCK_PIK_IDX_CLUS1_ATCLK] = { + .name = "CLUS1 ATCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(1)->ATCLK_CTRL, + .rate_table = rate_table_clus1_atclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus1_atclk), + .initial_rate = PIK_CLK_RATE_CLUS1_ATCLK, + }), + }, + [CLOCK_PIK_IDX_CLUS1_GIC] = { + .name = "CLUS1 GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(1)->GICCLK_CTRL, + .rate_table = rate_table_clus1_gic, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus1_gic), + .initial_rate = PIK_CLK_RATE_CLUS1_GIC, + }), + }, + [CLOCK_PIK_IDX_CLUS1_AMBACLK] = { + .name = "CLUS1 AMBACLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_CLUSTER(1)->AMBACLK_CTRL, + .rate_table = rate_table_clus1_ambaclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_clus1_ambaclk), + .initial_rate = PIK_CLK_RATE_CLUS1_AMBACLK, + }), + }, + [CLOCK_PIK_IDX_GPU] = { + .name = "GPU", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = true, + .control_reg = &PIK_GPU->GPUCLK_CTRL, + .divsys_reg = &PIK_GPU->GPUCLK_DIV1, + .divext_reg = &PIK_GPU->GPUCLK_DIV2, + .rate_table = rate_table_gpu, + .rate_count = FWK_ARRAY_SIZE(rate_table_gpu), + .initial_rate = PIK_CLK_RATE_GPU, + }), + }, + [CLOCK_PIK_IDX_DPU] = { + .name = "DPU", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = true, + .control_reg = &PIK_DPU->ACLKDP_CTRL, + .divsys_reg = &PIK_DPU->ACLKDP_DIV1, + .divext_reg = &PIK_DPU->ACLKDP_DIV2, + .rate_table = rate_table_dpu, + .rate_count = FWK_ARRAY_SIZE(rate_table_dpu), + .initial_rate = PIK_CLK_RATE_DPU, + }), + }, + [CLOCK_PIK_IDX_SCP_CORECLK] = { + .name = "SCP CORECLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SCP->CORECLK_CTRL, + .divsys_reg = &PIK_SCP->CORECLK_DIV1, + .rate_table = rate_table_scp_coreclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp_coreclk), + .initial_rate = PIK_CLK_RATE_SCP_CORECLK, + }), + }, + [CLOCK_PIK_IDX_SCP_AXICLK] = { + .name = "SCP AXICLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SCP->ACLK_CTRL, + .divsys_reg = &PIK_SCP->ACLK_DIV1, + .rate_table = rate_table_scp_aclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp_aclk), + .initial_rate = PIK_CLK_RATE_SCP_AXICLK, + }), + }, + [CLOCK_PIK_IDX_SCP_SYNCCLK] = { + .name = "SCP SYNCCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SCP->SYNCCLK_CTRL, + .divsys_reg = &PIK_SCP->SYNCCLK_DIV1, + .rate_table = rate_table_scp_syncclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp_syncclk), + .initial_rate = PIK_CLK_RATE_SCP_SYNCCLK, + }), + }, + [CLOCK_PIK_IDX_SYS_PPU] = { + .name = "SYS PPU", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->PPUCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->PPUCLK_DIV1, + .rate_table = rate_table_sys_ppu, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_ppu), + .initial_rate = PIK_CLK_RATE_SYS_PPU, + }), + }, + [CLOCK_PIK_IDX_INTERCONNECT] = { + .name = "INTERCONNECT", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->INTCLK_CTRL, + .divext_reg = &PIK_SYSTEM->INTCLK_DIV1, + .rate_table = rate_table_sys_intclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_intclk), + .initial_rate = PIK_CLK_RATE_INTERCONNECT, + }), + }, + [CLOCK_PIK_IDX_PCLKSCP] = { + .name = "PCLKSCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->PCLKSCP_CTRL, + .divsys_reg = &PIK_SYSTEM->PCLKSCP_DIV1, + .rate_table = rate_table_pclkscp, + .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), + .initial_rate = PIK_CLK_RATE_PCLKSCP, + }), + }, + [CLOCK_PIK_IDX_SYS_GIC] = { + .name = "SYS GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->GICCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->GICCLK_DIV1, + .rate_table = rate_table_gicclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), + .initial_rate = PIK_CLK_RATE_SYS_GIC, + }), + }, + [CLOCK_PIK_IDX_SYSPCLKDBG] = { + .name = "SYSPCLKDBG", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->SYSPCLKDBG_CTRL, + .divsys_reg = &PIK_SYSTEM->SYSPCLKDBG_DIV1, + .rate_table = rate_table_syspclkdbg, + .rate_count = FWK_ARRAY_SIZE(rate_table_syspclkdbg), + .initial_rate = PIK_CLK_RATE_SYSPCLKDBG, + }), + }, + [CLOCK_PIK_IDX_SYSPERCLK] = { + .name = "SYSPERCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->SYSPERCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->SYSPERCLK_DIV1, + .rate_table = rate_table_sysperclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk), + .initial_rate = PIK_CLK_RATE_SYSPERCLK, + }), + }, + [CLOCK_PIK_IDX_UART] = { + .name = "UART", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->UARTCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->UARTCLK_DIV1, + .rate_table = rate_table_uart, + .rate_count = FWK_ARRAY_SIZE(rate_table_uart), + .initial_rate = PIK_CLK_RATE_UART, + }), + }, + [CLOCK_PIK_IDX_TCU0] = { + .name = "TCU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->TCUCLK[0].TCUCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->TCUCLK[0].TCUCLK_DIV1, + .rate_table = rate_table_tcu0, + .rate_count = FWK_ARRAY_SIZE(rate_table_tcu0), + .initial_rate = PIK_CLK_RATE_TCU0, + }), + }, + [CLOCK_PIK_IDX_TCU1] = { + .name = "TCU1", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->TCUCLK[1].TCUCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->TCUCLK[1].TCUCLK_DIV1, + .rate_table = rate_table_tcu1, + .rate_count = FWK_ARRAY_SIZE(rate_table_tcu1), + .initial_rate = PIK_CLK_RATE_TCU1, + }), + }, + [CLOCK_PIK_IDX_TCU2] = { + .name = "TCU2", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->TCUCLK[2].TCUCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->TCUCLK[2].TCUCLK_DIV1, + .rate_table = rate_table_tcu2, + .rate_count = FWK_ARRAY_SIZE(rate_table_tcu2), + .initial_rate = PIK_CLK_RATE_TCU2, + }), + }, + [CLOCK_PIK_IDX_TCU3] = { + .name = "TCU3", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->TCUCLK[3].TCUCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->TCUCLK[3].TCUCLK_DIV1, + .rate_table = rate_table_tcu3, + .rate_count = FWK_ARRAY_SIZE(rate_table_tcu3), + .initial_rate = PIK_CLK_RATE_TCU3, + }), + }, + [CLOCK_PIK_IDX_ATCLKDBG] = { + .name = "ATCLKDBG", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_DEBUG->ATCLKDBG_CTRL, + .divsys_reg = &PIK_DEBUG->ATCLKDBG_DIV1, + .rate_table = rate_table_atclkdbg, + .rate_count = FWK_ARRAY_SIZE(rate_table_atclkdbg), + .initial_rate = PIK_CLK_RATE_ATCLKDBG, + }), + }, + [CLOCK_PIK_IDX_PCLKDBG] = { + .name = "PCLKDBG", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_SINGLE_SOURCE, + .is_group_member = false, + .control_reg = &PIK_DEBUG->PCLKDBG_CTRL, + .rate_table = rate_table_pclkdbg, + .rate_count = FWK_ARRAY_SIZE(rate_table_pclkdbg), + .initial_rate = PIK_CLK_RATE_PCLKDBG, + }), + }, + [CLOCK_PIK_IDX_TRACECLK] = { + .name = "TRACECLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_DEBUG->TRACECLK_CTRL, + .divsys_reg = &PIK_DEBUG->TRACECLK_DIV1, + .rate_table = rate_table_traceclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_traceclk), + .initial_rate = PIK_CLK_RATE_TRACECLK, + }), + }, + [CLOCK_PIK_IDX_DMC] = { + .name = "DMC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->DMCCLK_CTRL, + .divext_reg = &PIK_SYSTEM->DMCCLK_DIV1, + .rate_table = rate_table_sys_dmcclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_dmcclk), + .initial_rate = PIK_CLK_RATE_DMC, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) +{ + return pik_clock_element_table; +} + +const struct fwk_module_config config_pik_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), +}; -- GitLab From b757a513cbd3f2044e4a6c4287752b20bc7231c1 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:05:52 +0100 Subject: [PATCH 08/41] morello/morello_scp_soc: add cmsis RTX support Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Ie96d91bbc946934b16244f65e2a41bcbca96f192 --- product/morello/scp_ramfw_soc/RTX_Config.h | 56 ++++++++++++++++++++++ product/morello/scp_ramfw_soc/fmw_cmsis.h | 13 +++++ product/morello/scp_ramfw_soc/rtx_config.c | 56 ++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/RTX_Config.h create mode 100644 product/morello/scp_ramfw_soc/fmw_cmsis.h create mode 100644 product/morello/scp_ramfw_soc/rtx_config.c diff --git a/product/morello/scp_ramfw_soc/RTX_Config.h b/product/morello/scp_ramfw_soc/RTX_Config.h new file mode 100644 index 000000000..531d1ca03 --- /dev/null +++ b/product/morello/scp_ramfw_soc/RTX_Config.h @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RTX2 v5 configuration file. + * The file must be called RTX_Config.h as it is included by an RTX + * file in order to create an object file containing the configuration. + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +/* System */ +#define OS_DYNAMIC_MEM_SIZE 0 +#define OS_TICK_FREQ 1000 /* Hz */ +#define OS_ROBIN_ENABLE 0 +#define OS_ROBIN_TIMEOUT 0 +#define OS_ISR_FIFO_QUEUE 16 + +/* Thread */ +#define OS_THREAD_OBJ_MEM 0 +#define OS_THREAD_NUM 1 +#define OS_THREAD_DEF_STACK_NUM 0 +#define OS_THREAD_USER_STACK_SIZE 0 +#define OS_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_STACK_CHECK 1 +#define OS_STACK_WATERMARK 0 +#define OS_PRIVILEGE_MODE 1 + +/* Timer */ +#define OS_TIMER_OBJ_MEM 0 +#define OS_TIMER_NUM 1 +#define OS_TIMER_THREAD_PRIO 40 +#define OS_TIMER_THREAD_STACK_SIZE 200 +#define OS_TIMER_CB_QUEUE 4 + +/* Event flags */ +#define OS_EVFLAGS_OBJ_MEM 0 +#define OS_EVFLAGS_NUM 1 + +#define OS_MUTEX_OBJ_MEM 0 +#define OS_MUTEX_NUM 1 +#define OS_SEMAPHORE_OBJ_MEM 0 +#define OS_SEMAPHORE_NUM 1 +#define OS_MEMPOOL_OBJ_MEM 0 +#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_DATA_SIZE 0 +#define OS_MSGQUEUE_OBJ_MEM 0 +#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_DATA_SIZE 0 + +#endif /* RTX_CONFIG_H_ */ diff --git a/product/morello/scp_ramfw_soc/fmw_cmsis.h b/product/morello/scp_ramfw_soc/fmw_cmsis.h new file mode 100644 index 000000000..a00619334 --- /dev/null +++ b/product/morello/scp_ramfw_soc/fmw_cmsis.h @@ -0,0 +1,13 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include + +#endif /* FMW_CMSIS_H */ diff --git a/product/morello/scp_ramfw_soc/rtx_config.c b/product/morello/scp_ramfw_soc/rtx_config.c new file mode 100644 index 000000000..32af16307 --- /dev/null +++ b/product/morello/scp_ramfw_soc/rtx_config.c @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_system_clock.h" + +#include + +#include + +#include +#include + +/* + * Required by RTX to configure the SysTick timer. + */ +uint32_t SystemCoreClock = PIK_CLK_RATE_SCP_CORECLK; + +/* + * Idle thread + */ +__NO_RETURN void osRtxIdleThread(void *argument) +{ + while (true) { + __WFI(); + } +} + +/* + * OS error handler + */ +uint32_t osRtxErrorNotify(uint32_t code, void *object_id) +{ + osRtxIdleThread(object_id); +} + +uint32_t osRtxMemoryInit(void *mem, uint32_t size) +{ + return 1; +} + +void *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type) +{ + return fwk_mm_alloc(1, size); +} + +uint32_t osRtxMemoryFree(void *mem, void *block) +{ + fwk_mm_free(block); + + return 1; +} -- GitLab From f8a95554399d41a721491a648730997ba56846ca Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 09/41] morello/scp_ramfw_soc: add power management config Define and add configurations for system power domains, PPUs, etc. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I9f93d80275ad58922411bb845ded5adeaf49625f --- product/morello/include/morello_scc_reg.h | 1 + .../scp_ramfw_soc/config_power_domain.c | 251 ++++++++++++++++++ .../scp_ramfw_soc/config_power_domain.h | 31 +++ product/morello/scp_ramfw_soc/config_ppu_v0.c | 40 +++ product/morello/scp_ramfw_soc/config_ppu_v0.h | 13 + product/morello/scp_ramfw_soc/config_ppu_v1.c | 213 +++++++++++++++ .../scp_ramfw_soc/config_system_power.c | 94 +++++++ 7 files changed, 643 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_power_domain.c create mode 100644 product/morello/scp_ramfw_soc/config_power_domain.h create mode 100644 product/morello/scp_ramfw_soc/config_ppu_v0.c create mode 100644 product/morello/scp_ramfw_soc/config_ppu_v0.h create mode 100644 product/morello/scp_ramfw_soc/config_ppu_v1.c create mode 100644 product/morello/scp_ramfw_soc/config_system_power.c diff --git a/product/morello/include/morello_scc_reg.h b/product/morello/include/morello_scc_reg.h index 401020a0b..cfb835a40 100644 --- a/product/morello/include/morello_scc_reg.h +++ b/product/morello/include/morello_scc_reg.h @@ -232,4 +232,5 @@ struct scc_reg { #define SCC_SYS_MAN_RESET_CCIX_POS UINT32_C(11) #define SCC_SYS_MAN_RESET_PCIE_POS UINT32_C(10) +#define SCC_BOOTGPR1_L3_CACHE_EN_MASK UINT32_C(0x10) #endif /* MORELLO_SCC_REG_H */ diff --git a/product/morello/scp_ramfw_soc/config_power_domain.c b/product/morello/scp_ramfw_soc/config_power_domain.c new file mode 100644 index 000000000..2b5479283 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_power_domain.c @@ -0,0 +1,251 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Maximum power domain name size including the null terminator */ +#define PD_NAME_SIZE 16 + +/* Mask of the allowed states for the systop power domain */ +static const uint32_t systop_allowed_state_mask_table[2] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK | + (1 << MOD_SYSTEM_POWER_POWER_STATE_SLEEP0) | + (1 << MOD_SYSTEM_POWER_POWER_STATE_SLEEP1) +}; + +/* + * Mask of the allowed states for the top level power domains + * (but the cluster power domains) depending on the system states. + */ +static const uint32_t toplevel_allowed_state_mask_table[5] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK +}; + +/* + * Mask of the allowed states for the cluster power domain depending on the + * system states. + */ +static const uint32_t cluster_pd_allowed_state_mask_table[5] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MOD_PD_STATE_ON] = MORELLO_CLUSTER_VALID_STATE_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK +}; + +/* Mask of the allowed states for a core depending on the cluster states. */ +static const uint32_t core_pd_allowed_state_mask_table[6] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MOD_PD_STATE_ON] = MORELLO_CORE_VALID_STATE_MASK, + [MOD_PD_STATE_SLEEP] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MORELLO_POWER_DOMAIN_STATE_FUNC_RET] = MORELLO_CORE_VALID_STATE_MASK, + [MORELLO_POWER_DOMAIN_STATE_MEM_RET] = MOD_PD_STATE_OFF_MASK +}; + +/* Power module specific configuration data (none) */ +static const struct mod_power_domain_config morello_power_domain_config = { 0 }; + +/* Power domain element table pointer */ +struct fwk_element *element_table = NULL; + +/* Power domain element configuration table pointer */ +struct mod_power_domain_element_config *pd_config_table = NULL; + +/* + * The SCP's view of PD tree in a single chip mode looks like below: + * + * -------------SYSTOP0---------------- + * / / | \ \ + * / / | \ \ + * / / | \ \ + * CLUS0 CLUS1 DBGTOP0 GPUTOP0 DPUTOP0 + * / \ / \ + * CPU0--CPU1--CPU2--CPU3 + * + */ + +static struct fwk_element + morello_pd_single_chip_element_table[PD_SINGLE_CHIP_IDX_COUNT + 1] = { + [PD_SINGLE_CHIP_IDX_CLUS0CORE0] = { + .name = "CLUS0CORE0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CORE, + .parent_idx = PD_SINGLE_CHIP_IDX_CLUSTER0, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = core_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_CLUS0CORE1] = { + .name = "CLUS0CORE1", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CORE, + .parent_idx = PD_SINGLE_CHIP_IDX_CLUSTER0, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 1), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = core_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_CLUS1CORE0] = { + .name = "CLUS1CORE0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CORE, + .parent_idx = PD_SINGLE_CHIP_IDX_CLUSTER1, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 2), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = core_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_CLUS1CORE1] = { + .name = "CLUS1CORE1", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CORE, + .parent_idx = PD_SINGLE_CHIP_IDX_CLUSTER1, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 3), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = core_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_CLUSTER0] = { + .name = "CLUS0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .parent_idx = PD_SINGLE_CHIP_IDX_SYSTOP0, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 4), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_CLUSTER1] = { + .name = "CLUS1", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .parent_idx = PD_SINGLE_CHIP_IDX_SYSTOP0, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 5), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_DBGTOP0] = { + .name = "DBGTOP0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_DEVICE_DEBUG, + .parent_idx = PD_SINGLE_CHIP_IDX_SYSTOP0, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PPU_V0, PPU_V0_ELEMENT_IDX_DBGTOP), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V0, 0), + .allowed_state_mask_table = toplevel_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(toplevel_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_GPUTOP0] = { + .name = "GPUTOP0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_DEVICE, + .parent_idx = PD_SINGLE_CHIP_IDX_SYSTOP0, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 8), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = toplevel_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(toplevel_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_DPUTOP0] = { + .name = "DPUTOP0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_DEVICE, + .parent_idx = PD_SINGLE_CHIP_IDX_SYSTOP0, + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 9), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = toplevel_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(toplevel_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_SYSTOP0] = { + .name = "SYSTOP0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .parent_idx = PD_SINGLE_CHIP_IDX_NONE, + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) + }), + }, + [PD_SINGLE_CHIP_IDX_COUNT] = { 0 }, +}; + +/* + * Function definitions with internal linkage + */ +static const struct fwk_element *morello_power_domain_get_element_table( + fwk_id_t module_id) +{ + return morello_pd_single_chip_element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_power_domain = { + .elements = + FWK_MODULE_DYNAMIC_ELEMENTS(morello_power_domain_get_element_table), + .data = &morello_power_domain_config, +}; diff --git a/product/morello/scp_ramfw_soc/config_power_domain.h b/product/morello/scp_ramfw_soc/config_power_domain.h new file mode 100644 index 000000000..fa718afe9 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_power_domain.h @@ -0,0 +1,31 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_POWER_DOMAIN_H +#define CONFIG_POWER_DOMAIN_H + +#include + +/* + * Power domain indices in single chip use case + */ +enum pd_single_chip_idx { + PD_SINGLE_CHIP_IDX_CLUS0CORE0, + PD_SINGLE_CHIP_IDX_CLUS0CORE1, + PD_SINGLE_CHIP_IDX_CLUS1CORE0, + PD_SINGLE_CHIP_IDX_CLUS1CORE1, + PD_SINGLE_CHIP_IDX_CLUSTER0, + PD_SINGLE_CHIP_IDX_CLUSTER1, + PD_SINGLE_CHIP_IDX_DBGTOP0, + PD_SINGLE_CHIP_IDX_GPUTOP0, + PD_SINGLE_CHIP_IDX_DPUTOP0, + PD_SINGLE_CHIP_IDX_SYSTOP0, + PD_SINGLE_CHIP_IDX_COUNT, + PD_SINGLE_CHIP_IDX_NONE = UINT32_MAX +}; + +#endif /* CONFIG_POWER_DOMAIN_H */ diff --git a/product/morello/scp_ramfw_soc/config_ppu_v0.c b/product/morello/scp_ramfw_soc/config_ppu_v0.c new file mode 100644 index 000000000..5785728f7 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_ppu_v0.c @@ -0,0 +1,40 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include + +#include + +static struct fwk_element ppu_v0_element_table[PPU_V0_ELEMENT_IDX_COUNT + 1] = { + [PPU_V0_ELEMENT_IDX_DBGTOP] = { + .name = "DBGTOP", + .data = &((struct mod_ppu_v0_pd_config) { + .pd_type = MOD_PD_TYPE_DEVICE_DEBUG, + .ppu.reg_base = SCP_PPU_DEBUG_BASE, + .default_power_on = true, + }), + }, + [PPU_V0_ELEMENT_IDX_COUNT] = { 0 }, /* Termination entry */ +}; + +static const struct fwk_element *ppu_v0_get_element_table(fwk_id_t module_id) +{ + return ppu_v0_element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_ppu_v0 = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(ppu_v0_get_element_table), +}; diff --git a/product/morello/scp_ramfw_soc/config_ppu_v0.h b/product/morello/scp_ramfw_soc/config_ppu_v0.h new file mode 100644 index 000000000..81789031d --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_ppu_v0.h @@ -0,0 +1,13 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_PPU_V0_H +#define CONFIG_PPU_V0_H + +enum ppu_v0_element_idx { PPU_V0_ELEMENT_IDX_DBGTOP, PPU_V0_ELEMENT_IDX_COUNT }; + +#endif /* CONFIG_PPU_V0_H */ diff --git a/product/morello/scp_ramfw_soc/config_ppu_v1.c b/product/morello/scp_ramfw_soc/config_ppu_v1.c new file mode 100644 index 000000000..f1fcebdca --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_ppu_v1.c @@ -0,0 +1,213 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_power_domain.h" +#include "morello_core.h" +#include "morello_scc_reg.h" +#include "morello_scp_mmap.h" +#include "morello_scp_pik.h" + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Maximum PPU core name size including the null terminator */ +#define PPU_CORE_NAME_SIZE 16 + +/* Maximum PPU cluster name size including the null terminator */ +#define PPU_CLUS_NAME_SIZE 8 + +/* Identifiers for the static table */ +enum ppu_v1_static_element_idx { + PPU_V1_ELEMENT_IDX_SYS0, + PPU_V1_ELEMENT_IDX_SYS1, + PPU_V1_ELEMENT_IDX_GPUTOP0, + PPU_V1_ELEMENT_IDX_DPUTOP0, + PPU_V1_ELEMENT_IDX_COUNT +}; + +/* Lookup table for translating cluster indicies into CMN600 node IDs */ +static const unsigned int cluster_idx_to_node_id[2] = { 192, 140 }; + +/* Module configuration data */ +static struct mod_ppu_v1_config ppu_v1_config_data = { + .pd_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), +}; + +static struct fwk_element + ppu_v1_static_element_table[PPU_V1_ELEMENT_IDX_COUNT] = { + [PPU_V1_ELEMENT_IDX_SYS0] = { + .name = "SYS0", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS0_BASE, + .observer_id = FWK_ID_NONE_INIT, + .default_power_on = true, + }), + }, + [PPU_V1_ELEMENT_IDX_SYS1] = { + .name = "SYS1", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS1_BASE, + .observer_id = FWK_ID_NONE_INIT, + .default_power_on = true, + }), + }, + [PPU_V1_ELEMENT_IDX_GPUTOP0] = { + .name = "GPUTOP0", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_DEVICE, + .ppu.reg_base = SCP_PPU_GPU_BASE, + .observer_id = FWK_ID_NONE_INIT, + .default_power_on = true, + }), + }, + [PPU_V1_ELEMENT_IDX_DPUTOP0] = { + .name = "DPUTOP0", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_DEVICE, + .ppu.reg_base = SCP_PPU_DPU_BASE, + .observer_id = FWK_ID_NONE_INIT, + .default_power_on = true, + }), + }, +}; + +static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) +{ + struct fwk_element *element_table, *element; + struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; + unsigned int core_idx; + unsigned int cluster_idx; + unsigned int core_count; + unsigned int cluster_count; + unsigned int core_element_count = 0; + + core_count = morello_core_get_core_count(); + cluster_count = morello_core_get_cluster_count(); + + fwk_assert(cluster_count == FWK_ARRAY_SIZE(cluster_idx_to_node_id)); + + /* + * Allocate element descriptors based on: + * Number of cores + * + Number of cluster descriptors + * + Number of system power domain descriptors + * + 1 terminator descriptor + */ + element_table = fwk_mm_calloc( + core_count + cluster_count + + FWK_ARRAY_SIZE(ppu_v1_static_element_table) + 1, + sizeof(struct fwk_element)); + if (element_table == NULL) { + return NULL; + } + + pd_config_table = fwk_mm_calloc( + core_count + cluster_count, sizeof(struct mod_ppu_v1_pd_config)); + if (pd_config_table == NULL) { + return NULL; + } + + for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { + for (core_idx = 0; + core_idx < morello_core_get_core_per_cluster_count(cluster_idx); + core_idx++) { + element = &element_table[core_element_count]; + pd_config = &pd_config_table[core_element_count]; + + element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); + if (element->name == NULL) { + return NULL; + } + + (void)snprintf( + (char *)element->name, + PPU_CORE_NAME_SIZE, + "CLUS%uCORE%u", + (uint8_t)cluster_idx, + (uint8_t)core_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CORE; + pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(cluster_idx, core_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->cluster_id = FWK_ID_ELEMENT( + FWK_MODULE_IDX_PPU_V1, (core_count + cluster_idx)); + pd_config->observer_id = FWK_ID_NONE; + core_element_count++; + } + + element = &element_table[core_count + cluster_idx]; + pd_config = &pd_config_table[core_count + cluster_idx]; + + element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); + if (element->name == NULL) { + return NULL; + } + + (void)snprintf( + (char *)element->name, + PPU_CLUS_NAME_SIZE, + "CLUS%u", + (uint8_t)cluster_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CLUSTER; + pd_config->ppu.reg_base = SCP_PPU_CLUSTER_BASE(cluster_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->observer_id = fwk_module_id_cmn_skeena; + pd_config->observer_api = FWK_ID_API( + FWK_MODULE_IDX_CMN_SKEENA, MOD_CMN_SKEENA_API_IDX_PPU_OBSERVER); + pd_config->post_ppu_on_param = + (void *)&cluster_idx_to_node_id[cluster_idx]; + pd_config->opmode = (SCC->BOOT_GPR1 & SCC_BOOTGPR1_L3_CACHE_EN_MASK) ? + PPU_V1_OPMODE_04 : + PPU_V1_OPMODE_00; + } + + (void)memcpy( + &element_table[core_count + cluster_count], + ppu_v1_static_element_table, + sizeof(ppu_v1_static_element_table)); + + /* + * Configure pd_source_id with the SYSTOP identifier from the power domain + * module which is dynamically defined based on the number of cores. + */ + ppu_v1_config_data.pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, PD_SINGLE_CHIP_IDX_SYSTOP0); + + return element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_ppu_v1 = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(ppu_v1_get_element_table), + .data = &ppu_v1_config_data, +}; diff --git a/product/morello/scp_ramfw_soc/config_system_power.c b/product/morello/scp_ramfw_soc/config_system_power.c new file mode 100644 index 000000000..e51f745b7 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_system_power.c @@ -0,0 +1,94 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +static const uint8_t system_power_to_sys_ppu0_state[4] = { + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_OFF, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, +}; + +static const uint8_t system_power_to_sys_ppu1_state[4] = { + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_ON, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, +}; + +static struct fwk_element system_power_element_table[3] = { + [0] = { + .name = "SYS-PPU-0", + .data = &((struct mod_system_power_dev_config) { + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu0_state, + }), + }, + + [1] = { + .name = "SYS-PPU-1", + .data = &((struct mod_system_power_dev_config) { + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu1_state, + }), + }, + + [2] = { 0 }, /* Termination description */ +}; + +static struct mod_system_power_config system_power_config = { + .soc_wakeup_irq = SCP_EXT_IRQ, + + /* System driver */ + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MORELLO_SYSTEM), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MORELLO_SYSTEM, + MOD_MORELLO_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER), + + /* Initial system state */ + .initial_system_power_state = MOD_PD_STATE_OFF, +}; + +static const struct fwk_element *morello_system_get_element_table( + fwk_id_t unused) +{ + struct mod_system_power_dev_config *dev_config_table; + unsigned int ppu_idx_base; + unsigned int i; + + /* The system PPUs are placed after the cores, clusters & GPU, DPU PPUs */ + ppu_idx_base = + morello_core_get_core_count() + morello_core_get_cluster_count(); + + for (i = 0; i < (FWK_ARRAY_SIZE(system_power_element_table) - 1); i++) { + dev_config_table = + (struct mod_system_power_dev_config *)system_power_element_table[i] + .data; + dev_config_table->sys_ppu_id = + fwk_id_build_element_id(fwk_module_id_ppu_v1, ppu_idx_base + i); + } + + return system_power_element_table; +} + +const struct fwk_module_config config_system_power = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(morello_system_get_element_table), + .data = &system_power_config, +}; -- GitLab From f5316f9fd701b159184fa09c9d83b974053a969f Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 10/41] morello/scp_ramfw_soc: add MHU and SDS config data Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Ib6181bbc97d9e74979494d2cbb7abc7e28ef9aec --- product/morello/scp_ramfw_soc/config_mhu.c | 58 ++++++++++ product/morello/scp_ramfw_soc/config_sds.c | 128 +++++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_mhu.c create mode 100644 product/morello/scp_ramfw_soc/config_sds.c diff --git a/product/morello/scp_ramfw_soc/config_mhu.c b/product/morello/scp_ramfw_soc/config_mhu.c new file mode 100644 index 000000000..91a96dae4 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_mhu.c @@ -0,0 +1,58 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include + +#include + +static const struct fwk_element + mhu_element_table[MORELLO_MHU_DEVICE_IDX_COUNT + 1] = { + [MORELLO_MHU_DEVICE_IDX_S_CLUS0] = { + .name = "MHU_S_CLUSTER_0", + .sub_element_count = 1, + .data = &((struct mod_mhu_device_config) { + .irq = MHU_AP_SEC_IRQ, + .in = MHU_AP_TO_SCP_S(0), + .out = MHU_SCP_TO_AP_S(0), + }), + }, + [MORELLO_MHU_DEVICE_IDX_NS_CLUS0] = { + .name = "MHU_NS_CLUSTER_0", + .sub_element_count = 1, + .data = &((struct mod_mhu_device_config) { + .irq = MHU_AP_NONSEC_IRQ, + .in = MHU_AP_TO_SCP_NS(0), + .out = MHU_SCP_TO_AP_NS(0), + }), + }, + [MORELLO_MHU_DEVICE_IDX_S_MCP] = { + .name = "MHU_S_MCP", + .sub_element_count = 1, + .data = &((struct mod_mhu_device_config) { + .irq = MHU_MCP_SEC_IRQ, + .in = MHU_MCP_TO_SCP_S, + .out = MHU_SCP_TO_MCP_S, + }), + }, + [MORELLO_MHU_DEVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *mhu_get_element_table(fwk_id_t module_id) +{ + return mhu_element_table; +} + +struct fwk_module_config config_mhu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(mhu_get_element_table), +}; diff --git a/product/morello/scp_ramfw_soc/config_sds.c b/product/morello/scp_ramfw_soc/config_sds.c new file mode 100644 index 000000000..c3a22e6d4 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_sds.c @@ -0,0 +1,128 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +static const uint32_t version_packed = FWK_BUILD_VERSION; +static const uint32_t feature_flags = 0x00000000; + +static const struct mod_sds_region_desc + sds_module_regions[MORELLO_SDS_REGION_COUNT] = { + [MORELLO_SDS_REGION_SECURE] = { + .base = (void*)SCP_SDS_SECURE_BASE, + .size = SCP_SDS_SECURE_SIZE, + }, +#ifdef BUILD_MODE_DEBUG + [MORELLO_SDS_REGION_NONSECURE] = { + .base = (void *)SCP_SDS_NONSECURE_BASE, + .size = SCP_SDS_NONSECURE_SIZE, + }, +#endif +}; + +static_assert( + FWK_ARRAY_SIZE(sds_module_regions) == MORELLO_SDS_REGION_COUNT, + "Mismatch between number of SDS regions and number of regions " + "provided by the SDS configuration."); + +static const struct mod_sds_config sds_module_config = { + .regions = sds_module_regions, + .region_count = MORELLO_SDS_REGION_COUNT, + .clock_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT) +}; + +static struct fwk_element sds_element_table[8] = { + { + .name = "CPU Info", + .data = &((struct mod_sds_structure_desc){ + .id = MORELLO_SDS_CPU_INFO, + .size = MORELLO_SDS_CPU_INFO_SIZE, + .finalize = true, + }), + }, + { + .name = "Firmware version", + .data = &((struct mod_sds_structure_desc){ + .id = MORELLO_SDS_FIRMWARE_VERSION, + .size = MORELLO_SDS_FIRMWARE_VERSION_SIZE, + .payload = &version_packed, + .finalize = true, + }), + }, + { + .name = "Reset Syndrome", + .data = &((struct mod_sds_structure_desc){ + .id = MORELLO_SDS_RESET_SYNDROME, + .size = MORELLO_SDS_RESET_SYNDROME_SIZE, + .payload = (void *)(&PIK_SCP->RESET_SYNDROME), + .finalize = true, + }), + }, + { + .name = "Feature Availability", + .data = &((struct mod_sds_structure_desc){ + .id = MORELLO_SDS_FEATURE_AVAILABILITY, + .size = MORELLO_SDS_FEATURE_AVAILABILITY_SIZE, + .payload = &feature_flags, + .finalize = true, + }), + }, + { + .name = "Platform Info", + .data = &((struct mod_sds_structure_desc){ + .id = MORELLO_SDS_PLATFORM_INFO, + .size = MORELLO_SDS_PLATFORM_INFO_SIZE, + .finalize = true, + }), + }, + { + .name = "Boot Counters", + .data = &((struct mod_sds_structure_desc){ + .id = MORELLO_SDS_CPU_BOOTCTR, + .size = MORELLO_SDS_CPU_BOOTCTR_SIZE, + .finalize = true, + }), + }, + { + .name = "CPU Flags", + .data = &((struct mod_sds_structure_desc){ + .id = MORELLO_SDS_CPU_FLAGS, + .size = MORELLO_SDS_CPU_FLAGS_SIZE, + .finalize = true, + }), + }, + { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) +{ + static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size"); + + return sds_element_table; +} + +struct fwk_module_config config_sds = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(sds_get_element_table), + .data = &sds_module_config, +}; -- GitLab From 2ed3cf2613510945d7be9d54337e37a6382a1579 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 11/41] morello/scp_ramfw_soc: add configs for SCMI protocols Add configuration data for a few of the supported SCMI protocols - SCMI Base, System power and Power domain Management. Also, add configuration data for SMT module. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I7e85f2c61499cb53efb3b6e58787785b72134e2a --- product/morello/scp_ramfw_soc/config_scmi.c | 101 ++++++++++++++++ .../scp_ramfw_soc/config_scmi_power_domain.c | 11 ++ .../scp_ramfw_soc/config_scmi_system_power.c | 17 +++ product/morello/scp_ramfw_soc/config_smt.c | 112 ++++++++++++++++++ 4 files changed, 241 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_scmi.c create mode 100644 product/morello/scp_ramfw_soc/config_scmi_power_domain.c create mode 100644 product/morello/scp_ramfw_soc/config_scmi_system_power.c create mode 100644 product/morello/scp_ramfw_soc/config_smt.c diff --git a/product/morello/scp_ramfw_soc/config_scmi.c b/product/morello/scp_ramfw_soc/config_scmi.c new file mode 100644 index 000000000..3944d0f78 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_scmi.c @@ -0,0 +1,101 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include + +static const struct fwk_element + service_table[SCP_MORELLO_SCMI_SERVICE_IDX_COUNT + 1] = { + [SCP_MORELLO_SCMI_SERVICE_IDX_PSCI] = { + .name = "PSCI", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_MORELLO_SCMI_SERVICE_IDX_PSCI), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_OSPM] = { + .name = "OSPM", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_MORELLO_SCMI_SERVICE_IDX_OSPM), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_MCP] = { + .name = "MCP", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_MORELLO_SCMI_SERVICE_IDX_MCP), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NONE_INIT, + .scmi_agent_id = SCP_SCMI_AGENT_ID_MCP, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_COUNT] = { 0 } +}; + +static const struct fwk_element *get_service_table(fwk_id_t module_id) +{ + return service_table; +} + +static struct mod_scmi_agent agent_table[] = { + [SCP_SCMI_AGENT_ID_OSPM] = { + .type = SCMI_AGENT_TYPE_OSPM, + .name = "OSPM", + }, + [SCP_SCMI_AGENT_ID_PSCI] = { + .type = SCMI_AGENT_TYPE_PSCI, + .name = "PSCI", + }, + [SCP_SCMI_AGENT_ID_MCP] = { + .type = SCMI_AGENT_TYPE_MANAGEMENT, + .name = "MANAGEMENT", + }, +}; + +const struct fwk_module_config config_scmi = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_service_table), + .data = &((struct mod_scmi_config){ + .protocol_count_max = 8, + .agent_count = FWK_ARRAY_SIZE(agent_table) - 1, + .agent_table = agent_table, + .vendor_identifier = "arm", + .sub_vendor_identifier = "arm", + }), +}; diff --git a/product/morello/scp_ramfw_soc/config_scmi_power_domain.c b/product/morello/scp_ramfw_soc/config_scmi_power_domain.c new file mode 100644 index 000000000..cacaf67ea --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_scmi_power_domain.c @@ -0,0 +1,11 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* No elements, no module configuration data */ +struct fwk_module_config config_scmi_power_domain = { 0 }; diff --git a/product/morello/scp_ramfw_soc/config_scmi_system_power.c b/product/morello/scp_ramfw_soc/config_scmi_system_power.c new file mode 100644 index 000000000..4d2c54772 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_scmi_system_power.c @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +const struct fwk_module_config config_scmi_system_power = { + .data = &((struct mod_scmi_system_power_config){ + .system_view = MOD_SCMI_SYSTEM_VIEW_FULL, + .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0 }), +}; diff --git a/product/morello/scp_ramfw_soc/config_smt.c b/product/morello/scp_ramfw_soc/config_smt.c new file mode 100644 index 000000000..da4c92e70 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_smt.c @@ -0,0 +1,112 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + +static const struct fwk_element smt_element_table[] = { + [SCP_MORELLO_SCMI_SERVICE_IDX_PSCI] = { + .name = "PSCI", + .data = &((struct mod_smt_channel_config) { + .type = + MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX | + MOD_SMT_POLICY_SECURE, + .mailbox_address = + SCP_AP_SHARED_SECURE_RAM, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU, + MORELLO_MHU_DEVICE_IDX_S_CLUS0, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU, + 0), + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_OSPM] = { + .name = "OSPM", + .data = &((struct mod_smt_channel_config) { + .type = + MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX, + .mailbox_address = + SCP_AP_SHARED_NONSECURE_RAM, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU, + MORELLO_MHU_DEVICE_IDX_NS_CLUS0, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU, + 0), + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_MCP] = { + .name = "MCP", + .data = &((struct mod_smt_channel_config) { + .type = + MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX | + MOD_SMT_POLICY_SECURE, + .mailbox_address = + SCP_MCP_SHARED_SECURE_RAM, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU, + MORELLO_MHU_DEVICE_IDX_S_MCP, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU, + 0), + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *smt_get_element_table(fwk_id_t module_id) +{ + unsigned int idx; + struct mod_smt_channel_config *config; + + for (idx = 0; idx < SCP_MORELLO_SCMI_SERVICE_IDX_COUNT; idx++) { + config = (struct mod_smt_channel_config *)(smt_element_table[idx].data); + config->pd_source_id = FWK_ID_ELEMENT( + FWK_MODULE_IDX_POWER_DOMAIN, PD_SINGLE_CHIP_IDX_SYSTOP0); + } + + return smt_element_table; +} + +const struct fwk_module_config config_smt = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(smt_get_element_table), +}; -- GitLab From 7dd890be1b8ebc9bfbcd68812010951cba83c28c Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 12/41] morello/scp_ramfw_soc: add pl011 config data Add configuration data for PL011 UART module which is used as a console for firmware logs. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Iad75b1ca83072b9e04b99ae65a3a88847fbca4d3 --- product/morello/scp_ramfw_soc/config_pl011.c | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_pl011.c diff --git a/product/morello/scp_ramfw_soc/config_pl011.c b/product/morello/scp_ramfw_soc/config_pl011.c new file mode 100644 index 000000000..88137ed50 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_pl011.c @@ -0,0 +1,36 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_scp_mmap.h" +#include "morello_system_clock.h" + +#include + +#include +#include +#include + +/* + * PL011 module + */ +struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS({ + [0] = { + .name = "SCP-UART", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_NONE_INIT, + .pd_id = FWK_ID_NONE_INIT, + }, + }, + + [1] = { 0 }, + }), +}; -- GitLab From d71a910b23f2c29f665656806cdaa80901e63147 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 13/41] morello/scp_ramfw_soc: add timer related config data Add configuration data for the timer hal and generic timer modules. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I361656e1161087b668eeb308e931e93cc1cc3c0d --- product/morello/include/morello_alarm_idx.h | 1 + product/morello/scp_ramfw_soc/config_timer.c | 72 ++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_timer.c diff --git a/product/morello/include/morello_alarm_idx.h b/product/morello/include/morello_alarm_idx.h index 9453d4173..19f8bfd59 100644 --- a/product/morello/include/morello_alarm_idx.h +++ b/product/morello/include/morello_alarm_idx.h @@ -7,6 +7,7 @@ /* Alarm indices */ enum morello_alarm_idx { + MORELLO_PCIE_ALARM_IDX, #ifdef BUILD_HAS_DEBUGGER MORELLO_DEBUGGER_CLI_ALARM_IDX, #endif diff --git a/product/morello/scp_ramfw_soc/config_timer.c b/product/morello/scp_ramfw_soc/config_timer.c new file mode 100644 index 000000000..dbc03bcbd --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_timer.c @@ -0,0 +1,72 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_alarm_idx.h" + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +/* + * Generic timer driver config + */ +static const struct fwk_element gtimer_dev_table[2] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config){ + .hw_timer = SCP_REFCLK_CNTBASE0_BASE, + .hw_counter = SCP_REFCLK_CNTCTL_BASE, + .control = SCP_REFCLK_CNTCONTROL_BASE, + .frequency = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT) }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *gtimer_get_dev_table(fwk_id_t module_id) +{ + return gtimer_dev_table; +} + +const struct fwk_module_config config_gtimer = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(gtimer_get_dev_table), +}; + +/* + * Timer HAL config + */ +static const struct fwk_element timer_dev_table[2] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config) { + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = TIMREFCLK_IRQ, + }), + .sub_element_count = MORELLO_ALARM_IDX_COUNT, /* Number of alarms */ + }, + [1] = { 0 }, +}; + +static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) +{ + return timer_dev_table; +} + +const struct fwk_module_config config_timer = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(timer_get_dev_table), +}; -- GitLab From 86e1039d41a81af88dc9ec74b614b8dcaaedb0c3 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 14/41] morello/scp_ramfw_soc: add ssc and system_info config data Add configurations for ssc and system_info modules. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I98a73ca81c9d26bd05499215fc949866e3c54e77 --- product/morello/scp_ramfw_soc/config_ssc.c | 23 ++++++++++++++++++ .../scp_ramfw_soc/config_system_info.c | 24 +++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_ssc.c create mode 100644 product/morello/scp_ramfw_soc/config_system_info.c diff --git a/product/morello/scp_ramfw_soc/config_ssc.c b/product/morello/scp_ramfw_soc/config_ssc.c new file mode 100644 index 000000000..ba2bd9d49 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_ssc.c @@ -0,0 +1,23 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_scp_mmap.h" + +#include + +#include + +#include + +const struct fwk_module_config config_ssc = { + .data = + &(struct mod_ssc_config){ + .ssc_base = SCP_SSC_BASE, + .ssc_debug_cfg_set = 0xFF, + .product_name = "Morello SOC Platform", + }, +}; diff --git a/product/morello/scp_ramfw_soc/config_system_info.c b/product/morello/scp_ramfw_soc/config_system_info.c new file mode 100644 index 000000000..9431e5bcc --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_system_info.c @@ -0,0 +1,24 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include + +#include + +const struct fwk_module_config config_system_info = { + .data = &((struct mod_system_info_config){ + .system_info_driver_module_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SSC), + .system_info_driver_data_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SSC, + MOD_SSC_SYSTEM_INFO_DRIVER_DATA_API_IDX), + }), +}; -- GitLab From 1597b8e729602e96d0f4c9cdddb90817ed7ac7ea Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 15/41] morello/scp_ramfw_soc: add scmi clock and scmi mgmt configs Add configuration data for scmi clock and scmi management protocols. SCMI management protocol is used for facilitating SCMI communication between SCP and MCP. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I357d09daa3b174f8865d0ca7ca305387a6f2e17c --- .../morello/scp_ramfw_soc/config_scmi_clock.c | 45 +++++++++++++++++++ .../scp_ramfw_soc/config_scmi_management.c | 11 +++++ 2 files changed, 56 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_scmi_clock.c create mode 100644 product/morello/scp_ramfw_soc/config_scmi_management.c diff --git a/product/morello/scp_ramfw_soc/config_scmi_clock.c b/product/morello/scp_ramfw_soc/config_scmi_clock.c new file mode 100644 index 000000000..ebe96db6d --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_scmi_clock.c @@ -0,0 +1,45 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_scp_scmi.h" + +#include + +#include +#include +#include +#include + +static const struct mod_scmi_clock_device agent_device_table_ospm[2] = { + { + /* DPU */ + .element_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_DPU), + }, + { + /* PIXEL_0 */ + .element_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_PIXEL_0), + }, +}; + +static const struct mod_scmi_clock_agent + agent_table[SCP_SCMI_AGENT_ID_COUNT] = { + [SCP_SCMI_AGENT_ID_PSCI] = { 0 /* No access */ }, + [SCP_SCMI_AGENT_ID_OSPM] = { + .device_table = agent_device_table_ospm, + .device_count = FWK_ARRAY_SIZE(agent_device_table_ospm), + }, +}; + +const struct fwk_module_config config_scmi_clock = { + .data = &((struct mod_scmi_clock_config){ + .max_pending_transactions = 0, + .agent_table = agent_table, + .agent_count = FWK_ARRAY_SIZE(agent_table), + }), +}; diff --git a/product/morello/scp_ramfw_soc/config_scmi_management.c b/product/morello/scp_ramfw_soc/config_scmi_management.c new file mode 100644 index 000000000..e3484fafa --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_scmi_management.c @@ -0,0 +1,11 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* No elements, no module configuration data */ +struct fwk_module_config config_scmi_management = { 0 }; -- GitLab From 8b9608970cb4f94572a613e3020634ca9ee55505 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 16/41] morello/scp_ramfw_soc: add config data for cmn_skeena module Add configuration data for the CMN interconnect - cmn_skeena for Morello. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Iaf5d74ac95c9213c214b92cf31bf037291344838 --- product/morello/include/morello_scp_mmap.h | 18 +- .../morello/scp_ramfw_soc/config_cmn_skeena.c | 253 ++++++++++++++++++ 2 files changed, 265 insertions(+), 6 deletions(-) create mode 100644 product/morello/scp_ramfw_soc/config_cmn_skeena.c diff --git a/product/morello/include/morello_scp_mmap.h b/product/morello/include/morello_scp_mmap.h index 847823943..e7958aa39 100644 --- a/product/morello/include/morello_scp_mmap.h +++ b/product/morello/include/morello_scp_mmap.h @@ -106,16 +106,22 @@ #define CCIX_MSG_CFG_REG_SCP_BASE UINT32_C(0xC1850000) /* - * PCIe and CCIX Slave AXI space visible to SCP + * PCIe and CCIX Subordinate AXI space visible to SCP */ -#define PCIE_AXI_SLAVE_SCP_BASE UINT32_C(0x80000000) -#define CCIX_AXI_SLAVE_SCP_BASE UINT32_C(0x90000000) +#define PCIE_AXI_SUBORDINATE_SCP_BASE UINT32_C(0x80000000) +#define CCIX_AXI_SUBORDINATE_SCP_BASE UINT32_C(0x90000000) /* - * PCIe and CCIX Slave AXI in 64-bit space visible to AP + * PCIe and CCIX Subordinate AXI space visible to AP */ -#define PCIE_AXI64_SLAVE_AP_BASE UINT64_C(0x900000000) -#define CCIX_AXI64_SLAVE_AP_BASE UINT64_C(0x2900000000) +#define PCIE_AXI32_SUBORDINATE_AP_BASE UINT32_C(0x60000000) +#define CCIX_AXI32_SUBORDINATE_AP_BASE UINT32_C(0x70000000) + +/* + * PCIe and CCIX Subordinate AXI in 64-bit space visible to AP + */ +#define PCIE_AXI64_SUBORDINATE_AP_BASE UINT64_C(0x900000000) +#define CCIX_AXI64_SUBORDINATE_AP_BASE UINT64_C(0x3000000000) /* * 1MB window into AP memory space diff --git a/product/morello/scp_ramfw_soc/config_cmn_skeena.c b/product/morello/scp_ramfw_soc/config_cmn_skeena.c new file mode 100644 index 000000000..42d47a52f --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_cmn_skeena.c @@ -0,0 +1,253 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_scp_mmap.h" + +#include + +#include +#include +#include +#include + +#include +#include +#include + +/* + * CMN_SKEENA nodes + */ +#define DMC0_ID 268 +#define DMC1_ID 260 +#define NODE_ID_HND 68 +#define NODE_ID_HNI 72 +#define NODE_ID_SBSX 128 +#define NODE_ID_CCIX 76 + +static const unsigned int snf_table[4] = { + DMC0_ID, /* Maps to HN-F logical node 0 */ + DMC0_ID, /* Maps to HN-F logical node 1 */ + DMC1_ID, /* Maps to HN-F logical node 2 */ + DMC1_ID, /* Maps to HN-F logical node 3 */ +}; + +static const unsigned int rni_pcie_list[4] = { 12, 8, 4, 0 }; + +static const struct mod_cmn_skeena_memory_region_map mmap[19] = { + { + /* + * System cache backed region + * Map: 0x0000_0000_0000 - 0x07FF_FFFF_FFFF (8 TB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(8) * FWK_TIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_SYSCACHE, + }, + { + /* + * Boot region + * Map: 0x0000_0000_0000 - 0x0000_07FF_FFFF (128 MB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_SKEENA_REGION_TYPE_SYSCACHE_SUB, + .node_id = NODE_ID_SBSX, + }, + { + /* + * Peripherals + * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB) + */ + .base = UINT64_C(0x0008000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_1000_0000 - 0x00_1FFF_FFFF (256 MB) + */ + .base = UINT64_C(0x0010000000), + .size = UINT64_C(256) * FWK_MIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_2000_0000 - 0x00_3FFF_FFFF (512 MB) + */ + .base = UINT64_C(0x0020000000), + .size = UINT64_C(512) * FWK_MIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_4000_0000 - 0x00_5FFF_FFFF (512 MB) + */ + .base = UINT64_C(0x0040000000), + .size = UINT64_C(512) * FWK_MIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_6000_0000 - 0x00_6FFF_FFFF (256 MB) + */ + .base = UINT64_C(0x0060000000), + .size = UINT64_C(256) * FWK_MIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_7000_0000 - 0x00_7FFF_FFFF (256 MB) + */ + .base = UINT64_C(0x0070000000), + .size = UINT64_C(256) * FWK_MIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HNI, + }, + { + /* + * Peripherals + * Map: 0x04_0000_0000 - 0x07_FFFF_FFFF (16 GB) + */ + .base = UINT64_C(0x0400000000), + .size = UINT64_C(16) * FWK_GIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x08_0000_0000 - 0x0F_FFFF_FFFF (32 GB) + */ + .base = UINT64_C(0x0800000000), + .size = UINT64_C(32) * FWK_GIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x10_0000_0000 - 0x1F_FFFF_FFFF (64 GB) + */ + .base = UINT64_C(0x1000000000), + .size = UINT64_C(64) * FWK_GIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x20_0000_0000 - 0x27_FFFF_FFFF (32 GB) + */ + .base = UINT64_C(0x2000000000), + .size = UINT64_C(32) * FWK_GIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x28_0000_0000 - 0x2F_FFFF_FFFF (32 GB) + */ + .base = UINT64_C(0x2800000000), + .size = UINT64_C(32) * FWK_GIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x30_0000_0000 - 0x3F_FFFF_FFFF (64 GB) + */ + .base = UINT64_C(0x3000000000), + .size = UINT64_C(64) * FWK_GIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HNI, + }, + { + /* + * Peripherals + * Map: 0x40_0000_0000 - 0x4F_FFFF_FFFF (64 GB) + */ + .base = UINT64_C(0x4000000000), + .size = UINT64_C(64) * FWK_GIB, + .type = MOD_CMN_SKEENA_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HNI, + }, + { + /* + * Peripherals + * Map: 0x50_0000_0000 - 0x5F_FFFF_FFFF (64 GB) + */ + .base = UINT64_C(0x5000000000), + .size = UINT64_C(64) * FWK_GIB, + .type = MOD_CMN_SKEENA_REGION_TYPE_SYSCACHE_NONHASH, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x60_0000_0000 - 0x7F_FFFF_FFFF (128 GB) + */ + .base = UINT64_C(0x6000000000), + .size = UINT64_C(128) * FWK_GIB, + .type = MOD_CMN_SKEENA_REGION_TYPE_SYSCACHE_NONHASH, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x80_0000_0000 - 0x80_7FFF_FFFF (512 GB - 514 GB) + */ + .base = UINT64_C(0x8000000000), + .size = UINT64_C(2) * FWK_GIB, + .type = MOD_CMN_SKEENA_REGION_TYPE_SYSCACHE_NONHASH, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x400_0000_0000 - 0x7FF_FFFF_FFFF (4 TB) + */ + .base = UINT64_C(0x40000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_SKEENA_REGION_TYPE_CCIX, + .node_id = NODE_ID_CCIX, + }, +}; + +const struct fwk_module_config config_cmn_skeena = { + .data = + &(struct mod_cmn_skeena_config){ + .base = SCP_CMN_SKEENA_BASE, + .mesh_size_x = 5, + .mesh_size_y = 2, + .hnd_node_id = NODE_ID_HND, + .snf_table = snf_table, + .snf_count = FWK_ARRAY_SIZE(snf_table), + .sa_count = 2, + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .rni_pcie_table = rni_pcie_list, + .rni_pcie_count = FWK_ARRAY_SIZE(rni_pcie_list), + .chip_addr_space = UINT64_C(4) * FWK_TIB, + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + .hnf_cal_mode = false, + }, +}; -- GitLab From a0e06a293e306e6d8ddcdc855f40277e27640ed8 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 17/41] morello/scp_ramfw_soc: add config data for morello_pcie module Configure the CCIX root port outbound region map with the ECAM, MMIO32/64, and IO regions. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I774cb3a1714aa3aabdcdb29c35188d9eef0be348 --- .../scp_ramfw_soc/config_morello_pcie.c | 203 ++++++++++++++++++ 1 file changed, 203 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_morello_pcie.c diff --git a/product/morello/scp_ramfw_soc/config_morello_pcie.c b/product/morello/scp_ramfw_soc/config_morello_pcie.c new file mode 100644 index 000000000..7cdb7aace --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_morello_pcie.c @@ -0,0 +1,203 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_scp_mmap.h" + +#include + +#include +#include +#include +#include + +#include + +static struct morello_pcie_axi_ob_region_map pcie_axi_ob_mmap[13] = { + /* ECAM region */ + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(127) * FWK_GIB), + .size = UINT64_C(256) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_ECAM, + }, + /* Prefetchable MMIO64 region */ + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE, + .size = UINT64_C(4) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(4) * FWK_GIB), + .size = UINT64_C(8) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(12) * FWK_GIB), + .size = UINT64_C(16) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(28) * FWK_GIB), + .size = UINT64_C(64) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(92) * FWK_GIB), + .size = UINT64_C(32) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(124) * FWK_GIB), + .size = UINT64_C(2) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(126) * FWK_GIB), + .size = UINT64_C(1) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + /* Non-Prefetchable MMIO32 region*/ + { + .base = PCIE_AXI32_SUBORDINATE_AP_BASE, + .size = UINT64_C(128) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(128) * FWK_MIB), + .size = UINT64_C(64) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(192) * FWK_MIB), + .size = UINT64_C(32) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = PCIE_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(224) * FWK_MIB), + .size = UINT64_C(16) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + /* IO region*/ + { + .base = PCIE_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(240) * FWK_MIB), + .size = UINT64_C(16) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_IO, + }, +}; + +static struct morello_pcie_axi_ob_region_map ccix_axi_ob_mmap[13] = { + /* ECAM region */ + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(127) * FWK_GIB), + .size = UINT64_C(256) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_ECAM, + }, + /* Prefetchable MMIO64 region */ + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE, + .size = UINT64_C(64) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(64) * FWK_GIB), + .size = UINT64_C(32) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(96) * FWK_GIB), + .size = UINT64_C(16) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(112) * FWK_GIB), + .size = UINT64_C(8) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(120) * FWK_GIB), + .size = UINT64_C(4) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(124) * FWK_GIB), + .size = UINT64_C(2) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI64_SUBORDINATE_AP_BASE + (UINT64_C(126) * FWK_GIB), + .size = UINT64_C(1) * FWK_GIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + /* Non-Prefetchable MMIO32 region*/ + { + .base = CCIX_AXI32_SUBORDINATE_AP_BASE, + .size = UINT64_C(128) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(128) * FWK_MIB), + .size = UINT64_C(64) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(192) * FWK_MIB), + .size = UINT64_C(32) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + { + .base = CCIX_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(224) * FWK_MIB), + .size = UINT64_C(16) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_MMIO, + }, + /* IO region*/ + { + .base = CCIX_AXI32_SUBORDINATE_AP_BASE + (UINT64_C(240) * FWK_MIB), + .size = UINT64_C(16) * FWK_MIB, + .type = PCIE_AXI_OB_REGION_TYPE_IO, + }, +}; + +static const struct fwk_element morello_pcie_element_table[3] = { + [0] = { + .name = "Generic-PCIe", + .data = &((struct morello_pcie_dev_config) { + .ctrl_base = PCIE_IP_CFG_REG_SCP_BASE, + .global_config_base = PCIE_RC_CFG_REG_SCP_BASE, + .msg_base = PCIE_MSG_CFG_REG_SCP_BASE, + .axi_subordinate_base32 = PCIE_AXI_SUBORDINATE_SCP_BASE, + .axi_subordinate_base64 = PCIE_AXI64_SUBORDINATE_AP_BASE, + .ccix_capable = false, + .axi_ob_table = pcie_axi_ob_mmap, + .axi_ob_count = FWK_ARRAY_SIZE(pcie_axi_ob_mmap), + .pri_bus_num = 0, + }), + }, + [1] = { + .name = "CCIX-PCIe", + .data = &((struct morello_pcie_dev_config) { + .ctrl_base = CCIX_IP_CFG_REG_SCP_BASE, + .global_config_base = CCIX_RC_CFG_REG_SCP_BASE, + .msg_base = CCIX_MSG_CFG_REG_SCP_BASE, + .axi_subordinate_base32 = CCIX_AXI_SUBORDINATE_SCP_BASE, + .axi_subordinate_base64 = CCIX_AXI64_SUBORDINATE_AP_BASE, + .ccix_capable = true, + .axi_ob_table = ccix_axi_ob_mmap, + .axi_ob_count = FWK_ARRAY_SIZE(ccix_axi_ob_mmap), + .pri_bus_num = 0, + }), + }, + [2] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *morello_pcie_get_element_table( + fwk_id_t module_id) +{ + return morello_pcie_element_table; +} + +const struct fwk_module_config config_morello_pcie = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(morello_pcie_get_element_table), +}; -- GitLab From 97f95af1f95ee14ecbece3fd9439608fe0ff61a0 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 18/41] morello/scp_ramfw_soc: add support for dvfs/scmi_perf Enable DVFS (frequency scaling only). Voltage scaling is not supported at the moment and will be enabled at a later stage. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I1fa437ccd8de4c88f23fc8e29156fc2e831505ec --- product/morello/scp_ramfw_soc/config_dvfs.c | 169 ++++++++++++++++++ product/morello/scp_ramfw_soc/config_dvfs.h | 18 ++ .../morello/scp_ramfw_soc/config_mock_psu.c | 67 +++++++ .../morello/scp_ramfw_soc/config_mock_psu.h | 18 ++ product/morello/scp_ramfw_soc/config_psu.c | 64 +++++++ product/morello/scp_ramfw_soc/config_psu.h | 18 ++ .../morello/scp_ramfw_soc/config_scmi_perf.c | 31 ++++ 7 files changed, 385 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_dvfs.c create mode 100644 product/morello/scp_ramfw_soc/config_dvfs.h create mode 100644 product/morello/scp_ramfw_soc/config_mock_psu.c create mode 100644 product/morello/scp_ramfw_soc/config_mock_psu.h create mode 100644 product/morello/scp_ramfw_soc/config_psu.c create mode 100644 product/morello/scp_ramfw_soc/config_psu.h create mode 100644 product/morello/scp_ramfw_soc/config_scmi_perf.c diff --git a/product/morello/scp_ramfw_soc/config_dvfs.c b/product/morello/scp_ramfw_soc/config_dvfs.c new file mode 100644 index 000000000..445e1f30f --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_dvfs.c @@ -0,0 +1,169 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "config_dvfs.h" + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +static const struct mod_dvfs_domain_config cpu_group_0 = { + .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP0), + .latency = 1200, + .sustained_idx = 2, + .opps = + (struct mod_dvfs_opp[]){ + { + .level = CPU_CLOCK_SUD * 1000000UL, + .frequency = CPU_CLOCK_SUD * FWK_KHZ, + .voltage = 800, + .power = (0.16 * 1800 * 0.800 * 0.800), + }, + { + .level = CPU_CLOCK_UD * 1000000UL, + .frequency = CPU_CLOCK_UD * FWK_KHZ, + .voltage = 850, + .power = (0.16 * 1900 * 0.850 * 0.850), + }, + { + .level = CPU_CLOCK_NOM * 1000000UL, + .frequency = CPU_CLOCK_NOM * FWK_KHZ, + .voltage = 900, + .power = (0.16 * 2000 * 0.900 * 0.900), + }, + { + .level = CPU_CLOCK_OD * 1000000UL, + .frequency = CPU_CLOCK_OD * FWK_KHZ, + .voltage = 950, + .power = (0.16 * 2100 * 0.950 * 0.950), + }, + { + .level = CPU_CLOCK_SOD * 1000000UL, + .frequency = CPU_CLOCK_SOD * FWK_KHZ, + .voltage = 1000, + .power = (0.16 * 2200 * 1.000 * 1.000), + }, + { 0 }, + } +}; + +static const struct mod_dvfs_domain_config cpu_group_1 = { + .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP1), + .latency = 1200, + .sustained_idx = 2, + .opps = + (struct mod_dvfs_opp[]){ + { + .level = CPU_CLOCK_SUD * 1000000UL, + .frequency = CPU_CLOCK_SUD * FWK_KHZ, + .voltage = 800, + .power = (0.16 * 1800 * 0.800 * 0.800), + }, + { + .level = CPU_CLOCK_UD * 1000000UL, + .frequency = CPU_CLOCK_UD * FWK_KHZ, + .voltage = 850, + .power = (0.16 * 1900 * 0.850 * 0.850), + }, + { + .level = CPU_CLOCK_NOM * 1000000UL, + .frequency = CPU_CLOCK_NOM * FWK_KHZ, + .voltage = 900, + .power = (0.16 * 2000 * 0.900 * 0.900), + }, + { + .level = CPU_CLOCK_OD * 1000000UL, + .frequency = CPU_CLOCK_OD * FWK_KHZ, + .voltage = 950, + .power = (0.16 * 2100 * 0.950 * 0.950), + }, + { + .level = CPU_CLOCK_SOD * 1000000UL, + .frequency = CPU_CLOCK_SOD * FWK_KHZ, + .voltage = 1000, + .power = (0.16 * 2200 * 1.000 * 1.000), + }, + { 0 }, + } +}; + +static const struct mod_dvfs_domain_config gpu = { + .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 2), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_GPU), + .latency = 1200, + .sustained_idx = 4, + .opps = + (struct mod_dvfs_opp[]){ + { + .level = 450 * 1000000UL, + .frequency = 450 * FWK_KHZ, + .voltage = 800, + .power = (0.16 * 450 * 0.800 * 0.800), + }, + { + .level = 500 * 1000000UL, + .frequency = 500 * FWK_KHZ, + .voltage = 850, + .power = (0.16 * 500 * 0.850 * 0.850), + }, + { + .level = 550 * 1000000UL, + .frequency = 550 * FWK_KHZ, + .voltage = 900, + .power = (0.16 * 550 * 0.900 * 0.900), + }, + { + .level = 600 * 1000000UL, + .frequency = 600 * FWK_KHZ, + .voltage = 950, + .power = (0.16 * 600 * 0.950 * 0.950), + }, + { + .level = 650 * 1000000UL, + .frequency = 650 * FWK_KHZ, + .voltage = 1000, + .power = (0.16 * 650 * 1.000 * 1.000), + }, + { 0 }, + } +}; + +static const struct fwk_element element_table[DVFS_ELEMENT_IDX_COUNT + 1] = { + [DVFS_ELEMENT_IDX_CLUS0] = { + .name = "CLUSTER_0_CPUS", + .data = &cpu_group_0, + }, + [DVFS_ELEMENT_IDX_CLUS1] = { + .name = "CLUSTER_1_CPUS", + .data = &cpu_group_1, + }, + [DVFS_ELEMENT_IDX_GPU] = { + .name = "GPU", + .data = &gpu, + }, + { 0 } +}; + +static const struct fwk_element *dvfs_get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +struct fwk_module_config config_dvfs = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(dvfs_get_element_table), + .data = NULL, +}; diff --git a/product/morello/scp_ramfw_soc/config_dvfs.h b/product/morello/scp_ramfw_soc/config_dvfs.h new file mode 100644 index 000000000..ddaf75a84 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_dvfs.h @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_DVFS_H +#define CONFIG_DVFS_H + +enum dvfs_element_idx { + DVFS_ELEMENT_IDX_CLUS0, + DVFS_ELEMENT_IDX_CLUS1, + DVFS_ELEMENT_IDX_GPU, + DVFS_ELEMENT_IDX_COUNT +}; + +#endif /* CONFIG_DVFS_H */ diff --git a/product/morello/scp_ramfw_soc/config_mock_psu.c b/product/morello/scp_ramfw_soc/config_mock_psu.c new file mode 100644 index 000000000..38b44afbb --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_mock_psu.c @@ -0,0 +1,67 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +static const struct fwk_element + element_table[CONFIG_MOCK_PSU_ELEMENT_IDX_COUNT + 1] = { + [CONFIG_MOCK_PSU_ELEMENT_IDX_CLUS0] = { + .name = "CLUSTER_0_CPUS", + .data = &(const struct mod_mock_psu_element_cfg) { + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 800, + }, + }, + [CONFIG_MOCK_PSU_ELEMENT_IDX_CLUS1] = { + .name = "CLUSTER_1_CPUS", + .data = &(const struct mod_mock_psu_element_cfg) { + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 800, + }, + }, + [CONFIG_MOCK_PSU_ELEMENT_IDX_GPU] = { + .name = "GPU", + .data = &(const struct mod_mock_psu_element_cfg) { + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 1000, + }, + }, + { 0 } +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +struct fwk_module_config config_mock_psu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), + .data = NULL, +}; diff --git a/product/morello/scp_ramfw_soc/config_mock_psu.h b/product/morello/scp_ramfw_soc/config_mock_psu.h new file mode 100644 index 000000000..73f62e20e --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_mock_psu.h @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_MOCK_PSU_H +#define CONFIG_MOCK_PSU_H + +enum config_mock_psu_element_idx { + CONFIG_MOCK_PSU_ELEMENT_IDX_CLUS0, + CONFIG_MOCK_PSU_ELEMENT_IDX_CLUS1, + CONFIG_MOCK_PSU_ELEMENT_IDX_GPU, + CONFIG_MOCK_PSU_ELEMENT_IDX_COUNT, +}; + +#endif /* CONFIG_MOCK_PSU_H */ diff --git a/product/morello/scp_ramfw_soc/config_psu.c b/product/morello/scp_ramfw_soc/config_psu.c new file mode 100644 index 000000000..94f009df9 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_psu.c @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include + +#include +#include +#include + +static const struct fwk_element + element_table[CONFIG_PSU_ELEMENT_IDX_COUNT + 1] = { + [CONFIG_PSU_ELEMENT_IDX_CLUS0] = { + .name = "CLUSTER_0_CPUS", + .data = &(const struct mod_psu_element_cfg) { + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_MOCK_PSU, + CONFIG_MOCK_PSU_ELEMENT_IDX_CLUS0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER), + }, + }, + [CONFIG_PSU_ELEMENT_IDX_CLUS1] = { + .name = "CLUSTER_1_CPUS", + .data = &(const struct mod_psu_element_cfg) { + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_MOCK_PSU, + CONFIG_MOCK_PSU_ELEMENT_IDX_CLUS1), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER), + }, + }, + [CONFIG_PSU_ELEMENT_IDX_GPU] = { + .name = "GPU", + .data = &(const struct mod_psu_element_cfg) { + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_MOCK_PSU, + CONFIG_MOCK_PSU_ELEMENT_IDX_GPU), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER), + }, + }, + { 0 } +}; + +static const struct fwk_element *psu_get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +struct fwk_module_config config_psu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(psu_get_element_table), + .data = NULL, +}; diff --git a/product/morello/scp_ramfw_soc/config_psu.h b/product/morello/scp_ramfw_soc/config_psu.h new file mode 100644 index 000000000..ffc6205d1 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_psu.h @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_PSU_H +#define CONFIG_PSU_H + +enum config_psu_element_idx { + CONFIG_PSU_ELEMENT_IDX_CLUS0, + CONFIG_PSU_ELEMENT_IDX_CLUS1, + CONFIG_PSU_ELEMENT_IDX_GPU, + CONFIG_PSU_ELEMENT_IDX_COUNT, +}; + +#endif /* CONFIG_PSU_H */ diff --git a/product/morello/scp_ramfw_soc/config_scmi_perf.c b/product/morello/scp_ramfw_soc/config_scmi_perf.c new file mode 100644 index 000000000..592ec8a84 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_scmi_perf.c @@ -0,0 +1,31 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include + +#include + +static const struct mod_scmi_perf_domain_config + domains[DVFS_ELEMENT_IDX_COUNT] = { + [DVFS_ELEMENT_IDX_CLUS0] = {}, + [DVFS_ELEMENT_IDX_CLUS1] = {}, + [DVFS_ELEMENT_IDX_GPU] = {}, + }; + +struct fwk_module_config config_scmi_perf = { + .data = &((struct mod_scmi_perf_config){ + .domains = &domains, + .fast_channels_alarm_id = FWK_ID_NONE_INIT, + .perf_doms_count = FWK_ARRAY_SIZE(domains), + }), +}; -- GitLab From 2c62bfa7faab48bce0c068c1094ab1728af66ec1 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 19/41] morello/scp_ramfw_soc: add resource_perms configuration Expose the currently supported SCMI protocol-specific messages/ attributes for PSCI and OSPM agents to the resource_perms module. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I2ae5bf0196337ca0654da944b46534cb253e73db --- .../scp_ramfw_soc/config_resource_perms.c | 123 ++++++++++++++++++ tools/cppcheck_suppress_list.txt | 1 + 2 files changed, 124 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_resource_perms.c diff --git a/product/morello/scp_ramfw_soc/config_resource_perms.c b/product/morello/scp_ramfw_soc/config_resource_perms.c new file mode 100644 index 000000000..73381792d --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_resource_perms.c @@ -0,0 +1,123 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_scp_scmi.h" + +#include +#include + +#include +#include +#include +#include +#include + +/*! + * If the agent wants to modify permissions at run-time these tables + * must be allocated in writable memory. + */ + +#define AGENT_IDX(agent_id) (agent_id - 1) + +static struct mod_res_agent_protocol_permissions agent_protocol_permissions[2] = + { + [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = + { + .protocols = MOD_RES_PERMS_SCMI_ALL_PROTOCOLS_ALLOWED, + }, + + /* PSCI agent has no access to clock, perf and sensor protocol */ + [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = + { + .protocols = MOD_RES_PERMS_SCMI_CLOCK_PROTOCOL_DENIED | + MOD_RES_PERMS_SCMI_PERF_PROTOCOL_DENIED | + MOD_RES_PERMS_SCMI_SENSOR_PROTOCOL_DENIED, + }, + }; + +/* + * Messages have an index offset from 0x3 as all agents can access + * the VERSION/ATTRIBUTES/MSG_ATTRIBUTES messages for all + * protocols, hence message 0x3 maps to bit[0], message 0x4 maps + * to bit[1], etc. + */ +static struct mod_res_agent_msg_permissions + agent_msg_permissions[2] = + { + [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = + { + /* Example, Base, disable unused msg 12 */ + .messages[MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, + /* Power Domain */ + .messages[MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = + 0x0, + /* System Power Domain */ + .messages[MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, + /* Performance */ + .messages[MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = 0x0, + /* Clock management */ + .messages[MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0x0, + /* Sensors */ + .messages[MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, + /* Reset Domains */ + .messages[MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = + 0x0, + }, + [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = + { + .messages[0] = 0x0, /* Base */ + .messages[1] = 0x0, /* Power Domain */ + .messages[2] = 0x0, /* System Power Domain */ + .messages[3] = + ((1 + << (MOD_SCMI_PERF_DOMAIN_ATTRIBUTES - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (0 + << (MOD_SCMI_PERF_DESCRIBE_LEVELS - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LIMITS_SET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LIMITS_GET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LEVEL_SET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LEVEL_GET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_NOTIFY_LIMITS - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_NOTIFY_LEVEL - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_DESCRIBE_FAST_CHANNEL - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES))), + .messages[4] = + (1 + << (MOD_SCMI_CLOCK_CONFIG_SET - + MOD_SCMI_CLOCK_ATTRIBUTES)), /* Clock management */ + .messages[5] = 0x0, /* Sensors */ + }, + }; + +static struct mod_res_agent_permission agent_permissions = { + .agent_protocol_permissions = agent_protocol_permissions, + .agent_msg_permissions = agent_msg_permissions, +}; + +struct fwk_module_config config_resource_perms = { + .data = + &(struct mod_res_resource_perms_config){ + .agent_permissions = (uintptr_t)&agent_permissions, + .agent_count = SCP_SCMI_AGENT_ID_COUNT, + .protocol_count = 6, + }, +}; diff --git a/tools/cppcheck_suppress_list.txt b/tools/cppcheck_suppress_list.txt index 2d19d53fa..3b82144e9 100755 --- a/tools/cppcheck_suppress_list.txt +++ b/tools/cppcheck_suppress_list.txt @@ -180,6 +180,7 @@ arrayIndexOutOfBounds:*product/rdv1mc/module/platform_system/src/mod_platform_sy objectIndex:*product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.c:438 objectIndex:*product/morello/module/morello_pcie/src/morello_pcie.c:390 knownConditionTrueFalse:*product/n1sdp/module/n1sdp_dmc620/src/mod_n1sdp_dmc620.c:85 +syntaxError:*product/morello/scp_ramfw_soc/config_resource_perms.c:54 // Suppress CMSIS errors *:*/CMSIS*/* -- GitLab From 92650a88a48297d2adb0932ebf537134b297b9b8 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 20/41] morello/scp_ramfw_soc: add debugger_cli config data Add config data for the CLI debugger module which provides basic system investigation functionality such as memory read/write, register dumps, module initialization, etc. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Ifd2e9c640bcba41541b93c0e420bbafc369449a7 --- .../scp_ramfw_soc/config_debugger_cli.c | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_debugger_cli.c diff --git a/product/morello/scp_ramfw_soc/config_debugger_cli.c b/product/morello/scp_ramfw_soc/config_debugger_cli.c new file mode 100644 index 000000000..bd80195a8 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_debugger_cli.c @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_alarm_idx.h" + +#include + +#include + +/* + * Data for the debugger CLI module configuration + */ +static const struct mod_debugger_cli_module_config debugger_cli_data = { + .alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + MORELLO_DEBUGGER_CLI_ALARM_IDX), + .poll_period = 100 +}; + +/* + * Configuration for the debugger CLI module + */ +struct fwk_module_config config_debugger_cli = { .data = &debugger_cli_data }; -- GitLab From 485f3ebfeaf4373dc8827b673c1daa1f6d221127 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 21/41] morello/scp_ramfw_soc: add memory layout for linker script Add SCP Instruction/Data memory layout required by the linker script. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I7f2b32104c40ad13015e68b4510ec558e6993ca4 --- product/morello/scp_ramfw_soc/fmw_memory.h | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/fmw_memory.h diff --git a/product/morello/scp_ramfw_soc/fmw_memory.h b/product/morello/scp_ramfw_soc/fmw_memory.h new file mode 100644 index 000000000..db683a5d1 --- /dev/null +++ b/product/morello/scp_ramfw_soc/fmw_memory.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "morello_scp_system_mmap.h" + +#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FMW_MEM0_SIZE SCP_RAM0_SIZE +#define FMW_MEM0_BASE SCP_RAM0_BASE + +/* + * RAM data memory + */ +#define FMW_MEM1_SIZE SCP_RAM1_SIZE +#define FMW_MEM1_BASE SCP_RAM1_BASE + +#endif /* FMW_MEMORY_H */ -- GitLab From 08f290314d36bd65f514671cd9139ae5440fcd10 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 22/41] morello/scp_ramfw_soc: add config data for dmc_bing module Add configuration data for Morello's dmc_bing module. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Id3d05f6f5c524cca1404e9b344251546c2b07071 --- .../morello/scp_ramfw_soc/config_dmc_bing.c | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_dmc_bing.c diff --git a/product/morello/scp_ramfw_soc/config_dmc_bing.c b/product/morello/scp_ramfw_soc/config_dmc_bing.c new file mode 100644 index 000000000..26cf46dac --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_dmc_bing.c @@ -0,0 +1,58 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_scp_mmap.h" + +#include + +#include +#include +#include +#include + +#include + +/* Table of DMC_BING elements descriptions. */ +static struct fwk_element dmc_bing_element_table[3] = { + [0] = + { + .name = "DMC_BING-0", + .data = &((struct mod_dmc_bing_element_config){ + .dmc_bing_base = SCP_DMC0, + .ddr_phy_base = SCP_DDR_PHY0, + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + }), + }, + [1] = + { + .name = "DMC_BING-1", + .data = &((struct mod_dmc_bing_element_config){ + .dmc_bing_base = SCP_DMC1, + .ddr_phy_base = SCP_DDR_PHY1, + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + }), + }, + [2] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *dmc_bing_get_element_table(fwk_id_t module_id) +{ + return dmc_bing_element_table; +} + +/* Configuration of the DMC_BING module. */ +const struct fwk_module_config config_dmc_bing = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(dmc_bing_get_element_table), + .data = &((struct mod_dmc_bing_module_config){ + .ddr_speed = DDR_CLOCK_MHZ, + }), +}; -- GitLab From 0541f774cc5b0a1c6bda5c29b70680ad347ae98f Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 23/41] morello/scp_ramfw_soc: enable scp_ramfw image build Enable SCP RAM firmware build for Morello SoC. The target image is labelled as "scp_ramfw_soc". Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I7a1e00ea31a45b7d3af1efbb5364a7a6ee0fd135 --- product/morello/product.mk | 7 +- product/morello/scp_ramfw_soc/CMakeLists.txt | 88 ++++++++++++++++++ product/morello/scp_ramfw_soc/Firmware.cmake | 76 ++++++++++++++++ .../scp_ramfw_soc/Toolchain-ArmClang.cmake | 20 +++++ .../morello/scp_ramfw_soc/Toolchain-GNU.cmake | 18 ++++ product/morello/scp_ramfw_soc/firmware.mk | 89 +++++++++++++++++++ 6 files changed, 297 insertions(+), 1 deletion(-) create mode 100644 product/morello/scp_ramfw_soc/CMakeLists.txt create mode 100644 product/morello/scp_ramfw_soc/Firmware.cmake create mode 100644 product/morello/scp_ramfw_soc/Toolchain-ArmClang.cmake create mode 100644 product/morello/scp_ramfw_soc/Toolchain-GNU.cmake create mode 100644 product/morello/scp_ramfw_soc/firmware.mk diff --git a/product/morello/product.mk b/product/morello/product.mk index 3fcc9f081..8795cbe2b 100644 --- a/product/morello/product.mk +++ b/product/morello/product.mk @@ -6,4 +6,9 @@ # BS_PRODUCT_NAME := morello -BS_FIRMWARE_LIST := scp_ramfw_fvp mcp_ramfw_fvp scp_romfw mcp_romfw +BS_FIRMWARE_LIST := \ + scp_ramfw_fvp \ + mcp_ramfw_fvp \ + scp_romfw \ + mcp_romfw \ + scp_ramfw_soc diff --git a/product/morello/scp_ramfw_soc/CMakeLists.txt b/product/morello/scp_ramfw_soc/CMakeLists.txt new file mode 100644 index 000000000..4d1df9c22 --- /dev/null +++ b/product/morello/scp_ramfw_soc/CMakeLists.txt @@ -0,0 +1,88 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Create the firmware target. +# + +add_executable(morello-soc-bl2) + +target_include_directories( + morello-soc-bl2 PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../include" + "${CMAKE_CURRENT_SOURCE_DIR}") + +# cmake-lint: disable=E1122 + +target_sources( + morello-soc-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/rtx_config.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_armv7m_mpu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_ssc.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_system_info.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_power_domain.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_ppu_v0.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_ppu_v1.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_dmc_bing.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_system_power.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_mhu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_smt.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_sds.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_timer.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_cmn_skeena.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_system_power.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_power_domain.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_management.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_morello_pll.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_css_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_psu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_psu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_dvfs.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_perf.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_apcontext.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_resource_perms.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_morello_pcie.c" + "${CMAKE_CURRENT_SOURCE_DIR}/../src/morello_core.c") + +if(SCP_ENABLE_MULTITHREADING) + target_sources(morello-soc-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/rtx_config.c") + target_link_libraries(morello-soc-bl2 PRIVATE cmsis::rtos2-rtx) +endif() + +if(SCP_ENABLE_DEBUGGER_INIT) + target_compile_definitions(morello-soc-bl2 PRIVATE BUILD_HAS_DEBUGGER) + target_sources(morello-soc-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_debugger_cli.c") +endif() + +# +# Some of our firmware includes require CMSIS. +# + +target_link_libraries(morello-soc-bl2 PUBLIC cmsis::core-m) + +# +# We explicitly add the CMSIS include directories to our interfaceinclude +# directories. Each module target adds these include directories totheir own, +# allowing them to include any firmware includes we expose. +# + +target_include_directories( + morello-soc-bl2 + PUBLIC $) + +if(SCP_ENABLE_DEBUGGER_INIT) + list(APPEND SCP_MODULES "debugger-cli") +endif() + +set(SCP_MODULES ${SCP_MODULES} PARENT_SCOPE) +set(SCP_MODULE_PATHS ${SCP_MODULE_PATHS} PARENT_SCOPE) diff --git a/product/morello/scp_ramfw_soc/Firmware.cmake b/product/morello/scp_ramfw_soc/Firmware.cmake new file mode 100644 index 000000000..7edb5de05 --- /dev/null +++ b/product/morello/scp_ramfw_soc/Firmware.cmake @@ -0,0 +1,76 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Configure the build system. +# + +set(SCP_FIRMWARE "morello-soc-bl2") + +set(SCP_FIRMWARE_TARGET "morello-soc-bl2") + +set(SCP_TOOLCHAIN_INIT "GNU") + +set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) + +set(SCP_ENABLE_MULTITHREADING_INIT FALSE) + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +set(SCP_ARCHITECTURE "armv7-m") + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +set(SCP_ENABLE_IPO_INIT FALSE) + +set(SCP_ENABLE_DEBUGGER_INIT FALSE) + +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../../../module/fip") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_pll") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/dmc_bing") +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/morello_system") +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/scmi_management") +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/morello_pcie") + +# The order of the modules in the following list is the order in which the +# modules are initialized, bound, started during the pre-runtime phase. +# any change in the order will cause firmware initialization errors. + +list(APPEND SCP_MODULES "pl011") +list(APPEND SCP_MODULES "cmn-skeena") +list(APPEND SCP_MODULES "apcontext") +list(APPEND SCP_MODULES "power-domain") +list(APPEND SCP_MODULES "ppu-v1") +list(APPEND SCP_MODULES "ppu-v0") +list(APPEND SCP_MODULES "system-power") +list(APPEND SCP_MODULES "morello-pll") +list(APPEND SCP_MODULES "dmc-bing") +list(APPEND SCP_MODULES "mhu") +list(APPEND SCP_MODULES "smt") +list(APPEND SCP_MODULES "scmi") +list(APPEND SCP_MODULES "sds") +list(APPEND SCP_MODULES "pik-clock") +list(APPEND SCP_MODULES "css-clock") +list(APPEND SCP_MODULES "clock") +list(APPEND SCP_MODULES "gtimer") +list(APPEND SCP_MODULES "timer") +list(APPEND SCP_MODULES "scmi-power-domain") +list(APPEND SCP_MODULES "scmi-system-power") +list(APPEND SCP_MODULES "scmi-management") +list(APPEND SCP_MODULES "fip") +list(APPEND SCP_MODULES "morello-pcie") +list(APPEND SCP_MODULES "ssc") +list(APPEND SCP_MODULES "system-info") +list(APPEND SCP_MODULES "psu") +list(APPEND SCP_MODULES "mock-psu") +list(APPEND SCP_MODULES "dvfs") +list(APPEND SCP_MODULES "scmi-perf") +list(APPEND SCP_MODULES "morello-system") +list(APPEND SCP_MODULES "resource-perms") diff --git a/product/morello/scp_ramfw_soc/Toolchain-ArmClang.cmake b/product/morello/scp_ramfw_soc/Toolchain-ArmClang.cmake new file mode 100644 index 000000000..6e9e3fa0f --- /dev/null +++ b/product/morello/scp_ramfw_soc/Toolchain-ArmClang.cmake @@ -0,0 +1,20 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cmake-lint: disable=C0301 + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/ArmClang-Baremetal.cmake" +) diff --git a/product/morello/scp_ramfw_soc/Toolchain-GNU.cmake b/product/morello/scp_ramfw_soc/Toolchain-GNU.cmake new file mode 100644 index 000000000..a4ea7a3f7 --- /dev/null +++ b/product/morello/scp_ramfw_soc/Toolchain-GNU.cmake @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") + +set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/morello/scp_ramfw_soc/firmware.mk b/product/morello/scp_ramfw_soc/firmware.mk new file mode 100644 index 000000000..b53ad4b95 --- /dev/null +++ b/product/morello/scp_ramfw_soc/firmware.mk @@ -0,0 +1,89 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# The order of the modules in the BS_FIRMWARE_MODULES list is the order in which +# the modules are initialized, bound, started during the pre-runtime phase. +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := no +BS_FIRMWARE_HAS_NOTIFICATION := yes + +BS_FIRMWARE_MODULES := \ + armv7m_mpu \ + pl011 \ + cmn_skeena \ + apcontext \ + power_domain \ + morello_pll \ + ppu_v1 \ + system_power \ + dmc_bing \ + mhu \ + smt \ + scmi \ + sds \ + pik_clock \ + ppu_v0 \ + css_clock \ + clock \ + gtimer \ + timer \ + dvfs \ + psu \ + mock_psu \ + scmi_power_domain \ + scmi_clock \ + scmi_perf \ + scmi_system_power \ + scmi_management \ + resource_perms \ + fip \ + morello_pcie \ + ssc \ + system_info \ + morello_system + +BS_FIRMWARE_SOURCES := \ + rtx_config.c \ + morello_core.c \ + config_armv7m_mpu.c \ + config_ssc.c \ + config_system_info.c \ + config_pl011.c \ + config_power_domain.c \ + config_ppu_v0.c \ + config_ppu_v1.c \ + config_dmc_bing.c \ + config_system_power.c \ + config_mhu.c \ + config_smt.c \ + config_scmi.c \ + config_sds.c \ + config_timer.c \ + config_cmn_skeena.c \ + config_scmi_system_power.c \ + config_scmi_power_domain.c \ + config_scmi_clock.c \ + config_morello_pll.c \ + config_pik_clock.c \ + config_css_clock.c \ + config_clock.c \ + config_apcontext.c \ + config_dvfs.c \ + config_psu.c \ + config_mock_psu.c \ + config_scmi_perf.c \ + config_scmi_management.c \ + config_resource_perms.c \ + config_morello_pcie.c \ + +ifeq ($(BUILD_HAS_DEBUGGER),yes) + BS_FIRMWARE_MODULES += debugger_cli + BS_FIRMWARE_SOURCES += config_debugger_cli.c +endif + +include $(BS_DIR)/firmware.mk -- GitLab From 04b45b5321f652df6fcf771b5767e76c20afe572 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 24/41] morello/mcp_ramfw_soc: add clock related config data Add MCP RAM firmware config data for MCP system and pik clocks. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I690b3f5edfc08365169aa8cec4ca74398e2b2408 --- product/morello/mcp_ramfw_soc/config_clock.c | 14 ++++ product/morello/mcp_ramfw_soc/config_clock.h | 28 +++++++ .../morello/mcp_ramfw_soc/config_pik_clock.c | 81 +++++++++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 product/morello/mcp_ramfw_soc/config_clock.c create mode 100644 product/morello/mcp_ramfw_soc/config_clock.h create mode 100644 product/morello/mcp_ramfw_soc/config_pik_clock.c diff --git a/product/morello/mcp_ramfw_soc/config_clock.c b/product/morello/mcp_ramfw_soc/config_clock.c new file mode 100644 index 000000000..f1da76946 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_clock.c @@ -0,0 +1,14 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* + * Empty placeholder for compatibility as all clocks are + * managed by SCP. + */ +const struct fwk_module_config config_clock = { 0 }; diff --git a/product/morello/mcp_ramfw_soc/config_clock.h b/product/morello/mcp_ramfw_soc/config_clock.h new file mode 100644 index 000000000..5f1714b9a --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_clock.h @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_CLOCK_H +#define CONFIG_CLOCK_H + +#include + +/* + * PIK clock rates. + */ +#define PIK_CLK_RATE_MCP_CORECLK (300 * FWK_MHZ) +#define PIK_CLK_RATE_MCP_AXICLK (300 * FWK_MHZ) + +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CLOCK_PIK_IDX_MCP_CORECLK, + CLOCK_PIK_IDX_MCP_AXICLK, + CLOCK_PIK_IDX_COUNT +}; + +#endif /* CONFIG_CLOCK_H */ diff --git a/product/morello/mcp_ramfw_soc/config_pik_clock.c b/product/morello/mcp_ramfw_soc/config_pik_clock.c new file mode 100644 index 000000000..91e0acc4c --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_pik_clock.c @@ -0,0 +1,81 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include + +/* + * Rate lookup tables + */ + +static const struct mod_pik_clock_rate rate_table_mcp_coreclk[1] = { + { + .rate = PIK_CLK_RATE_MCP_CORECLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_CORECLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_mcp_axiclk[1] = { + { + .rate = PIK_CLK_RATE_MCP_AXICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_AXICLK, + }, +}; + +static const struct fwk_element + pik_clock_element_table[CLOCK_PIK_IDX_COUNT + 1] = { + [CLOCK_PIK_IDX_MCP_CORECLK] = { + .name = "MCP CORECLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_MCP->CORECLK_CTRL, + .divsys_reg = &PIK_MCP->CORECLK_DIV1, + .rate_table = rate_table_mcp_coreclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_coreclk), + .initial_rate = PIK_CLK_RATE_MCP_CORECLK, + .defer_initialization = true, + }), + }, + [CLOCK_PIK_IDX_MCP_AXICLK] = { + .name = "MCP AXICLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_MCP->CORECLK_CTRL, + .divsys_reg = &PIK_MCP->CORECLK_DIV1, + .rate_table = rate_table_mcp_axiclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_axiclk), + .initial_rate = PIK_CLK_RATE_MCP_AXICLK, + .defer_initialization = true, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) +{ + return pik_clock_element_table; +} + +const struct fwk_module_config config_pik_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), +}; -- GitLab From 3c55eb953ec1a536effe4607ea9185f092e6d97c Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 25/41] morello/mcp_ramfw_soc: add cmsis rtx config data Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: If2e1f2cf3d9ae372e80d5dc67f85545a87cc7fb7 --- product/morello/mcp_ramfw_soc/RTX_Config.h | 56 ++++++++++++++++++++++ product/morello/mcp_ramfw_soc/fmw_cmsis.h | 13 +++++ product/morello/mcp_ramfw_soc/rtx_config.c | 56 ++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 product/morello/mcp_ramfw_soc/RTX_Config.h create mode 100644 product/morello/mcp_ramfw_soc/fmw_cmsis.h create mode 100644 product/morello/mcp_ramfw_soc/rtx_config.c diff --git a/product/morello/mcp_ramfw_soc/RTX_Config.h b/product/morello/mcp_ramfw_soc/RTX_Config.h new file mode 100644 index 000000000..531d1ca03 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/RTX_Config.h @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RTX2 v5 configuration file. + * The file must be called RTX_Config.h as it is included by an RTX + * file in order to create an object file containing the configuration. + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +/* System */ +#define OS_DYNAMIC_MEM_SIZE 0 +#define OS_TICK_FREQ 1000 /* Hz */ +#define OS_ROBIN_ENABLE 0 +#define OS_ROBIN_TIMEOUT 0 +#define OS_ISR_FIFO_QUEUE 16 + +/* Thread */ +#define OS_THREAD_OBJ_MEM 0 +#define OS_THREAD_NUM 1 +#define OS_THREAD_DEF_STACK_NUM 0 +#define OS_THREAD_USER_STACK_SIZE 0 +#define OS_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_STACK_CHECK 1 +#define OS_STACK_WATERMARK 0 +#define OS_PRIVILEGE_MODE 1 + +/* Timer */ +#define OS_TIMER_OBJ_MEM 0 +#define OS_TIMER_NUM 1 +#define OS_TIMER_THREAD_PRIO 40 +#define OS_TIMER_THREAD_STACK_SIZE 200 +#define OS_TIMER_CB_QUEUE 4 + +/* Event flags */ +#define OS_EVFLAGS_OBJ_MEM 0 +#define OS_EVFLAGS_NUM 1 + +#define OS_MUTEX_OBJ_MEM 0 +#define OS_MUTEX_NUM 1 +#define OS_SEMAPHORE_OBJ_MEM 0 +#define OS_SEMAPHORE_NUM 1 +#define OS_MEMPOOL_OBJ_MEM 0 +#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_DATA_SIZE 0 +#define OS_MSGQUEUE_OBJ_MEM 0 +#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_DATA_SIZE 0 + +#endif /* RTX_CONFIG_H_ */ diff --git a/product/morello/mcp_ramfw_soc/fmw_cmsis.h b/product/morello/mcp_ramfw_soc/fmw_cmsis.h new file mode 100644 index 000000000..04d6f286f --- /dev/null +++ b/product/morello/mcp_ramfw_soc/fmw_cmsis.h @@ -0,0 +1,13 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include + +#endif /* FMW_CMSIS_H */ diff --git a/product/morello/mcp_ramfw_soc/rtx_config.c b/product/morello/mcp_ramfw_soc/rtx_config.c new file mode 100644 index 000000000..d51788201 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/rtx_config.c @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_system_clock.h" + +#include + +#include + +#include +#include + +/* + * Required by RTX to configure the SysTick timer. + */ +uint32_t SystemCoreClock = PIK_CLK_RATE_MCP_CORECLK; + +/* + * Idle thread + */ +__NO_RETURN void osRtxIdleThread(void *argument) +{ + while (true) { + __WFI(); + } +} + +/* + * OS error handler + */ +uint32_t osRtxErrorNotify(uint32_t code, void *object_id) +{ + osRtxIdleThread(object_id); +} + +uint32_t osRtxMemoryInit(void *mem, uint32_t size) +{ + return 1; +} + +void *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type) +{ + return fwk_mm_alloc(1, size); +} + +uint32_t osRtxMemoryFree(void *mem, void *block) +{ + fwk_mm_free(block); + + return 1; +} -- GitLab From db680df950d53dd87c1a739a0fc8e3d71e3b11f8 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 26/41] morello/mcp_ramfw_soc: add mpu config data Add configuration data for Armv7 MPU and MCP instruction/data memory layout for linker script. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I8f05b9fee2dca6ab6e9bf794252998fbae5332da --- .../morello/mcp_ramfw_soc/config_armv7m_mpu.c | 63 +++++++++++++++++++ product/morello/mcp_ramfw_soc/fmw_memory.h | 30 +++++++++ 2 files changed, 93 insertions(+) create mode 100644 product/morello/mcp_ramfw_soc/config_armv7m_mpu.c create mode 100644 product/morello/mcp_ramfw_soc/fmw_memory.h diff --git a/product/morello/mcp_ramfw_soc/config_armv7m_mpu.c b/product/morello/mcp_ramfw_soc/config_armv7m_mpu.c new file mode 100644 index 000000000..435780ae5 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_armv7m_mpu.c @@ -0,0 +1,63 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include + +static const ARM_MPU_Region_t regions[3] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 0, + 1, + 0, + ARM_MPU_REGION_SIZE_4GB), + }, + { + /* 0x0080_0000 - 0x0087_FFFF */ + .RBAR = ARM_MPU_RBAR(1, MCP_RAM0_BASE), + .RASR = ARM_MPU_RASR( + 0, + ARM_MPU_AP_PRO, + 0, + 0, + 1, + 0, + 0, + ARM_MPU_REGION_SIZE_512KB), + }, + { + /* 0x2000_0000 - 0x2003_FFFF */ + .RBAR = ARM_MPU_RBAR(2, MCP_RAM1_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 0, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; diff --git a/product/morello/mcp_ramfw_soc/fmw_memory.h b/product/morello/mcp_ramfw_soc/fmw_memory.h new file mode 100644 index 000000000..6c1485d57 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/fmw_memory.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "morello_mcp_system_mmap.h" + +#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FMW_MEM0_SIZE MCP_RAM0_SIZE +#define FMW_MEM0_BASE MCP_RAM0_BASE + +/* + * RAM data memory + */ +#define FMW_MEM1_SIZE MCP_RAM1_SIZE +#define FMW_MEM1_BASE MCP_RAM1_BASE + +#endif /* FMW_MEMORY_H */ -- GitLab From c7ea0424428995e6c9edcda5b8cad04560828a4a Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 27/41] morello/mcp_ramfw_soc: add scmi and mhu config data Add configuration data for SCMI agent to be used by MCP for communication with SCP. Also, add config files for mhu and smt modules. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Ic2ec8d747550e59fb3e0e325cdf0ea0f46683b3e --- product/morello/mcp_ramfw_soc/config_mhu.c | 40 +++++++++++++++++ .../morello/mcp_ramfw_soc/config_scmi_agent.c | 45 +++++++++++++++++++ product/morello/mcp_ramfw_soc/config_smt.c | 45 +++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 product/morello/mcp_ramfw_soc/config_mhu.c create mode 100644 product/morello/mcp_ramfw_soc/config_scmi_agent.c create mode 100644 product/morello/mcp_ramfw_soc/config_smt.c diff --git a/product/morello/mcp_ramfw_soc/config_mhu.c b/product/morello/mcp_ramfw_soc/config_mhu.c new file mode 100644 index 000000000..441d50393 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_mhu.c @@ -0,0 +1,40 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include + +#include + +static const struct fwk_element + mhu_element_table[MORELLO_MHU_DEVICE_IDX_COUNT + 1] = { + [MORELLO_MHU_DEVICE_IDX_S_SCP] = { + .name = "MHU_S_SCP", + .sub_element_count = 1, + .data = &((struct mod_mhu_device_config){ + .irq = MHU_SCP_SEC_IRQ, + .in = MHU_SCP_TO_MCP_S, + .out = MHU_MCP_TO_SCP_S, + }), + }, + [MORELLO_MHU_DEVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *mhu_get_element_table(fwk_id_t module_id) +{ + return mhu_element_table; +} + +struct fwk_module_config config_morello_mhu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(mhu_get_element_table), +}; diff --git a/product/morello/mcp_ramfw_soc/config_scmi_agent.c b/product/morello/mcp_ramfw_soc/config_scmi_agent.c new file mode 100644 index 000000000..5976d3a73 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_scmi_agent.c @@ -0,0 +1,45 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include + +static const struct fwk_element + agent_table[MCP_MORELLO_SCMI_AGENT_IDX_COUNT + 1] = { + [MCP_MORELLO_SCMI_AGENT_IDX_MANAGEMENT] = { + .name = "MCP-AGENT", + .data = &((struct mod_scmi_agent_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_MORELLO_SMT, + MCP_MORELLO_SCMI_AGENT_IDX_MANAGEMENT), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MORELLO_SMT, + MOD_SMT_API_IDX_SCMI_AGENT_TRANSPORT), + }), + }, + [MCP_MORELLO_SCMI_AGENT_IDX_COUNT] = { 0 } +}; + +static const struct fwk_element *get_agent_table(fwk_id_t module_id) +{ + return agent_table; +} + +const struct fwk_module_config config_scmi_agent = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_agent_table), + .data = NULL, +}; diff --git a/product/morello/mcp_ramfw_soc/config_smt.c b/product/morello/mcp_ramfw_soc/config_smt.c new file mode 100644 index 000000000..7e548c2d6 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_smt.c @@ -0,0 +1,45 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +static const struct fwk_element smt_element_table[2] = { + [0] = { + .name = "MANAGEMENT-S", + .data = &((struct mod_smt_channel_config){ + .type = MOD_SMT_CHANNEL_TYPE_MASTER, + .policies = MOD_SMT_POLICY_SECURE, + .mailbox_address = (uintptr_t)SCMI_PAYLOAD_SCP_TO_MCP_S, + .mailbox_size = MCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MORELLO_MHU, + MORELLO_MHU_DEVICE_IDX_S_SCP, + 0), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MORELLO_MHU, 0), + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *smt_get_element_table(fwk_id_t module_id) +{ + return smt_element_table; +} + +const struct fwk_module_config config_morello_smt = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(smt_get_element_table), +}; -- GitLab From 4994ec2dbb20679230fc5e7dce6f29903f32e76f Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 28/41] morello/mcp_ramfw_soc: add pl011 config data Add configuration data for PL011 UART module which is used as a console for firmware logs. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: Ib32a33fd8ec5d86b140164449ff808c404a31302 --- product/morello/mcp_ramfw_soc/config_pl011.c | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 product/morello/mcp_ramfw_soc/config_pl011.c diff --git a/product/morello/mcp_ramfw_soc/config_pl011.c b/product/morello/mcp_ramfw_soc/config_pl011.c new file mode 100644 index 000000000..3a8d07caa --- /dev/null +++ b/product/morello/mcp_ramfw_soc/config_pl011.c @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_mcp_mmap.h" +#include "morello_system_clock.h" + +#include + +#include +#include +#include + +struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS({ + [0] = { + .name = "MCP-UART", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = MCP_UART0_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_NONE_INIT, + }, + }, + + [1] = { 0 }, + }), +}; -- GitLab From 082a67981afda2c16c0a692a0350a5ca26a5275c Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Mon, 21 Jun 2021 16:03:43 +0100 Subject: [PATCH 29/41] morello/mcp_ramfw_soc: enable mcp ramfw image build Enable MCP RAM firmware build for Morello SoC. The target image is labelled as "mcp_ramfw_soc". Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I61a09113b1a567f4c208b90605e604a508e7258b --- product/morello/mcp_ramfw_soc/CMakeLists.txt | 51 +++++++++++++++++++ product/morello/mcp_ramfw_soc/Firmware.cmake | 40 +++++++++++++++ .../mcp_ramfw_soc/Toolchain-ArmClang.cmake | 20 ++++++++ .../morello/mcp_ramfw_soc/Toolchain-GNU.cmake | 18 +++++++ product/morello/mcp_ramfw_soc/firmware.mk | 38 ++++++++++++++ product/morello/product.mk | 3 +- 6 files changed, 169 insertions(+), 1 deletion(-) create mode 100644 product/morello/mcp_ramfw_soc/CMakeLists.txt create mode 100644 product/morello/mcp_ramfw_soc/Firmware.cmake create mode 100644 product/morello/mcp_ramfw_soc/Toolchain-ArmClang.cmake create mode 100644 product/morello/mcp_ramfw_soc/Toolchain-GNU.cmake create mode 100644 product/morello/mcp_ramfw_soc/firmware.mk diff --git a/product/morello/mcp_ramfw_soc/CMakeLists.txt b/product/morello/mcp_ramfw_soc/CMakeLists.txt new file mode 100644 index 000000000..b2886351c --- /dev/null +++ b/product/morello/mcp_ramfw_soc/CMakeLists.txt @@ -0,0 +1,51 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Create the firmware target. +# + +add_executable(morello-soc-mcp-bl2) + +target_include_directories( + morello-soc-mcp-bl2 PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../include" + "${CMAKE_CURRENT_SOURCE_DIR}") + +# cmake-lint: disable=E1122 + +target_sources( + morello-soc-mcp-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/rtx_config.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_armv7m_mpu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_mhu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_smt.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_agent.c") + +if(SCP_ENABLE_MULTITHREADING) + target_sources(morello-soc-mcp-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/rtx_config.c") + target_link_libraries(morello-soc-mcp-bl2 PRIVATE cmsis::rtos2-rtx) +endif() + +# +# Some of our firmware includes require CMSIS. +# + +target_link_libraries(morello-soc-mcp-bl2 PUBLIC cmsis::core-m) + +# +# We explicitly add the CMSIS include directories to our interfaceinclude +# directories. Each module target adds these include directories totheir own, +# allowing them to include any firmware includes we expose. +# + +target_include_directories( + morello-soc-mcp-bl2 + PUBLIC $) diff --git a/product/morello/mcp_ramfw_soc/Firmware.cmake b/product/morello/mcp_ramfw_soc/Firmware.cmake new file mode 100644 index 000000000..e6810a200 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/Firmware.cmake @@ -0,0 +1,40 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_FIRMWARE "morello-soc-mcp-bl2") +set(SCP_FIRMWARE_TARGET "morello-soc-mcp-bl2") + +set(SCP_TOOLCHAIN_INIT "GNU") + +set(SCP_FIRMWARE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") + +set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) + +set(SCP_ARCHITECTURE "armv7-m") + +set(SCP_ENABLE_MULTITHREADING_INIT FALSE) + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/morello_mcp_system") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_smt") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_mhu") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/scmi_agent") + +# The order of the modules in the following list is the order in which the +# modules are initialized, bound, started during the pre-runtime phase. +# any change in the order will cause firmware initialization errors. + +list(APPEND SCP_MODULES "armv7m-mpu") +list(APPEND SCP_MODULES "pl011") +list(APPEND SCP_MODULES "pik-clock") +list(APPEND SCP_MODULES "clock") +list(APPEND SCP_MODULES "morello-smt") +list(APPEND SCP_MODULES "morello-mhu") +list(APPEND SCP_MODULES "scmi-agent") +list(APPEND SCP_MODULES "morello-mcp-system") diff --git a/product/morello/mcp_ramfw_soc/Toolchain-ArmClang.cmake b/product/morello/mcp_ramfw_soc/Toolchain-ArmClang.cmake new file mode 100644 index 000000000..6e9e3fa0f --- /dev/null +++ b/product/morello/mcp_ramfw_soc/Toolchain-ArmClang.cmake @@ -0,0 +1,20 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cmake-lint: disable=C0301 + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/ArmClang-Baremetal.cmake" +) diff --git a/product/morello/mcp_ramfw_soc/Toolchain-GNU.cmake b/product/morello/mcp_ramfw_soc/Toolchain-GNU.cmake new file mode 100644 index 000000000..a4ea7a3f7 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/Toolchain-GNU.cmake @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") + +set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/morello/mcp_ramfw_soc/firmware.mk b/product/morello/mcp_ramfw_soc/firmware.mk new file mode 100644 index 000000000..b0f6bc5b8 --- /dev/null +++ b/product/morello/mcp_ramfw_soc/firmware.mk @@ -0,0 +1,38 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# The order of the modules in the BS_FIRMWARE_MODULES list is the order in which +# the modules are initialized, bound, started during the pre-runtime phase. +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := no +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := \ + power_domain \ + css_clock + +BS_FIRMWARE_MODULES := \ + armv7m_mpu \ + pl011 \ + pik_clock \ + clock \ + morello_mhu \ + morello_smt \ + scmi_agent \ + morello_mcp_system + +BS_FIRMWARE_SOURCES := \ + rtx_config.c \ + config_armv7m_mpu.c \ + config_pl011.c \ + config_pik_clock.c \ + config_clock.c \ + config_mhu.c \ + config_smt.c \ + config_scmi_agent.c + +include $(BS_DIR)/firmware.mk diff --git a/product/morello/product.mk b/product/morello/product.mk index 8795cbe2b..2b3e8d238 100644 --- a/product/morello/product.mk +++ b/product/morello/product.mk @@ -11,4 +11,5 @@ BS_FIRMWARE_LIST := \ mcp_ramfw_fvp \ scp_romfw \ mcp_romfw \ - scp_ramfw_soc + scp_ramfw_soc \ + mcp_ramfw_soc -- GitLab From ed0450133b39ca82e5f7a4c79434d26248f885f2 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Thu, 24 Jun 2021 11:20:01 +0100 Subject: [PATCH 30/41] morello/scp_ramfw_soc: include cadence i2c configuration Add configuration data required by cdns_i2c, a SCP core module. This module is required to communicate to attached DIMM in order to query the DRAM configuration/information. Signed-off-by: Manoj Kumar Signed-off-by: Anurag Koul Change-Id: I9dae87e9db6b70bd403150d7259129d48489aa64 --- product/morello/scp_ramfw_soc/CMakeLists.txt | 1 + product/morello/scp_ramfw_soc/Firmware.cmake | 2 + .../morello/scp_ramfw_soc/config_cdns_i2c.c | 62 +++++++++++++++++++ product/morello/scp_ramfw_soc/firmware.mk | 2 + 4 files changed, 67 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_cdns_i2c.c diff --git a/product/morello/scp_ramfw_soc/CMakeLists.txt b/product/morello/scp_ramfw_soc/CMakeLists.txt index 4d1df9c22..a69faea76 100644 --- a/product/morello/scp_ramfw_soc/CMakeLists.txt +++ b/product/morello/scp_ramfw_soc/CMakeLists.txt @@ -50,6 +50,7 @@ target_sources( "${CMAKE_CURRENT_SOURCE_DIR}/config_apcontext.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_resource_perms.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_morello_pcie.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_cdns_i2c.c" "${CMAKE_CURRENT_SOURCE_DIR}/../src/morello_core.c") if(SCP_ENABLE_MULTITHREADING) diff --git a/product/morello/scp_ramfw_soc/Firmware.cmake b/product/morello/scp_ramfw_soc/Firmware.cmake index 7edb5de05..aa38441b4 100644 --- a/product/morello/scp_ramfw_soc/Firmware.cmake +++ b/product/morello/scp_ramfw_soc/Firmware.cmake @@ -31,6 +31,7 @@ set(SCP_ENABLE_DEBUGGER_INIT FALSE) list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../../../module/fip") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_pll") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/cdns_i2c") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/dmc_bing") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_system") @@ -51,6 +52,7 @@ list(APPEND SCP_MODULES "ppu-v1") list(APPEND SCP_MODULES "ppu-v0") list(APPEND SCP_MODULES "system-power") list(APPEND SCP_MODULES "morello-pll") +list(APPEND SCP_MODULES "cdns-i2c") list(APPEND SCP_MODULES "dmc-bing") list(APPEND SCP_MODULES "mhu") list(APPEND SCP_MODULES "smt") diff --git a/product/morello/scp_ramfw_soc/config_cdns_i2c.c b/product/morello/scp_ramfw_soc/config_cdns_i2c.c new file mode 100644 index 000000000..1604d29aa --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_cdns_i2c.c @@ -0,0 +1,62 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_scp_mmap.h" + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +static const struct fwk_element i2c_element_desc_table[3] = { + [0] = { + .name = "SPD-I2C", + .data = &((struct mod_cdns_i2c_device_config) { + .reg_base = DIMM_SPD_I2C_BASE, + .clock_rate_hz = OSC_FREQ_HZ, + .bus_speed_hz = MOD_CDNS_I2C_SPEED_NORMAL, + .mode = MOD_CDNS_I2C_MASTER_MODE, + .ack_en = MOD_CDNS_I2C_ACK_ENABLE, + .addr_size = MOD_CDNS_I2C_ADDRESS_7_BIT, + .hold_mode = MOD_CDNS_I2C_HOLD_ON, + .callback_mod_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { + .name = "C2C-I2C", + .data = &((struct mod_cdns_i2c_device_config) { + .reg_base = SCP_I2C0_BASE, + .clock_rate_hz = (50UL * FWK_MHZ), + .bus_speed_hz = MOD_CDNS_I2C_SPEED_NORMAL, + .mode = MOD_CDNS_I2C_SLAVE_MODE, + .ack_en = MOD_CDNS_I2C_ACK_ENABLE, + .addr_size = MOD_CDNS_I2C_ADDRESS_7_BIT, + .hold_mode = MOD_CDNS_I2C_HOLD_OFF, + .slave_addr = 0x14, + .irq = SCP_I2C0_IRQ, + .callback_mod_id = FWK_ID_NONE_INIT, + }), + }, + [2] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *get_i2c_table(fwk_id_t module_id) +{ + return i2c_element_desc_table; +} + +const struct fwk_module_config config_cdns_i2c = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_i2c_table), +}; diff --git a/product/morello/scp_ramfw_soc/firmware.mk b/product/morello/scp_ramfw_soc/firmware.mk index b53ad4b95..eaed8e054 100644 --- a/product/morello/scp_ramfw_soc/firmware.mk +++ b/product/morello/scp_ramfw_soc/firmware.mk @@ -21,6 +21,7 @@ BS_FIRMWARE_MODULES := \ morello_pll \ ppu_v1 \ system_power \ + cdns_i2c \ dmc_bing \ mhu \ smt \ @@ -80,6 +81,7 @@ BS_FIRMWARE_SOURCES := \ config_scmi_management.c \ config_resource_perms.c \ config_morello_pcie.c \ + config_cdns_i2c.c ifeq ($(BUILD_HAS_DEBUGGER),yes) BS_FIRMWARE_MODULES += debugger_cli -- GitLab From c6f5a5c7b60731af4747a9232a303d7ace31cf86 Mon Sep 17 00:00:00 2001 From: Arnold Gabriel Benedict Date: Fri, 18 Jun 2021 16:35:54 +0100 Subject: [PATCH 31/41] morello: add dynamic calculation of PLL parameters Add functionalily to calculate the PLL parameters for any given frequency as opposed to having the parameters statically defined in the PLL configuration file for each particular frequency. Signed-off-by: Arnold Gabriel Benedict Signed-off-by: Anurag Koul Change-Id: I97391122a919efdb550cf8569f6f60d66b5663bc --- .../include/internal/morello_pll.h | 10 +- .../morello_pll/include/mod_morello_pll.h | 28 --- .../module/morello_pll/src/mod_morello_pll.c | 166 +++++++++++------- product/morello/scp_ramfw_fvp/config_clock.h | 4 +- .../scp_ramfw_fvp/config_morello_pll.c | 13 -- .../scp_ramfw_soc/config_morello_pll.c | 13 -- 6 files changed, 117 insertions(+), 117 deletions(-) diff --git a/product/morello/module/morello_pll/include/internal/morello_pll.h b/product/morello/module/morello_pll/include/internal/morello_pll.h index 41ffcc0d4..872d8ea96 100644 --- a/product/morello/module/morello_pll/include/internal/morello_pll.h +++ b/product/morello/module/morello_pll/include/internal/morello_pll.h @@ -30,8 +30,11 @@ #define PLL_POSTDIV2_POS 28 #define PLL_LOCK_STATUS_POS 31 +/*! The minimum reference frequency post REFDIV stage */ +#define MOD_MORELLO_PLL_REF_MIN (2UL * FWK_MHZ) + /*! The minimum frequency that the PLL hardware can output. */ -#define MOD_MORELLO_PLL_RATE_MIN (50UL * FWK_MHZ) +#define MOD_MORELLO_PLL_RATE_MIN (16UL * FWK_MHZ) /*! The maximum frequency that the PLL hardware can output. */ #define MOD_MORELLO_PLL_RATE_MAX (3200UL * FWK_MHZ) @@ -44,6 +47,11 @@ /*! The maximum feedback divider value */ #define MOD_MORELLO_PLL_FBDIV_MAX 1600 +/*! The minimum frequency output that post divider requires. */ +#define MOD_MORELLO_PLL_FVCO_MIN (800UL * FWK_MHZ) +/*! The maximum frequency output that post divider handles. */ +#define MOD_MORELLO_PLL_FVCO_MAX (3200UL * FWK_MHZ) + /*! The minimum reference clock divider value */ #define MOD_MORELLO_PLL_REFDIV_MIN 1 /*! The maximum reference clock divider value */ diff --git a/product/morello/module/morello_pll/include/mod_morello_pll.h b/product/morello/module/morello_pll/include/mod_morello_pll.h index 8a5fc0e5e..1583f43bc 100644 --- a/product/morello/module/morello_pll/include/mod_morello_pll.h +++ b/product/morello/module/morello_pll/include/mod_morello_pll.h @@ -66,34 +66,6 @@ struct mod_morello_pll_dev_config { const bool defer_initialization; }; -/*! - * \brief PLL parameter values for non-absolute frequencies. - */ -struct morello_pll_custom_freq_param_entry { - /*! Required output frequency value in MHz */ - uint16_t freq_value_mhz; - - /*! Feedback divider value for this frequency */ - uint16_t fbdiv; - - /*! Reference clock divider value for this frequency */ - uint8_t refdiv; - - /*! Post divider 1 value for this frequency */ - uint8_t postdiv; -}; - -/*! - * \brief MORELLO PLL module configuration. - */ -struct morello_pll_module_config { - /*! Pointer to custom frequency table */ - struct morello_pll_custom_freq_param_entry *custom_freq_table; - - /*! Size of custom frequency table */ - size_t custom_freq_table_size; -}; - /*! * \} */ diff --git a/product/morello/module/morello_pll/src/mod_morello_pll.c b/product/morello/module/morello_pll/src/mod_morello_pll.c index f2cb80d17..6b3925ff8 100644 --- a/product/morello/module/morello_pll/src/mod_morello_pll.c +++ b/product/morello/module/morello_pll/src/mod_morello_pll.c @@ -21,6 +21,8 @@ #include #include +#define FREQ_TOLERANCE_HZ 10000 + /* Device context */ struct morello_pll_dev_ctx { /* Configuration data of the PLL instance */ @@ -59,58 +61,102 @@ static int pll_set_rate( uint64_t rate, enum mod_clock_round_mode unused) { - uint64_t rounded_rate; - uint16_t fbdiv; - uint8_t refdiv; - uint8_t postdiv; + float fbdiv_f, fvco, fout; + uint16_t fbdiv_d; + uint8_t postdiv1, postdiv2, refdiv; + int64_t diff; uint32_t wait_cycles; - uint16_t rate_val_mhz; const struct mod_morello_pll_dev_config *config = NULL; - struct morello_pll_custom_freq_param_entry *freq_entry = NULL; - size_t i; fwk_assert(ctx != NULL); fwk_assert(rate <= ((uint64_t)UINT16_MAX * FWK_MHZ)); config = ctx->config; - if (ctx->current_state == MOD_CLOCK_STATE_STOPPED) + if (ctx->current_state == MOD_CLOCK_STATE_STOPPED) { return FWK_E_PWRSTATE; + } - if ((rate < MOD_MORELLO_PLL_RATE_MIN) || (rate > MOD_MORELLO_PLL_RATE_MAX)) + if ((rate < MOD_MORELLO_PLL_RATE_MIN) || + (rate > MOD_MORELLO_PLL_RATE_MAX)) { return FWK_E_RANGE; - - /* Assume initial refdiv and postdiv to be 1 */ - refdiv = MOD_MORELLO_PLL_REFDIV_MIN; - postdiv = MOD_MORELLO_PLL_POSTDIV_MIN; - fbdiv = rate / config->ref_rate; - rounded_rate = fbdiv * config->ref_rate; + } /* - * If required output value is not exact multiplication of reference - * clock value then look for the frequency in custom frequencies table. + * If requested frequency is integer multiple of reference frequency + * then the fbdiv_d calculation is a simple division provided it is + * within the valid range. */ - if (rounded_rate != rate) { - rate_val_mhz = (uint16_t)(rate / FWK_MHZ); - for (i = 0; i < module_ctx.mod_config->custom_freq_table_size; i++) { - freq_entry = &module_ctx.mod_config->custom_freq_table[i]; - if (freq_entry->freq_value_mhz == rate_val_mhz) { - fbdiv = freq_entry->fbdiv; - refdiv = freq_entry->refdiv; - postdiv = freq_entry->postdiv; - goto result; + if ((rate % config->ref_rate) == 0) { + fbdiv_d = rate / config->ref_rate; + if ((fbdiv_d >= MOD_MORELLO_PLL_FBDIV_MIN) && + (fbdiv_d <= MOD_MORELLO_PLL_FBDIV_MAX)) { + refdiv = 1; + postdiv1 = 1; + postdiv2 = 1; + goto write_pll_params; + } + } + + for (postdiv2 = MOD_MORELLO_PLL_POSTDIV_MIN; + postdiv2 <= MOD_MORELLO_PLL_POSTDIV_MAX; + postdiv2++) { + for (postdiv1 = MOD_MORELLO_PLL_POSTDIV_MIN; + postdiv1 <= MOD_MORELLO_PLL_POSTDIV_MAX; + postdiv1++) { + for (refdiv = MOD_MORELLO_PLL_REFDIV_MIN; + refdiv <= MOD_MORELLO_PLL_REFDIV_MAX; + refdiv++) { + /* Check if REF input is valid */ + if (((float)config->ref_rate / (float)refdiv) < + (float)MOD_MORELLO_PLL_REF_MIN) { + continue; + } + + fbdiv_f = (float)(rate * postdiv1 * postdiv2 * refdiv) / + (float)config->ref_rate; + fbdiv_d = (uint16_t)fbdiv_f; + + /* Round fbdiv_d to nearest integer */ + fbdiv_d = + ((fbdiv_f - (float)fbdiv_d) < 0.5) ? fbdiv_d : fbdiv_d + 1; + + /* Check if fbdiv_d is in valid range */ + if ((fbdiv_d < MOD_MORELLO_PLL_FBDIV_MIN) || + (fbdiv_d > MOD_MORELLO_PLL_FBDIV_MAX)) { + continue; + } + + fvco = + (((float)config->ref_rate / (float)refdiv) * + (float)fbdiv_d); + /* Check if VCO output is in valid range */ + if ((fvco < (float)MOD_MORELLO_PLL_FVCO_MIN) || + (fvco > (float)MOD_MORELLO_PLL_FVCO_MAX)) { + continue; + } + + fout = fvco / (float)postdiv1 / (float)postdiv2; + diff = (uint64_t)fout - rate; + if (diff < 0) { + diff = diff * -1; + } + + if (diff <= FREQ_TOLERANCE_HZ) { + goto write_pll_params; + } } } - /* Custom frequency table does not have matching frequency */ - return FWK_E_RANGE; } + /* We have reached end of loop without valid parameters */ + return FWK_E_SUPPORT; -result: +write_pll_params: /* Configure PLL settings */ *config->control_reg0 = - (fbdiv << PLL_FBDIV_BIT_POS) | (refdiv << PLL_REFDIV_POS); + (fbdiv_d << PLL_FBDIV_BIT_POS) | (refdiv << PLL_REFDIV_POS); *config->control_reg1 = - (postdiv << PLL_POSTDIV1_POS) | (1 << PLL_POSTDIV2_POS); + (postdiv1 << PLL_POSTDIV1_POS) | (postdiv2 << PLL_POSTDIV2_POS); /* Enable PLL settings */ *config->control_reg0 |= (UINT32_C(1) << PLL_PLLEN_POS); @@ -120,8 +166,9 @@ result: while ((*config->control_reg1 & (UINT32_C(1) << PLL_LOCK_STATUS_POS)) == 0) { wait_cycles--; - if (wait_cycles == 0) + if (wait_cycles == 0) { return FWK_E_TIMEOUT; + } } /* Store the current configured PLL rate */ @@ -141,8 +188,9 @@ static int morello_pll_set_rate( { struct morello_pll_dev_ctx *ctx = NULL; - if (!fwk_module_is_valid_element_id(dev_id)) + if (!fwk_module_is_valid_element_id(dev_id)) { return FWK_E_PARAM; + } ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(dev_id); @@ -153,8 +201,9 @@ static int morello_pll_get_rate(fwk_id_t dev_id, uint64_t *rate) { struct morello_pll_dev_ctx *ctx = NULL; - if ((!fwk_module_is_valid_element_id(dev_id)) || (rate == NULL)) + if ((!fwk_module_is_valid_element_id(dev_id)) || (rate == NULL)) { return FWK_E_PARAM; + } ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(dev_id); *rate = ctx->current_rate; @@ -173,8 +222,9 @@ static int morello_pll_get_rate_from_index( static int morello_pll_set_state(fwk_id_t dev_id, enum mod_clock_state state) { - if (state == MOD_CLOCK_STATE_RUNNING) + if (state == MOD_CLOCK_STATE_RUNNING) { return FWK_SUCCESS; + } /* PLLs can only be stopped by a parent power domain state change. */ return FWK_E_SUPPORT; @@ -184,8 +234,9 @@ static int morello_pll_get_state(fwk_id_t dev_id, enum mod_clock_state *state) { struct morello_pll_dev_ctx *ctx = NULL; - if ((!fwk_module_is_valid_element_id(dev_id)) || (state == NULL)) + if ((!fwk_module_is_valid_element_id(dev_id)) || (state == NULL)) { return FWK_E_PARAM; + } ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(dev_id); *state = ctx->current_state; @@ -195,8 +246,9 @@ static int morello_pll_get_state(fwk_id_t dev_id, enum mod_clock_state *state) static int morello_pll_get_range(fwk_id_t dev_id, struct mod_clock_range *range) { - if ((!fwk_module_is_valid_element_id(dev_id)) || (range == NULL)) + if ((!fwk_module_is_valid_element_id(dev_id)) || (range == NULL)) { return FWK_E_PARAM; + } range->rate_type = MOD_CLOCK_RATE_TYPE_CONTINUOUS; range->min = MOD_MORELLO_PLL_RATE_MIN; @@ -211,13 +263,15 @@ static int morello_pll_power_state_change(fwk_id_t dev_id, unsigned int state) uint64_t rate; struct morello_pll_dev_ctx *ctx = NULL; - if (!fwk_module_is_valid_element_id(dev_id)) + if (!fwk_module_is_valid_element_id(dev_id)) { return FWK_E_PARAM; + } ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(dev_id); - if (state != MOD_PD_STATE_ON) + if (state != MOD_PD_STATE_ON) { return FWK_SUCCESS; + } ctx->current_state = MOD_CLOCK_STATE_RUNNING; @@ -240,14 +294,16 @@ static int morello_pll_power_state_pending_change( { struct morello_pll_dev_ctx *ctx = NULL; - if (!fwk_module_is_valid_element_id(dev_id)) + if (!fwk_module_is_valid_element_id(dev_id)) { return FWK_E_PARAM; + } ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(dev_id); - if (next_state == MOD_PD_STATE_OFF) + if (next_state == MOD_PD_STATE_OFF) { /* Just mark the PLL as stopped */ ctx->current_state = MOD_CLOCK_STATE_STOPPED; + } return FWK_SUCCESS; } @@ -270,32 +326,18 @@ static const struct mod_clock_drv_api morello_pll_api = { static int morello_pll_init( fwk_id_t module_id, unsigned int element_count, - const void *config) + const void *data) { - size_t i; - struct morello_pll_custom_freq_param_entry *freq_entry; - - if ((element_count == 0) || (config == NULL)) + if (element_count == 0) { return FWK_E_PARAM; + } module_ctx.dev_count = element_count; module_ctx.dev_ctx_table = fwk_mm_calloc(element_count, sizeof(struct morello_pll_dev_ctx)); - if (module_ctx.dev_ctx_table == NULL) + if (module_ctx.dev_ctx_table == NULL) { return FWK_E_NOMEM; - - module_ctx.mod_config = config; - /* Validate custom frequency table entries */ - for (i = 0; i < module_ctx.mod_config->custom_freq_table_size; i++) { - freq_entry = &module_ctx.mod_config->custom_freq_table[i]; - if ((freq_entry->fbdiv < MOD_MORELLO_PLL_FBDIV_MIN) || - (freq_entry->fbdiv > MOD_MORELLO_PLL_FBDIV_MAX) || - (freq_entry->refdiv < MOD_MORELLO_PLL_REFDIV_MIN) || - (freq_entry->refdiv > MOD_MORELLO_PLL_REFDIV_MAX) || - (freq_entry->postdiv < MOD_MORELLO_PLL_POSTDIV_MIN) || - (freq_entry->postdiv > MOD_MORELLO_PLL_POSTDIV_MAX)) - return FWK_E_RANGE; } return FWK_SUCCESS; @@ -314,11 +356,13 @@ static int morello_pll_element_init( /* Check for valid element configuration data */ if ((ctx->config->control_reg0 == NULL) || - (ctx->config->control_reg1 == NULL) || (ctx->config->ref_rate == 0)) + (ctx->config->control_reg1 == NULL) || (ctx->config->ref_rate == 0)) { return FWK_E_PARAM; + } - if (ctx->config->defer_initialization) + if (ctx->config->defer_initialization) { return FWK_SUCCESS; + } ctx->initialized = true; ctx->current_state = MOD_CLOCK_STATE_RUNNING; diff --git a/product/morello/scp_ramfw_fvp/config_clock.h b/product/morello/scp_ramfw_fvp/config_clock.h index 676ba94fe..76be8c2a2 100644 --- a/product/morello/scp_ramfw_fvp/config_clock.h +++ b/product/morello/scp_ramfw_fvp/config_clock.h @@ -13,7 +13,9 @@ /* * DDR Subsystem clock in MHz */ -#define DDR_CLOCK_MHZ 1333 +/* 1333 MHz */ +#define DDR_CLOCK_MHZ (4000.0 / 3) +/* (4400.0/3) for 1466MHz */ /* * SCC & PIK clock rates. diff --git a/product/morello/scp_ramfw_fvp/config_morello_pll.c b/product/morello/scp_ramfw_fvp/config_morello_pll.c index f042e0c5b..9e9a34512 100644 --- a/product/morello/scp_ramfw_fvp/config_morello_pll.c +++ b/product/morello/scp_ramfw_fvp/config_morello_pll.c @@ -16,15 +16,6 @@ #include #include -static struct morello_pll_custom_freq_param_entry freq_table[] = { - { - .freq_value_mhz = 1333, - .fbdiv = 160, - .refdiv = 3, - .postdiv = 2, - }, -}; - static const struct fwk_element morello_pll_element_table[] = { [CLOCK_PLL_IDX_CPU0] = { @@ -97,8 +88,4 @@ static const struct fwk_element *morello_pll_get_element_table( const struct fwk_module_config config_morello_pll = { .elements = FWK_MODULE_DYNAMIC_ELEMENTS(morello_pll_get_element_table), - .data = &((struct morello_pll_module_config){ - .custom_freq_table = freq_table, - .custom_freq_table_size = FWK_ARRAY_SIZE(freq_table), - }), }; diff --git a/product/morello/scp_ramfw_soc/config_morello_pll.c b/product/morello/scp_ramfw_soc/config_morello_pll.c index ef1f95fd3..54d0a34e6 100644 --- a/product/morello/scp_ramfw_soc/config_morello_pll.c +++ b/product/morello/scp_ramfw_soc/config_morello_pll.c @@ -16,15 +16,6 @@ #include #include -static struct morello_pll_custom_freq_param_entry freq_table[1] = { - { - .freq_value_mhz = 1333, - .fbdiv = 160, - .refdiv = 3, - .postdiv = 2, - }, -}; - static const struct fwk_element morello_pll_element_table[CLOCK_PLL_IDX_COUNT + 1] = { [CLOCK_PLL_IDX_CPU0] = { @@ -119,8 +110,4 @@ static const struct fwk_element *morello_pll_get_element_table( const struct fwk_module_config config_morello_pll = { .elements = FWK_MODULE_DYNAMIC_ELEMENTS(morello_pll_get_element_table), - .data = &((struct morello_pll_module_config){ - .custom_freq_table = freq_table, - .custom_freq_table_size = FWK_ARRAY_SIZE(freq_table), - }), }; -- GitLab From 852a7146acd63d237f2e42ebf5fff554d7bc124b Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Thu, 21 Oct 2021 18:29:29 +0530 Subject: [PATCH 32/41] morello: Pass BOOT_GPR1 information in morello_platform_info The BOOT_GPR1 information is now passed over to TF-A via the shared sds_platform_info structure by SCP. The BOOT_GPR1 implements the configuration bits in BOOT_GPR1 SCC register. The configuration bits currently includes: - Bit 0 - Bing client/server mode configuration - Bit 1 - Reserved - Bit 2 - Bing C1 tag cache enable/disable - Bit 3 - Bing C2 tag cache enable/disable Signed-off-by: Manoj Kumar Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul Change-Id: Ida3f70bf8f5cbd050aec3a137ef29bbaa42cf31c --- product/morello/include/morello_sds.h | 2 +- .../morello/module/morello_system/src/mod_morello_system.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/product/morello/include/morello_sds.h b/product/morello/include/morello_sds.h index f025f705f..8ff1f4dd5 100644 --- a/product/morello/include/morello_sds.h +++ b/product/morello/include/morello_sds.h @@ -44,7 +44,7 @@ enum morello_sds_region_idx { #define MORELLO_SDS_FEATURE_AVAILABILITY_SIZE 4 #define MORELLO_SDS_CPU_BOOTCTR_SIZE 256 #define MORELLO_SDS_CPU_FLAGS_SIZE 256 -#define MORELLO_SDS_PLATFORM_INFO_SIZE 18 +#define MORELLO_SDS_PLATFORM_INFO_SIZE 22 /* * Field masks and offsets for the MORELLO_SDS_AP_CPU_INFO structure. diff --git a/product/morello/module/morello_system/src/mod_morello_system.c b/product/morello/module/morello_system/src/mod_morello_system.c index b974f0ad8..19943bf3e 100644 --- a/product/morello/module/morello_system/src/mod_morello_system.c +++ b/product/morello/module/morello_system/src/mod_morello_system.c @@ -59,6 +59,8 @@ struct FWK_PACKED morello_platform_info { uint8_t slave_count; /* If multichip mode */ bool multichip_mode; + /* Platform SCC configuration */ + uint32_t scc_config; }; /* MultiChip information */ @@ -268,6 +270,8 @@ static int morello_system_fill_platform_info(void) (uint32_t)(size >> 32), (uint32_t)size); + sds_platform_info.scc_config = SCC->BOOT_GPR1; + return morello_system_ctx.sds_api->struct_write( sds_structure_desc->id, 0, -- GitLab From c429ba23e7bdec968de277d98c83d6a09912e7bd Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Thu, 21 Oct 2021 18:52:30 +0530 Subject: [PATCH 33/41] morello: remove opmode and enable_ecc config options By default, SCP would boot in server mode and configuration of the client/server mode would be done in other bootloader stages. Opmode (client/server) is now controller via SCC BOOT_GPR1 register bits and is no longer required in the SCP DMC config. Co-authored-by: Manoj Kumar Signed-off-by: Manoj Kumar Signed-off-by: Chandni Cherukuri Change-Id: Ib1246c0b724883819f92bbf6db94e78572bf1db2 --- .../module/dmc_bing/include/mod_dmc_bing.h | 12 ----- .../module/dmc_bing/src/mod_dmc_bing.c | 45 +------------------ .../morello/scp_ramfw_fvp/config_dmc_bing.c | 2 - tools/cppcheck_suppress_list.txt | 1 + 4 files changed, 2 insertions(+), 58 deletions(-) diff --git a/product/morello/module/dmc_bing/include/mod_dmc_bing.h b/product/morello/module/dmc_bing/include/mod_dmc_bing.h index 5d8665eaa..155a4665c 100644 --- a/product/morello/module/dmc_bing/include/mod_dmc_bing.h +++ b/product/morello/module/dmc_bing/include/mod_dmc_bing.h @@ -634,14 +634,6 @@ struct mod_dmc_bing_reg { * \brief DDR training data slices position */ #define DDR_ADDR_DATA_SLICES_POS 12 -/*! - * \brief Bing operation in server mode - */ -#define BING_OPMODE_SERVER 0 -/*! - * \brief Bing operation in client mode - */ -#define BING_OPMODE_CLIENT 1 /*! * \brief Offset for Abort Register */ @@ -720,10 +712,6 @@ enum mod_dmc_bing_api_idx { struct mod_dmc_bing_module_config { /*! DDR operating frequency */ uint16_t ddr_speed; - /*! Bing operating mode */ - uint8_t opmode; - /*! Bing ECC control */ - bool enable_ecc; }; /*! diff --git a/product/morello/module/dmc_bing/src/mod_dmc_bing.c b/product/morello/module/dmc_bing/src/mod_dmc_bing.c index 020fc7c7c..ad467ac51 100644 --- a/product/morello/module/dmc_bing/src/mod_dmc_bing.c +++ b/product/morello/module/dmc_bing/src/mod_dmc_bing.c @@ -436,17 +436,10 @@ static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) static int dmc_bing_config(struct mod_dmc_bing_reg *dmc, fwk_id_t ddr_id) { - const struct mod_dmc_bing_module_config *mod_config; uint64_t mem_size; - uint64_t tag_mem_base; int status; - mod_config = fwk_module_get_data(FWK_ID_MODULE(FWK_MODULE_IDX_DMC_BING)); - - FWK_LOG_INFO( - "[DDR] Initialising DMC-Bing at 0x%x in %s mode", - (uintptr_t)dmc, - (mod_config->opmode == 0) ? "server" : "client"); + FWK_LOG_INFO("[DDR] Initialising DMC-Bing at 0x%x", (uintptr_t)dmc); dmc_bing_config_interrupt(ddr_id); @@ -555,42 +548,6 @@ static int dmc_bing_config(struct mod_dmc_bing_reg *dmc, fwk_id_t ddr_id) ddr_get_dimm_size(&mem_size); - if (mod_config->opmode == BING_OPMODE_CLIENT) { - usable_mem_size = mem_size - (mem_size / 128ULL); - - /* Linear DDR address */ - tag_mem_base = usable_mem_size; - tag_mem_base = tag_mem_base / 4; - /* Reverse translation */ - if (tag_mem_base < 0x80000000ULL) - tag_mem_base += 0x80000000ULL; - else - tag_mem_base = tag_mem_base - 0x80000000ULL + 0x8080000000ULL; - - dmc->CAPABILITY_CTRL = 0x1; - dmc->TAG_CACHE_CFG = 0x7; - dmc->MEMORY_ADDRESS_CTRL = (uint32_t)tag_mem_base; - dmc->MEMORY_ADDRESS_CTRL2 = (uint32_t)(tag_mem_base >> 32); - dmc->MEMORY_ACCESS_CTRL |= (1 << 16); - - FWK_LOG_INFO( - "[DDR] Tag base set to 0x%" PRIX32 "%" PRIX32, - dmc->MEMORY_ADDRESS_CTRL2, - dmc->MEMORY_ADDRESS_CTRL); - } else { - dmc->CAPABILITY_CTRL = 0; - usable_mem_size = mem_size; - } - - if (mod_config->enable_ecc) { - FWK_LOG_INFO("[DDR] Enabling ECC settings"); - dmc->ERR0CTLR0 |= 0x00000001; - dmc->ERR0CTLR1 |= 0x00000011; - dmc->BING_SPL_CTRL_REG &= ~0xC; - } else { - FWK_LOG_INFO("[DDR] Using DDR without ECC"); - dmc->BING_SPL_CTRL_REG |= 0xC; - } dmc->DIRECT_CMD = 0x0001000C; dmc->USER_CONFIG0_NEXT = 0x1; diff --git a/product/morello/scp_ramfw_fvp/config_dmc_bing.c b/product/morello/scp_ramfw_fvp/config_dmc_bing.c index 45af1cf53..29d311aa7 100644 --- a/product/morello/scp_ramfw_fvp/config_dmc_bing.c +++ b/product/morello/scp_ramfw_fvp/config_dmc_bing.c @@ -54,7 +54,5 @@ const struct fwk_module_config config_dmc_bing = { .elements = FWK_MODULE_DYNAMIC_ELEMENTS(dmc_bing_get_element_table), .data = &((struct mod_dmc_bing_module_config){ .ddr_speed = DDR_CLOCK_MHZ, - .opmode = BING_OPMODE_CLIENT, - .enable_ecc = false, }), }; diff --git a/tools/cppcheck_suppress_list.txt b/tools/cppcheck_suppress_list.txt index 3b82144e9..e82ba0026 100755 --- a/tools/cppcheck_suppress_list.txt +++ b/tools/cppcheck_suppress_list.txt @@ -181,6 +181,7 @@ objectIndex:*product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.c:438 objectIndex:*product/morello/module/morello_pcie/src/morello_pcie.c:390 knownConditionTrueFalse:*product/n1sdp/module/n1sdp_dmc620/src/mod_n1sdp_dmc620.c:85 syntaxError:*product/morello/scp_ramfw_soc/config_resource_perms.c:54 +syntaxError:*product/morello/module/dmc_bing/include/mod_dmc_bing.h:787 // Suppress CMSIS errors *:*/CMSIS*/* -- GitLab From 1dc37963ce41a3365dd8a4be5b26521d6530420a Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Thu, 21 Oct 2021 19:43:33 +0530 Subject: [PATCH 34/41] morello: Add SoC specific changes to dmc_bing module This patch adds the DIMM and Morello DDR PHY changes required for Morello SoC Platform. mod_dmc_bing.c file has also been modified to incorporate SoC specific changes. Co-authored-by: Manoj Kumar Signed-off-by: Manoj Kumar Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul Change-Id: I07956302ff70978498e70e45487cc9f22b373024 --- .../morello/module/dmc_bing/CMakeLists.txt | 20 + .../include/internal/morello_ddr_phy_reg.h | 2450 +++++++++++++++++ .../module/dmc_bing/include/mod_dmc_bing.h | 27 +- product/morello/module/dmc_bing/src/Makefile | 10 + .../module/dmc_bing/src/ddr_phy_values_1200.c | 1646 +++++++++++ .../module/dmc_bing/src/ddr_phy_values_1333.c | 1615 +++++++++++ .../module/dmc_bing/src/ddr_phy_values_800.c | 1547 +++++++++++ .../morello/module/dmc_bing/src/dimm_spd.c | 880 ++++++ .../morello/module/dmc_bing/src/dimm_spd.h | 492 ++++ .../module/dmc_bing/src/mod_dmc_bing.c | 872 +++++- .../module/dmc_bing/src/morello_ddr_phy.c | 998 +++++++ .../module/dmc_bing/src/morello_ddr_phy.h | 143 + tools/cppcheck_suppress_list.txt | 2 +- 13 files changed, 10661 insertions(+), 41 deletions(-) create mode 100644 product/morello/module/dmc_bing/include/internal/morello_ddr_phy_reg.h create mode 100644 product/morello/module/dmc_bing/src/ddr_phy_values_1200.c create mode 100644 product/morello/module/dmc_bing/src/ddr_phy_values_1333.c create mode 100644 product/morello/module/dmc_bing/src/ddr_phy_values_800.c create mode 100644 product/morello/module/dmc_bing/src/dimm_spd.c create mode 100644 product/morello/module/dmc_bing/src/dimm_spd.h create mode 100644 product/morello/module/dmc_bing/src/morello_ddr_phy.c create mode 100644 product/morello/module/dmc_bing/src/morello_ddr_phy.h diff --git a/product/morello/module/dmc_bing/CMakeLists.txt b/product/morello/module/dmc_bing/CMakeLists.txt index ad08f77d7..dc6cfe34a 100644 --- a/product/morello/module/dmc_bing/CMakeLists.txt +++ b/product/morello/module/dmc_bing/CMakeLists.txt @@ -6,6 +6,10 @@ # add_library(${SCP_MODULE_TARGET} SCP_MODULE) +if(SCP_ENABLE_PLAT_FVP) +target_compile_definitions(${SCP_MODULE_TARGET} PUBLIC -DPLAT_FVP=1) +endif() + target_include_directories(${SCP_MODULE_TARGET} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") @@ -13,3 +17,19 @@ target_sources(${SCP_MODULE_TARGET} PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_dmc_bing.c") target_link_libraries(${SCP_MODULE_TARGET} PRIVATE module-clock module-timer) + +# source and include files and libraries required by morello soc platform +if(NOT SCP_ENABLE_PLAT_FVP) +target_include_directories(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src") + + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/dimm_spd.c" + "${CMAKE_CURRENT_SOURCE_DIR}/src/morello_ddr_phy.c" + "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_800.c" + "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_1200.c" + "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_1333.c") + +target_link_libraries(${SCP_MODULE_TARGET} PRIVATE module-cdns-i2c) +endif() diff --git a/product/morello/module/dmc_bing/include/internal/morello_ddr_phy_reg.h b/product/morello/module/dmc_bing/include/internal/morello_ddr_phy_reg.h new file mode 100644 index 000000000..9042f0c9b --- /dev/null +++ b/product/morello/module/dmc_bing/include/internal/morello_ddr_phy_reg.h @@ -0,0 +1,2450 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Morello DDR PHY configuration registers. + */ + +#ifndef MORELLO_DDR_PHY_REG_H +#define MORELLO_DDR_PHY_REG_H + +#include + +#include + +/* + * Morello DDR PHY register definitions. + */ +struct mod_morello_ddr_phy_reg { + FWK_RW uint32_t DENALI_PHY_00_DATA; + FWK_RW uint32_t DENALI_PHY_01_DATA; + FWK_RW uint32_t DENALI_PHY_02_DATA; + FWK_RW uint32_t DENALI_PHY_03_DATA; + FWK_RW uint32_t DENALI_PHY_04_DATA; + FWK_RW uint32_t DENALI_PHY_05_DATA; + FWK_RW uint32_t DENALI_PHY_06_DATA; + FWK_RW uint32_t DENALI_PHY_07_DATA; + FWK_RW uint32_t DENALI_PHY_08_DATA; + FWK_RW uint32_t DENALI_PHY_09_DATA; + FWK_RW uint32_t DENALI_PHY_10_DATA; + FWK_RW uint32_t DENALI_PHY_11_DATA; + FWK_RW uint32_t DENALI_PHY_12_DATA; + FWK_RW uint32_t DENALI_PHY_13_DATA; + FWK_RW uint32_t DENALI_PHY_14_DATA; + FWK_RW uint32_t DENALI_PHY_15_DATA; + FWK_RW uint32_t DENALI_PHY_16_DATA; + FWK_RW uint32_t DENALI_PHY_17_DATA; + FWK_RW uint32_t DENALI_PHY_18_DATA; + FWK_RW uint32_t DENALI_PHY_19_DATA; + FWK_RW uint32_t DENALI_PHY_20_DATA; + FWK_RW uint32_t DENALI_PHY_21_DATA; + FWK_RW uint32_t DENALI_PHY_22_DATA; + FWK_RW uint32_t DENALI_PHY_23_DATA; + FWK_RW uint32_t DENALI_PHY_24_DATA; + FWK_RW uint32_t DENALI_PHY_25_DATA; + FWK_RW uint32_t DENALI_PHY_26_DATA; + FWK_RW uint32_t DENALI_PHY_27_DATA; + FWK_RW uint32_t DENALI_PHY_28_DATA; + FWK_RW uint32_t DENALI_PHY_29_DATA; + FWK_RW uint32_t DENALI_PHY_30_DATA; + FWK_RW uint32_t DENALI_PHY_31_DATA; + FWK_RW uint32_t DENALI_PHY_32_DATA; + FWK_RW uint32_t DENALI_PHY_33_DATA; + FWK_RW uint32_t DENALI_PHY_34_DATA; + FWK_RW uint32_t DENALI_PHY_35_DATA; + FWK_RW uint32_t DENALI_PHY_36_DATA; + FWK_RW uint32_t DENALI_PHY_37_DATA; + FWK_RW uint32_t DENALI_PHY_38_DATA; + FWK_RW uint32_t DENALI_PHY_39_DATA; + FWK_RW uint32_t DENALI_PHY_40_DATA; + FWK_RW uint32_t DENALI_PHY_41_DATA; + FWK_RW uint32_t DENALI_PHY_42_DATA; + FWK_RW uint32_t DENALI_PHY_43_DATA; + FWK_RW uint32_t DENALI_PHY_44_DATA; + FWK_RW uint32_t DENALI_PHY_45_DATA; + FWK_RW uint32_t DENALI_PHY_46_DATA; + FWK_RW uint32_t DENALI_PHY_47_DATA; + FWK_RW uint32_t DENALI_PHY_48_DATA; + FWK_RW uint32_t DENALI_PHY_49_DATA; + FWK_RW uint32_t DENALI_PHY_50_DATA; + FWK_RW uint32_t DENALI_PHY_51_DATA; + FWK_RW uint32_t DENALI_PHY_52_DATA; + FWK_RW uint32_t DENALI_PHY_53_DATA; + FWK_RW uint32_t DENALI_PHY_54_DATA; + FWK_RW uint32_t DENALI_PHY_55_DATA; + FWK_RW uint32_t DENALI_PHY_56_DATA; + FWK_RW uint32_t DENALI_PHY_57_DATA; + FWK_RW uint32_t DENALI_PHY_58_DATA; + FWK_RW uint32_t DENALI_PHY_59_DATA; + FWK_RW uint32_t DENALI_PHY_60_DATA; + FWK_RW uint32_t DENALI_PHY_61_DATA; + FWK_RW uint32_t DENALI_PHY_62_DATA; + FWK_RW uint32_t DENALI_PHY_63_DATA; + FWK_RW uint32_t DENALI_PHY_64_DATA; + FWK_RW uint32_t DENALI_PHY_65_DATA; + FWK_RW uint32_t DENALI_PHY_66_DATA; + FWK_RW uint32_t DENALI_PHY_67_DATA; + FWK_RW uint32_t DENALI_PHY_68_DATA; + FWK_RW uint32_t DENALI_PHY_69_DATA; + FWK_RW uint32_t DENALI_PHY_70_DATA; + FWK_RW uint32_t DENALI_PHY_71_DATA; + FWK_RW uint32_t DENALI_PHY_72_DATA; + FWK_RW uint32_t DENALI_PHY_73_DATA; + FWK_RW uint32_t DENALI_PHY_74_DATA; + FWK_RW uint32_t DENALI_PHY_75_DATA; + FWK_RW uint32_t DENALI_PHY_76_DATA; + FWK_RW uint32_t DENALI_PHY_77_DATA; + FWK_RW uint32_t DENALI_PHY_78_DATA; + FWK_RW uint32_t DENALI_PHY_79_DATA; + FWK_RW uint32_t DENALI_PHY_80_DATA; + FWK_RW uint32_t DENALI_PHY_81_DATA; + FWK_RW uint32_t DENALI_PHY_82_DATA; + FWK_RW uint32_t DENALI_PHY_83_DATA; + FWK_RW uint32_t DENALI_PHY_84_DATA; + FWK_RW uint32_t DENALI_PHY_85_DATA; + FWK_RW uint32_t DENALI_PHY_86_DATA; + FWK_RW uint32_t DENALI_PHY_87_DATA; + FWK_RW uint32_t DENALI_PHY_88_DATA; + FWK_RW uint32_t DENALI_PHY_89_DATA; + FWK_RW uint32_t DENALI_PHY_90_DATA; + FWK_RW uint32_t DENALI_PHY_91_DATA; + FWK_RW uint32_t DENALI_PHY_92_DATA; + FWK_RW uint32_t DENALI_PHY_93_DATA; + FWK_RW uint32_t DENALI_PHY_94_DATA; + FWK_RW uint32_t DENALI_PHY_95_DATA; + FWK_RW uint32_t DENALI_PHY_96_DATA; + FWK_RW uint32_t DENALI_PHY_97_DATA; + FWK_RW uint32_t DENALI_PHY_98_DATA; + FWK_RW uint32_t DENALI_PHY_99_DATA; + FWK_RW uint32_t DENALI_PHY_100_DATA; + FWK_RW uint32_t DENALI_PHY_101_DATA; + FWK_RW uint32_t DENALI_PHY_102_DATA; + FWK_RW uint32_t DENALI_PHY_103_DATA; + FWK_RW uint32_t DENALI_PHY_104_DATA; + FWK_RW uint32_t DENALI_PHY_105_DATA; + FWK_RW uint32_t DENALI_PHY_106_DATA; + FWK_RW uint32_t DENALI_PHY_107_DATA; + FWK_RW uint32_t DENALI_PHY_108_DATA; + FWK_RW uint32_t DENALI_PHY_109_DATA; + FWK_RW uint32_t DENALI_PHY_110_DATA; + FWK_RW uint32_t DENALI_PHY_111_DATA; + FWK_RW uint32_t DENALI_PHY_112_DATA; + FWK_RW uint32_t DENALI_PHY_113_DATA; + FWK_RW uint32_t DENALI_PHY_114_DATA; + FWK_RW uint32_t DENALI_PHY_115_DATA; + FWK_RW uint32_t DENALI_PHY_116_DATA; + FWK_RW uint32_t DENALI_PHY_117_DATA; + FWK_RW uint32_t DENALI_PHY_118_DATA; + FWK_RW uint32_t DENALI_PHY_119_DATA; + FWK_RW uint32_t DENALI_PHY_120_DATA; + FWK_RW uint32_t DENALI_PHY_121_DATA; + FWK_RW uint32_t DENALI_PHY_122_DATA; + FWK_RW uint32_t DENALI_PHY_123_DATA; + FWK_RW uint32_t DENALI_PHY_124_DATA; + FWK_RW uint32_t DENALI_PHY_125_DATA; + FWK_RW uint32_t DENALI_PHY_126_DATA; + FWK_RW uint32_t DENALI_PHY_127_DATA; + FWK_RW uint32_t DENALI_PHY_128_DATA; + FWK_RW uint32_t DENALI_PHY_129_DATA; + FWK_RW uint32_t DENALI_PHY_130_DATA; + FWK_RW uint32_t DENALI_PHY_131_DATA; + FWK_RW uint32_t DENALI_PHY_132_DATA; + FWK_RW uint32_t DENALI_PHY_133_DATA; + FWK_RW uint32_t DENALI_PHY_134_DATA; + FWK_RW uint32_t DENALI_PHY_135_DATA; + FWK_RW uint32_t DENALI_PHY_136_DATA; + FWK_RW uint32_t DENALI_PHY_137_DATA; + FWK_RW uint32_t DENALI_PHY_138_DATA; + FWK_RW uint32_t DENALI_PHY_139_DATA; + FWK_RW uint32_t DENALI_PHY_140_DATA; + FWK_RW uint32_t DENALI_PHY_141_DATA; + FWK_RW uint32_t DENALI_PHY_142_DATA; + FWK_RW uint32_t DENALI_PHY_143_DATA; + FWK_RW uint32_t DENALI_PHY_144_DATA; + FWK_RW uint32_t DENALI_PHY_145_DATA; + FWK_RW uint32_t DENALI_PHY_146_DATA; + FWK_RW uint32_t DENALI_PHY_147_DATA; + FWK_RW uint32_t DENALI_PHY_148_DATA; + FWK_RW uint32_t DENALI_PHY_149_DATA; + FWK_RW uint32_t DENALI_PHY_150_DATA; + FWK_RW uint32_t DENALI_PHY_151_DATA; + FWK_RW uint32_t DENALI_PHY_152_DATA; + FWK_RW uint32_t DENALI_PHY_153_DATA; + FWK_RW uint32_t DENALI_PHY_154_DATA; + FWK_RW uint32_t DENALI_PHY_155_DATA; + FWK_RW uint32_t DENALI_PHY_156_DATA; + FWK_RW uint32_t DENALI_PHY_157_DATA; + FWK_RW uint32_t DENALI_PHY_158_DATA; + FWK_RW uint32_t DENALI_PHY_159_DATA; + FWK_RW uint32_t DENALI_PHY_160_DATA; + FWK_RW uint32_t DENALI_PHY_161_DATA; + FWK_RW uint32_t DENALI_PHY_162_DATA; + FWK_RW uint32_t DENALI_PHY_163_DATA; + FWK_RW uint32_t DENALI_PHY_164_DATA; + FWK_RW uint32_t DENALI_PHY_165_DATA; + FWK_RW uint32_t DENALI_PHY_166_DATA; + FWK_RW uint32_t DENALI_PHY_167_DATA; + FWK_RW uint32_t DENALI_PHY_168_DATA; + FWK_RW uint32_t DENALI_PHY_169_DATA; + FWK_RW uint32_t DENALI_PHY_170_DATA; + FWK_RW uint32_t DENALI_PHY_171_DATA; + FWK_RW uint32_t DENALI_PHY_172_DATA; + FWK_RW uint32_t DENALI_PHY_173_DATA; + FWK_RW uint32_t DENALI_PHY_174_DATA; + FWK_RW uint32_t DENALI_PHY_175_DATA; + FWK_RW uint32_t DENALI_PHY_176_DATA; + FWK_RW uint32_t DENALI_PHY_177_DATA; + FWK_RW uint32_t DENALI_PHY_178_DATA; + FWK_RW uint32_t DENALI_PHY_179_DATA; + FWK_RW uint32_t DENALI_PHY_180_DATA; + FWK_RW uint32_t DENALI_PHY_181_DATA; + FWK_RW uint32_t DENALI_PHY_182_DATA; + FWK_RW uint32_t DENALI_PHY_183_DATA; + FWK_RW uint32_t DENALI_PHY_184_DATA; + FWK_RW uint32_t DENALI_PHY_185_DATA; + FWK_RW uint32_t DENALI_PHY_186_DATA; + FWK_RW uint32_t DENALI_PHY_187_DATA; + FWK_RW uint32_t DENALI_PHY_188_DATA; + FWK_RW uint32_t DENALI_PHY_189_DATA; + FWK_RW uint32_t DENALI_PHY_190_DATA; + FWK_RW uint32_t DENALI_PHY_191_DATA; + FWK_RW uint32_t DENALI_PHY_192_DATA; + FWK_RW uint32_t DENALI_PHY_193_DATA; + FWK_RW uint32_t DENALI_PHY_194_DATA; + FWK_RW uint32_t DENALI_PHY_195_DATA; + FWK_RW uint32_t DENALI_PHY_196_DATA; + FWK_RW uint32_t DENALI_PHY_197_DATA; + FWK_RW uint32_t DENALI_PHY_198_DATA; + FWK_RW uint32_t DENALI_PHY_199_DATA; + FWK_RW uint32_t DENALI_PHY_200_DATA; + FWK_RW uint32_t DENALI_PHY_201_DATA; + FWK_RW uint32_t DENALI_PHY_202_DATA; + FWK_RW uint32_t DENALI_PHY_203_DATA; + FWK_RW uint32_t DENALI_PHY_204_DATA; + FWK_RW uint32_t DENALI_PHY_205_DATA; + FWK_RW uint32_t DENALI_PHY_206_DATA; + FWK_RW uint32_t DENALI_PHY_207_DATA; + FWK_RW uint32_t DENALI_PHY_208_DATA; + FWK_RW uint32_t DENALI_PHY_209_DATA; + FWK_RW uint32_t DENALI_PHY_210_DATA; + FWK_RW uint32_t DENALI_PHY_211_DATA; + FWK_RW uint32_t DENALI_PHY_212_DATA; + FWK_RW uint32_t DENALI_PHY_213_DATA; + FWK_RW uint32_t DENALI_PHY_214_DATA; + FWK_RW uint32_t DENALI_PHY_215_DATA; + FWK_RW uint32_t DENALI_PHY_216_DATA; + FWK_RW uint32_t DENALI_PHY_217_DATA; + FWK_RW uint32_t DENALI_PHY_218_DATA; + FWK_RW uint32_t DENALI_PHY_219_DATA; + FWK_RW uint32_t DENALI_PHY_220_DATA; + FWK_RW uint32_t DENALI_PHY_221_DATA; + FWK_RW uint32_t DENALI_PHY_222_DATA; + FWK_RW uint32_t DENALI_PHY_223_DATA; + FWK_RW uint32_t DENALI_PHY_224_DATA; + FWK_RW uint32_t DENALI_PHY_225_DATA; + FWK_RW uint32_t DENALI_PHY_226_DATA; + FWK_RW uint32_t DENALI_PHY_227_DATA; + FWK_RW uint32_t DENALI_PHY_228_DATA; + FWK_RW uint32_t DENALI_PHY_229_DATA; + FWK_RW uint32_t DENALI_PHY_230_DATA; + FWK_RW uint32_t DENALI_PHY_231_DATA; + FWK_RW uint32_t DENALI_PHY_232_DATA; + FWK_RW uint32_t DENALI_PHY_233_DATA; + FWK_RW uint32_t DENALI_PHY_234_DATA; + FWK_RW uint32_t DENALI_PHY_235_DATA; + FWK_RW uint32_t DENALI_PHY_236_DATA; + FWK_RW uint32_t DENALI_PHY_237_DATA; + FWK_RW uint32_t DENALI_PHY_238_DATA; + FWK_RW uint32_t DENALI_PHY_239_DATA; + FWK_RW uint32_t DENALI_PHY_240_DATA; + FWK_RW uint32_t DENALI_PHY_241_DATA; + FWK_RW uint32_t DENALI_PHY_242_DATA; + FWK_RW uint32_t DENALI_PHY_243_DATA; + FWK_RW uint32_t DENALI_PHY_244_DATA; + FWK_RW uint32_t DENALI_PHY_245_DATA; + FWK_RW uint32_t DENALI_PHY_246_DATA; + FWK_RW uint32_t DENALI_PHY_247_DATA; + FWK_RW uint32_t DENALI_PHY_248_DATA; + FWK_RW uint32_t DENALI_PHY_249_DATA; + FWK_RW uint32_t DENALI_PHY_250_DATA; + FWK_RW uint32_t DENALI_PHY_251_DATA; + FWK_RW uint32_t DENALI_PHY_252_DATA; + FWK_RW uint32_t DENALI_PHY_253_DATA; + FWK_RW uint32_t DENALI_PHY_254_DATA; + FWK_RW uint32_t DENALI_PHY_255_DATA; + FWK_RW uint32_t DENALI_PHY_256_DATA; + FWK_RW uint32_t DENALI_PHY_257_DATA; + FWK_RW uint32_t DENALI_PHY_258_DATA; + FWK_RW uint32_t DENALI_PHY_259_DATA; + FWK_RW uint32_t DENALI_PHY_260_DATA; + FWK_RW uint32_t DENALI_PHY_261_DATA; + FWK_RW uint32_t DENALI_PHY_262_DATA; + FWK_RW uint32_t DENALI_PHY_263_DATA; + FWK_RW uint32_t DENALI_PHY_264_DATA; + FWK_RW uint32_t DENALI_PHY_265_DATA; + FWK_RW uint32_t DENALI_PHY_266_DATA; + FWK_RW uint32_t DENALI_PHY_267_DATA; + FWK_RW uint32_t DENALI_PHY_268_DATA; + FWK_RW uint32_t DENALI_PHY_269_DATA; + FWK_RW uint32_t DENALI_PHY_270_DATA; + FWK_RW uint32_t DENALI_PHY_271_DATA; + FWK_RW uint32_t DENALI_PHY_272_DATA; + FWK_RW uint32_t DENALI_PHY_273_DATA; + FWK_RW uint32_t DENALI_PHY_274_DATA; + FWK_RW uint32_t DENALI_PHY_275_DATA; + FWK_RW uint32_t DENALI_PHY_276_DATA; + FWK_RW uint32_t DENALI_PHY_277_DATA; + FWK_RW uint32_t DENALI_PHY_278_DATA; + FWK_RW uint32_t DENALI_PHY_279_DATA; + FWK_RW uint32_t DENALI_PHY_280_DATA; + FWK_RW uint32_t DENALI_PHY_281_DATA; + FWK_RW uint32_t DENALI_PHY_282_DATA; + FWK_RW uint32_t DENALI_PHY_283_DATA; + FWK_RW uint32_t DENALI_PHY_284_DATA; + FWK_RW uint32_t DENALI_PHY_285_DATA; + FWK_RW uint32_t DENALI_PHY_286_DATA; + FWK_RW uint32_t DENALI_PHY_287_DATA; + FWK_RW uint32_t DENALI_PHY_288_DATA; + FWK_RW uint32_t DENALI_PHY_289_DATA; + FWK_RW uint32_t DENALI_PHY_290_DATA; + FWK_RW uint32_t DENALI_PHY_291_DATA; + FWK_RW uint32_t DENALI_PHY_292_DATA; + FWK_RW uint32_t DENALI_PHY_293_DATA; + FWK_RW uint32_t DENALI_PHY_294_DATA; + FWK_RW uint32_t DENALI_PHY_295_DATA; + FWK_RW uint32_t DENALI_PHY_296_DATA; + FWK_RW uint32_t DENALI_PHY_297_DATA; + FWK_RW uint32_t DENALI_PHY_298_DATA; + FWK_RW uint32_t DENALI_PHY_299_DATA; + FWK_RW uint32_t DENALI_PHY_300_DATA; + FWK_RW uint32_t DENALI_PHY_301_DATA; + FWK_RW uint32_t DENALI_PHY_302_DATA; + FWK_RW uint32_t DENALI_PHY_303_DATA; + FWK_RW uint32_t DENALI_PHY_304_DATA; + FWK_RW uint32_t DENALI_PHY_305_DATA; + FWK_RW uint32_t DENALI_PHY_306_DATA; + FWK_RW uint32_t DENALI_PHY_307_DATA; + FWK_RW uint32_t DENALI_PHY_308_DATA; + FWK_RW uint32_t DENALI_PHY_309_DATA; + FWK_RW uint32_t DENALI_PHY_310_DATA; + FWK_RW uint32_t DENALI_PHY_311_DATA; + FWK_RW uint32_t DENALI_PHY_312_DATA; + FWK_RW uint32_t DENALI_PHY_313_DATA; + FWK_RW uint32_t DENALI_PHY_314_DATA; + FWK_RW uint32_t DENALI_PHY_315_DATA; + FWK_RW uint32_t DENALI_PHY_316_DATA; + FWK_RW uint32_t DENALI_PHY_317_DATA; + FWK_RW uint32_t DENALI_PHY_318_DATA; + FWK_RW uint32_t DENALI_PHY_319_DATA; + FWK_RW uint32_t DENALI_PHY_320_DATA; + FWK_RW uint32_t DENALI_PHY_321_DATA; + FWK_RW uint32_t DENALI_PHY_322_DATA; + FWK_RW uint32_t DENALI_PHY_323_DATA; + FWK_RW uint32_t DENALI_PHY_324_DATA; + FWK_RW uint32_t DENALI_PHY_325_DATA; + FWK_RW uint32_t DENALI_PHY_326_DATA; + FWK_RW uint32_t DENALI_PHY_327_DATA; + FWK_RW uint32_t DENALI_PHY_328_DATA; + FWK_RW uint32_t DENALI_PHY_329_DATA; + FWK_RW uint32_t DENALI_PHY_330_DATA; + FWK_RW uint32_t DENALI_PHY_331_DATA; + FWK_RW uint32_t DENALI_PHY_332_DATA; + FWK_RW uint32_t DENALI_PHY_333_DATA; + FWK_RW uint32_t DENALI_PHY_334_DATA; + FWK_RW uint32_t DENALI_PHY_335_DATA; + FWK_RW uint32_t DENALI_PHY_336_DATA; + FWK_RW uint32_t DENALI_PHY_337_DATA; + FWK_RW uint32_t DENALI_PHY_338_DATA; + FWK_RW uint32_t DENALI_PHY_339_DATA; + FWK_RW uint32_t DENALI_PHY_340_DATA; + FWK_RW uint32_t DENALI_PHY_341_DATA; + FWK_RW uint32_t DENALI_PHY_342_DATA; + FWK_RW uint32_t DENALI_PHY_343_DATA; + FWK_RW uint32_t DENALI_PHY_344_DATA; + FWK_RW uint32_t DENALI_PHY_345_DATA; + FWK_RW uint32_t DENALI_PHY_346_DATA; + FWK_RW uint32_t DENALI_PHY_347_DATA; + FWK_RW uint32_t DENALI_PHY_348_DATA; + FWK_RW uint32_t DENALI_PHY_349_DATA; + FWK_RW uint32_t DENALI_PHY_350_DATA; + FWK_RW uint32_t DENALI_PHY_351_DATA; + FWK_RW uint32_t DENALI_PHY_352_DATA; + FWK_RW uint32_t DENALI_PHY_353_DATA; + FWK_RW uint32_t DENALI_PHY_354_DATA; + FWK_RW uint32_t DENALI_PHY_355_DATA; + FWK_RW uint32_t DENALI_PHY_356_DATA; + FWK_RW uint32_t DENALI_PHY_357_DATA; + FWK_RW uint32_t DENALI_PHY_358_DATA; + FWK_RW uint32_t DENALI_PHY_359_DATA; + FWK_RW uint32_t DENALI_PHY_360_DATA; + FWK_RW uint32_t DENALI_PHY_361_DATA; + FWK_RW uint32_t DENALI_PHY_362_DATA; + FWK_RW uint32_t DENALI_PHY_363_DATA; + FWK_RW uint32_t DENALI_PHY_364_DATA; + FWK_RW uint32_t DENALI_PHY_365_DATA; + FWK_RW uint32_t DENALI_PHY_366_DATA; + FWK_RW uint32_t DENALI_PHY_367_DATA; + FWK_RW uint32_t DENALI_PHY_368_DATA; + FWK_RW uint32_t DENALI_PHY_369_DATA; + FWK_RW uint32_t DENALI_PHY_370_DATA; + FWK_RW uint32_t DENALI_PHY_371_DATA; + FWK_RW uint32_t DENALI_PHY_372_DATA; + FWK_RW uint32_t DENALI_PHY_373_DATA; + FWK_RW uint32_t DENALI_PHY_374_DATA; + FWK_RW uint32_t DENALI_PHY_375_DATA; + FWK_RW uint32_t DENALI_PHY_376_DATA; + FWK_RW uint32_t DENALI_PHY_377_DATA; + FWK_RW uint32_t DENALI_PHY_378_DATA; + FWK_RW uint32_t DENALI_PHY_379_DATA; + FWK_RW uint32_t DENALI_PHY_380_DATA; + FWK_RW uint32_t DENALI_PHY_381_DATA; + FWK_RW uint32_t DENALI_PHY_382_DATA; + FWK_RW uint32_t DENALI_PHY_383_DATA; + FWK_RW uint32_t DENALI_PHY_384_DATA; + FWK_RW uint32_t DENALI_PHY_385_DATA; + FWK_RW uint32_t DENALI_PHY_386_DATA; + FWK_RW uint32_t DENALI_PHY_387_DATA; + FWK_RW uint32_t DENALI_PHY_388_DATA; + FWK_RW uint32_t DENALI_PHY_389_DATA; + FWK_RW uint32_t DENALI_PHY_390_DATA; + FWK_RW uint32_t DENALI_PHY_391_DATA; + FWK_RW uint32_t DENALI_PHY_392_DATA; + FWK_RW uint32_t DENALI_PHY_393_DATA; + FWK_RW uint32_t DENALI_PHY_394_DATA; + FWK_RW uint32_t DENALI_PHY_395_DATA; + FWK_RW uint32_t DENALI_PHY_396_DATA; + FWK_RW uint32_t DENALI_PHY_397_DATA; + FWK_RW uint32_t DENALI_PHY_398_DATA; + FWK_RW uint32_t DENALI_PHY_399_DATA; + FWK_RW uint32_t DENALI_PHY_400_DATA; + FWK_RW uint32_t DENALI_PHY_401_DATA; + FWK_RW uint32_t DENALI_PHY_402_DATA; + FWK_RW uint32_t DENALI_PHY_403_DATA; + FWK_RW uint32_t DENALI_PHY_404_DATA; + FWK_RW uint32_t DENALI_PHY_405_DATA; + FWK_RW uint32_t DENALI_PHY_406_DATA; + FWK_RW uint32_t DENALI_PHY_407_DATA; + FWK_RW uint32_t DENALI_PHY_408_DATA; + FWK_RW uint32_t DENALI_PHY_409_DATA; + FWK_RW uint32_t DENALI_PHY_410_DATA; + FWK_RW uint32_t DENALI_PHY_411_DATA; + FWK_RW uint32_t DENALI_PHY_412_DATA; + FWK_RW uint32_t DENALI_PHY_413_DATA; + FWK_RW uint32_t DENALI_PHY_414_DATA; + FWK_RW uint32_t DENALI_PHY_415_DATA; + FWK_RW uint32_t DENALI_PHY_416_DATA; + FWK_RW uint32_t DENALI_PHY_417_DATA; + FWK_RW uint32_t DENALI_PHY_418_DATA; + FWK_RW uint32_t DENALI_PHY_419_DATA; + FWK_RW uint32_t DENALI_PHY_420_DATA; + FWK_RW uint32_t DENALI_PHY_421_DATA; + FWK_RW uint32_t DENALI_PHY_422_DATA; + FWK_RW uint32_t DENALI_PHY_423_DATA; + FWK_RW uint32_t DENALI_PHY_424_DATA; + FWK_RW uint32_t DENALI_PHY_425_DATA; + FWK_RW uint32_t DENALI_PHY_426_DATA; + FWK_RW uint32_t DENALI_PHY_427_DATA; + FWK_RW uint32_t DENALI_PHY_428_DATA; + FWK_RW uint32_t DENALI_PHY_429_DATA; + FWK_RW uint32_t DENALI_PHY_430_DATA; + FWK_RW uint32_t DENALI_PHY_431_DATA; + FWK_RW uint32_t DENALI_PHY_432_DATA; + FWK_RW uint32_t DENALI_PHY_433_DATA; + FWK_RW uint32_t DENALI_PHY_434_DATA; + FWK_RW uint32_t DENALI_PHY_435_DATA; + FWK_RW uint32_t DENALI_PHY_436_DATA; + FWK_RW uint32_t DENALI_PHY_437_DATA; + FWK_RW uint32_t DENALI_PHY_438_DATA; + FWK_RW uint32_t DENALI_PHY_439_DATA; + FWK_RW uint32_t DENALI_PHY_440_DATA; + FWK_RW uint32_t DENALI_PHY_441_DATA; + FWK_RW uint32_t DENALI_PHY_442_DATA; + FWK_RW uint32_t DENALI_PHY_443_DATA; + FWK_RW uint32_t DENALI_PHY_444_DATA; + FWK_RW uint32_t DENALI_PHY_445_DATA; + FWK_RW uint32_t DENALI_PHY_446_DATA; + FWK_RW uint32_t DENALI_PHY_447_DATA; + FWK_RW uint32_t DENALI_PHY_448_DATA; + FWK_RW uint32_t DENALI_PHY_449_DATA; + FWK_RW uint32_t DENALI_PHY_450_DATA; + FWK_RW uint32_t DENALI_PHY_451_DATA; + FWK_RW uint32_t DENALI_PHY_452_DATA; + FWK_RW uint32_t DENALI_PHY_453_DATA; + FWK_RW uint32_t DENALI_PHY_454_DATA; + FWK_RW uint32_t DENALI_PHY_455_DATA; + FWK_RW uint32_t DENALI_PHY_456_DATA; + FWK_RW uint32_t DENALI_PHY_457_DATA; + FWK_RW uint32_t DENALI_PHY_458_DATA; + FWK_RW uint32_t DENALI_PHY_459_DATA; + FWK_RW uint32_t DENALI_PHY_460_DATA; + FWK_RW uint32_t DENALI_PHY_461_DATA; + FWK_RW uint32_t DENALI_PHY_462_DATA; + FWK_RW uint32_t DENALI_PHY_463_DATA; + FWK_RW uint32_t DENALI_PHY_464_DATA; + FWK_RW uint32_t DENALI_PHY_465_DATA; + FWK_RW uint32_t DENALI_PHY_466_DATA; + FWK_RW uint32_t DENALI_PHY_467_DATA; + FWK_RW uint32_t DENALI_PHY_468_DATA; + FWK_RW uint32_t DENALI_PHY_469_DATA; + FWK_RW uint32_t DENALI_PHY_470_DATA; + FWK_RW uint32_t DENALI_PHY_471_DATA; + FWK_RW uint32_t DENALI_PHY_472_DATA; + FWK_RW uint32_t DENALI_PHY_473_DATA; + FWK_RW uint32_t DENALI_PHY_474_DATA; + FWK_RW uint32_t DENALI_PHY_475_DATA; + FWK_RW uint32_t DENALI_PHY_476_DATA; + FWK_RW uint32_t DENALI_PHY_477_DATA; + FWK_RW uint32_t DENALI_PHY_478_DATA; + FWK_RW uint32_t DENALI_PHY_479_DATA; + FWK_RW uint32_t DENALI_PHY_480_DATA; + FWK_RW uint32_t DENALI_PHY_481_DATA; + FWK_RW uint32_t DENALI_PHY_482_DATA; + FWK_RW uint32_t DENALI_PHY_483_DATA; + FWK_RW uint32_t DENALI_PHY_484_DATA; + FWK_RW uint32_t DENALI_PHY_485_DATA; + FWK_RW uint32_t DENALI_PHY_486_DATA; + FWK_RW uint32_t DENALI_PHY_487_DATA; + FWK_RW uint32_t DENALI_PHY_488_DATA; + FWK_RW uint32_t DENALI_PHY_489_DATA; + FWK_RW uint32_t DENALI_PHY_490_DATA; + FWK_RW uint32_t DENALI_PHY_491_DATA; + FWK_RW uint32_t DENALI_PHY_492_DATA; + FWK_RW uint32_t DENALI_PHY_493_DATA; + FWK_RW uint32_t DENALI_PHY_494_DATA; + FWK_RW uint32_t DENALI_PHY_495_DATA; + FWK_RW uint32_t DENALI_PHY_496_DATA; + FWK_RW uint32_t DENALI_PHY_497_DATA; + FWK_RW uint32_t DENALI_PHY_498_DATA; + FWK_RW uint32_t DENALI_PHY_499_DATA; + FWK_RW uint32_t DENALI_PHY_500_DATA; + FWK_RW uint32_t DENALI_PHY_501_DATA; + FWK_RW uint32_t DENALI_PHY_502_DATA; + FWK_RW uint32_t DENALI_PHY_503_DATA; + FWK_RW uint32_t DENALI_PHY_504_DATA; + FWK_RW uint32_t DENALI_PHY_505_DATA; + FWK_RW uint32_t DENALI_PHY_506_DATA; + FWK_RW uint32_t DENALI_PHY_507_DATA; + FWK_RW uint32_t DENALI_PHY_508_DATA; + FWK_RW uint32_t DENALI_PHY_509_DATA; + FWK_RW uint32_t DENALI_PHY_510_DATA; + FWK_RW uint32_t DENALI_PHY_511_DATA; + FWK_RW uint32_t DENALI_PHY_512_DATA; + FWK_RW uint32_t DENALI_PHY_513_DATA; + FWK_RW uint32_t DENALI_PHY_514_DATA; + FWK_RW uint32_t DENALI_PHY_515_DATA; + FWK_RW uint32_t DENALI_PHY_516_DATA; + FWK_RW uint32_t DENALI_PHY_517_DATA; + FWK_RW uint32_t DENALI_PHY_518_DATA; + FWK_RW uint32_t DENALI_PHY_519_DATA; + FWK_RW uint32_t DENALI_PHY_520_DATA; + FWK_RW uint32_t DENALI_PHY_521_DATA; + FWK_RW uint32_t DENALI_PHY_522_DATA; + FWK_RW uint32_t DENALI_PHY_523_DATA; + FWK_RW uint32_t DENALI_PHY_524_DATA; + FWK_RW uint32_t DENALI_PHY_525_DATA; + FWK_RW uint32_t DENALI_PHY_526_DATA; + FWK_RW uint32_t DENALI_PHY_527_DATA; + FWK_RW uint32_t DENALI_PHY_528_DATA; + FWK_RW uint32_t DENALI_PHY_529_DATA; + FWK_RW uint32_t DENALI_PHY_530_DATA; + FWK_RW uint32_t DENALI_PHY_531_DATA; + FWK_RW uint32_t DENALI_PHY_532_DATA; + FWK_RW uint32_t DENALI_PHY_533_DATA; + FWK_RW uint32_t DENALI_PHY_534_DATA; + FWK_RW uint32_t DENALI_PHY_535_DATA; + FWK_RW uint32_t DENALI_PHY_536_DATA; + FWK_RW uint32_t DENALI_PHY_537_DATA; + FWK_RW uint32_t DENALI_PHY_538_DATA; + FWK_RW uint32_t DENALI_PHY_539_DATA; + FWK_RW uint32_t DENALI_PHY_540_DATA; + FWK_RW uint32_t DENALI_PHY_541_DATA; + FWK_RW uint32_t DENALI_PHY_542_DATA; + FWK_RW uint32_t DENALI_PHY_543_DATA; + FWK_RW uint32_t DENALI_PHY_544_DATA; + FWK_RW uint32_t DENALI_PHY_545_DATA; + FWK_RW uint32_t DENALI_PHY_546_DATA; + FWK_RW uint32_t DENALI_PHY_547_DATA; + FWK_RW uint32_t DENALI_PHY_548_DATA; + FWK_RW uint32_t DENALI_PHY_549_DATA; + FWK_RW uint32_t DENALI_PHY_550_DATA; + FWK_RW uint32_t DENALI_PHY_551_DATA; + FWK_RW uint32_t DENALI_PHY_552_DATA; + FWK_RW uint32_t DENALI_PHY_553_DATA; + FWK_RW uint32_t DENALI_PHY_554_DATA; + FWK_RW uint32_t DENALI_PHY_555_DATA; + FWK_RW uint32_t DENALI_PHY_556_DATA; + FWK_RW uint32_t DENALI_PHY_557_DATA; + FWK_RW uint32_t DENALI_PHY_558_DATA; + FWK_RW uint32_t DENALI_PHY_559_DATA; + FWK_RW uint32_t DENALI_PHY_560_DATA; + FWK_RW uint32_t DENALI_PHY_561_DATA; + FWK_RW uint32_t DENALI_PHY_562_DATA; + FWK_RW uint32_t DENALI_PHY_563_DATA; + FWK_RW uint32_t DENALI_PHY_564_DATA; + FWK_RW uint32_t DENALI_PHY_565_DATA; + FWK_RW uint32_t DENALI_PHY_566_DATA; + FWK_RW uint32_t DENALI_PHY_567_DATA; + FWK_RW uint32_t DENALI_PHY_568_DATA; + FWK_RW uint32_t DENALI_PHY_569_DATA; + FWK_RW uint32_t DENALI_PHY_570_DATA; + FWK_RW uint32_t DENALI_PHY_571_DATA; + FWK_RW uint32_t DENALI_PHY_572_DATA; + FWK_RW uint32_t DENALI_PHY_573_DATA; + FWK_RW uint32_t DENALI_PHY_574_DATA; + FWK_RW uint32_t DENALI_PHY_575_DATA; + FWK_RW uint32_t DENALI_PHY_576_DATA; + FWK_RW uint32_t DENALI_PHY_577_DATA; + FWK_RW uint32_t DENALI_PHY_578_DATA; + FWK_RW uint32_t DENALI_PHY_579_DATA; + FWK_RW uint32_t DENALI_PHY_580_DATA; + FWK_RW uint32_t DENALI_PHY_581_DATA; + FWK_RW uint32_t DENALI_PHY_582_DATA; + FWK_RW uint32_t DENALI_PHY_583_DATA; + FWK_RW uint32_t DENALI_PHY_584_DATA; + FWK_RW uint32_t DENALI_PHY_585_DATA; + FWK_RW uint32_t DENALI_PHY_586_DATA; + FWK_RW uint32_t DENALI_PHY_587_DATA; + FWK_RW uint32_t DENALI_PHY_588_DATA; + FWK_RW uint32_t DENALI_PHY_589_DATA; + FWK_RW uint32_t DENALI_PHY_590_DATA; + FWK_RW uint32_t DENALI_PHY_591_DATA; + FWK_RW uint32_t DENALI_PHY_592_DATA; + FWK_RW uint32_t DENALI_PHY_593_DATA; + FWK_RW uint32_t DENALI_PHY_594_DATA; + FWK_RW uint32_t DENALI_PHY_595_DATA; + FWK_RW uint32_t DENALI_PHY_596_DATA; + FWK_RW uint32_t DENALI_PHY_597_DATA; + FWK_RW uint32_t DENALI_PHY_598_DATA; + FWK_RW uint32_t DENALI_PHY_599_DATA; + FWK_RW uint32_t DENALI_PHY_600_DATA; + FWK_RW uint32_t DENALI_PHY_601_DATA; + FWK_RW uint32_t DENALI_PHY_602_DATA; + FWK_RW uint32_t DENALI_PHY_603_DATA; + FWK_RW uint32_t DENALI_PHY_604_DATA; + FWK_RW uint32_t DENALI_PHY_605_DATA; + FWK_RW uint32_t DENALI_PHY_606_DATA; + FWK_RW uint32_t DENALI_PHY_607_DATA; + FWK_RW uint32_t DENALI_PHY_608_DATA; + FWK_RW uint32_t DENALI_PHY_609_DATA; + FWK_RW uint32_t DENALI_PHY_610_DATA; + FWK_RW uint32_t DENALI_PHY_611_DATA; + FWK_RW uint32_t DENALI_PHY_612_DATA; + FWK_RW uint32_t DENALI_PHY_613_DATA; + FWK_RW uint32_t DENALI_PHY_614_DATA; + FWK_RW uint32_t DENALI_PHY_615_DATA; + FWK_RW uint32_t DENALI_PHY_616_DATA; + FWK_RW uint32_t DENALI_PHY_617_DATA; + FWK_RW uint32_t DENALI_PHY_618_DATA; + FWK_RW uint32_t DENALI_PHY_619_DATA; + FWK_RW uint32_t DENALI_PHY_620_DATA; + FWK_RW uint32_t DENALI_PHY_621_DATA; + FWK_RW uint32_t DENALI_PHY_622_DATA; + FWK_RW uint32_t DENALI_PHY_623_DATA; + FWK_RW uint32_t DENALI_PHY_624_DATA; + FWK_RW uint32_t DENALI_PHY_625_DATA; + FWK_RW uint32_t DENALI_PHY_626_DATA; + FWK_RW uint32_t DENALI_PHY_627_DATA; + FWK_RW uint32_t DENALI_PHY_628_DATA; + FWK_RW uint32_t DENALI_PHY_629_DATA; + FWK_RW uint32_t DENALI_PHY_630_DATA; + FWK_RW uint32_t DENALI_PHY_631_DATA; + FWK_RW uint32_t DENALI_PHY_632_DATA; + FWK_RW uint32_t DENALI_PHY_633_DATA; + FWK_RW uint32_t DENALI_PHY_634_DATA; + FWK_RW uint32_t DENALI_PHY_635_DATA; + FWK_RW uint32_t DENALI_PHY_636_DATA; + FWK_RW uint32_t DENALI_PHY_637_DATA; + FWK_RW uint32_t DENALI_PHY_638_DATA; + FWK_RW uint32_t DENALI_PHY_639_DATA; + FWK_RW uint32_t DENALI_PHY_640_DATA; + FWK_RW uint32_t DENALI_PHY_641_DATA; + FWK_RW uint32_t DENALI_PHY_642_DATA; + FWK_RW uint32_t DENALI_PHY_643_DATA; + FWK_RW uint32_t DENALI_PHY_644_DATA; + FWK_RW uint32_t DENALI_PHY_645_DATA; + FWK_RW uint32_t DENALI_PHY_646_DATA; + FWK_RW uint32_t DENALI_PHY_647_DATA; + FWK_RW uint32_t DENALI_PHY_648_DATA; + FWK_RW uint32_t DENALI_PHY_649_DATA; + FWK_RW uint32_t DENALI_PHY_650_DATA; + FWK_RW uint32_t DENALI_PHY_651_DATA; + FWK_RW uint32_t DENALI_PHY_652_DATA; + FWK_RW uint32_t DENALI_PHY_653_DATA; + FWK_RW uint32_t DENALI_PHY_654_DATA; + FWK_RW uint32_t DENALI_PHY_655_DATA; + FWK_RW uint32_t DENALI_PHY_656_DATA; + FWK_RW uint32_t DENALI_PHY_657_DATA; + FWK_RW uint32_t DENALI_PHY_658_DATA; + FWK_RW uint32_t DENALI_PHY_659_DATA; + FWK_RW uint32_t DENALI_PHY_660_DATA; + FWK_RW uint32_t DENALI_PHY_661_DATA; + FWK_RW uint32_t DENALI_PHY_662_DATA; + FWK_RW uint32_t DENALI_PHY_663_DATA; + FWK_RW uint32_t DENALI_PHY_664_DATA; + FWK_RW uint32_t DENALI_PHY_665_DATA; + FWK_RW uint32_t DENALI_PHY_666_DATA; + FWK_RW uint32_t DENALI_PHY_667_DATA; + FWK_RW uint32_t DENALI_PHY_668_DATA; + FWK_RW uint32_t DENALI_PHY_669_DATA; + FWK_RW uint32_t DENALI_PHY_670_DATA; + FWK_RW uint32_t DENALI_PHY_671_DATA; + FWK_RW uint32_t DENALI_PHY_672_DATA; + FWK_RW uint32_t DENALI_PHY_673_DATA; + FWK_RW uint32_t DENALI_PHY_674_DATA; + FWK_RW uint32_t DENALI_PHY_675_DATA; + FWK_RW uint32_t DENALI_PHY_676_DATA; + FWK_RW uint32_t DENALI_PHY_677_DATA; + FWK_RW uint32_t DENALI_PHY_678_DATA; + FWK_RW uint32_t DENALI_PHY_679_DATA; + FWK_RW uint32_t DENALI_PHY_680_DATA; + FWK_RW uint32_t DENALI_PHY_681_DATA; + FWK_RW uint32_t DENALI_PHY_682_DATA; + FWK_RW uint32_t DENALI_PHY_683_DATA; + FWK_RW uint32_t DENALI_PHY_684_DATA; + FWK_RW uint32_t DENALI_PHY_685_DATA; + FWK_RW uint32_t DENALI_PHY_686_DATA; + FWK_RW uint32_t DENALI_PHY_687_DATA; + FWK_RW uint32_t DENALI_PHY_688_DATA; + FWK_RW uint32_t DENALI_PHY_689_DATA; + FWK_RW uint32_t DENALI_PHY_690_DATA; + FWK_RW uint32_t DENALI_PHY_691_DATA; + FWK_RW uint32_t DENALI_PHY_692_DATA; + FWK_RW uint32_t DENALI_PHY_693_DATA; + FWK_RW uint32_t DENALI_PHY_694_DATA; + FWK_RW uint32_t DENALI_PHY_695_DATA; + FWK_RW uint32_t DENALI_PHY_696_DATA; + FWK_RW uint32_t DENALI_PHY_697_DATA; + FWK_RW uint32_t DENALI_PHY_698_DATA; + FWK_RW uint32_t DENALI_PHY_699_DATA; + FWK_RW uint32_t DENALI_PHY_700_DATA; + FWK_RW uint32_t DENALI_PHY_701_DATA; + FWK_RW uint32_t DENALI_PHY_702_DATA; + FWK_RW uint32_t DENALI_PHY_703_DATA; + FWK_RW uint32_t DENALI_PHY_704_DATA; + FWK_RW uint32_t DENALI_PHY_705_DATA; + FWK_RW uint32_t DENALI_PHY_706_DATA; + FWK_RW uint32_t DENALI_PHY_707_DATA; + FWK_RW uint32_t DENALI_PHY_708_DATA; + FWK_RW uint32_t DENALI_PHY_709_DATA; + FWK_RW uint32_t DENALI_PHY_710_DATA; + FWK_RW uint32_t DENALI_PHY_711_DATA; + FWK_RW uint32_t DENALI_PHY_712_DATA; + FWK_RW uint32_t DENALI_PHY_713_DATA; + FWK_RW uint32_t DENALI_PHY_714_DATA; + FWK_RW uint32_t DENALI_PHY_715_DATA; + FWK_RW uint32_t DENALI_PHY_716_DATA; + FWK_RW uint32_t DENALI_PHY_717_DATA; + FWK_RW uint32_t DENALI_PHY_718_DATA; + FWK_RW uint32_t DENALI_PHY_719_DATA; + FWK_RW uint32_t DENALI_PHY_720_DATA; + FWK_RW uint32_t DENALI_PHY_721_DATA; + FWK_RW uint32_t DENALI_PHY_722_DATA; + FWK_RW uint32_t DENALI_PHY_723_DATA; + FWK_RW uint32_t DENALI_PHY_724_DATA; + FWK_RW uint32_t DENALI_PHY_725_DATA; + FWK_RW uint32_t DENALI_PHY_726_DATA; + FWK_RW uint32_t DENALI_PHY_727_DATA; + FWK_RW uint32_t DENALI_PHY_728_DATA; + FWK_RW uint32_t DENALI_PHY_729_DATA; + FWK_RW uint32_t DENALI_PHY_730_DATA; + FWK_RW uint32_t DENALI_PHY_731_DATA; + FWK_RW uint32_t DENALI_PHY_732_DATA; + FWK_RW uint32_t DENALI_PHY_733_DATA; + FWK_RW uint32_t DENALI_PHY_734_DATA; + FWK_RW uint32_t DENALI_PHY_735_DATA; + FWK_RW uint32_t DENALI_PHY_736_DATA; + FWK_RW uint32_t DENALI_PHY_737_DATA; + FWK_RW uint32_t DENALI_PHY_738_DATA; + FWK_RW uint32_t DENALI_PHY_739_DATA; + FWK_RW uint32_t DENALI_PHY_740_DATA; + FWK_RW uint32_t DENALI_PHY_741_DATA; + FWK_RW uint32_t DENALI_PHY_742_DATA; + FWK_RW uint32_t DENALI_PHY_743_DATA; + FWK_RW uint32_t DENALI_PHY_744_DATA; + FWK_RW uint32_t DENALI_PHY_745_DATA; + FWK_RW uint32_t DENALI_PHY_746_DATA; + FWK_RW uint32_t DENALI_PHY_747_DATA; + FWK_RW uint32_t DENALI_PHY_748_DATA; + FWK_RW uint32_t DENALI_PHY_749_DATA; + FWK_RW uint32_t DENALI_PHY_750_DATA; + FWK_RW uint32_t DENALI_PHY_751_DATA; + FWK_RW uint32_t DENALI_PHY_752_DATA; + FWK_RW uint32_t DENALI_PHY_753_DATA; + FWK_RW uint32_t DENALI_PHY_754_DATA; + FWK_RW uint32_t DENALI_PHY_755_DATA; + FWK_RW uint32_t DENALI_PHY_756_DATA; + FWK_RW uint32_t DENALI_PHY_757_DATA; + FWK_RW uint32_t DENALI_PHY_758_DATA; + FWK_RW uint32_t DENALI_PHY_759_DATA; + FWK_RW uint32_t DENALI_PHY_760_DATA; + FWK_RW uint32_t DENALI_PHY_761_DATA; + FWK_RW uint32_t DENALI_PHY_762_DATA; + FWK_RW uint32_t DENALI_PHY_763_DATA; + FWK_RW uint32_t DENALI_PHY_764_DATA; + FWK_RW uint32_t DENALI_PHY_765_DATA; + FWK_RW uint32_t DENALI_PHY_766_DATA; + FWK_RW uint32_t DENALI_PHY_767_DATA; + FWK_RW uint32_t DENALI_PHY_768_DATA; + FWK_RW uint32_t DENALI_PHY_769_DATA; + FWK_RW uint32_t DENALI_PHY_770_DATA; + FWK_RW uint32_t DENALI_PHY_771_DATA; + FWK_RW uint32_t DENALI_PHY_772_DATA; + FWK_RW uint32_t DENALI_PHY_773_DATA; + FWK_RW uint32_t DENALI_PHY_774_DATA; + FWK_RW uint32_t DENALI_PHY_775_DATA; + FWK_RW uint32_t DENALI_PHY_776_DATA; + FWK_RW uint32_t DENALI_PHY_777_DATA; + FWK_RW uint32_t DENALI_PHY_778_DATA; + FWK_RW uint32_t DENALI_PHY_779_DATA; + FWK_RW uint32_t DENALI_PHY_780_DATA; + FWK_RW uint32_t DENALI_PHY_781_DATA; + FWK_RW uint32_t DENALI_PHY_782_DATA; + FWK_RW uint32_t DENALI_PHY_783_DATA; + FWK_RW uint32_t DENALI_PHY_784_DATA; + FWK_RW uint32_t DENALI_PHY_785_DATA; + FWK_RW uint32_t DENALI_PHY_786_DATA; + FWK_RW uint32_t DENALI_PHY_787_DATA; + FWK_RW uint32_t DENALI_PHY_788_DATA; + FWK_RW uint32_t DENALI_PHY_789_DATA; + FWK_RW uint32_t DENALI_PHY_790_DATA; + FWK_RW uint32_t DENALI_PHY_791_DATA; + FWK_RW uint32_t DENALI_PHY_792_DATA; + FWK_RW uint32_t DENALI_PHY_793_DATA; + FWK_RW uint32_t DENALI_PHY_794_DATA; + FWK_RW uint32_t DENALI_PHY_795_DATA; + FWK_RW uint32_t DENALI_PHY_796_DATA; + FWK_RW uint32_t DENALI_PHY_797_DATA; + FWK_RW uint32_t DENALI_PHY_798_DATA; + FWK_RW uint32_t DENALI_PHY_799_DATA; + FWK_RW uint32_t DENALI_PHY_800_DATA; + FWK_RW uint32_t DENALI_PHY_801_DATA; + FWK_RW uint32_t DENALI_PHY_802_DATA; + FWK_RW uint32_t DENALI_PHY_803_DATA; + FWK_RW uint32_t DENALI_PHY_804_DATA; + FWK_RW uint32_t DENALI_PHY_805_DATA; + FWK_RW uint32_t DENALI_PHY_806_DATA; + FWK_RW uint32_t DENALI_PHY_807_DATA; + FWK_RW uint32_t DENALI_PHY_808_DATA; + FWK_RW uint32_t DENALI_PHY_809_DATA; + FWK_RW uint32_t DENALI_PHY_810_DATA; + FWK_RW uint32_t DENALI_PHY_811_DATA; + FWK_RW uint32_t DENALI_PHY_812_DATA; + FWK_RW uint32_t DENALI_PHY_813_DATA; + FWK_RW uint32_t DENALI_PHY_814_DATA; + FWK_RW uint32_t DENALI_PHY_815_DATA; + FWK_RW uint32_t DENALI_PHY_816_DATA; + FWK_RW uint32_t DENALI_PHY_817_DATA; + FWK_RW uint32_t DENALI_PHY_818_DATA; + FWK_RW uint32_t DENALI_PHY_819_DATA; + FWK_RW uint32_t DENALI_PHY_820_DATA; + FWK_RW uint32_t DENALI_PHY_821_DATA; + FWK_RW uint32_t DENALI_PHY_822_DATA; + FWK_RW uint32_t DENALI_PHY_823_DATA; + FWK_RW uint32_t DENALI_PHY_824_DATA; + FWK_RW uint32_t DENALI_PHY_825_DATA; + FWK_RW uint32_t DENALI_PHY_826_DATA; + FWK_RW uint32_t DENALI_PHY_827_DATA; + FWK_RW uint32_t DENALI_PHY_828_DATA; + FWK_RW uint32_t DENALI_PHY_829_DATA; + FWK_RW uint32_t DENALI_PHY_830_DATA; + FWK_RW uint32_t DENALI_PHY_831_DATA; + FWK_RW uint32_t DENALI_PHY_832_DATA; + FWK_RW uint32_t DENALI_PHY_833_DATA; + FWK_RW uint32_t DENALI_PHY_834_DATA; + FWK_RW uint32_t DENALI_PHY_835_DATA; + FWK_RW uint32_t DENALI_PHY_836_DATA; + FWK_RW uint32_t DENALI_PHY_837_DATA; + FWK_RW uint32_t DENALI_PHY_838_DATA; + FWK_RW uint32_t DENALI_PHY_839_DATA; + FWK_RW uint32_t DENALI_PHY_840_DATA; + FWK_RW uint32_t DENALI_PHY_841_DATA; + FWK_RW uint32_t DENALI_PHY_842_DATA; + FWK_RW uint32_t DENALI_PHY_843_DATA; + FWK_RW uint32_t DENALI_PHY_844_DATA; + FWK_RW uint32_t DENALI_PHY_845_DATA; + FWK_RW uint32_t DENALI_PHY_846_DATA; + FWK_RW uint32_t DENALI_PHY_847_DATA; + FWK_RW uint32_t DENALI_PHY_848_DATA; + FWK_RW uint32_t DENALI_PHY_849_DATA; + FWK_RW uint32_t DENALI_PHY_850_DATA; + FWK_RW uint32_t DENALI_PHY_851_DATA; + FWK_RW uint32_t DENALI_PHY_852_DATA; + FWK_RW uint32_t DENALI_PHY_853_DATA; + FWK_RW uint32_t DENALI_PHY_854_DATA; + FWK_RW uint32_t DENALI_PHY_855_DATA; + FWK_RW uint32_t DENALI_PHY_856_DATA; + FWK_RW uint32_t DENALI_PHY_857_DATA; + FWK_RW uint32_t DENALI_PHY_858_DATA; + FWK_RW uint32_t DENALI_PHY_859_DATA; + FWK_RW uint32_t DENALI_PHY_860_DATA; + FWK_RW uint32_t DENALI_PHY_861_DATA; + FWK_RW uint32_t DENALI_PHY_862_DATA; + FWK_RW uint32_t DENALI_PHY_863_DATA; + FWK_RW uint32_t DENALI_PHY_864_DATA; + FWK_RW uint32_t DENALI_PHY_865_DATA; + FWK_RW uint32_t DENALI_PHY_866_DATA; + FWK_RW uint32_t DENALI_PHY_867_DATA; + FWK_RW uint32_t DENALI_PHY_868_DATA; + FWK_RW uint32_t DENALI_PHY_869_DATA; + FWK_RW uint32_t DENALI_PHY_870_DATA; + FWK_RW uint32_t DENALI_PHY_871_DATA; + FWK_RW uint32_t DENALI_PHY_872_DATA; + FWK_RW uint32_t DENALI_PHY_873_DATA; + FWK_RW uint32_t DENALI_PHY_874_DATA; + FWK_RW uint32_t DENALI_PHY_875_DATA; + FWK_RW uint32_t DENALI_PHY_876_DATA; + FWK_RW uint32_t DENALI_PHY_877_DATA; + FWK_RW uint32_t DENALI_PHY_878_DATA; + FWK_RW uint32_t DENALI_PHY_879_DATA; + FWK_RW uint32_t DENALI_PHY_880_DATA; + FWK_RW uint32_t DENALI_PHY_881_DATA; + FWK_RW uint32_t DENALI_PHY_882_DATA; + FWK_RW uint32_t DENALI_PHY_883_DATA; + FWK_RW uint32_t DENALI_PHY_884_DATA; + FWK_RW uint32_t DENALI_PHY_885_DATA; + FWK_RW uint32_t DENALI_PHY_886_DATA; + FWK_RW uint32_t DENALI_PHY_887_DATA; + FWK_RW uint32_t DENALI_PHY_888_DATA; + FWK_RW uint32_t DENALI_PHY_889_DATA; + FWK_RW uint32_t DENALI_PHY_890_DATA; + FWK_RW uint32_t DENALI_PHY_891_DATA; + FWK_RW uint32_t DENALI_PHY_892_DATA; + FWK_RW uint32_t DENALI_PHY_893_DATA; + FWK_RW uint32_t DENALI_PHY_894_DATA; + FWK_RW uint32_t DENALI_PHY_895_DATA; + FWK_RW uint32_t DENALI_PHY_896_DATA; + FWK_RW uint32_t DENALI_PHY_897_DATA; + FWK_RW uint32_t DENALI_PHY_898_DATA; + FWK_RW uint32_t DENALI_PHY_899_DATA; + FWK_RW uint32_t DENALI_PHY_900_DATA; + FWK_RW uint32_t DENALI_PHY_901_DATA; + FWK_RW uint32_t DENALI_PHY_902_DATA; + FWK_RW uint32_t DENALI_PHY_903_DATA; + FWK_RW uint32_t DENALI_PHY_904_DATA; + FWK_RW uint32_t DENALI_PHY_905_DATA; + FWK_RW uint32_t DENALI_PHY_906_DATA; + FWK_RW uint32_t DENALI_PHY_907_DATA; + FWK_RW uint32_t DENALI_PHY_908_DATA; + FWK_RW uint32_t DENALI_PHY_909_DATA; + FWK_RW uint32_t DENALI_PHY_910_DATA; + FWK_RW uint32_t DENALI_PHY_911_DATA; + FWK_RW uint32_t DENALI_PHY_912_DATA; + FWK_RW uint32_t DENALI_PHY_913_DATA; + FWK_RW uint32_t DENALI_PHY_914_DATA; + FWK_RW uint32_t DENALI_PHY_915_DATA; + FWK_RW uint32_t DENALI_PHY_916_DATA; + FWK_RW uint32_t DENALI_PHY_917_DATA; + FWK_RW uint32_t DENALI_PHY_918_DATA; + FWK_RW uint32_t DENALI_PHY_919_DATA; + FWK_RW uint32_t DENALI_PHY_920_DATA; + FWK_RW uint32_t DENALI_PHY_921_DATA; + FWK_RW uint32_t DENALI_PHY_922_DATA; + FWK_RW uint32_t DENALI_PHY_923_DATA; + FWK_RW uint32_t DENALI_PHY_924_DATA; + FWK_RW uint32_t DENALI_PHY_925_DATA; + FWK_RW uint32_t DENALI_PHY_926_DATA; + FWK_RW uint32_t DENALI_PHY_927_DATA; + FWK_RW uint32_t DENALI_PHY_928_DATA; + FWK_RW uint32_t DENALI_PHY_929_DATA; + FWK_RW uint32_t DENALI_PHY_930_DATA; + FWK_RW uint32_t DENALI_PHY_931_DATA; + FWK_RW uint32_t DENALI_PHY_932_DATA; + FWK_RW uint32_t DENALI_PHY_933_DATA; + FWK_RW uint32_t DENALI_PHY_934_DATA; + FWK_RW uint32_t DENALI_PHY_935_DATA; + FWK_RW uint32_t DENALI_PHY_936_DATA; + FWK_RW uint32_t DENALI_PHY_937_DATA; + FWK_RW uint32_t DENALI_PHY_938_DATA; + FWK_RW uint32_t DENALI_PHY_939_DATA; + FWK_RW uint32_t DENALI_PHY_940_DATA; + FWK_RW uint32_t DENALI_PHY_941_DATA; + FWK_RW uint32_t DENALI_PHY_942_DATA; + FWK_RW uint32_t DENALI_PHY_943_DATA; + FWK_RW uint32_t DENALI_PHY_944_DATA; + FWK_RW uint32_t DENALI_PHY_945_DATA; + FWK_RW uint32_t DENALI_PHY_946_DATA; + FWK_RW uint32_t DENALI_PHY_947_DATA; + FWK_RW uint32_t DENALI_PHY_948_DATA; + FWK_RW uint32_t DENALI_PHY_949_DATA; + FWK_RW uint32_t DENALI_PHY_950_DATA; + FWK_RW uint32_t DENALI_PHY_951_DATA; + FWK_RW uint32_t DENALI_PHY_952_DATA; + FWK_RW uint32_t DENALI_PHY_953_DATA; + FWK_RW uint32_t DENALI_PHY_954_DATA; + FWK_RW uint32_t DENALI_PHY_955_DATA; + FWK_RW uint32_t DENALI_PHY_956_DATA; + FWK_RW uint32_t DENALI_PHY_957_DATA; + FWK_RW uint32_t DENALI_PHY_958_DATA; + FWK_RW uint32_t DENALI_PHY_959_DATA; + FWK_RW uint32_t DENALI_PHY_960_DATA; + FWK_RW uint32_t DENALI_PHY_961_DATA; + FWK_RW uint32_t DENALI_PHY_962_DATA; + FWK_RW uint32_t DENALI_PHY_963_DATA; + FWK_RW uint32_t DENALI_PHY_964_DATA; + FWK_RW uint32_t DENALI_PHY_965_DATA; + FWK_RW uint32_t DENALI_PHY_966_DATA; + FWK_RW uint32_t DENALI_PHY_967_DATA; + FWK_RW uint32_t DENALI_PHY_968_DATA; + FWK_RW uint32_t DENALI_PHY_969_DATA; + FWK_RW uint32_t DENALI_PHY_970_DATA; + FWK_RW uint32_t DENALI_PHY_971_DATA; + FWK_RW uint32_t DENALI_PHY_972_DATA; + FWK_RW uint32_t DENALI_PHY_973_DATA; + FWK_RW uint32_t DENALI_PHY_974_DATA; + FWK_RW uint32_t DENALI_PHY_975_DATA; + FWK_RW uint32_t DENALI_PHY_976_DATA; + FWK_RW uint32_t DENALI_PHY_977_DATA; + FWK_RW uint32_t DENALI_PHY_978_DATA; + FWK_RW uint32_t DENALI_PHY_979_DATA; + FWK_RW uint32_t DENALI_PHY_980_DATA; + FWK_RW uint32_t DENALI_PHY_981_DATA; + FWK_RW uint32_t DENALI_PHY_982_DATA; + FWK_RW uint32_t DENALI_PHY_983_DATA; + FWK_RW uint32_t DENALI_PHY_984_DATA; + FWK_RW uint32_t DENALI_PHY_985_DATA; + FWK_RW uint32_t DENALI_PHY_986_DATA; + FWK_RW uint32_t DENALI_PHY_987_DATA; + FWK_RW uint32_t DENALI_PHY_988_DATA; + FWK_RW uint32_t DENALI_PHY_989_DATA; + FWK_RW uint32_t DENALI_PHY_990_DATA; + FWK_RW uint32_t DENALI_PHY_991_DATA; + FWK_RW uint32_t DENALI_PHY_992_DATA; + FWK_RW uint32_t DENALI_PHY_993_DATA; + FWK_RW uint32_t DENALI_PHY_994_DATA; + FWK_RW uint32_t DENALI_PHY_995_DATA; + FWK_RW uint32_t DENALI_PHY_996_DATA; + FWK_RW uint32_t DENALI_PHY_997_DATA; + FWK_RW uint32_t DENALI_PHY_998_DATA; + FWK_RW uint32_t DENALI_PHY_999_DATA; + FWK_RW uint32_t DENALI_PHY_1000_DATA; + FWK_RW uint32_t DENALI_PHY_1001_DATA; + FWK_RW uint32_t DENALI_PHY_1002_DATA; + FWK_RW uint32_t DENALI_PHY_1003_DATA; + FWK_RW uint32_t DENALI_PHY_1004_DATA; + FWK_RW uint32_t DENALI_PHY_1005_DATA; + FWK_RW uint32_t DENALI_PHY_1006_DATA; + FWK_RW uint32_t DENALI_PHY_1007_DATA; + FWK_RW uint32_t DENALI_PHY_1008_DATA; + FWK_RW uint32_t DENALI_PHY_1009_DATA; + FWK_RW uint32_t DENALI_PHY_1010_DATA; + FWK_RW uint32_t DENALI_PHY_1011_DATA; + FWK_RW uint32_t DENALI_PHY_1012_DATA; + FWK_RW uint32_t DENALI_PHY_1013_DATA; + FWK_RW uint32_t DENALI_PHY_1014_DATA; + FWK_RW uint32_t DENALI_PHY_1015_DATA; + FWK_RW uint32_t DENALI_PHY_1016_DATA; + FWK_RW uint32_t DENALI_PHY_1017_DATA; + FWK_RW uint32_t DENALI_PHY_1018_DATA; + FWK_RW uint32_t DENALI_PHY_1019_DATA; + FWK_RW uint32_t DENALI_PHY_1020_DATA; + FWK_RW uint32_t DENALI_PHY_1021_DATA; + FWK_RW uint32_t DENALI_PHY_1022_DATA; + FWK_RW uint32_t DENALI_PHY_1023_DATA; + FWK_RW uint32_t DENALI_PHY_1024_DATA; + FWK_RW uint32_t DENALI_PHY_1025_DATA; + FWK_RW uint32_t DENALI_PHY_1026_DATA; + FWK_RW uint32_t DENALI_PHY_1027_DATA; + FWK_RW uint32_t DENALI_PHY_1028_DATA; + FWK_RW uint32_t DENALI_PHY_1029_DATA; + FWK_RW uint32_t DENALI_PHY_1030_DATA; + FWK_RW uint32_t DENALI_PHY_1031_DATA; + FWK_RW uint32_t DENALI_PHY_1032_DATA; + FWK_RW uint32_t DENALI_PHY_1033_DATA; + FWK_RW uint32_t DENALI_PHY_1034_DATA; + FWK_RW uint32_t DENALI_PHY_1035_DATA; + FWK_RW uint32_t DENALI_PHY_1036_DATA; + FWK_RW uint32_t DENALI_PHY_1037_DATA; + FWK_RW uint32_t DENALI_PHY_1038_DATA; + FWK_RW uint32_t DENALI_PHY_1039_DATA; + FWK_RW uint32_t DENALI_PHY_1040_DATA; + FWK_RW uint32_t DENALI_PHY_1041_DATA; + FWK_RW uint32_t DENALI_PHY_1042_DATA; + FWK_RW uint32_t DENALI_PHY_1043_DATA; + FWK_RW uint32_t DENALI_PHY_1044_DATA; + FWK_RW uint32_t DENALI_PHY_1045_DATA; + FWK_RW uint32_t DENALI_PHY_1046_DATA; + FWK_RW uint32_t DENALI_PHY_1047_DATA; + FWK_RW uint32_t DENALI_PHY_1048_DATA; + FWK_RW uint32_t DENALI_PHY_1049_DATA; + FWK_RW uint32_t DENALI_PHY_1050_DATA; + FWK_RW uint32_t DENALI_PHY_1051_DATA; + FWK_RW uint32_t DENALI_PHY_1052_DATA; + FWK_RW uint32_t DENALI_PHY_1053_DATA; + FWK_RW uint32_t DENALI_PHY_1054_DATA; + FWK_RW uint32_t DENALI_PHY_1055_DATA; + FWK_RW uint32_t DENALI_PHY_1056_DATA; + FWK_RW uint32_t DENALI_PHY_1057_DATA; + FWK_RW uint32_t DENALI_PHY_1058_DATA; + FWK_RW uint32_t DENALI_PHY_1059_DATA; + FWK_RW uint32_t DENALI_PHY_1060_DATA; + FWK_RW uint32_t DENALI_PHY_1061_DATA; + FWK_RW uint32_t DENALI_PHY_1062_DATA; + FWK_RW uint32_t DENALI_PHY_1063_DATA; + FWK_RW uint32_t DENALI_PHY_1064_DATA; + FWK_RW uint32_t DENALI_PHY_1065_DATA; + FWK_RW uint32_t DENALI_PHY_1066_DATA; + FWK_RW uint32_t DENALI_PHY_1067_DATA; + FWK_RW uint32_t DENALI_PHY_1068_DATA; + FWK_RW uint32_t DENALI_PHY_1069_DATA; + FWK_RW uint32_t DENALI_PHY_1070_DATA; + FWK_RW uint32_t DENALI_PHY_1071_DATA; + FWK_RW uint32_t DENALI_PHY_1072_DATA; + FWK_RW uint32_t DENALI_PHY_1073_DATA; + FWK_RW uint32_t DENALI_PHY_1074_DATA; + FWK_RW uint32_t DENALI_PHY_1075_DATA; + FWK_RW uint32_t DENALI_PHY_1076_DATA; + FWK_RW uint32_t DENALI_PHY_1077_DATA; + FWK_RW uint32_t DENALI_PHY_1078_DATA; + FWK_RW uint32_t DENALI_PHY_1079_DATA; + FWK_RW uint32_t DENALI_PHY_1080_DATA; + FWK_RW uint32_t DENALI_PHY_1081_DATA; + FWK_RW uint32_t DENALI_PHY_1082_DATA; + FWK_RW uint32_t DENALI_PHY_1083_DATA; + FWK_RW uint32_t DENALI_PHY_1084_DATA; + FWK_RW uint32_t DENALI_PHY_1085_DATA; + FWK_RW uint32_t DENALI_PHY_1086_DATA; + FWK_RW uint32_t DENALI_PHY_1087_DATA; + FWK_RW uint32_t DENALI_PHY_1088_DATA; + FWK_RW uint32_t DENALI_PHY_1089_DATA; + FWK_RW uint32_t DENALI_PHY_1090_DATA; + FWK_RW uint32_t DENALI_PHY_1091_DATA; + FWK_RW uint32_t DENALI_PHY_1092_DATA; + FWK_RW uint32_t DENALI_PHY_1093_DATA; + FWK_RW uint32_t DENALI_PHY_1094_DATA; + FWK_RW uint32_t DENALI_PHY_1095_DATA; + FWK_RW uint32_t DENALI_PHY_1096_DATA; + FWK_RW uint32_t DENALI_PHY_1097_DATA; + FWK_RW uint32_t DENALI_PHY_1098_DATA; + FWK_RW uint32_t DENALI_PHY_1099_DATA; + FWK_RW uint32_t DENALI_PHY_1100_DATA; + FWK_RW uint32_t DENALI_PHY_1101_DATA; + FWK_RW uint32_t DENALI_PHY_1102_DATA; + FWK_RW uint32_t DENALI_PHY_1103_DATA; + FWK_RW uint32_t DENALI_PHY_1104_DATA; + FWK_RW uint32_t DENALI_PHY_1105_DATA; + FWK_RW uint32_t DENALI_PHY_1106_DATA; + FWK_RW uint32_t DENALI_PHY_1107_DATA; + FWK_RW uint32_t DENALI_PHY_1108_DATA; + FWK_RW uint32_t DENALI_PHY_1109_DATA; + FWK_RW uint32_t DENALI_PHY_1110_DATA; + FWK_RW uint32_t DENALI_PHY_1111_DATA; + FWK_RW uint32_t DENALI_PHY_1112_DATA; + FWK_RW uint32_t DENALI_PHY_1113_DATA; + FWK_RW uint32_t DENALI_PHY_1114_DATA; + FWK_RW uint32_t DENALI_PHY_1115_DATA; + FWK_RW uint32_t DENALI_PHY_1116_DATA; + FWK_RW uint32_t DENALI_PHY_1117_DATA; + FWK_RW uint32_t DENALI_PHY_1118_DATA; + FWK_RW uint32_t DENALI_PHY_1119_DATA; + FWK_RW uint32_t DENALI_PHY_1120_DATA; + FWK_RW uint32_t DENALI_PHY_1121_DATA; + FWK_RW uint32_t DENALI_PHY_1122_DATA; + FWK_RW uint32_t DENALI_PHY_1123_DATA; + FWK_RW uint32_t DENALI_PHY_1124_DATA; + FWK_RW uint32_t DENALI_PHY_1125_DATA; + FWK_RW uint32_t DENALI_PHY_1126_DATA; + FWK_RW uint32_t DENALI_PHY_1127_DATA; + FWK_RW uint32_t DENALI_PHY_1128_DATA; + FWK_RW uint32_t DENALI_PHY_1129_DATA; + FWK_RW uint32_t DENALI_PHY_1130_DATA; + FWK_RW uint32_t DENALI_PHY_1131_DATA; + FWK_RW uint32_t DENALI_PHY_1132_DATA; + FWK_RW uint32_t DENALI_PHY_1133_DATA; + FWK_RW uint32_t DENALI_PHY_1134_DATA; + FWK_RW uint32_t DENALI_PHY_1135_DATA; + FWK_RW uint32_t DENALI_PHY_1136_DATA; + FWK_RW uint32_t DENALI_PHY_1137_DATA; + FWK_RW uint32_t DENALI_PHY_1138_DATA; + FWK_RW uint32_t DENALI_PHY_1139_DATA; + FWK_RW uint32_t DENALI_PHY_1140_DATA; + FWK_RW uint32_t DENALI_PHY_1141_DATA; + FWK_RW uint32_t DENALI_PHY_1142_DATA; + FWK_RW uint32_t DENALI_PHY_1143_DATA; + FWK_RW uint32_t DENALI_PHY_1144_DATA; + FWK_RW uint32_t DENALI_PHY_1145_DATA; + FWK_RW uint32_t DENALI_PHY_1146_DATA; + FWK_RW uint32_t DENALI_PHY_1147_DATA; + FWK_RW uint32_t DENALI_PHY_1148_DATA; + FWK_RW uint32_t DENALI_PHY_1149_DATA; + FWK_RW uint32_t DENALI_PHY_1150_DATA; + FWK_RW uint32_t DENALI_PHY_1151_DATA; + FWK_RW uint32_t DENALI_PHY_1152_DATA; + FWK_RW uint32_t DENALI_PHY_1153_DATA; + FWK_RW uint32_t DENALI_PHY_1154_DATA; + FWK_RW uint32_t DENALI_PHY_1155_DATA; + FWK_RW uint32_t DENALI_PHY_1156_DATA; + FWK_RW uint32_t DENALI_PHY_1157_DATA; + FWK_RW uint32_t DENALI_PHY_1158_DATA; + FWK_RW uint32_t DENALI_PHY_1159_DATA; + FWK_RW uint32_t DENALI_PHY_1160_DATA; + FWK_RW uint32_t DENALI_PHY_1161_DATA; + FWK_RW uint32_t DENALI_PHY_1162_DATA; + FWK_RW uint32_t DENALI_PHY_1163_DATA; + FWK_RW uint32_t DENALI_PHY_1164_DATA; + FWK_RW uint32_t DENALI_PHY_1165_DATA; + FWK_RW uint32_t DENALI_PHY_1166_DATA; + FWK_RW uint32_t DENALI_PHY_1167_DATA; + FWK_RW uint32_t DENALI_PHY_1168_DATA; + FWK_RW uint32_t DENALI_PHY_1169_DATA; + FWK_RW uint32_t DENALI_PHY_1170_DATA; + FWK_RW uint32_t DENALI_PHY_1171_DATA; + FWK_RW uint32_t DENALI_PHY_1172_DATA; + FWK_RW uint32_t DENALI_PHY_1173_DATA; + FWK_RW uint32_t DENALI_PHY_1174_DATA; + FWK_RW uint32_t DENALI_PHY_1175_DATA; + FWK_RW uint32_t DENALI_PHY_1176_DATA; + FWK_RW uint32_t DENALI_PHY_1177_DATA; + FWK_RW uint32_t DENALI_PHY_1178_DATA; + FWK_RW uint32_t DENALI_PHY_1179_DATA; + FWK_RW uint32_t DENALI_PHY_1180_DATA; + FWK_RW uint32_t DENALI_PHY_1181_DATA; + FWK_RW uint32_t DENALI_PHY_1182_DATA; + FWK_RW uint32_t DENALI_PHY_1183_DATA; + FWK_RW uint32_t DENALI_PHY_1184_DATA; + FWK_RW uint32_t DENALI_PHY_1185_DATA; + FWK_RW uint32_t DENALI_PHY_1186_DATA; + FWK_RW uint32_t DENALI_PHY_1187_DATA; + FWK_RW uint32_t DENALI_PHY_1188_DATA; + FWK_RW uint32_t DENALI_PHY_1189_DATA; + FWK_RW uint32_t DENALI_PHY_1190_DATA; + FWK_RW uint32_t DENALI_PHY_1191_DATA; + FWK_RW uint32_t DENALI_PHY_1192_DATA; + FWK_RW uint32_t DENALI_PHY_1193_DATA; + FWK_RW uint32_t DENALI_PHY_1194_DATA; + FWK_RW uint32_t DENALI_PHY_1195_DATA; + FWK_RW uint32_t DENALI_PHY_1196_DATA; + FWK_RW uint32_t DENALI_PHY_1197_DATA; + FWK_RW uint32_t DENALI_PHY_1198_DATA; + FWK_RW uint32_t DENALI_PHY_1199_DATA; + FWK_RW uint32_t DENALI_PHY_1200_DATA; + FWK_RW uint32_t DENALI_PHY_1201_DATA; + FWK_RW uint32_t DENALI_PHY_1202_DATA; + FWK_RW uint32_t DENALI_PHY_1203_DATA; + FWK_RW uint32_t DENALI_PHY_1204_DATA; + FWK_RW uint32_t DENALI_PHY_1205_DATA; + FWK_RW uint32_t DENALI_PHY_1206_DATA; + FWK_RW uint32_t DENALI_PHY_1207_DATA; + FWK_RW uint32_t DENALI_PHY_1208_DATA; + FWK_RW uint32_t DENALI_PHY_1209_DATA; + FWK_RW uint32_t DENALI_PHY_1210_DATA; + FWK_RW uint32_t DENALI_PHY_1211_DATA; + FWK_RW uint32_t DENALI_PHY_1212_DATA; + FWK_RW uint32_t DENALI_PHY_1213_DATA; + FWK_RW uint32_t DENALI_PHY_1214_DATA; + FWK_RW uint32_t DENALI_PHY_1215_DATA; + FWK_RW uint32_t DENALI_PHY_1216_DATA; + FWK_RW uint32_t DENALI_PHY_1217_DATA; + FWK_RW uint32_t DENALI_PHY_1218_DATA; + FWK_RW uint32_t DENALI_PHY_1219_DATA; + FWK_RW uint32_t DENALI_PHY_1220_DATA; + FWK_RW uint32_t DENALI_PHY_1221_DATA; + FWK_RW uint32_t DENALI_PHY_1222_DATA; + FWK_RW uint32_t DENALI_PHY_1223_DATA; + FWK_RW uint32_t DENALI_PHY_1224_DATA; + FWK_RW uint32_t DENALI_PHY_1225_DATA; + FWK_RW uint32_t DENALI_PHY_1226_DATA; + FWK_RW uint32_t DENALI_PHY_1227_DATA; + FWK_RW uint32_t DENALI_PHY_1228_DATA; + FWK_RW uint32_t DENALI_PHY_1229_DATA; + FWK_RW uint32_t DENALI_PHY_1230_DATA; + FWK_RW uint32_t DENALI_PHY_1231_DATA; + FWK_RW uint32_t DENALI_PHY_1232_DATA; + FWK_RW uint32_t DENALI_PHY_1233_DATA; + FWK_RW uint32_t DENALI_PHY_1234_DATA; + FWK_RW uint32_t DENALI_PHY_1235_DATA; + FWK_RW uint32_t DENALI_PHY_1236_DATA; + FWK_RW uint32_t DENALI_PHY_1237_DATA; + FWK_RW uint32_t DENALI_PHY_1238_DATA; + FWK_RW uint32_t DENALI_PHY_1239_DATA; + FWK_RW uint32_t DENALI_PHY_1240_DATA; + FWK_RW uint32_t DENALI_PHY_1241_DATA; + FWK_RW uint32_t DENALI_PHY_1242_DATA; + FWK_RW uint32_t DENALI_PHY_1243_DATA; + FWK_RW uint32_t DENALI_PHY_1244_DATA; + FWK_RW uint32_t DENALI_PHY_1245_DATA; + FWK_RW uint32_t DENALI_PHY_1246_DATA; + FWK_RW uint32_t DENALI_PHY_1247_DATA; + FWK_RW uint32_t DENALI_PHY_1248_DATA; + FWK_RW uint32_t DENALI_PHY_1249_DATA; + FWK_RW uint32_t DENALI_PHY_1250_DATA; + FWK_RW uint32_t DENALI_PHY_1251_DATA; + FWK_RW uint32_t DENALI_PHY_1252_DATA; + FWK_RW uint32_t DENALI_PHY_1253_DATA; + FWK_RW uint32_t DENALI_PHY_1254_DATA; + FWK_RW uint32_t DENALI_PHY_1255_DATA; + FWK_RW uint32_t DENALI_PHY_1256_DATA; + FWK_RW uint32_t DENALI_PHY_1257_DATA; + FWK_RW uint32_t DENALI_PHY_1258_DATA; + FWK_RW uint32_t DENALI_PHY_1259_DATA; + FWK_RW uint32_t DENALI_PHY_1260_DATA; + FWK_RW uint32_t DENALI_PHY_1261_DATA; + FWK_RW uint32_t DENALI_PHY_1262_DATA; + FWK_RW uint32_t DENALI_PHY_1263_DATA; + FWK_RW uint32_t DENALI_PHY_1264_DATA; + FWK_RW uint32_t DENALI_PHY_1265_DATA; + FWK_RW uint32_t DENALI_PHY_1266_DATA; + FWK_RW uint32_t DENALI_PHY_1267_DATA; + FWK_RW uint32_t DENALI_PHY_1268_DATA; + FWK_RW uint32_t DENALI_PHY_1269_DATA; + FWK_RW uint32_t DENALI_PHY_1270_DATA; + FWK_RW uint32_t DENALI_PHY_1271_DATA; + FWK_RW uint32_t DENALI_PHY_1272_DATA; + FWK_RW uint32_t DENALI_PHY_1273_DATA; + FWK_RW uint32_t DENALI_PHY_1274_DATA; + FWK_RW uint32_t DENALI_PHY_1275_DATA; + FWK_RW uint32_t DENALI_PHY_1276_DATA; + FWK_RW uint32_t DENALI_PHY_1277_DATA; + FWK_RW uint32_t DENALI_PHY_1278_DATA; + FWK_RW uint32_t DENALI_PHY_1279_DATA; + FWK_RW uint32_t DENALI_PHY_1280_DATA; + FWK_RW uint32_t DENALI_PHY_1281_DATA; + FWK_RW uint32_t DENALI_PHY_1282_DATA; + FWK_RW uint32_t DENALI_PHY_1283_DATA; + FWK_RW uint32_t DENALI_PHY_1284_DATA; + FWK_RW uint32_t DENALI_PHY_1285_DATA; + FWK_RW uint32_t DENALI_PHY_1286_DATA; + FWK_RW uint32_t DENALI_PHY_1287_DATA; + FWK_RW uint32_t DENALI_PHY_1288_DATA; + FWK_RW uint32_t DENALI_PHY_1289_DATA; + FWK_RW uint32_t DENALI_PHY_1290_DATA; + FWK_RW uint32_t DENALI_PHY_1291_DATA; + FWK_RW uint32_t DENALI_PHY_1292_DATA; + FWK_RW uint32_t DENALI_PHY_1293_DATA; + FWK_RW uint32_t DENALI_PHY_1294_DATA; + FWK_RW uint32_t DENALI_PHY_1295_DATA; + FWK_RW uint32_t DENALI_PHY_1296_DATA; + FWK_RW uint32_t DENALI_PHY_1297_DATA; + FWK_RW uint32_t DENALI_PHY_1298_DATA; + FWK_RW uint32_t DENALI_PHY_1299_DATA; + FWK_RW uint32_t DENALI_PHY_1300_DATA; + FWK_RW uint32_t DENALI_PHY_1301_DATA; + FWK_RW uint32_t DENALI_PHY_1302_DATA; + FWK_RW uint32_t DENALI_PHY_1303_DATA; + FWK_RW uint32_t DENALI_PHY_1304_DATA; + FWK_RW uint32_t DENALI_PHY_1305_DATA; + FWK_RW uint32_t DENALI_PHY_1306_DATA; + FWK_RW uint32_t DENALI_PHY_1307_DATA; + FWK_RW uint32_t DENALI_PHY_1308_DATA; + FWK_RW uint32_t DENALI_PHY_1309_DATA; + FWK_RW uint32_t DENALI_PHY_1310_DATA; + FWK_RW uint32_t DENALI_PHY_1311_DATA; + FWK_RW uint32_t DENALI_PHY_1312_DATA; + FWK_RW uint32_t DENALI_PHY_1313_DATA; + FWK_RW uint32_t DENALI_PHY_1314_DATA; + FWK_RW uint32_t DENALI_PHY_1315_DATA; + FWK_RW uint32_t DENALI_PHY_1316_DATA; + FWK_RW uint32_t DENALI_PHY_1317_DATA; + FWK_RW uint32_t DENALI_PHY_1318_DATA; + FWK_RW uint32_t DENALI_PHY_1319_DATA; + FWK_RW uint32_t DENALI_PHY_1320_DATA; + FWK_RW uint32_t DENALI_PHY_1321_DATA; + FWK_RW uint32_t DENALI_PHY_1322_DATA; + FWK_RW uint32_t DENALI_PHY_1323_DATA; + FWK_RW uint32_t DENALI_PHY_1324_DATA; + FWK_RW uint32_t DENALI_PHY_1325_DATA; + FWK_RW uint32_t DENALI_PHY_1326_DATA; + FWK_RW uint32_t DENALI_PHY_1327_DATA; + FWK_RW uint32_t DENALI_PHY_1328_DATA; + FWK_RW uint32_t DENALI_PHY_1329_DATA; + FWK_RW uint32_t DENALI_PHY_1330_DATA; + FWK_RW uint32_t DENALI_PHY_1331_DATA; + FWK_RW uint32_t DENALI_PHY_1332_DATA; + FWK_RW uint32_t DENALI_PHY_1333_DATA; + FWK_RW uint32_t DENALI_PHY_1334_DATA; + FWK_RW uint32_t DENALI_PHY_1335_DATA; + FWK_RW uint32_t DENALI_PHY_1336_DATA; + FWK_RW uint32_t DENALI_PHY_1337_DATA; + FWK_RW uint32_t DENALI_PHY_1338_DATA; + FWK_RW uint32_t DENALI_PHY_1339_DATA; + FWK_RW uint32_t DENALI_PHY_1340_DATA; + FWK_RW uint32_t DENALI_PHY_1341_DATA; + FWK_RW uint32_t DENALI_PHY_1342_DATA; + FWK_RW uint32_t DENALI_PHY_1343_DATA; + FWK_RW uint32_t DENALI_PHY_1344_DATA; + FWK_RW uint32_t DENALI_PHY_1345_DATA; + FWK_RW uint32_t DENALI_PHY_1346_DATA; + FWK_RW uint32_t DENALI_PHY_1347_DATA; + FWK_RW uint32_t DENALI_PHY_1348_DATA; + FWK_RW uint32_t DENALI_PHY_1349_DATA; + FWK_RW uint32_t DENALI_PHY_1350_DATA; + FWK_RW uint32_t DENALI_PHY_1351_DATA; + FWK_RW uint32_t DENALI_PHY_1352_DATA; + FWK_RW uint32_t DENALI_PHY_1353_DATA; + FWK_RW uint32_t DENALI_PHY_1354_DATA; + FWK_RW uint32_t DENALI_PHY_1355_DATA; + FWK_RW uint32_t DENALI_PHY_1356_DATA; + FWK_RW uint32_t DENALI_PHY_1357_DATA; + FWK_RW uint32_t DENALI_PHY_1358_DATA; + FWK_RW uint32_t DENALI_PHY_1359_DATA; + FWK_RW uint32_t DENALI_PHY_1360_DATA; + FWK_RW uint32_t DENALI_PHY_1361_DATA; + FWK_RW uint32_t DENALI_PHY_1362_DATA; + FWK_RW uint32_t DENALI_PHY_1363_DATA; + FWK_RW uint32_t DENALI_PHY_1364_DATA; + FWK_RW uint32_t DENALI_PHY_1365_DATA; + FWK_RW uint32_t DENALI_PHY_1366_DATA; + FWK_RW uint32_t DENALI_PHY_1367_DATA; + FWK_RW uint32_t DENALI_PHY_1368_DATA; + FWK_RW uint32_t DENALI_PHY_1369_DATA; + FWK_RW uint32_t DENALI_PHY_1370_DATA; + FWK_RW uint32_t DENALI_PHY_1371_DATA; + FWK_RW uint32_t DENALI_PHY_1372_DATA; + FWK_RW uint32_t DENALI_PHY_1373_DATA; + FWK_RW uint32_t DENALI_PHY_1374_DATA; + FWK_RW uint32_t DENALI_PHY_1375_DATA; + FWK_RW uint32_t DENALI_PHY_1376_DATA; + FWK_RW uint32_t DENALI_PHY_1377_DATA; + FWK_RW uint32_t DENALI_PHY_1378_DATA; + FWK_RW uint32_t DENALI_PHY_1379_DATA; + FWK_RW uint32_t DENALI_PHY_1380_DATA; + FWK_RW uint32_t DENALI_PHY_1381_DATA; + FWK_RW uint32_t DENALI_PHY_1382_DATA; + FWK_RW uint32_t DENALI_PHY_1383_DATA; + FWK_RW uint32_t DENALI_PHY_1384_DATA; + FWK_RW uint32_t DENALI_PHY_1385_DATA; + FWK_RW uint32_t DENALI_PHY_1386_DATA; + FWK_RW uint32_t DENALI_PHY_1387_DATA; + FWK_RW uint32_t DENALI_PHY_1388_DATA; + FWK_RW uint32_t DENALI_PHY_1389_DATA; + FWK_RW uint32_t DENALI_PHY_1390_DATA; + FWK_RW uint32_t DENALI_PHY_1391_DATA; + FWK_RW uint32_t DENALI_PHY_1392_DATA; + FWK_RW uint32_t DENALI_PHY_1393_DATA; + FWK_RW uint32_t DENALI_PHY_1394_DATA; + FWK_RW uint32_t DENALI_PHY_1395_DATA; + FWK_RW uint32_t DENALI_PHY_1396_DATA; + FWK_RW uint32_t DENALI_PHY_1397_DATA; + FWK_RW uint32_t DENALI_PHY_1398_DATA; + FWK_RW uint32_t DENALI_PHY_1399_DATA; + FWK_RW uint32_t DENALI_PHY_1400_DATA; + FWK_RW uint32_t DENALI_PHY_1401_DATA; + FWK_RW uint32_t DENALI_PHY_1402_DATA; + FWK_RW uint32_t DENALI_PHY_1403_DATA; + FWK_RW uint32_t DENALI_PHY_1404_DATA; + FWK_RW uint32_t DENALI_PHY_1405_DATA; + FWK_RW uint32_t DENALI_PHY_1406_DATA; + FWK_RW uint32_t DENALI_PHY_1407_DATA; + FWK_RW uint32_t DENALI_PHY_1408_DATA; + FWK_RW uint32_t DENALI_PHY_1409_DATA; + FWK_RW uint32_t DENALI_PHY_1410_DATA; + FWK_RW uint32_t DENALI_PHY_1411_DATA; + FWK_RW uint32_t DENALI_PHY_1412_DATA; + FWK_RW uint32_t DENALI_PHY_1413_DATA; + FWK_RW uint32_t DENALI_PHY_1414_DATA; + FWK_RW uint32_t DENALI_PHY_1415_DATA; + FWK_RW uint32_t DENALI_PHY_1416_DATA; + FWK_RW uint32_t DENALI_PHY_1417_DATA; + FWK_RW uint32_t DENALI_PHY_1418_DATA; + FWK_RW uint32_t DENALI_PHY_1419_DATA; + FWK_RW uint32_t DENALI_PHY_1420_DATA; + FWK_RW uint32_t DENALI_PHY_1421_DATA; + FWK_RW uint32_t DENALI_PHY_1422_DATA; + FWK_RW uint32_t DENALI_PHY_1423_DATA; + FWK_RW uint32_t DENALI_PHY_1424_DATA; + FWK_RW uint32_t DENALI_PHY_1425_DATA; + FWK_RW uint32_t DENALI_PHY_1426_DATA; + FWK_RW uint32_t DENALI_PHY_1427_DATA; + FWK_RW uint32_t DENALI_PHY_1428_DATA; + FWK_RW uint32_t DENALI_PHY_1429_DATA; + FWK_RW uint32_t DENALI_PHY_1430_DATA; + FWK_RW uint32_t DENALI_PHY_1431_DATA; + FWK_RW uint32_t DENALI_PHY_1432_DATA; + FWK_RW uint32_t DENALI_PHY_1433_DATA; + FWK_RW uint32_t DENALI_PHY_1434_DATA; + FWK_RW uint32_t DENALI_PHY_1435_DATA; + FWK_RW uint32_t DENALI_PHY_1436_DATA; + FWK_RW uint32_t DENALI_PHY_1437_DATA; + FWK_RW uint32_t DENALI_PHY_1438_DATA; + FWK_RW uint32_t DENALI_PHY_1439_DATA; + FWK_RW uint32_t DENALI_PHY_1440_DATA; + FWK_RW uint32_t DENALI_PHY_1441_DATA; + FWK_RW uint32_t DENALI_PHY_1442_DATA; + FWK_RW uint32_t DENALI_PHY_1443_DATA; + FWK_RW uint32_t DENALI_PHY_1444_DATA; + FWK_RW uint32_t DENALI_PHY_1445_DATA; + FWK_RW uint32_t DENALI_PHY_1446_DATA; + FWK_RW uint32_t DENALI_PHY_1447_DATA; + FWK_RW uint32_t DENALI_PHY_1448_DATA; + FWK_RW uint32_t DENALI_PHY_1449_DATA; + FWK_RW uint32_t DENALI_PHY_1450_DATA; + FWK_RW uint32_t DENALI_PHY_1451_DATA; + FWK_RW uint32_t DENALI_PHY_1452_DATA; + FWK_RW uint32_t DENALI_PHY_1453_DATA; + FWK_RW uint32_t DENALI_PHY_1454_DATA; + FWK_RW uint32_t DENALI_PHY_1455_DATA; + FWK_RW uint32_t DENALI_PHY_1456_DATA; + FWK_RW uint32_t DENALI_PHY_1457_DATA; + FWK_RW uint32_t DENALI_PHY_1458_DATA; + FWK_RW uint32_t DENALI_PHY_1459_DATA; + FWK_RW uint32_t DENALI_PHY_1460_DATA; + FWK_RW uint32_t DENALI_PHY_1461_DATA; + FWK_RW uint32_t DENALI_PHY_1462_DATA; + FWK_RW uint32_t DENALI_PHY_1463_DATA; + FWK_RW uint32_t DENALI_PHY_1464_DATA; + FWK_RW uint32_t DENALI_PHY_1465_DATA; + FWK_RW uint32_t DENALI_PHY_1466_DATA; + FWK_RW uint32_t DENALI_PHY_1467_DATA; + FWK_RW uint32_t DENALI_PHY_1468_DATA; + FWK_RW uint32_t DENALI_PHY_1469_DATA; + FWK_RW uint32_t DENALI_PHY_1470_DATA; + FWK_RW uint32_t DENALI_PHY_1471_DATA; + FWK_RW uint32_t DENALI_PHY_1472_DATA; + FWK_RW uint32_t DENALI_PHY_1473_DATA; + FWK_RW uint32_t DENALI_PHY_1474_DATA; + FWK_RW uint32_t DENALI_PHY_1475_DATA; + FWK_RW uint32_t DENALI_PHY_1476_DATA; + FWK_RW uint32_t DENALI_PHY_1477_DATA; + FWK_RW uint32_t DENALI_PHY_1478_DATA; + FWK_RW uint32_t DENALI_PHY_1479_DATA; + FWK_RW uint32_t DENALI_PHY_1480_DATA; + FWK_RW uint32_t DENALI_PHY_1481_DATA; + FWK_RW uint32_t DENALI_PHY_1482_DATA; + FWK_RW uint32_t DENALI_PHY_1483_DATA; + FWK_RW uint32_t DENALI_PHY_1484_DATA; + FWK_RW uint32_t DENALI_PHY_1485_DATA; + FWK_RW uint32_t DENALI_PHY_1486_DATA; + FWK_RW uint32_t DENALI_PHY_1487_DATA; + FWK_RW uint32_t DENALI_PHY_1488_DATA; + FWK_RW uint32_t DENALI_PHY_1489_DATA; + FWK_RW uint32_t DENALI_PHY_1490_DATA; + FWK_RW uint32_t DENALI_PHY_1491_DATA; + FWK_RW uint32_t DENALI_PHY_1492_DATA; + FWK_RW uint32_t DENALI_PHY_1493_DATA; + FWK_RW uint32_t DENALI_PHY_1494_DATA; + FWK_RW uint32_t DENALI_PHY_1495_DATA; + FWK_RW uint32_t DENALI_PHY_1496_DATA; + FWK_RW uint32_t DENALI_PHY_1497_DATA; + FWK_RW uint32_t DENALI_PHY_1498_DATA; + FWK_RW uint32_t DENALI_PHY_1499_DATA; + FWK_RW uint32_t DENALI_PHY_1500_DATA; + FWK_RW uint32_t DENALI_PHY_1501_DATA; + FWK_RW uint32_t DENALI_PHY_1502_DATA; + FWK_RW uint32_t DENALI_PHY_1503_DATA; + FWK_RW uint32_t DENALI_PHY_1504_DATA; + FWK_RW uint32_t DENALI_PHY_1505_DATA; + FWK_RW uint32_t DENALI_PHY_1506_DATA; + FWK_RW uint32_t DENALI_PHY_1507_DATA; + FWK_RW uint32_t DENALI_PHY_1508_DATA; + FWK_RW uint32_t DENALI_PHY_1509_DATA; + FWK_RW uint32_t DENALI_PHY_1510_DATA; + FWK_RW uint32_t DENALI_PHY_1511_DATA; + FWK_RW uint32_t DENALI_PHY_1512_DATA; + FWK_RW uint32_t DENALI_PHY_1513_DATA; + FWK_RW uint32_t DENALI_PHY_1514_DATA; + FWK_RW uint32_t DENALI_PHY_1515_DATA; + FWK_RW uint32_t DENALI_PHY_1516_DATA; + FWK_RW uint32_t DENALI_PHY_1517_DATA; + FWK_RW uint32_t DENALI_PHY_1518_DATA; + FWK_RW uint32_t DENALI_PHY_1519_DATA; + FWK_RW uint32_t DENALI_PHY_1520_DATA; + FWK_RW uint32_t DENALI_PHY_1521_DATA; + FWK_RW uint32_t DENALI_PHY_1522_DATA; + FWK_RW uint32_t DENALI_PHY_1523_DATA; + FWK_RW uint32_t DENALI_PHY_1524_DATA; + FWK_RW uint32_t DENALI_PHY_1525_DATA; + FWK_RW uint32_t DENALI_PHY_1526_DATA; + FWK_RW uint32_t DENALI_PHY_1527_DATA; + FWK_RW uint32_t DENALI_PHY_1528_DATA; + FWK_RW uint32_t DENALI_PHY_1529_DATA; + FWK_RW uint32_t DENALI_PHY_1530_DATA; + FWK_RW uint32_t DENALI_PHY_1531_DATA; + FWK_RW uint32_t DENALI_PHY_1532_DATA; + FWK_RW uint32_t DENALI_PHY_1533_DATA; + FWK_RW uint32_t DENALI_PHY_1534_DATA; + FWK_RW uint32_t DENALI_PHY_1535_DATA; + FWK_RW uint32_t DENALI_PHY_1536_DATA; + FWK_RW uint32_t DENALI_PHY_1537_DATA; + FWK_RW uint32_t DENALI_PHY_1538_DATA; + FWK_RW uint32_t DENALI_PHY_1539_DATA; + FWK_RW uint32_t DENALI_PHY_1540_DATA; + FWK_RW uint32_t DENALI_PHY_1541_DATA; + FWK_RW uint32_t DENALI_PHY_1542_DATA; + FWK_RW uint32_t DENALI_PHY_1543_DATA; + FWK_RW uint32_t DENALI_PHY_1544_DATA; + FWK_RW uint32_t DENALI_PHY_1545_DATA; + FWK_RW uint32_t DENALI_PHY_1546_DATA; + FWK_RW uint32_t DENALI_PHY_1547_DATA; + FWK_RW uint32_t DENALI_PHY_1548_DATA; + FWK_RW uint32_t DENALI_PHY_1549_DATA; + FWK_RW uint32_t DENALI_PHY_1550_DATA; + FWK_RW uint32_t DENALI_PHY_1551_DATA; + FWK_RW uint32_t DENALI_PHY_1552_DATA; + FWK_RW uint32_t DENALI_PHY_1553_DATA; + FWK_RW uint32_t DENALI_PHY_1554_DATA; + FWK_RW uint32_t DENALI_PHY_1555_DATA; + FWK_RW uint32_t DENALI_PHY_1556_DATA; + FWK_RW uint32_t DENALI_PHY_1557_DATA; + FWK_RW uint32_t DENALI_PHY_1558_DATA; + FWK_RW uint32_t DENALI_PHY_1559_DATA; + FWK_RW uint32_t DENALI_PHY_1560_DATA; + FWK_RW uint32_t DENALI_PHY_1561_DATA; + FWK_RW uint32_t DENALI_PHY_1562_DATA; + FWK_RW uint32_t DENALI_PHY_1563_DATA; + FWK_RW uint32_t DENALI_PHY_1564_DATA; + FWK_RW uint32_t DENALI_PHY_1565_DATA; + FWK_RW uint32_t DENALI_PHY_1566_DATA; + FWK_RW uint32_t DENALI_PHY_1567_DATA; + FWK_RW uint32_t DENALI_PHY_1568_DATA; + FWK_RW uint32_t DENALI_PHY_1569_DATA; + FWK_RW uint32_t DENALI_PHY_1570_DATA; + FWK_RW uint32_t DENALI_PHY_1571_DATA; + FWK_RW uint32_t DENALI_PHY_1572_DATA; + FWK_RW uint32_t DENALI_PHY_1573_DATA; + FWK_RW uint32_t DENALI_PHY_1574_DATA; + FWK_RW uint32_t DENALI_PHY_1575_DATA; + FWK_RW uint32_t DENALI_PHY_1576_DATA; + FWK_RW uint32_t DENALI_PHY_1577_DATA; + FWK_RW uint32_t DENALI_PHY_1578_DATA; + FWK_RW uint32_t DENALI_PHY_1579_DATA; + FWK_RW uint32_t DENALI_PHY_1580_DATA; + FWK_RW uint32_t DENALI_PHY_1581_DATA; + FWK_RW uint32_t DENALI_PHY_1582_DATA; + FWK_RW uint32_t DENALI_PHY_1583_DATA; + FWK_RW uint32_t DENALI_PHY_1584_DATA; + FWK_RW uint32_t DENALI_PHY_1585_DATA; + FWK_RW uint32_t DENALI_PHY_1586_DATA; + FWK_RW uint32_t DENALI_PHY_1587_DATA; + FWK_RW uint32_t DENALI_PHY_1588_DATA; + FWK_RW uint32_t DENALI_PHY_1589_DATA; + FWK_RW uint32_t DENALI_PHY_1590_DATA; + FWK_RW uint32_t DENALI_PHY_1591_DATA; + FWK_RW uint32_t DENALI_PHY_1592_DATA; + FWK_RW uint32_t DENALI_PHY_1593_DATA; + FWK_RW uint32_t DENALI_PHY_1594_DATA; + FWK_RW uint32_t DENALI_PHY_1595_DATA; + FWK_RW uint32_t DENALI_PHY_1596_DATA; + FWK_RW uint32_t DENALI_PHY_1597_DATA; + FWK_RW uint32_t DENALI_PHY_1598_DATA; + FWK_RW uint32_t DENALI_PHY_1599_DATA; + FWK_RW uint32_t DENALI_PHY_1600_DATA; + FWK_RW uint32_t DENALI_PHY_1601_DATA; + FWK_RW uint32_t DENALI_PHY_1602_DATA; + FWK_RW uint32_t DENALI_PHY_1603_DATA; + FWK_RW uint32_t DENALI_PHY_1604_DATA; + FWK_RW uint32_t DENALI_PHY_1605_DATA; + FWK_RW uint32_t DENALI_PHY_1606_DATA; + FWK_RW uint32_t DENALI_PHY_1607_DATA; + FWK_RW uint32_t DENALI_PHY_1608_DATA; + FWK_RW uint32_t DENALI_PHY_1609_DATA; + FWK_RW uint32_t DENALI_PHY_1610_DATA; + FWK_RW uint32_t DENALI_PHY_1611_DATA; + FWK_RW uint32_t DENALI_PHY_1612_DATA; + FWK_RW uint32_t DENALI_PHY_1613_DATA; + FWK_RW uint32_t DENALI_PHY_1614_DATA; + FWK_RW uint32_t DENALI_PHY_1615_DATA; + FWK_RW uint32_t DENALI_PHY_1616_DATA; + FWK_RW uint32_t DENALI_PHY_1617_DATA; + FWK_RW uint32_t DENALI_PHY_1618_DATA; + FWK_RW uint32_t DENALI_PHY_1619_DATA; + FWK_RW uint32_t DENALI_PHY_1620_DATA; + FWK_RW uint32_t DENALI_PHY_1621_DATA; + FWK_RW uint32_t DENALI_PHY_1622_DATA; + FWK_RW uint32_t DENALI_PHY_1623_DATA; + FWK_RW uint32_t DENALI_PHY_1624_DATA; + FWK_RW uint32_t DENALI_PHY_1625_DATA; + FWK_RW uint32_t DENALI_PHY_1626_DATA; + FWK_RW uint32_t DENALI_PHY_1627_DATA; + FWK_RW uint32_t DENALI_PHY_1628_DATA; + FWK_RW uint32_t DENALI_PHY_1629_DATA; + FWK_RW uint32_t DENALI_PHY_1630_DATA; + FWK_RW uint32_t DENALI_PHY_1631_DATA; + FWK_RW uint32_t DENALI_PHY_1632_DATA; + FWK_RW uint32_t DENALI_PHY_1633_DATA; + FWK_RW uint32_t DENALI_PHY_1634_DATA; + FWK_RW uint32_t DENALI_PHY_1635_DATA; + FWK_RW uint32_t DENALI_PHY_1636_DATA; + FWK_RW uint32_t DENALI_PHY_1637_DATA; + FWK_RW uint32_t DENALI_PHY_1638_DATA; + FWK_RW uint32_t DENALI_PHY_1639_DATA; + FWK_RW uint32_t DENALI_PHY_1640_DATA; + FWK_RW uint32_t DENALI_PHY_1641_DATA; + FWK_RW uint32_t DENALI_PHY_1642_DATA; + FWK_RW uint32_t DENALI_PHY_1643_DATA; + FWK_RW uint32_t DENALI_PHY_1644_DATA; + FWK_RW uint32_t DENALI_PHY_1645_DATA; + FWK_RW uint32_t DENALI_PHY_1646_DATA; + FWK_RW uint32_t DENALI_PHY_1647_DATA; + FWK_RW uint32_t DENALI_PHY_1648_DATA; + FWK_RW uint32_t DENALI_PHY_1649_DATA; + FWK_RW uint32_t DENALI_PHY_1650_DATA; + FWK_RW uint32_t DENALI_PHY_1651_DATA; + FWK_RW uint32_t DENALI_PHY_1652_DATA; + FWK_RW uint32_t DENALI_PHY_1653_DATA; + FWK_RW uint32_t DENALI_PHY_1654_DATA; + FWK_RW uint32_t DENALI_PHY_1655_DATA; + FWK_RW uint32_t DENALI_PHY_1656_DATA; + FWK_RW uint32_t DENALI_PHY_1657_DATA; + FWK_RW uint32_t DENALI_PHY_1658_DATA; + FWK_RW uint32_t DENALI_PHY_1659_DATA; + FWK_RW uint32_t DENALI_PHY_1660_DATA; + FWK_RW uint32_t DENALI_PHY_1661_DATA; + FWK_RW uint32_t DENALI_PHY_1662_DATA; + FWK_RW uint32_t DENALI_PHY_1663_DATA; + FWK_RW uint32_t DENALI_PHY_1664_DATA; + FWK_RW uint32_t DENALI_PHY_1665_DATA; + FWK_RW uint32_t DENALI_PHY_1666_DATA; + FWK_RW uint32_t DENALI_PHY_1667_DATA; + FWK_RW uint32_t DENALI_PHY_1668_DATA; + FWK_RW uint32_t DENALI_PHY_1669_DATA; + FWK_RW uint32_t DENALI_PHY_1670_DATA; + FWK_RW uint32_t DENALI_PHY_1671_DATA; + FWK_RW uint32_t DENALI_PHY_1672_DATA; + FWK_RW uint32_t DENALI_PHY_1673_DATA; + FWK_RW uint32_t DENALI_PHY_1674_DATA; + FWK_RW uint32_t DENALI_PHY_1675_DATA; + FWK_RW uint32_t DENALI_PHY_1676_DATA; + FWK_RW uint32_t DENALI_PHY_1677_DATA; + FWK_RW uint32_t DENALI_PHY_1678_DATA; + FWK_RW uint32_t DENALI_PHY_1679_DATA; + FWK_RW uint32_t DENALI_PHY_1680_DATA; + FWK_RW uint32_t DENALI_PHY_1681_DATA; + FWK_RW uint32_t DENALI_PHY_1682_DATA; + FWK_RW uint32_t DENALI_PHY_1683_DATA; + FWK_RW uint32_t DENALI_PHY_1684_DATA; + FWK_RW uint32_t DENALI_PHY_1685_DATA; + FWK_RW uint32_t DENALI_PHY_1686_DATA; + FWK_RW uint32_t DENALI_PHY_1687_DATA; + FWK_RW uint32_t DENALI_PHY_1688_DATA; + FWK_RW uint32_t DENALI_PHY_1689_DATA; + FWK_RW uint32_t DENALI_PHY_1690_DATA; + FWK_RW uint32_t DENALI_PHY_1691_DATA; + FWK_RW uint32_t DENALI_PHY_1692_DATA; + FWK_RW uint32_t DENALI_PHY_1693_DATA; + FWK_RW uint32_t DENALI_PHY_1694_DATA; + FWK_RW uint32_t DENALI_PHY_1695_DATA; + FWK_RW uint32_t DENALI_PHY_1696_DATA; + FWK_RW uint32_t DENALI_PHY_1697_DATA; + FWK_RW uint32_t DENALI_PHY_1698_DATA; + FWK_RW uint32_t DENALI_PHY_1699_DATA; + FWK_RW uint32_t DENALI_PHY_1700_DATA; + FWK_RW uint32_t DENALI_PHY_1701_DATA; + FWK_RW uint32_t DENALI_PHY_1702_DATA; + FWK_RW uint32_t DENALI_PHY_1703_DATA; + FWK_RW uint32_t DENALI_PHY_1704_DATA; + FWK_RW uint32_t DENALI_PHY_1705_DATA; + FWK_RW uint32_t DENALI_PHY_1706_DATA; + FWK_RW uint32_t DENALI_PHY_1707_DATA; + FWK_RW uint32_t DENALI_PHY_1708_DATA; + FWK_RW uint32_t DENALI_PHY_1709_DATA; + FWK_RW uint32_t DENALI_PHY_1710_DATA; + FWK_RW uint32_t DENALI_PHY_1711_DATA; + FWK_RW uint32_t DENALI_PHY_1712_DATA; + FWK_RW uint32_t DENALI_PHY_1713_DATA; + FWK_RW uint32_t DENALI_PHY_1714_DATA; + FWK_RW uint32_t DENALI_PHY_1715_DATA; + FWK_RW uint32_t DENALI_PHY_1716_DATA; + FWK_RW uint32_t DENALI_PHY_1717_DATA; + FWK_RW uint32_t DENALI_PHY_1718_DATA; + FWK_RW uint32_t DENALI_PHY_1719_DATA; + FWK_RW uint32_t DENALI_PHY_1720_DATA; + FWK_RW uint32_t DENALI_PHY_1721_DATA; + FWK_RW uint32_t DENALI_PHY_1722_DATA; + FWK_RW uint32_t DENALI_PHY_1723_DATA; + FWK_RW uint32_t DENALI_PHY_1724_DATA; + FWK_RW uint32_t DENALI_PHY_1725_DATA; + FWK_RW uint32_t DENALI_PHY_1726_DATA; + FWK_RW uint32_t DENALI_PHY_1727_DATA; + FWK_RW uint32_t DENALI_PHY_1728_DATA; + FWK_RW uint32_t DENALI_PHY_1729_DATA; + FWK_RW uint32_t DENALI_PHY_1730_DATA; + FWK_RW uint32_t DENALI_PHY_1731_DATA; + FWK_RW uint32_t DENALI_PHY_1732_DATA; + FWK_RW uint32_t DENALI_PHY_1733_DATA; + FWK_RW uint32_t DENALI_PHY_1734_DATA; + FWK_RW uint32_t DENALI_PHY_1735_DATA; + FWK_RW uint32_t DENALI_PHY_1736_DATA; + FWK_RW uint32_t DENALI_PHY_1737_DATA; + FWK_RW uint32_t DENALI_PHY_1738_DATA; + FWK_RW uint32_t DENALI_PHY_1739_DATA; + FWK_RW uint32_t DENALI_PHY_1740_DATA; + FWK_RW uint32_t DENALI_PHY_1741_DATA; + FWK_RW uint32_t DENALI_PHY_1742_DATA; + FWK_RW uint32_t DENALI_PHY_1743_DATA; + FWK_RW uint32_t DENALI_PHY_1744_DATA; + FWK_RW uint32_t DENALI_PHY_1745_DATA; + FWK_RW uint32_t DENALI_PHY_1746_DATA; + FWK_RW uint32_t DENALI_PHY_1747_DATA; + FWK_RW uint32_t DENALI_PHY_1748_DATA; + FWK_RW uint32_t DENALI_PHY_1749_DATA; + FWK_RW uint32_t DENALI_PHY_1750_DATA; + FWK_RW uint32_t DENALI_PHY_1751_DATA; + FWK_RW uint32_t DENALI_PHY_1752_DATA; + FWK_RW uint32_t DENALI_PHY_1753_DATA; + FWK_RW uint32_t DENALI_PHY_1754_DATA; + FWK_RW uint32_t DENALI_PHY_1755_DATA; + FWK_RW uint32_t DENALI_PHY_1756_DATA; + FWK_RW uint32_t DENALI_PHY_1757_DATA; + FWK_RW uint32_t DENALI_PHY_1758_DATA; + FWK_RW uint32_t DENALI_PHY_1759_DATA; + FWK_RW uint32_t DENALI_PHY_1760_DATA; + FWK_RW uint32_t DENALI_PHY_1761_DATA; + FWK_RW uint32_t DENALI_PHY_1762_DATA; + FWK_RW uint32_t DENALI_PHY_1763_DATA; + FWK_RW uint32_t DENALI_PHY_1764_DATA; + FWK_RW uint32_t DENALI_PHY_1765_DATA; + FWK_RW uint32_t DENALI_PHY_1766_DATA; + FWK_RW uint32_t DENALI_PHY_1767_DATA; + FWK_RW uint32_t DENALI_PHY_1768_DATA; + FWK_RW uint32_t DENALI_PHY_1769_DATA; + FWK_RW uint32_t DENALI_PHY_1770_DATA; + FWK_RW uint32_t DENALI_PHY_1771_DATA; + FWK_RW uint32_t DENALI_PHY_1772_DATA; + FWK_RW uint32_t DENALI_PHY_1773_DATA; + FWK_RW uint32_t DENALI_PHY_1774_DATA; + FWK_RW uint32_t DENALI_PHY_1775_DATA; + FWK_RW uint32_t DENALI_PHY_1776_DATA; + FWK_RW uint32_t DENALI_PHY_1777_DATA; + FWK_RW uint32_t DENALI_PHY_1778_DATA; + FWK_RW uint32_t DENALI_PHY_1779_DATA; + FWK_RW uint32_t DENALI_PHY_1780_DATA; + FWK_RW uint32_t DENALI_PHY_1781_DATA; + FWK_RW uint32_t DENALI_PHY_1782_DATA; + FWK_RW uint32_t DENALI_PHY_1783_DATA; + FWK_RW uint32_t DENALI_PHY_1784_DATA; + FWK_RW uint32_t DENALI_PHY_1785_DATA; + FWK_RW uint32_t DENALI_PHY_1786_DATA; + FWK_RW uint32_t DENALI_PHY_1787_DATA; + FWK_RW uint32_t DENALI_PHY_1788_DATA; + FWK_RW uint32_t DENALI_PHY_1789_DATA; + FWK_RW uint32_t DENALI_PHY_1790_DATA; + FWK_RW uint32_t DENALI_PHY_1791_DATA; + FWK_RW uint32_t DENALI_PHY_1792_DATA; + FWK_RW uint32_t DENALI_PHY_1793_DATA; + FWK_RW uint32_t DENALI_PHY_1794_DATA; + FWK_RW uint32_t DENALI_PHY_1795_DATA; + FWK_RW uint32_t DENALI_PHY_1796_DATA; + FWK_RW uint32_t DENALI_PHY_1797_DATA; + FWK_RW uint32_t DENALI_PHY_1798_DATA; + FWK_RW uint32_t DENALI_PHY_1799_DATA; + FWK_RW uint32_t DENALI_PHY_1800_DATA; + FWK_RW uint32_t DENALI_PHY_1801_DATA; + FWK_RW uint32_t DENALI_PHY_1802_DATA; + FWK_RW uint32_t DENALI_PHY_1803_DATA; + FWK_RW uint32_t DENALI_PHY_1804_DATA; + FWK_RW uint32_t DENALI_PHY_1805_DATA; + FWK_RW uint32_t DENALI_PHY_1806_DATA; + FWK_RW uint32_t DENALI_PHY_1807_DATA; + FWK_RW uint32_t DENALI_PHY_1808_DATA; + FWK_RW uint32_t DENALI_PHY_1809_DATA; + FWK_RW uint32_t DENALI_PHY_1810_DATA; + FWK_RW uint32_t DENALI_PHY_1811_DATA; + FWK_RW uint32_t DENALI_PHY_1812_DATA; + FWK_RW uint32_t DENALI_PHY_1813_DATA; + FWK_RW uint32_t DENALI_PHY_1814_DATA; + FWK_RW uint32_t DENALI_PHY_1815_DATA; + FWK_RW uint32_t DENALI_PHY_1816_DATA; + FWK_RW uint32_t DENALI_PHY_1817_DATA; + FWK_RW uint32_t DENALI_PHY_1818_DATA; + FWK_RW uint32_t DENALI_PHY_1819_DATA; + FWK_RW uint32_t DENALI_PHY_1820_DATA; + FWK_RW uint32_t DENALI_PHY_1821_DATA; + FWK_RW uint32_t DENALI_PHY_1822_DATA; + FWK_RW uint32_t DENALI_PHY_1823_DATA; + FWK_RW uint32_t DENALI_PHY_1824_DATA; + FWK_RW uint32_t DENALI_PHY_1825_DATA; + FWK_RW uint32_t DENALI_PHY_1826_DATA; + FWK_RW uint32_t DENALI_PHY_1827_DATA; + FWK_RW uint32_t DENALI_PHY_1828_DATA; + FWK_RW uint32_t DENALI_PHY_1829_DATA; + FWK_RW uint32_t DENALI_PHY_1830_DATA; + FWK_RW uint32_t DENALI_PHY_1831_DATA; + FWK_RW uint32_t DENALI_PHY_1832_DATA; + FWK_RW uint32_t DENALI_PHY_1833_DATA; + FWK_RW uint32_t DENALI_PHY_1834_DATA; + FWK_RW uint32_t DENALI_PHY_1835_DATA; + FWK_RW uint32_t DENALI_PHY_1836_DATA; + FWK_RW uint32_t DENALI_PHY_1837_DATA; + FWK_RW uint32_t DENALI_PHY_1838_DATA; + FWK_RW uint32_t DENALI_PHY_1839_DATA; + FWK_RW uint32_t DENALI_PHY_1840_DATA; + FWK_RW uint32_t DENALI_PHY_1841_DATA; + FWK_RW uint32_t DENALI_PHY_1842_DATA; + FWK_RW uint32_t DENALI_PHY_1843_DATA; + FWK_RW uint32_t DENALI_PHY_1844_DATA; + FWK_RW uint32_t DENALI_PHY_1845_DATA; + FWK_RW uint32_t DENALI_PHY_1846_DATA; + FWK_RW uint32_t DENALI_PHY_1847_DATA; + FWK_RW uint32_t DENALI_PHY_1848_DATA; + FWK_RW uint32_t DENALI_PHY_1849_DATA; + FWK_RW uint32_t DENALI_PHY_1850_DATA; + FWK_RW uint32_t DENALI_PHY_1851_DATA; + FWK_RW uint32_t DENALI_PHY_1852_DATA; + FWK_RW uint32_t DENALI_PHY_1853_DATA; + FWK_RW uint32_t DENALI_PHY_1854_DATA; + FWK_RW uint32_t DENALI_PHY_1855_DATA; + FWK_RW uint32_t DENALI_PHY_1856_DATA; + FWK_RW uint32_t DENALI_PHY_1857_DATA; + FWK_RW uint32_t DENALI_PHY_1858_DATA; + FWK_RW uint32_t DENALI_PHY_1859_DATA; + FWK_RW uint32_t DENALI_PHY_1860_DATA; + FWK_RW uint32_t DENALI_PHY_1861_DATA; + FWK_RW uint32_t DENALI_PHY_1862_DATA; + FWK_RW uint32_t DENALI_PHY_1863_DATA; + FWK_RW uint32_t DENALI_PHY_1864_DATA; + FWK_RW uint32_t DENALI_PHY_1865_DATA; + FWK_RW uint32_t DENALI_PHY_1866_DATA; + FWK_RW uint32_t DENALI_PHY_1867_DATA; + FWK_RW uint32_t DENALI_PHY_1868_DATA; + FWK_RW uint32_t DENALI_PHY_1869_DATA; + FWK_RW uint32_t DENALI_PHY_1870_DATA; + FWK_RW uint32_t DENALI_PHY_1871_DATA; + FWK_RW uint32_t DENALI_PHY_1872_DATA; + FWK_RW uint32_t DENALI_PHY_1873_DATA; + FWK_RW uint32_t DENALI_PHY_1874_DATA; + FWK_RW uint32_t DENALI_PHY_1875_DATA; + FWK_RW uint32_t DENALI_PHY_1876_DATA; + FWK_RW uint32_t DENALI_PHY_1877_DATA; + FWK_RW uint32_t DENALI_PHY_1878_DATA; + FWK_RW uint32_t DENALI_PHY_1879_DATA; + FWK_RW uint32_t DENALI_PHY_1880_DATA; + FWK_RW uint32_t DENALI_PHY_1881_DATA; + FWK_RW uint32_t DENALI_PHY_1882_DATA; + FWK_RW uint32_t DENALI_PHY_1883_DATA; + FWK_RW uint32_t DENALI_PHY_1884_DATA; + FWK_RW uint32_t DENALI_PHY_1885_DATA; + FWK_RW uint32_t DENALI_PHY_1886_DATA; + FWK_RW uint32_t DENALI_PHY_1887_DATA; + FWK_RW uint32_t DENALI_PHY_1888_DATA; + FWK_RW uint32_t DENALI_PHY_1889_DATA; + FWK_RW uint32_t DENALI_PHY_1890_DATA; + FWK_RW uint32_t DENALI_PHY_1891_DATA; + FWK_RW uint32_t DENALI_PHY_1892_DATA; + FWK_RW uint32_t DENALI_PHY_1893_DATA; + FWK_RW uint32_t DENALI_PHY_1894_DATA; + FWK_RW uint32_t DENALI_PHY_1895_DATA; + FWK_RW uint32_t DENALI_PHY_1896_DATA; + FWK_RW uint32_t DENALI_PHY_1897_DATA; + FWK_RW uint32_t DENALI_PHY_1898_DATA; + FWK_RW uint32_t DENALI_PHY_1899_DATA; + FWK_RW uint32_t DENALI_PHY_1900_DATA; + FWK_RW uint32_t DENALI_PHY_1901_DATA; + FWK_RW uint32_t DENALI_PHY_1902_DATA; + FWK_RW uint32_t DENALI_PHY_1903_DATA; + FWK_RW uint32_t DENALI_PHY_1904_DATA; + FWK_RW uint32_t DENALI_PHY_1905_DATA; + FWK_RW uint32_t DENALI_PHY_1906_DATA; + FWK_RW uint32_t DENALI_PHY_1907_DATA; + FWK_RW uint32_t DENALI_PHY_1908_DATA; + FWK_RW uint32_t DENALI_PHY_1909_DATA; + FWK_RW uint32_t DENALI_PHY_1910_DATA; + FWK_RW uint32_t DENALI_PHY_1911_DATA; + FWK_RW uint32_t DENALI_PHY_1912_DATA; + FWK_RW uint32_t DENALI_PHY_1913_DATA; + FWK_RW uint32_t DENALI_PHY_1914_DATA; + FWK_RW uint32_t DENALI_PHY_1915_DATA; + FWK_RW uint32_t DENALI_PHY_1916_DATA; + FWK_RW uint32_t DENALI_PHY_1917_DATA; + FWK_RW uint32_t DENALI_PHY_1918_DATA; + FWK_RW uint32_t DENALI_PHY_1919_DATA; + FWK_RW uint32_t DENALI_PHY_1920_DATA; + FWK_RW uint32_t DENALI_PHY_1921_DATA; + FWK_RW uint32_t DENALI_PHY_1922_DATA; + FWK_RW uint32_t DENALI_PHY_1923_DATA; + FWK_RW uint32_t DENALI_PHY_1924_DATA; + FWK_RW uint32_t DENALI_PHY_1925_DATA; + FWK_RW uint32_t DENALI_PHY_1926_DATA; + FWK_RW uint32_t DENALI_PHY_1927_DATA; + FWK_RW uint32_t DENALI_PHY_1928_DATA; + FWK_RW uint32_t DENALI_PHY_1929_DATA; + FWK_RW uint32_t DENALI_PHY_1930_DATA; + FWK_RW uint32_t DENALI_PHY_1931_DATA; + FWK_RW uint32_t DENALI_PHY_1932_DATA; + FWK_RW uint32_t DENALI_PHY_1933_DATA; + FWK_RW uint32_t DENALI_PHY_1934_DATA; + FWK_RW uint32_t DENALI_PHY_1935_DATA; + FWK_RW uint32_t DENALI_PHY_1936_DATA; + FWK_RW uint32_t DENALI_PHY_1937_DATA; + FWK_RW uint32_t DENALI_PHY_1938_DATA; + FWK_RW uint32_t DENALI_PHY_1939_DATA; + FWK_RW uint32_t DENALI_PHY_1940_DATA; + FWK_RW uint32_t DENALI_PHY_1941_DATA; + FWK_RW uint32_t DENALI_PHY_1942_DATA; + FWK_RW uint32_t DENALI_PHY_1943_DATA; + FWK_RW uint32_t DENALI_PHY_1944_DATA; + FWK_RW uint32_t DENALI_PHY_1945_DATA; + FWK_RW uint32_t DENALI_PHY_1946_DATA; + FWK_RW uint32_t DENALI_PHY_1947_DATA; + FWK_RW uint32_t DENALI_PHY_1948_DATA; + FWK_RW uint32_t DENALI_PHY_1949_DATA; + FWK_RW uint32_t DENALI_PHY_1950_DATA; + FWK_RW uint32_t DENALI_PHY_1951_DATA; + FWK_RW uint32_t DENALI_PHY_1952_DATA; + FWK_RW uint32_t DENALI_PHY_1953_DATA; + FWK_RW uint32_t DENALI_PHY_1954_DATA; + FWK_RW uint32_t DENALI_PHY_1955_DATA; + FWK_RW uint32_t DENALI_PHY_1956_DATA; + FWK_RW uint32_t DENALI_PHY_1957_DATA; + FWK_RW uint32_t DENALI_PHY_1958_DATA; + FWK_RW uint32_t DENALI_PHY_1959_DATA; + FWK_RW uint32_t DENALI_PHY_1960_DATA; + FWK_RW uint32_t DENALI_PHY_1961_DATA; + FWK_RW uint32_t DENALI_PHY_1962_DATA; + FWK_RW uint32_t DENALI_PHY_1963_DATA; + FWK_RW uint32_t DENALI_PHY_1964_DATA; + FWK_RW uint32_t DENALI_PHY_1965_DATA; + FWK_RW uint32_t DENALI_PHY_1966_DATA; + FWK_RW uint32_t DENALI_PHY_1967_DATA; + FWK_RW uint32_t DENALI_PHY_1968_DATA; + FWK_RW uint32_t DENALI_PHY_1969_DATA; + FWK_RW uint32_t DENALI_PHY_1970_DATA; + FWK_RW uint32_t DENALI_PHY_1971_DATA; + FWK_RW uint32_t DENALI_PHY_1972_DATA; + FWK_RW uint32_t DENALI_PHY_1973_DATA; + FWK_RW uint32_t DENALI_PHY_1974_DATA; + FWK_RW uint32_t DENALI_PHY_1975_DATA; + FWK_RW uint32_t DENALI_PHY_1976_DATA; + FWK_RW uint32_t DENALI_PHY_1977_DATA; + FWK_RW uint32_t DENALI_PHY_1978_DATA; + FWK_RW uint32_t DENALI_PHY_1979_DATA; + FWK_RW uint32_t DENALI_PHY_1980_DATA; + FWK_RW uint32_t DENALI_PHY_1981_DATA; + FWK_RW uint32_t DENALI_PHY_1982_DATA; + FWK_RW uint32_t DENALI_PHY_1983_DATA; + FWK_RW uint32_t DENALI_PHY_1984_DATA; + FWK_RW uint32_t DENALI_PHY_1985_DATA; + FWK_RW uint32_t DENALI_PHY_1986_DATA; + FWK_RW uint32_t DENALI_PHY_1987_DATA; + FWK_RW uint32_t DENALI_PHY_1988_DATA; + FWK_RW uint32_t DENALI_PHY_1989_DATA; + FWK_RW uint32_t DENALI_PHY_1990_DATA; + FWK_RW uint32_t DENALI_PHY_1991_DATA; + FWK_RW uint32_t DENALI_PHY_1992_DATA; + FWK_RW uint32_t DENALI_PHY_1993_DATA; + FWK_RW uint32_t DENALI_PHY_1994_DATA; + FWK_RW uint32_t DENALI_PHY_1995_DATA; + FWK_RW uint32_t DENALI_PHY_1996_DATA; + FWK_RW uint32_t DENALI_PHY_1997_DATA; + FWK_RW uint32_t DENALI_PHY_1998_DATA; + FWK_RW uint32_t DENALI_PHY_1999_DATA; + FWK_RW uint32_t DENALI_PHY_2000_DATA; + FWK_RW uint32_t DENALI_PHY_2001_DATA; + FWK_RW uint32_t DENALI_PHY_2002_DATA; + FWK_RW uint32_t DENALI_PHY_2003_DATA; + FWK_RW uint32_t DENALI_PHY_2004_DATA; + FWK_RW uint32_t DENALI_PHY_2005_DATA; + FWK_RW uint32_t DENALI_PHY_2006_DATA; + FWK_RW uint32_t DENALI_PHY_2007_DATA; + FWK_RW uint32_t DENALI_PHY_2008_DATA; + FWK_RW uint32_t DENALI_PHY_2009_DATA; + FWK_RW uint32_t DENALI_PHY_2010_DATA; + FWK_RW uint32_t DENALI_PHY_2011_DATA; + FWK_RW uint32_t DENALI_PHY_2012_DATA; + FWK_RW uint32_t DENALI_PHY_2013_DATA; + FWK_RW uint32_t DENALI_PHY_2014_DATA; + FWK_RW uint32_t DENALI_PHY_2015_DATA; + FWK_RW uint32_t DENALI_PHY_2016_DATA; + FWK_RW uint32_t DENALI_PHY_2017_DATA; + FWK_RW uint32_t DENALI_PHY_2018_DATA; + FWK_RW uint32_t DENALI_PHY_2019_DATA; + FWK_RW uint32_t DENALI_PHY_2020_DATA; + FWK_RW uint32_t DENALI_PHY_2021_DATA; + FWK_RW uint32_t DENALI_PHY_2022_DATA; + FWK_RW uint32_t DENALI_PHY_2023_DATA; + FWK_RW uint32_t DENALI_PHY_2024_DATA; + FWK_RW uint32_t DENALI_PHY_2025_DATA; + FWK_RW uint32_t DENALI_PHY_2026_DATA; + FWK_RW uint32_t DENALI_PHY_2027_DATA; + FWK_RW uint32_t DENALI_PHY_2028_DATA; + FWK_RW uint32_t DENALI_PHY_2029_DATA; + FWK_RW uint32_t DENALI_PHY_2030_DATA; + FWK_RW uint32_t DENALI_PHY_2031_DATA; + FWK_RW uint32_t DENALI_PHY_2032_DATA; + FWK_RW uint32_t DENALI_PHY_2033_DATA; + FWK_RW uint32_t DENALI_PHY_2034_DATA; + FWK_RW uint32_t DENALI_PHY_2035_DATA; + FWK_RW uint32_t DENALI_PHY_2036_DATA; + FWK_RW uint32_t DENALI_PHY_2037_DATA; + FWK_RW uint32_t DENALI_PHY_2038_DATA; + FWK_RW uint32_t DENALI_PHY_2039_DATA; + FWK_RW uint32_t DENALI_PHY_2040_DATA; + FWK_RW uint32_t DENALI_PHY_2041_DATA; + FWK_RW uint32_t DENALI_PHY_2042_DATA; + FWK_RW uint32_t DENALI_PHY_2043_DATA; + FWK_RW uint32_t DENALI_PHY_2044_DATA; + FWK_RW uint32_t DENALI_PHY_2045_DATA; + FWK_RW uint32_t DENALI_PHY_2046_DATA; + FWK_RW uint32_t DENALI_PHY_2047_DATA; + FWK_RW uint32_t DENALI_PHY_2048_DATA; + FWK_RW uint32_t DENALI_PHY_2049_DATA; + FWK_RW uint32_t DENALI_PHY_2050_DATA; + FWK_RW uint32_t DENALI_PHY_2051_DATA; + FWK_RW uint32_t DENALI_PHY_2052_DATA; + FWK_RW uint32_t DENALI_PHY_2053_DATA; + FWK_RW uint32_t DENALI_PHY_2054_DATA; + FWK_RW uint32_t DENALI_PHY_2055_DATA; + FWK_RW uint32_t DENALI_PHY_2056_DATA; + FWK_RW uint32_t DENALI_PHY_2057_DATA; + FWK_RW uint32_t DENALI_PHY_2058_DATA; + FWK_RW uint32_t DENALI_PHY_2059_DATA; + FWK_RW uint32_t DENALI_PHY_2060_DATA; + FWK_RW uint32_t DENALI_PHY_2061_DATA; + FWK_RW uint32_t DENALI_PHY_2062_DATA; + FWK_RW uint32_t DENALI_PHY_2063_DATA; + FWK_RW uint32_t DENALI_PHY_2064_DATA; + FWK_RW uint32_t DENALI_PHY_2065_DATA; + FWK_RW uint32_t DENALI_PHY_2066_DATA; + FWK_RW uint32_t DENALI_PHY_2067_DATA; + FWK_RW uint32_t DENALI_PHY_2068_DATA; + FWK_RW uint32_t DENALI_PHY_2069_DATA; + FWK_RW uint32_t DENALI_PHY_2070_DATA; + FWK_RW uint32_t DENALI_PHY_2071_DATA; + FWK_RW uint32_t DENALI_PHY_2072_DATA; + FWK_RW uint32_t DENALI_PHY_2073_DATA; + FWK_RW uint32_t DENALI_PHY_2074_DATA; + FWK_RW uint32_t DENALI_PHY_2075_DATA; + FWK_RW uint32_t DENALI_PHY_2076_DATA; + FWK_RW uint32_t DENALI_PHY_2077_DATA; + FWK_RW uint32_t DENALI_PHY_2078_DATA; + FWK_RW uint32_t DENALI_PHY_2079_DATA; + FWK_RW uint32_t DENALI_PHY_2080_DATA; + FWK_RW uint32_t DENALI_PHY_2081_DATA; + FWK_RW uint32_t DENALI_PHY_2082_DATA; + FWK_RW uint32_t DENALI_PHY_2083_DATA; + FWK_RW uint32_t DENALI_PHY_2084_DATA; + FWK_RW uint32_t DENALI_PHY_2085_DATA; + FWK_RW uint32_t DENALI_PHY_2086_DATA; + FWK_RW uint32_t DENALI_PHY_2087_DATA; + FWK_RW uint32_t DENALI_PHY_2088_DATA; + FWK_RW uint32_t DENALI_PHY_2089_DATA; + FWK_RW uint32_t DENALI_PHY_2090_DATA; + FWK_RW uint32_t DENALI_PHY_2091_DATA; + FWK_RW uint32_t DENALI_PHY_2092_DATA; + FWK_RW uint32_t DENALI_PHY_2093_DATA; + FWK_RW uint32_t DENALI_PHY_2094_DATA; + FWK_RW uint32_t DENALI_PHY_2095_DATA; + FWK_RW uint32_t DENALI_PHY_2096_DATA; + FWK_RW uint32_t DENALI_PHY_2097_DATA; + FWK_RW uint32_t DENALI_PHY_2098_DATA; + FWK_RW uint32_t DENALI_PHY_2099_DATA; + FWK_RW uint32_t DENALI_PHY_2100_DATA; + FWK_RW uint32_t DENALI_PHY_2101_DATA; + FWK_RW uint32_t DENALI_PHY_2102_DATA; + FWK_RW uint32_t DENALI_PHY_2103_DATA; + FWK_RW uint32_t DENALI_PHY_2104_DATA; + FWK_RW uint32_t DENALI_PHY_2105_DATA; + FWK_RW uint32_t DENALI_PHY_2106_DATA; + FWK_RW uint32_t DENALI_PHY_2107_DATA; + FWK_RW uint32_t DENALI_PHY_2108_DATA; + FWK_RW uint32_t DENALI_PHY_2109_DATA; + FWK_RW uint32_t DENALI_PHY_2110_DATA; + FWK_RW uint32_t DENALI_PHY_2111_DATA; + FWK_RW uint32_t DENALI_PHY_2112_DATA; + FWK_RW uint32_t DENALI_PHY_2113_DATA; + FWK_RW uint32_t DENALI_PHY_2114_DATA; + FWK_RW uint32_t DENALI_PHY_2115_DATA; + FWK_RW uint32_t DENALI_PHY_2116_DATA; + FWK_RW uint32_t DENALI_PHY_2117_DATA; + FWK_RW uint32_t DENALI_PHY_2118_DATA; + FWK_RW uint32_t DENALI_PHY_2119_DATA; + FWK_RW uint32_t DENALI_PHY_2120_DATA; + FWK_RW uint32_t DENALI_PHY_2121_DATA; + FWK_RW uint32_t DENALI_PHY_2122_DATA; + FWK_RW uint32_t DENALI_PHY_2123_DATA; + FWK_RW uint32_t DENALI_PHY_2124_DATA; + FWK_RW uint32_t DENALI_PHY_2125_DATA; + FWK_RW uint32_t DENALI_PHY_2126_DATA; + FWK_RW uint32_t DENALI_PHY_2127_DATA; + FWK_RW uint32_t DENALI_PHY_2128_DATA; + FWK_RW uint32_t DENALI_PHY_2129_DATA; + FWK_RW uint32_t DENALI_PHY_2130_DATA; + FWK_RW uint32_t DENALI_PHY_2131_DATA; + FWK_RW uint32_t DENALI_PHY_2132_DATA; + FWK_RW uint32_t DENALI_PHY_2133_DATA; + FWK_RW uint32_t DENALI_PHY_2134_DATA; + FWK_RW uint32_t DENALI_PHY_2135_DATA; + FWK_RW uint32_t DENALI_PHY_2136_DATA; + FWK_RW uint32_t DENALI_PHY_2137_DATA; + FWK_RW uint32_t DENALI_PHY_2138_DATA; + FWK_RW uint32_t DENALI_PHY_2139_DATA; + FWK_RW uint32_t DENALI_PHY_2140_DATA; + FWK_RW uint32_t DENALI_PHY_2141_DATA; + FWK_RW uint32_t DENALI_PHY_2142_DATA; + FWK_RW uint32_t DENALI_PHY_2143_DATA; + FWK_RW uint32_t DENALI_PHY_2144_DATA; + FWK_RW uint32_t DENALI_PHY_2145_DATA; + FWK_RW uint32_t DENALI_PHY_2146_DATA; + FWK_RW uint32_t DENALI_PHY_2147_DATA; + FWK_RW uint32_t DENALI_PHY_2148_DATA; + FWK_RW uint32_t DENALI_PHY_2149_DATA; + FWK_RW uint32_t DENALI_PHY_2150_DATA; + FWK_RW uint32_t DENALI_PHY_2151_DATA; + FWK_RW uint32_t DENALI_PHY_2152_DATA; + FWK_RW uint32_t DENALI_PHY_2153_DATA; + FWK_RW uint32_t DENALI_PHY_2154_DATA; + FWK_RW uint32_t DENALI_PHY_2155_DATA; + FWK_RW uint32_t DENALI_PHY_2156_DATA; + FWK_RW uint32_t DENALI_PHY_2157_DATA; + FWK_RW uint32_t DENALI_PHY_2158_DATA; + FWK_RW uint32_t DENALI_PHY_2159_DATA; + FWK_RW uint32_t DENALI_PHY_2160_DATA; + FWK_RW uint32_t DENALI_PHY_2161_DATA; + FWK_RW uint32_t DENALI_PHY_2162_DATA; + FWK_RW uint32_t DENALI_PHY_2163_DATA; + FWK_RW uint32_t DENALI_PHY_2164_DATA; + FWK_RW uint32_t DENALI_PHY_2165_DATA; + FWK_RW uint32_t DENALI_PHY_2166_DATA; + FWK_RW uint32_t DENALI_PHY_2167_DATA; + FWK_RW uint32_t DENALI_PHY_2168_DATA; + FWK_RW uint32_t DENALI_PHY_2169_DATA; + FWK_RW uint32_t DENALI_PHY_2170_DATA; + FWK_RW uint32_t DENALI_PHY_2171_DATA; + FWK_RW uint32_t DENALI_PHY_2172_DATA; + FWK_RW uint32_t DENALI_PHY_2173_DATA; + FWK_RW uint32_t DENALI_PHY_2174_DATA; + FWK_RW uint32_t DENALI_PHY_2175_DATA; + FWK_RW uint32_t DENALI_PHY_2176_DATA; + FWK_RW uint32_t DENALI_PHY_2177_DATA; + FWK_RW uint32_t DENALI_PHY_2178_DATA; + FWK_RW uint32_t DENALI_PHY_2179_DATA; + FWK_RW uint32_t DENALI_PHY_2180_DATA; + FWK_RW uint32_t DENALI_PHY_2181_DATA; + FWK_RW uint32_t DENALI_PHY_2182_DATA; + FWK_RW uint32_t DENALI_PHY_2183_DATA; + FWK_RW uint32_t DENALI_PHY_2184_DATA; + FWK_RW uint32_t DENALI_PHY_2185_DATA; + FWK_RW uint32_t DENALI_PHY_2186_DATA; + FWK_RW uint32_t DENALI_PHY_2187_DATA; + FWK_RW uint32_t DENALI_PHY_2188_DATA; + FWK_RW uint32_t DENALI_PHY_2189_DATA; + FWK_RW uint32_t DENALI_PHY_2190_DATA; + FWK_RW uint32_t DENALI_PHY_2191_DATA; + FWK_RW uint32_t DENALI_PHY_2192_DATA; + FWK_RW uint32_t DENALI_PHY_2193_DATA; + FWK_RW uint32_t DENALI_PHY_2194_DATA; + FWK_RW uint32_t DENALI_PHY_2195_DATA; + FWK_RW uint32_t DENALI_PHY_2196_DATA; + FWK_RW uint32_t DENALI_PHY_2197_DATA; + FWK_RW uint32_t DENALI_PHY_2198_DATA; + FWK_RW uint32_t DENALI_PHY_2199_DATA; + FWK_RW uint32_t DENALI_PHY_2200_DATA; + FWK_RW uint32_t DENALI_PHY_2201_DATA; + FWK_RW uint32_t DENALI_PHY_2202_DATA; + FWK_RW uint32_t DENALI_PHY_2203_DATA; + FWK_RW uint32_t DENALI_PHY_2204_DATA; + FWK_RW uint32_t DENALI_PHY_2205_DATA; + FWK_RW uint32_t DENALI_PHY_2206_DATA; + FWK_RW uint32_t DENALI_PHY_2207_DATA; + FWK_RW uint32_t DENALI_PHY_2208_DATA; + FWK_RW uint32_t DENALI_PHY_2209_DATA; + FWK_RW uint32_t DENALI_PHY_2210_DATA; + FWK_RW uint32_t DENALI_PHY_2211_DATA; + FWK_RW uint32_t DENALI_PHY_2212_DATA; + FWK_RW uint32_t DENALI_PHY_2213_DATA; + FWK_RW uint32_t DENALI_PHY_2214_DATA; + FWK_RW uint32_t DENALI_PHY_2215_DATA; + FWK_RW uint32_t DENALI_PHY_2216_DATA; + FWK_RW uint32_t DENALI_PHY_2217_DATA; + FWK_RW uint32_t DENALI_PHY_2218_DATA; + FWK_RW uint32_t DENALI_PHY_2219_DATA; + FWK_RW uint32_t DENALI_PHY_2220_DATA; + FWK_RW uint32_t DENALI_PHY_2221_DATA; + FWK_RW uint32_t DENALI_PHY_2222_DATA; + FWK_RW uint32_t DENALI_PHY_2223_DATA; + FWK_RW uint32_t DENALI_PHY_2224_DATA; + FWK_RW uint32_t DENALI_PHY_2225_DATA; + FWK_RW uint32_t DENALI_PHY_2226_DATA; + FWK_RW uint32_t DENALI_PHY_2227_DATA; + FWK_RW uint32_t DENALI_PHY_2228_DATA; + FWK_RW uint32_t DENALI_PHY_2229_DATA; + FWK_RW uint32_t DENALI_PHY_2230_DATA; + FWK_RW uint32_t DENALI_PHY_2231_DATA; + FWK_RW uint32_t DENALI_PHY_2232_DATA; + FWK_RW uint32_t DENALI_PHY_2233_DATA; + FWK_RW uint32_t DENALI_PHY_2234_DATA; + FWK_RW uint32_t DENALI_PHY_2235_DATA; + FWK_RW uint32_t DENALI_PHY_2236_DATA; + FWK_RW uint32_t DENALI_PHY_2237_DATA; + FWK_RW uint32_t DENALI_PHY_2238_DATA; + FWK_RW uint32_t DENALI_PHY_2239_DATA; + FWK_RW uint32_t DENALI_PHY_2240_DATA; + FWK_RW uint32_t DENALI_PHY_2241_DATA; + FWK_RW uint32_t DENALI_PHY_2242_DATA; + FWK_RW uint32_t DENALI_PHY_2243_DATA; + FWK_RW uint32_t DENALI_PHY_2244_DATA; + FWK_RW uint32_t DENALI_PHY_2245_DATA; + FWK_RW uint32_t DENALI_PHY_2246_DATA; + FWK_RW uint32_t DENALI_PHY_2247_DATA; + FWK_RW uint32_t DENALI_PHY_2248_DATA; + FWK_RW uint32_t DENALI_PHY_2249_DATA; + FWK_RW uint32_t DENALI_PHY_2250_DATA; + FWK_RW uint32_t DENALI_PHY_2251_DATA; + FWK_RW uint32_t DENALI_PHY_2252_DATA; + FWK_RW uint32_t DENALI_PHY_2253_DATA; + FWK_RW uint32_t DENALI_PHY_2254_DATA; + FWK_RW uint32_t DENALI_PHY_2255_DATA; + FWK_RW uint32_t DENALI_PHY_2256_DATA; + FWK_RW uint32_t DENALI_PHY_2257_DATA; + FWK_RW uint32_t DENALI_PHY_2258_DATA; + FWK_RW uint32_t DENALI_PHY_2259_DATA; + FWK_RW uint32_t DENALI_PHY_2260_DATA; + FWK_RW uint32_t DENALI_PHY_2261_DATA; + FWK_RW uint32_t DENALI_PHY_2262_DATA; + FWK_RW uint32_t DENALI_PHY_2263_DATA; + FWK_RW uint32_t DENALI_PHY_2264_DATA; + FWK_RW uint32_t DENALI_PHY_2265_DATA; + FWK_RW uint32_t DENALI_PHY_2266_DATA; + FWK_RW uint32_t DENALI_PHY_2267_DATA; + FWK_RW uint32_t DENALI_PHY_2268_DATA; + FWK_RW uint32_t DENALI_PHY_2269_DATA; + FWK_RW uint32_t DENALI_PHY_2270_DATA; + FWK_RW uint32_t DENALI_PHY_2271_DATA; + FWK_RW uint32_t DENALI_PHY_2272_DATA; + FWK_RW uint32_t DENALI_PHY_2273_DATA; + FWK_RW uint32_t DENALI_PHY_2274_DATA; + FWK_RW uint32_t DENALI_PHY_2275_DATA; + FWK_RW uint32_t DENALI_PHY_2276_DATA; + FWK_RW uint32_t DENALI_PHY_2277_DATA; + FWK_RW uint32_t DENALI_PHY_2278_DATA; + FWK_RW uint32_t DENALI_PHY_2279_DATA; + FWK_RW uint32_t DENALI_PHY_2280_DATA; + FWK_RW uint32_t DENALI_PHY_2281_DATA; + FWK_RW uint32_t DENALI_PHY_2282_DATA; + FWK_RW uint32_t DENALI_PHY_2283_DATA; + FWK_RW uint32_t DENALI_PHY_2284_DATA; + FWK_RW uint32_t DENALI_PHY_2285_DATA; + FWK_RW uint32_t DENALI_PHY_2286_DATA; + FWK_RW uint32_t DENALI_PHY_2287_DATA; + FWK_RW uint32_t DENALI_PHY_2288_DATA; + FWK_RW uint32_t DENALI_PHY_2289_DATA; + FWK_RW uint32_t DENALI_PHY_2290_DATA; + FWK_RW uint32_t DENALI_PHY_2291_DATA; + FWK_RW uint32_t DENALI_PHY_2292_DATA; + FWK_RW uint32_t DENALI_PHY_2293_DATA; + FWK_RW uint32_t DENALI_PHY_2294_DATA; + FWK_RW uint32_t DENALI_PHY_2295_DATA; + FWK_RW uint32_t DENALI_PHY_2296_DATA; + FWK_RW uint32_t DENALI_PHY_2297_DATA; + FWK_RW uint32_t DENALI_PHY_2298_DATA; + FWK_RW uint32_t DENALI_PHY_2299_DATA; + FWK_RW uint32_t DENALI_PHY_2300_DATA; + FWK_RW uint32_t DENALI_PHY_2301_DATA; + FWK_RW uint32_t DENALI_PHY_2302_DATA; + FWK_RW uint32_t DENALI_PHY_2303_DATA; + FWK_RW uint32_t DENALI_PHY_2304_DATA; + FWK_RW uint32_t DENALI_PHY_2305_DATA; + FWK_RW uint32_t DENALI_PHY_2306_DATA; + FWK_RW uint32_t DENALI_PHY_2307_DATA; + FWK_RW uint32_t DENALI_PHY_2308_DATA; + FWK_RW uint32_t DENALI_PHY_2309_DATA; + FWK_RW uint32_t DENALI_PHY_2310_DATA; + FWK_RW uint32_t DENALI_PHY_2311_DATA; + FWK_RW uint32_t DENALI_PHY_2312_DATA; + FWK_RW uint32_t DENALI_PHY_2313_DATA; + FWK_RW uint32_t DENALI_PHY_2314_DATA; + FWK_RW uint32_t DENALI_PHY_2315_DATA; + FWK_RW uint32_t DENALI_PHY_2316_DATA; + FWK_RW uint32_t DENALI_PHY_2317_DATA; + FWK_RW uint32_t DENALI_PHY_2318_DATA; + FWK_RW uint32_t DENALI_PHY_2319_DATA; + FWK_RW uint32_t DENALI_PHY_2320_DATA; + FWK_RW uint32_t DENALI_PHY_2321_DATA; + FWK_RW uint32_t DENALI_PHY_2322_DATA; + FWK_RW uint32_t DENALI_PHY_2323_DATA; + FWK_RW uint32_t DENALI_PHY_2324_DATA; + FWK_RW uint32_t DENALI_PHY_2325_DATA; + FWK_RW uint32_t DENALI_PHY_2326_DATA; + FWK_RW uint32_t DENALI_PHY_2327_DATA; + FWK_RW uint32_t DENALI_PHY_2328_DATA; + FWK_RW uint32_t DENALI_PHY_2329_DATA; + FWK_RW uint32_t DENALI_PHY_2330_DATA; + FWK_RW uint32_t DENALI_PHY_2331_DATA; + FWK_RW uint32_t DENALI_PHY_2332_DATA; + FWK_RW uint32_t DENALI_PHY_2333_DATA; + FWK_RW uint32_t DENALI_PHY_2334_DATA; + FWK_RW uint32_t DENALI_PHY_2335_DATA; + FWK_RW uint32_t DENALI_PHY_2336_DATA; + FWK_RW uint32_t DENALI_PHY_2337_DATA; + FWK_RW uint32_t DENALI_PHY_2338_DATA; + FWK_RW uint32_t DENALI_PHY_2339_DATA; + FWK_RW uint32_t DENALI_PHY_2340_DATA; + FWK_RW uint32_t DENALI_PHY_2341_DATA; + FWK_RW uint32_t DENALI_PHY_2342_DATA; + FWK_RW uint32_t DENALI_PHY_2343_DATA; + FWK_RW uint32_t DENALI_PHY_2344_DATA; + FWK_RW uint32_t DENALI_PHY_2345_DATA; + FWK_RW uint32_t DENALI_PHY_2346_DATA; + FWK_RW uint32_t DENALI_PHY_2347_DATA; + FWK_RW uint32_t DENALI_PHY_2348_DATA; + FWK_RW uint32_t DENALI_PHY_2349_DATA; + FWK_RW uint32_t DENALI_PHY_2350_DATA; + FWK_RW uint32_t DENALI_PHY_2351_DATA; + FWK_RW uint32_t DENALI_PHY_2352_DATA; + FWK_RW uint32_t DENALI_PHY_2353_DATA; + FWK_RW uint32_t DENALI_PHY_2354_DATA; + FWK_RW uint32_t DENALI_PHY_2355_DATA; + FWK_RW uint32_t DENALI_PHY_2356_DATA; + FWK_RW uint32_t DENALI_PHY_2357_DATA; + FWK_RW uint32_t DENALI_PHY_2358_DATA; + FWK_RW uint32_t DENALI_PHY_2359_DATA; + FWK_RW uint32_t DENALI_PHY_2360_DATA; + FWK_RW uint32_t DENALI_PHY_2361_DATA; + FWK_RW uint32_t DENALI_PHY_2362_DATA; + FWK_RW uint32_t DENALI_PHY_2363_DATA; + FWK_RW uint32_t DENALI_PHY_2364_DATA; + FWK_RW uint32_t DENALI_PHY_2365_DATA; + FWK_RW uint32_t DENALI_PHY_2366_DATA; + FWK_RW uint32_t DENALI_PHY_2367_DATA; + FWK_RW uint32_t DENALI_PHY_2368_DATA; + FWK_RW uint32_t DENALI_PHY_2369_DATA; + FWK_RW uint32_t DENALI_PHY_2370_DATA; + FWK_RW uint32_t DENALI_PHY_2371_DATA; + FWK_RW uint32_t DENALI_PHY_2372_DATA; + FWK_RW uint32_t DENALI_PHY_2373_DATA; + FWK_RW uint32_t DENALI_PHY_2374_DATA; + FWK_RW uint32_t DENALI_PHY_2375_DATA; + FWK_RW uint32_t DENALI_PHY_2376_DATA; + FWK_RW uint32_t DENALI_PHY_2377_DATA; + FWK_RW uint32_t DENALI_PHY_2378_DATA; + FWK_RW uint32_t DENALI_PHY_2379_DATA; + FWK_RW uint32_t DENALI_PHY_2380_DATA; + FWK_RW uint32_t DENALI_PHY_2381_DATA; + FWK_RW uint32_t DENALI_PHY_2382_DATA; + FWK_RW uint32_t DENALI_PHY_2383_DATA; + FWK_RW uint32_t DENALI_PHY_2384_DATA; + FWK_RW uint32_t DENALI_PHY_2385_DATA; + FWK_RW uint32_t DENALI_PHY_2386_DATA; + FWK_RW uint32_t DENALI_PHY_2387_DATA; + FWK_RW uint32_t DENALI_PHY_2388_DATA; + FWK_RW uint32_t DENALI_PHY_2389_DATA; + FWK_RW uint32_t DENALI_PHY_2390_DATA; + FWK_RW uint32_t DENALI_PHY_2391_DATA; + FWK_RW uint32_t DENALI_PHY_2392_DATA; + FWK_RW uint32_t DENALI_PHY_2393_DATA; + FWK_RW uint32_t DENALI_PHY_2394_DATA; + FWK_RW uint32_t DENALI_PHY_2395_DATA; + FWK_RW uint32_t DENALI_PHY_2396_DATA; + FWK_RW uint32_t DENALI_PHY_2397_DATA; + FWK_RW uint32_t DENALI_PHY_2398_DATA; + FWK_RW uint32_t DENALI_PHY_2399_DATA; + FWK_RW uint32_t DENALI_PHY_2400_DATA; + FWK_RW uint32_t DENALI_PHY_2401_DATA; + FWK_RW uint32_t DENALI_PHY_2402_DATA; + FWK_RW uint32_t DENALI_PHY_2403_DATA; + FWK_RW uint32_t DENALI_PHY_2404_DATA; + FWK_RW uint32_t DENALI_PHY_2405_DATA; + FWK_RW uint32_t DENALI_PHY_2406_DATA; + FWK_RW uint32_t DENALI_PHY_2407_DATA; + FWK_RW uint32_t DENALI_PHY_2408_DATA; + FWK_RW uint32_t DENALI_PHY_2409_DATA; + FWK_RW uint32_t DENALI_PHY_2410_DATA; + FWK_RW uint32_t DENALI_PHY_2411_DATA; + FWK_RW uint32_t DENALI_PHY_2412_DATA; + FWK_RW uint32_t DENALI_PHY_2413_DATA; + FWK_RW uint32_t DENALI_PHY_2414_DATA; + FWK_RW uint32_t DENALI_PHY_2415_DATA; + FWK_RW uint32_t DENALI_PHY_2416_DATA; + FWK_RW uint32_t DENALI_PHY_2417_DATA; + FWK_RW uint32_t DENALI_PHY_2418_DATA; + FWK_RW uint32_t DENALI_PHY_2419_DATA; + FWK_RW uint32_t DENALI_PHY_2420_DATA; + FWK_RW uint32_t DENALI_PHY_2421_DATA; + FWK_RW uint32_t DENALI_PHY_2422_DATA; + FWK_RW uint32_t DENALI_PHY_2423_DATA; + FWK_RW uint32_t DENALI_PHY_2424_DATA; + FWK_RW uint32_t DENALI_PHY_2425_DATA; +}; + +#endif /* MORELLO_DDR_PHY_REG_H */ diff --git a/product/morello/module/dmc_bing/include/mod_dmc_bing.h b/product/morello/module/dmc_bing/include/mod_dmc_bing.h index 155a4665c..0e4050835 100644 --- a/product/morello/module/dmc_bing/include/mod_dmc_bing.h +++ b/product/morello/module/dmc_bing/include/mod_dmc_bing.h @@ -308,13 +308,13 @@ struct mod_dmc_bing_reg { uint32_t RESERVED33; FWK_RW uint32_t ERR0CTLR0; FWK_RW uint32_t ERR0CTLR1; - FWK_R uint32_t ERR0STATUS; + FWK_RW uint32_t ERR0STATUS; uint8_t RESERVED34[0x740 - 0x714]; FWK_R uint32_t ERR1FR; uint32_t RESERVED35; FWK_R uint32_t ERR1CTLR; uint32_t RESERVED36; - FWK_R uint32_t ERR1STATUS; + FWK_RW uint32_t ERR1STATUS; uint32_t RESERVED37; FWK_RW uint32_t ERR1ADDR0; FWK_RW uint32_t ERR1ADDR1; @@ -329,7 +329,7 @@ struct mod_dmc_bing_reg { uint32_t RESERVED39; FWK_R uint32_t ERR2CTLR; uint32_t RESERVED40; - FWK_R uint32_t ERR2STATUS; + FWK_RW uint32_t ERR2STATUS; uint32_t RESERVED41; FWK_RW uint32_t ERR2ADDR0; FWK_RW uint32_t ERR2ADDR1; @@ -344,16 +344,18 @@ struct mod_dmc_bing_reg { uint32_t RESERVED43; FWK_R uint32_t ERR3CTLR; uint32_t RESERVED44; - FWK_R uint32_t ERR3STATUS; + FWK_RW uint32_t ERR3STATUS; uint32_t RESERVED45; FWK_RW uint32_t ERR3ADDR0; FWK_RW uint32_t ERR3ADDR1; - uint8_t RESERVED46[0x800 - 0x7E0]; + FWK_R uint32_t ERR3MISC0; + FWK_R uint32_t ERR3MISC1; + uint8_t RESERVED46[0x800 - 0x7E8]; FWK_R uint32_t ERR4FR; uint32_t RESERVED47; FWK_R uint32_t ERR4CTLR; uint32_t RESERVED48; - FWK_R uint32_t ERR4STATUS; + FWK_RW uint32_t ERR4STATUS; uint32_t RESERVED49; FWK_RW uint32_t ERR4ADDR0; FWK_RW uint32_t ERR4ADDR1; @@ -365,7 +367,7 @@ struct mod_dmc_bing_reg { uint32_t RESERVED51; FWK_R uint32_t ERR5CTLR; uint32_t RESERVED52; - FWK_R uint32_t ERR5STATUS; + FWK_RW uint32_t ERR5STATUS; uint32_t RESERVED53; FWK_RW uint32_t ERR5ADDR0; FWK_RW uint32_t ERR5ADDR1; @@ -377,7 +379,7 @@ struct mod_dmc_bing_reg { uint32_t RESERVED55; FWK_R uint32_t ERR6CTLR; uint32_t RESERVED56; - FWK_R uint32_t ERR6STATUS; + FWK_RW uint32_t ERR6STATUS; uint32_t RESERVED57; FWK_RW uint32_t ERR6ADDR0; FWK_RW uint32_t ERR6ADDR1; @@ -800,6 +802,15 @@ enum mod_dmc_ddr_training_type { /*! Training type count */ DDR_ADDR_TRAIN_TYPE_COUNT, }; + +/*! + * \brief Delay Function + * + * \param ms Number of milliseconds delay required. + * + * \retval NONE + */ +void delay_ms(uint32_t ms); /*! * \} */ diff --git a/product/morello/module/dmc_bing/src/Makefile b/product/morello/module/dmc_bing/src/Makefile index 0624052e7..7e974d70f 100644 --- a/product/morello/module/dmc_bing/src/Makefile +++ b/product/morello/module/dmc_bing/src/Makefile @@ -6,6 +6,16 @@ # BS_LIB_NAME := mod_dmc_bing +ifeq ($(PLAT_FVP), 1) BS_LIB_SOURCES += mod_dmc_bing.c +else +BS_LIB_SOURCES += \ + mod_dmc_bing.c \ + dimm_spd.c \ + morello_ddr_phy.c \ + ddr_phy_values_800.c \ + ddr_phy_values_1200.c \ + ddr_phy_values_1333.c +endif include $(BS_DIR)/lib.mk diff --git a/product/morello/module/dmc_bing/src/ddr_phy_values_1200.c b/product/morello/module/dmc_bing/src/ddr_phy_values_1200.c new file mode 100644 index 000000000..4fe2a65c6 --- /dev/null +++ b/product/morello/module/dmc_bing/src/ddr_phy_values_1200.c @@ -0,0 +1,1646 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Morello DDR-PHY register value configuration for 1200MHz speed. + */ + +#include + +#include + +#include + +#include + +#include +#include + +static uint8_t PHY_WRITE_PATH_LAT_ADD_2400[9] = { 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +static uint16_t PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[9] = { 0x100, 0x100, 0, + 0, 0, 0, + 0, 0x100, 0 }; +static uint8_t PHY_WRLVL_EARLY_FORCE_ZERO_2400[9] = { + 0, 0, 0, 0, 1, 0, 0, 0, 0 +}; +static uint32_t PHY_PAD_VREF_CTRL_DQ_2400; +static uint32_t VREF_TRAINING_CTRL_2400 = 0x00042520; +static uint16_t phy_dq_tsel_select_value = 0x9990; +static uint16_t phy_dqs_tsel_select_value = 0x9990; +static uint32_t phy_pad_data_drive_value = 0x2000073F; +static uint32_t phy_pad_clk_drive_value = 0x0006BF99; + +void ddr_phy_config_1200( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info, + int dmc_id) +{ + fwk_assert((ddr_phy != NULL) && (info != NULL)); + + if (info->number_of_ranks == 1) { + PHY_PAD_VREF_CTRL_DQ_2400 = 0x1234; + } else { + PHY_PAD_VREF_CTRL_DQ_2400 = 0x1260; + phy_dq_tsel_select_value = 0x8890; + phy_dqs_tsel_select_value = 0x8890; + } + + ddr_phy->DENALI_PHY_00_DATA = 0x76543210; + ddr_phy->DENALI_PHY_01_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_02_DATA = 0x00000000; + ddr_phy->DENALI_PHY_03_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_04_DATA = 0x00000000; + ddr_phy->DENALI_PHY_05_DATA = 0x00000000; + ddr_phy->DENALI_PHY_06_DATA = 0x00010000; + ddr_phy->DENALI_PHY_07_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_08_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_09_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_10_DATA = 0x00010000; + ddr_phy->DENALI_PHY_11_DATA = 0x00000000; + ddr_phy->DENALI_PHY_12_DATA = 0x00000000; + ddr_phy->DENALI_PHY_13_DATA = 0x01000100; + ddr_phy->DENALI_PHY_14_DATA = 0x00000000; + ddr_phy->DENALI_PHY_15_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_16_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_17_DATA = 0x00000008; + ddr_phy->DENALI_PHY_18_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_19_DATA = 0x00005555; + ddr_phy->DENALI_PHY_20_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_21_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_22_DATA = 0x00005656; + ddr_phy->DENALI_PHY_23_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_24_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_25_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_26_DATA = 0x00000000; + ddr_phy->DENALI_PHY_27_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_28_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_29_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_30_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_31_DATA = 0x00000000; + ddr_phy->DENALI_PHY_32_DATA = 0x04080000; + ddr_phy->DENALI_PHY_33_DATA = 0x08040400; + ddr_phy->DENALI_PHY_34_DATA = 0x00000004; + ddr_phy->DENALI_PHY_35_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_36_DATA = 0x00000000; + ddr_phy->DENALI_PHY_37_DATA = 0x00000000; + ddr_phy->DENALI_PHY_38_DATA = 0x00000000; + ddr_phy->DENALI_PHY_39_DATA = 0x00000000; + ddr_phy->DENALI_PHY_40_DATA = 0x00000000; + ddr_phy->DENALI_PHY_41_DATA = 0x00000000; + ddr_phy->DENALI_PHY_42_DATA = 0x00000000; + ddr_phy->DENALI_PHY_43_DATA = 0x00000000; + ddr_phy->DENALI_PHY_44_DATA = 0x00000000; + ddr_phy->DENALI_PHY_45_DATA = 0x00000000; + ddr_phy->DENALI_PHY_46_DATA = 0x00000000; + ddr_phy->DENALI_PHY_47_DATA = 0x00000000; + ddr_phy->DENALI_PHY_48_DATA = 0x00000000; + ddr_phy->DENALI_PHY_49_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_50_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_50_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_51_DATA = 0x00000000; + ddr_phy->DENALI_PHY_52_DATA = 0x00000000; + ddr_phy->DENALI_PHY_53_DATA = 0x00000000; + ddr_phy->DENALI_PHY_54_DATA = 0x00000000; + ddr_phy->DENALI_PHY_55_DATA = 0x20000004; + ddr_phy->DENALI_PHY_56_DATA = 0x00000000; + ddr_phy->DENALI_PHY_57_DATA = 0x00000000; + ddr_phy->DENALI_PHY_58_DATA = 0x00000000; + ddr_phy->DENALI_PHY_59_DATA = 0x00000000; + ddr_phy->DENALI_PHY_60_DATA = 0x00000000; + ddr_phy->DENALI_PHY_61_DATA = 0x00000000; + ddr_phy->DENALI_PHY_62_DATA = 0x00000000; + ddr_phy->DENALI_PHY_63_DATA = 0x00000000; + ddr_phy->DENALI_PHY_64_DATA = 0x00000000; + ddr_phy->DENALI_PHY_65_DATA = 0x00000000; + ddr_phy->DENALI_PHY_66_DATA = 0x00000000; + ddr_phy->DENALI_PHY_67_DATA = 0x00000000; + ddr_phy->DENALI_PHY_68_DATA = 0x00000000; + ddr_phy->DENALI_PHY_69_DATA = 0x00000000; + ddr_phy->DENALI_PHY_70_DATA = 0x00000000; + ddr_phy->DENALI_PHY_71_DATA = 0x00000000; + ddr_phy->DENALI_PHY_72_DATA = 0x00000000; + ddr_phy->DENALI_PHY_73_DATA = 0x00000000; + ddr_phy->DENALI_PHY_74_DATA = 0x00000000; + ddr_phy->DENALI_PHY_75_DATA = 0x00000000; + ddr_phy->DENALI_PHY_76_DATA = 0x00000000; + ddr_phy->DENALI_PHY_77_DATA = 0x00000000; + ddr_phy->DENALI_PHY_78_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_79_DATA = 0x00000000; + ddr_phy->DENALI_PHY_80_DATA = 0x00000000; + ddr_phy->DENALI_PHY_81_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_82_DATA = 0x02700270; + ddr_phy->DENALI_PHY_83_DATA = 0x02700270; + ddr_phy->DENALI_PHY_84_DATA = 0x02700270; + ddr_phy->DENALI_PHY_85_DATA = 0x02700270; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_82_DATA = 0x02800280; + ddr_phy->DENALI_PHY_83_DATA = 0x02800280; + ddr_phy->DENALI_PHY_84_DATA = 0x02800280; + ddr_phy->DENALI_PHY_85_DATA = 0x02800280; + } else { + ddr_phy->DENALI_PHY_82_DATA = 0x02800280; + ddr_phy->DENALI_PHY_83_DATA = 0x02800280; + ddr_phy->DENALI_PHY_84_DATA = 0x02800280; + ddr_phy->DENALI_PHY_85_DATA = 0x02800280; + } + ddr_phy->DENALI_PHY_86_DATA = 0x00000280; + ddr_phy->DENALI_PHY_87_DATA = 0x00000000; + ddr_phy->DENALI_PHY_88_DATA = 0x00000000; + ddr_phy->DENALI_PHY_89_DATA = 0x00000000; + ddr_phy->DENALI_PHY_90_DATA = 0x00000000; + ddr_phy->DENALI_PHY_91_DATA = 0x00000000; + ddr_phy->DENALI_PHY_92_DATA = 0x00800080; + ddr_phy->DENALI_PHY_93_DATA = 0x00800080; + ddr_phy->DENALI_PHY_94_DATA = 0x00800080; + ddr_phy->DENALI_PHY_95_DATA = 0x00800080; + ddr_phy->DENALI_PHY_96_DATA = 0x00800080; + ddr_phy->DENALI_PHY_97_DATA = 0x00800080; + ddr_phy->DENALI_PHY_98_DATA = 0x00800080; + ddr_phy->DENALI_PHY_99_DATA = 0x00800080; + ddr_phy->DENALI_PHY_100_DATA = 0x00800080; + ddr_phy->DENALI_PHY_101_DATA = 0x00800080; + ddr_phy->DENALI_PHY_102_DATA = 0x00800080; + ddr_phy->DENALI_PHY_103_DATA = 0x00800080; + ddr_phy->DENALI_PHY_104_DATA = 0x00800080; + ddr_phy->DENALI_PHY_105_DATA = 0x00800080; + ddr_phy->DENALI_PHY_106_DATA = 0x00800080; + ddr_phy->DENALI_PHY_107_DATA = 0x00800080; + ddr_phy->DENALI_PHY_108_DATA = 0x00800080; + ddr_phy->DENALI_PHY_109_DATA = 0x00800080; + ddr_phy->DENALI_PHY_110_DATA = 0x10040001; + ddr_phy->DENALI_PHY_111_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_112_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_113_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_114_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[0]); + ddr_phy->DENALI_PHY_115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_116_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_117_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_118_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[0]); + ddr_phy->DENALI_PHY_119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_120_DATA = 0x00800802; + ddr_phy->DENALI_PHY_121_DATA = 0x00081020; + ddr_phy->DENALI_PHY_122_DATA = 0x04010000; + ddr_phy->DENALI_PHY_123_DATA = 0x61314042; + ddr_phy->DENALI_PHY_124_DATA = 0x00314000; + ddr_phy->DENALI_PHY_125_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_126_DATA = 0x05010080; + ddr_phy->DENALI_PHY_127_DATA = 0x00000400; + ddr_phy->DENALI_PHY_128_DATA = 0x42100010; + ddr_phy->DENALI_PHY_129_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_130_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_131_DATA = 0x40420100; + ddr_phy->DENALI_PHY_132_DATA = 0x40518031; + ddr_phy->DENALI_PHY_133_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_134_DATA = 0x00000233; + ddr_phy->DENALI_PHY_135_DATA = 0x00000203; + ddr_phy->DENALI_PHY_136_DATA = 0x03000100; + ddr_phy->DENALI_PHY_137_DATA = 0x20202000; + ddr_phy->DENALI_PHY_138_DATA = 0x20202020; + ddr_phy->DENALI_PHY_139_DATA = 0x80202020; + ddr_phy->DENALI_PHY_140_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_141_DATA = 0x00000000; + ddr_phy->DENALI_PHY_142_DATA = 0x00000000; + ddr_phy->DENALI_PHY_256_DATA = 0x76543210; + ddr_phy->DENALI_PHY_257_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_258_DATA = 0x00000000; + ddr_phy->DENALI_PHY_259_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_260_DATA = 0x00000000; + ddr_phy->DENALI_PHY_261_DATA = 0x00000000; + ddr_phy->DENALI_PHY_262_DATA = 0x00010000; + ddr_phy->DENALI_PHY_263_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_264_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_265_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_266_DATA = 0x00010000; + ddr_phy->DENALI_PHY_267_DATA = 0x00000000; + ddr_phy->DENALI_PHY_268_DATA = 0x00000000; + ddr_phy->DENALI_PHY_269_DATA = 0x01000100; + ddr_phy->DENALI_PHY_270_DATA = 0x00000000; + ddr_phy->DENALI_PHY_271_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_272_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_273_DATA = 0x00000008; + ddr_phy->DENALI_PHY_274_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_275_DATA = 0x00005555; + ddr_phy->DENALI_PHY_276_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_277_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_278_DATA = 0x00005656; + ddr_phy->DENALI_PHY_279_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_280_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_281_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_283_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_284_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_285_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_286_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_287_DATA = 0x00000000; + ddr_phy->DENALI_PHY_288_DATA = 0x04080000; + ddr_phy->DENALI_PHY_289_DATA = 0x08040400; + ddr_phy->DENALI_PHY_290_DATA = 0x00000004; + ddr_phy->DENALI_PHY_291_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_293_DATA = 0x00000000; + ddr_phy->DENALI_PHY_294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_295_DATA = 0x00000000; + ddr_phy->DENALI_PHY_296_DATA = 0x00000000; + ddr_phy->DENALI_PHY_297_DATA = 0x00000000; + ddr_phy->DENALI_PHY_298_DATA = 0x00000000; + ddr_phy->DENALI_PHY_299_DATA = 0x00000000; + ddr_phy->DENALI_PHY_300_DATA = 0x00000000; + ddr_phy->DENALI_PHY_301_DATA = 0x00000000; + ddr_phy->DENALI_PHY_302_DATA = 0x00000000; + ddr_phy->DENALI_PHY_303_DATA = 0x00000000; + ddr_phy->DENALI_PHY_304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_305_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_306_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_306_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_309_DATA = 0x00000000; + ddr_phy->DENALI_PHY_310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_311_DATA = 0x20000004; + ddr_phy->DENALI_PHY_312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_313_DATA = 0x00000000; + ddr_phy->DENALI_PHY_314_DATA = 0x00000000; + ddr_phy->DENALI_PHY_315_DATA = 0x00000000; + ddr_phy->DENALI_PHY_316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_329_DATA = 0x00000000; + ddr_phy->DENALI_PHY_330_DATA = 0x00000000; + ddr_phy->DENALI_PHY_331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_334_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_335_DATA = 0x00000000; + ddr_phy->DENALI_PHY_336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_337_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_338_DATA = 0x02780278; + ddr_phy->DENALI_PHY_339_DATA = 0x02780278; + ddr_phy->DENALI_PHY_340_DATA = 0x02780278; + ddr_phy->DENALI_PHY_341_DATA = 0x02780278; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_338_DATA = 0x02800280; + ddr_phy->DENALI_PHY_339_DATA = 0x02800280; + ddr_phy->DENALI_PHY_340_DATA = 0x02800280; + ddr_phy->DENALI_PHY_341_DATA = 0x02800280; + } else { + ddr_phy->DENALI_PHY_338_DATA = 0x02800280; + ddr_phy->DENALI_PHY_339_DATA = 0x02800280; + ddr_phy->DENALI_PHY_340_DATA = 0x02800280; + ddr_phy->DENALI_PHY_341_DATA = 0x02800280; + } + ddr_phy->DENALI_PHY_342_DATA = 0x00000280; + ddr_phy->DENALI_PHY_343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_348_DATA = 0x00800080; + ddr_phy->DENALI_PHY_349_DATA = 0x00800080; + ddr_phy->DENALI_PHY_350_DATA = 0x00800080; + ddr_phy->DENALI_PHY_351_DATA = 0x00800080; + ddr_phy->DENALI_PHY_352_DATA = 0x00800080; + ddr_phy->DENALI_PHY_353_DATA = 0x00800080; + ddr_phy->DENALI_PHY_354_DATA = 0x00800080; + ddr_phy->DENALI_PHY_355_DATA = 0x00800080; + ddr_phy->DENALI_PHY_356_DATA = 0x00800080; + ddr_phy->DENALI_PHY_357_DATA = 0x00800080; + ddr_phy->DENALI_PHY_358_DATA = 0x00800080; + ddr_phy->DENALI_PHY_359_DATA = 0x00800080; + ddr_phy->DENALI_PHY_360_DATA = 0x00800080; + ddr_phy->DENALI_PHY_361_DATA = 0x00800080; + ddr_phy->DENALI_PHY_362_DATA = 0x00800080; + ddr_phy->DENALI_PHY_363_DATA = 0x00800080; + ddr_phy->DENALI_PHY_364_DATA = 0x00800080; + ddr_phy->DENALI_PHY_365_DATA = 0x00800080; + ddr_phy->DENALI_PHY_366_DATA = 0x10040001; + ddr_phy->DENALI_PHY_367_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_368_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_369_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_370_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[1]); + ddr_phy->DENALI_PHY_371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_372_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_373_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_374_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[1]); + ddr_phy->DENALI_PHY_375_DATA = 0x00000000; + ddr_phy->DENALI_PHY_376_DATA = 0x00800802; + ddr_phy->DENALI_PHY_377_DATA = 0x00081020; + ddr_phy->DENALI_PHY_378_DATA = 0x04010000; + ddr_phy->DENALI_PHY_379_DATA = 0x61314042; + ddr_phy->DENALI_PHY_380_DATA = 0x00314000; + ddr_phy->DENALI_PHY_381_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_382_DATA = 0x05010080; + ddr_phy->DENALI_PHY_383_DATA = 0x00000400; + ddr_phy->DENALI_PHY_384_DATA = 0x42100010; + ddr_phy->DENALI_PHY_385_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_386_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_387_DATA = 0x40420100; + ddr_phy->DENALI_PHY_388_DATA = 0x40518031; + ddr_phy->DENALI_PHY_389_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_390_DATA = 0x00000233; + ddr_phy->DENALI_PHY_391_DATA = 0x00000203; + ddr_phy->DENALI_PHY_392_DATA = 0x03000100; + ddr_phy->DENALI_PHY_393_DATA = 0x20202000; + ddr_phy->DENALI_PHY_394_DATA = 0x20202020; + ddr_phy->DENALI_PHY_395_DATA = 0x80202020; + ddr_phy->DENALI_PHY_396_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_397_DATA = 0x00000000; + ddr_phy->DENALI_PHY_398_DATA = 0x00000000; + ddr_phy->DENALI_PHY_512_DATA = 0x76543210; + ddr_phy->DENALI_PHY_513_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_514_DATA = 0x00000000; + ddr_phy->DENALI_PHY_515_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_516_DATA = 0x00000000; + ddr_phy->DENALI_PHY_517_DATA = 0x00000000; + ddr_phy->DENALI_PHY_518_DATA = 0x00010000; + ddr_phy->DENALI_PHY_519_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_520_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_521_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_522_DATA = 0x00010000; + ddr_phy->DENALI_PHY_523_DATA = 0x00000000; + ddr_phy->DENALI_PHY_524_DATA = 0x00000000; + ddr_phy->DENALI_PHY_525_DATA = 0x01000100; + ddr_phy->DENALI_PHY_526_DATA = 0x00000000; + ddr_phy->DENALI_PHY_527_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_528_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_529_DATA = 0x00000008; + ddr_phy->DENALI_PHY_530_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_531_DATA = 0x00005555; + ddr_phy->DENALI_PHY_532_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_533_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_534_DATA = 0x00005656; + ddr_phy->DENALI_PHY_535_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_536_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_537_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_539_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_540_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_541_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_542_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_543_DATA = 0x00000000; + ddr_phy->DENALI_PHY_544_DATA = 0x04080000; + ddr_phy->DENALI_PHY_545_DATA = 0x08040400; + ddr_phy->DENALI_PHY_546_DATA = 0x00000004; + ddr_phy->DENALI_PHY_547_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_549_DATA = 0x00000000; + ddr_phy->DENALI_PHY_550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_551_DATA = 0x00000000; + ddr_phy->DENALI_PHY_552_DATA = 0x00000000; + ddr_phy->DENALI_PHY_553_DATA = 0x00000000; + ddr_phy->DENALI_PHY_554_DATA = 0x00000000; + ddr_phy->DENALI_PHY_555_DATA = 0x00000000; + ddr_phy->DENALI_PHY_556_DATA = 0x00000000; + ddr_phy->DENALI_PHY_557_DATA = 0x00000000; + ddr_phy->DENALI_PHY_558_DATA = 0x00000000; + ddr_phy->DENALI_PHY_559_DATA = 0x00000000; + ddr_phy->DENALI_PHY_560_DATA = 0x00000000; + ddr_phy->DENALI_PHY_561_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_562_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_562_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_563_DATA = 0x00000000; + ddr_phy->DENALI_PHY_564_DATA = 0x00000000; + ddr_phy->DENALI_PHY_565_DATA = 0x00000000; + ddr_phy->DENALI_PHY_566_DATA = 0x00000000; + ddr_phy->DENALI_PHY_567_DATA = 0x20000004; + ddr_phy->DENALI_PHY_568_DATA = 0x00000000; + ddr_phy->DENALI_PHY_569_DATA = 0x00000000; + ddr_phy->DENALI_PHY_570_DATA = 0x00000000; + ddr_phy->DENALI_PHY_571_DATA = 0x00000000; + ddr_phy->DENALI_PHY_572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_585_DATA = 0x00000000; + ddr_phy->DENALI_PHY_586_DATA = 0x00000000; + ddr_phy->DENALI_PHY_587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_590_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_591_DATA = 0x00000000; + ddr_phy->DENALI_PHY_592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_593_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_594_DATA = 0x02800280; + ddr_phy->DENALI_PHY_595_DATA = 0x02800280; + ddr_phy->DENALI_PHY_596_DATA = 0x02800280; + ddr_phy->DENALI_PHY_597_DATA = 0x02800280; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_594_DATA = 0x02800280; + ddr_phy->DENALI_PHY_595_DATA = 0x02800280; + ddr_phy->DENALI_PHY_596_DATA = 0x02800280; + ddr_phy->DENALI_PHY_597_DATA = 0x02800280; + } else { + ddr_phy->DENALI_PHY_594_DATA = 0x02780278; + ddr_phy->DENALI_PHY_595_DATA = 0x02780278; + ddr_phy->DENALI_PHY_596_DATA = 0x02780278; + ddr_phy->DENALI_PHY_597_DATA = 0x02780278; + } + ddr_phy->DENALI_PHY_598_DATA = 0x00000280; + ddr_phy->DENALI_PHY_599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_604_DATA = 0x00800080; + ddr_phy->DENALI_PHY_605_DATA = 0x00800080; + ddr_phy->DENALI_PHY_606_DATA = 0x00800080; + ddr_phy->DENALI_PHY_607_DATA = 0x00800080; + ddr_phy->DENALI_PHY_608_DATA = 0x00800080; + ddr_phy->DENALI_PHY_609_DATA = 0x00800080; + ddr_phy->DENALI_PHY_610_DATA = 0x00800080; + ddr_phy->DENALI_PHY_611_DATA = 0x00800080; + ddr_phy->DENALI_PHY_612_DATA = 0x00800080; + ddr_phy->DENALI_PHY_613_DATA = 0x00800080; + ddr_phy->DENALI_PHY_614_DATA = 0x00800080; + ddr_phy->DENALI_PHY_615_DATA = 0x00800080; + ddr_phy->DENALI_PHY_616_DATA = 0x00800080; + ddr_phy->DENALI_PHY_617_DATA = 0x00800080; + ddr_phy->DENALI_PHY_618_DATA = 0x00800080; + ddr_phy->DENALI_PHY_619_DATA = 0x00800080; + ddr_phy->DENALI_PHY_620_DATA = 0x00800080; + ddr_phy->DENALI_PHY_621_DATA = 0x00800080; + ddr_phy->DENALI_PHY_622_DATA = 0x10040001; + ddr_phy->DENALI_PHY_623_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_624_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_625_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_626_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[2]); + ddr_phy->DENALI_PHY_627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_628_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_629_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_630_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[2]); + ddr_phy->DENALI_PHY_631_DATA = 0x00000000; + ddr_phy->DENALI_PHY_632_DATA = 0x00800802; + ddr_phy->DENALI_PHY_633_DATA = 0x00081020; + ddr_phy->DENALI_PHY_634_DATA = 0x04010000; + ddr_phy->DENALI_PHY_635_DATA = 0x61314042; + ddr_phy->DENALI_PHY_636_DATA = 0x00314000; + ddr_phy->DENALI_PHY_637_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_638_DATA = 0x05010080; + ddr_phy->DENALI_PHY_639_DATA = 0x00000400; + ddr_phy->DENALI_PHY_640_DATA = 0x42100010; + ddr_phy->DENALI_PHY_641_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_642_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_643_DATA = 0x40420100; + ddr_phy->DENALI_PHY_644_DATA = 0x40518031; + ddr_phy->DENALI_PHY_645_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_646_DATA = 0x00000233; + ddr_phy->DENALI_PHY_647_DATA = 0x00000203; + ddr_phy->DENALI_PHY_648_DATA = 0x03000100; + ddr_phy->DENALI_PHY_649_DATA = 0x20202000; + ddr_phy->DENALI_PHY_650_DATA = 0x20202020; + ddr_phy->DENALI_PHY_651_DATA = 0x80202020; + ddr_phy->DENALI_PHY_652_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_653_DATA = 0x00000000; + ddr_phy->DENALI_PHY_654_DATA = 0x00000000; + ddr_phy->DENALI_PHY_768_DATA = 0x76543210; + ddr_phy->DENALI_PHY_769_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_770_DATA = 0x00000000; + ddr_phy->DENALI_PHY_771_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_772_DATA = 0x00000000; + ddr_phy->DENALI_PHY_773_DATA = 0x00000000; + ddr_phy->DENALI_PHY_774_DATA = 0x00010000; + ddr_phy->DENALI_PHY_775_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_776_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_777_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_778_DATA = 0x00010000; + ddr_phy->DENALI_PHY_779_DATA = 0x00000000; + ddr_phy->DENALI_PHY_780_DATA = 0x00000000; + ddr_phy->DENALI_PHY_781_DATA = 0x01000100; + ddr_phy->DENALI_PHY_782_DATA = 0x00000000; + ddr_phy->DENALI_PHY_783_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_784_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_785_DATA = 0x00000008; + ddr_phy->DENALI_PHY_786_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_787_DATA = 0x00005555; + ddr_phy->DENALI_PHY_788_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_789_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_790_DATA = 0x00005656; + ddr_phy->DENALI_PHY_791_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_792_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_793_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_795_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_796_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_797_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_798_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_799_DATA = 0x00000000; + ddr_phy->DENALI_PHY_800_DATA = 0x04080000; + ddr_phy->DENALI_PHY_801_DATA = 0x08040400; + ddr_phy->DENALI_PHY_802_DATA = 0x00000004; + ddr_phy->DENALI_PHY_803_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_805_DATA = 0x00000000; + ddr_phy->DENALI_PHY_806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_807_DATA = 0x00000000; + ddr_phy->DENALI_PHY_808_DATA = 0x00000000; + ddr_phy->DENALI_PHY_809_DATA = 0x00000000; + ddr_phy->DENALI_PHY_810_DATA = 0x00000000; + ddr_phy->DENALI_PHY_811_DATA = 0x00000000; + ddr_phy->DENALI_PHY_812_DATA = 0x00000000; + ddr_phy->DENALI_PHY_813_DATA = 0x00000000; + ddr_phy->DENALI_PHY_814_DATA = 0x00000000; + ddr_phy->DENALI_PHY_815_DATA = 0x00000000; + ddr_phy->DENALI_PHY_816_DATA = 0x00000000; + ddr_phy->DENALI_PHY_817_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_818_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_818_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_819_DATA = 0x00000000; + ddr_phy->DENALI_PHY_820_DATA = 0x00000000; + ddr_phy->DENALI_PHY_821_DATA = 0x00000000; + ddr_phy->DENALI_PHY_822_DATA = 0x00000000; + ddr_phy->DENALI_PHY_823_DATA = 0x20000004; + ddr_phy->DENALI_PHY_824_DATA = 0x00000000; + ddr_phy->DENALI_PHY_825_DATA = 0x00000000; + ddr_phy->DENALI_PHY_826_DATA = 0x00000000; + ddr_phy->DENALI_PHY_827_DATA = 0x00000000; + ddr_phy->DENALI_PHY_828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_841_DATA = 0x00000000; + ddr_phy->DENALI_PHY_842_DATA = 0x00000000; + ddr_phy->DENALI_PHY_843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_846_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_847_DATA = 0x00000000; + ddr_phy->DENALI_PHY_848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_849_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_850_DATA = 0x02600260; + ddr_phy->DENALI_PHY_851_DATA = 0x02600260; + ddr_phy->DENALI_PHY_852_DATA = 0x02600260; + ddr_phy->DENALI_PHY_853_DATA = 0x02600260; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_850_DATA = 0x02700270; + ddr_phy->DENALI_PHY_851_DATA = 0x02700270; + ddr_phy->DENALI_PHY_852_DATA = 0x02700270; + ddr_phy->DENALI_PHY_853_DATA = 0x02700270; + } else { + ddr_phy->DENALI_PHY_850_DATA = 0x02800280; + ddr_phy->DENALI_PHY_851_DATA = 0x02800280; + ddr_phy->DENALI_PHY_852_DATA = 0x02800280; + ddr_phy->DENALI_PHY_853_DATA = 0x02800280; + } + ddr_phy->DENALI_PHY_854_DATA = 0x00000280; + ddr_phy->DENALI_PHY_855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_860_DATA = 0x00800080; + ddr_phy->DENALI_PHY_861_DATA = 0x00800080; + ddr_phy->DENALI_PHY_862_DATA = 0x00800080; + ddr_phy->DENALI_PHY_863_DATA = 0x00800080; + ddr_phy->DENALI_PHY_864_DATA = 0x00800080; + ddr_phy->DENALI_PHY_865_DATA = 0x00800080; + ddr_phy->DENALI_PHY_866_DATA = 0x00800080; + ddr_phy->DENALI_PHY_867_DATA = 0x00800080; + ddr_phy->DENALI_PHY_868_DATA = 0x00800080; + ddr_phy->DENALI_PHY_869_DATA = 0x00800080; + ddr_phy->DENALI_PHY_870_DATA = 0x00800080; + ddr_phy->DENALI_PHY_871_DATA = 0x00800080; + ddr_phy->DENALI_PHY_872_DATA = 0x00800080; + ddr_phy->DENALI_PHY_873_DATA = 0x00800080; + ddr_phy->DENALI_PHY_874_DATA = 0x00800080; + ddr_phy->DENALI_PHY_875_DATA = 0x00800080; + ddr_phy->DENALI_PHY_876_DATA = 0x00800080; + ddr_phy->DENALI_PHY_877_DATA = 0x00800080; + ddr_phy->DENALI_PHY_878_DATA = 0x10040001; + ddr_phy->DENALI_PHY_879_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_880_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_881_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_882_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[3]); + ddr_phy->DENALI_PHY_883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_884_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_885_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_886_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[3]); + ddr_phy->DENALI_PHY_887_DATA = 0x00000000; + ddr_phy->DENALI_PHY_888_DATA = 0x00800802; + ddr_phy->DENALI_PHY_889_DATA = 0x00081020; + ddr_phy->DENALI_PHY_890_DATA = 0x04010000; + ddr_phy->DENALI_PHY_891_DATA = 0x61314042; + ddr_phy->DENALI_PHY_892_DATA = 0x00314000; + ddr_phy->DENALI_PHY_893_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_894_DATA = 0x05010080; + ddr_phy->DENALI_PHY_895_DATA = 0x00000400; + ddr_phy->DENALI_PHY_896_DATA = 0x42100010; + ddr_phy->DENALI_PHY_897_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_898_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_899_DATA = 0x40420100; + ddr_phy->DENALI_PHY_900_DATA = 0x40518031; + ddr_phy->DENALI_PHY_901_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_902_DATA = 0x00000233; + ddr_phy->DENALI_PHY_903_DATA = 0x00000203; + ddr_phy->DENALI_PHY_904_DATA = 0x03000100; + ddr_phy->DENALI_PHY_905_DATA = 0x20202000; + ddr_phy->DENALI_PHY_906_DATA = 0x20202020; + ddr_phy->DENALI_PHY_907_DATA = 0x80202020; + ddr_phy->DENALI_PHY_908_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_909_DATA = 0x00000000; + ddr_phy->DENALI_PHY_910_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1024_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1025_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1026_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1027_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1028_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1029_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1030_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1031_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1032_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1033_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1034_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1035_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1036_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1037_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1038_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1039_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_1040_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1041_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1042_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1043_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1044_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1045_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1046_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1047_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1048_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1049_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1051_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1052_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1053_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1054_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_1055_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1056_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1057_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1058_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1059_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1061_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1063_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1064_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1065_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1066_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1067_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1068_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1069_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1070_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1071_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1072_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1073_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1074_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1074_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1075_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1076_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1077_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1078_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1079_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1080_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1081_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1082_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1083_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1097_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1098_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1102_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1103_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1105_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_1106_DATA = 0x02100230; + ddr_phy->DENALI_PHY_1107_DATA = 0x02300230; + ddr_phy->DENALI_PHY_1108_DATA = 0x02300230; + ddr_phy->DENALI_PHY_1109_DATA = 0x02300230; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_1106_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1107_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1108_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1109_DATA = 0x02500250; + } else { + ddr_phy->DENALI_PHY_1106_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1107_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1108_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1109_DATA = 0x02600260; + } + ddr_phy->DENALI_PHY_1110_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1116_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1117_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1118_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1119_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1120_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1121_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1122_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1123_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1124_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1125_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1126_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1127_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1128_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1129_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1130_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1131_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1132_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1133_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1134_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1135_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1136_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1137_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[4] << 16) | 0x00000100; + ddr_phy->DENALI_PHY_1138_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[4]); + ddr_phy->DENALI_PHY_1139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1140_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1141_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[4] << 16) | 0x00000100; + ddr_phy->DENALI_PHY_1142_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[4]); + ddr_phy->DENALI_PHY_1143_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1144_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1145_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1146_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1147_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1148_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1149_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1150_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1151_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1152_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1153_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1154_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1155_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1156_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1157_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1158_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1159_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1160_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1161_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1162_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1163_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1164_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1165_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1166_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1280_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1281_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1283_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1284_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1285_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1286_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1287_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1288_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1289_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1290_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1291_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1293_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1295_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_1296_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1297_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1298_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1299_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1300_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1301_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1302_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1303_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1304_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1305_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1307_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1308_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1309_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1310_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_1311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1312_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1313_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1314_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1315_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1329_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1330_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1330_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1334_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1335_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1337_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1338_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1339_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1340_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1341_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1342_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1348_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1349_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1350_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1351_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1352_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1353_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1354_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1355_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1356_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1357_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1358_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1359_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1360_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1361_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_1362_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1363_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1364_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1365_DATA = 0x02500250; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_1362_DATA = 0x02300230; + ddr_phy->DENALI_PHY_1363_DATA = 0x02300230; + ddr_phy->DENALI_PHY_1364_DATA = 0x02300230; + ddr_phy->DENALI_PHY_1365_DATA = 0x02300230; + } else { + ddr_phy->DENALI_PHY_1362_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1363_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1364_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1365_DATA = 0x02800280; + } + ddr_phy->DENALI_PHY_1366_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1367_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1368_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1369_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1370_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1372_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1373_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1374_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1375_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1376_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1377_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1378_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1379_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1380_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1381_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1382_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1383_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1384_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1385_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1386_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1387_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1388_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1389_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1390_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1391_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1392_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1393_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1394_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[5]); + ddr_phy->DENALI_PHY_1395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1396_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1397_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1398_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[5]); + ddr_phy->DENALI_PHY_1399_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1400_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1401_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1402_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1403_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1404_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1405_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1406_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1407_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1408_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1409_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1410_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1411_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1412_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1413_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1414_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1415_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1416_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1417_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1418_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1419_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1420_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1536_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1537_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1539_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1540_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1541_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1542_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1543_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1544_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1545_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1546_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1547_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1549_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1551_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_1552_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1553_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1554_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1555_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1556_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1557_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1558_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1559_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1560_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1561_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1562_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1563_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1564_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1565_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1566_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_1567_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1568_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1569_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1570_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1571_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1585_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1586_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1586_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1590_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1591_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1593_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1594_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1595_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1596_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1597_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1598_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1604_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1605_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1606_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1607_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1608_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1609_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1610_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1611_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1612_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1613_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1614_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1615_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1616_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1617_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_1618_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1619_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1620_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1621_DATA = 0x02700270; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_1618_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1619_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1620_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1621_DATA = 0x02800280; + } else { + ddr_phy->DENALI_PHY_1618_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1619_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1620_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1621_DATA = 0x02800280; + } + ddr_phy->DENALI_PHY_1622_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1623_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1624_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1625_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1626_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1628_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1629_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1630_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1631_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1632_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1633_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1634_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1635_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1636_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1637_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1638_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1639_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1640_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1641_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1642_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1643_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1644_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1645_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1646_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1647_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1648_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1649_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1650_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[6]); + ddr_phy->DENALI_PHY_1651_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1652_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1653_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1654_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[6]); + ddr_phy->DENALI_PHY_1655_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1656_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1657_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1658_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1659_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1660_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1661_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1662_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1663_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1664_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1665_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1666_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1667_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1668_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1669_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1670_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1671_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1672_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1673_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1674_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1675_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1676_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1677_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1678_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1792_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1793_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1795_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1796_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1797_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1798_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1799_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1800_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1801_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1802_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1803_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1805_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1807_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_1808_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1809_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1810_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1811_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1812_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1813_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1814_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1815_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1816_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1817_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1818_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1819_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1820_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1821_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1822_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_1823_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1824_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1825_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1826_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1827_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1841_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1842_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1842_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1846_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1847_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1849_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1850_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1851_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1852_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1853_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1854_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1860_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1861_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1862_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1863_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1864_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1865_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1866_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1867_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1868_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1869_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1870_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1871_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1872_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1873_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1874_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1875_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1876_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1877_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1878_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1879_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1880_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1881_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1882_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1884_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1885_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1886_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1887_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1888_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1889_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1890_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1891_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1892_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1893_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1894_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1895_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1896_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1897_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1898_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1899_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1900_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1901_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1902_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1903_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1904_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1905_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1906_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[7]); + ddr_phy->DENALI_PHY_1907_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1908_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1909_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1910_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[7]); + ddr_phy->DENALI_PHY_1911_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1912_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1913_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1914_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1915_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1916_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1917_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1918_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1919_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1920_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1921_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1922_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1923_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1924_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1925_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1926_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1927_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1928_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1929_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1930_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1931_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1932_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1933_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1934_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2048_DATA = 0x76543210; + ddr_phy->DENALI_PHY_2049_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_2050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2051_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_2052_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2053_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2054_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2055_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_2056_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_2057_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_2058_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2059_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2061_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2063_DATA = VREF_TRAINING_CTRL_2400; + ddr_phy->DENALI_PHY_2064_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_2065_DATA = 0x00000008; + ddr_phy->DENALI_PHY_2066_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_2067_DATA = 0x00005555; + ddr_phy->DENALI_PHY_2068_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2069_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_2070_DATA = 0x00005656; + ddr_phy->DENALI_PHY_2071_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2072_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2073_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2074_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2075_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_2076_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_2077_DATA = (PHY_PAD_VREF_CTRL_DQ_2400 << 16) | 0x0000; + ddr_phy->DENALI_PHY_2078_DATA = PHY_PAD_VREF_CTRL_DQ_2400; + ddr_phy->DENALI_PHY_2079_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2080_DATA = 0x04080000; + ddr_phy->DENALI_PHY_2081_DATA = 0x08040400; + ddr_phy->DENALI_PHY_2082_DATA = 0x00000004; + ddr_phy->DENALI_PHY_2083_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_2084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2097_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_2098_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_2098_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_2099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2102_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2103_DATA = 0x20000004; + ddr_phy->DENALI_PHY_2104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2105_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2106_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2107_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2108_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2109_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2110_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2116_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2117_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2118_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2120_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2121_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2122_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2123_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2124_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2125_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2126_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_2127_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2128_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2129_DATA = 0x04000000; + if ((info->number_of_ranks == 1) && (dmc_id == 0)) { + ddr_phy->DENALI_PHY_2130_DATA = 0x02600260; + ddr_phy->DENALI_PHY_2131_DATA = 0x02600260; + ddr_phy->DENALI_PHY_2132_DATA = 0x02600260; + ddr_phy->DENALI_PHY_2133_DATA = 0x02600260; + } else if ((info->number_of_ranks == 1) && (dmc_id == 1)) { + ddr_phy->DENALI_PHY_2130_DATA = 0x02700270; + ddr_phy->DENALI_PHY_2131_DATA = 0x02700270; + ddr_phy->DENALI_PHY_2132_DATA = 0x02700270; + ddr_phy->DENALI_PHY_2133_DATA = 0x02700270; + } else { + ddr_phy->DENALI_PHY_2130_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2131_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2132_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2133_DATA = 0x02800280; + } + ddr_phy->DENALI_PHY_2134_DATA = 0x00000280; + ddr_phy->DENALI_PHY_2135_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2136_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2137_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2138_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2140_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2141_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2142_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2143_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2144_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2145_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2146_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2147_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2148_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2149_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2150_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2151_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2152_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2153_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2154_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2155_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2156_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2157_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2158_DATA = 0x10040001; + ddr_phy->DENALI_PHY_2159_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_2160_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2161_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2162_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[8]); + ddr_phy->DENALI_PHY_2163_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2164_DATA = + (PHY_WRITE_PATH_LAT_ADD_2400[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2165_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2400[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2166_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2400[8]); + ddr_phy->DENALI_PHY_2167_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2168_DATA = 0x00800802; + ddr_phy->DENALI_PHY_2169_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2170_DATA = 0x04010000; + ddr_phy->DENALI_PHY_2171_DATA = 0x61314042; + ddr_phy->DENALI_PHY_2172_DATA = 0x00314000; + ddr_phy->DENALI_PHY_2173_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_2174_DATA = 0x05010080; + ddr_phy->DENALI_PHY_2175_DATA = 0x00000400; + ddr_phy->DENALI_PHY_2176_DATA = 0x42100010; + ddr_phy->DENALI_PHY_2177_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_2178_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_2179_DATA = 0x40420100; + ddr_phy->DENALI_PHY_2180_DATA = 0x40518031; + ddr_phy->DENALI_PHY_2181_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_2182_DATA = 0x00000233; + ddr_phy->DENALI_PHY_2183_DATA = 0x00000203; + ddr_phy->DENALI_PHY_2184_DATA = 0x03000100; + ddr_phy->DENALI_PHY_2185_DATA = 0x20202000; + ddr_phy->DENALI_PHY_2186_DATA = 0x20202020; + ddr_phy->DENALI_PHY_2187_DATA = 0x80202020; + ddr_phy->DENALI_PHY_2188_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_2189_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2190_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2305_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2309_DATA = 0x00050000; + ddr_phy->DENALI_PHY_2310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2313_DATA = 0x02010000; + ddr_phy->DENALI_PHY_2314_DATA = 0x00008008; + ddr_phy->DENALI_PHY_2315_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2320_DATA = 0x00010100; + ddr_phy->DENALI_PHY_2321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2327_DATA = 0x64000000; + ddr_phy->DENALI_PHY_2328_DATA = 0x00000050; + ddr_phy->DENALI_PHY_2329_DATA = 0x014A114A; + ddr_phy->DENALI_PHY_2330_DATA = 0x0000014A; + ddr_phy->DENALI_PHY_2331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2332_DATA = 0x00163F00; + ddr_phy->DENALI_PHY_2333_DATA = 0x42080010; + ddr_phy->DENALI_PHY_2334_DATA = 0x0100003E; + ddr_phy->DENALI_PHY_2335_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2336_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2337_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2338_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2339_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2340_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2341_DATA = 0x80002020; + ddr_phy->DENALI_PHY_2342_DATA = 0x00124924; + ddr_phy->DENALI_PHY_2343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2347_DATA = 0x070A0707; + ddr_phy->DENALI_PHY_2348_DATA = 0x00005400; + ddr_phy->DENALI_PHY_2349_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2350_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2351_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2352_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2353_DATA = phy_pad_data_drive_value; + ddr_phy->DENALI_PHY_2354_DATA = 0x0000073F; + ddr_phy->DENALI_PHY_2355_DATA = 0x0006BF00; + ddr_phy->DENALI_PHY_2356_DATA = 0x013200E0; + ddr_phy->DENALI_PHY_2357_DATA = phy_pad_clk_drive_value; + ddr_phy->DENALI_PHY_2358_DATA = 0x00007000; + ddr_phy->DENALI_PHY_2359_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2360_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2361_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2362_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2363_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2364_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2365_DATA = 0x00073F10; + ddr_phy->DENALI_PHY_2366_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2367_DATA = 0x00024410; + ddr_phy->DENALI_PHY_2368_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2369_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2370_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2371_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2372_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2373_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2374_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2375_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2376_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2377_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2378_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2379_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2380_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2381_DATA = 0x04102089; + ddr_phy->DENALI_PHY_2382_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2383_DATA = 0x00020011; + ddr_phy->DENALI_PHY_2384_DATA = 0x00021000; + ddr_phy->DENALI_PHY_2385_DATA = 0x00000448; + ddr_phy->DENALI_PHY_2386_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2387_DATA = 0x04000408; + ddr_phy->DENALI_PHY_2388_DATA = 0x00000020; + ddr_phy->DENALI_PHY_2389_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2390_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2391_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2392_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2393_DATA = 0x03000000; + ddr_phy->DENALI_PHY_2394_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2396_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2397_DATA = 0x04102035; + ddr_phy->DENALI_PHY_2398_DATA = 0x00041020; + ddr_phy->DENALI_PHY_2399_DATA = 0x01C98C98; + ddr_phy->DENALI_PHY_2400_DATA = 0x3F400000; + ddr_phy->DENALI_PHY_2401_DATA = 0x3F3F1F3F; + ddr_phy->DENALI_PHY_2402_DATA = 0x1F3F3F1F; + ddr_phy->DENALI_PHY_2403_DATA = 0x001F3F3F; + ddr_phy->DENALI_PHY_2404_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2405_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2406_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2407_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2408_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2409_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2410_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2411_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2412_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2413_DATA = 0x00040700; + ddr_phy->DENALI_PHY_2414_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2415_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2416_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2417_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2418_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2419_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2420_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2423_DATA = 0x00000002; + ddr_phy->DENALI_PHY_2424_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2425_DATA = 0x0000000F; +} diff --git a/product/morello/module/dmc_bing/src/ddr_phy_values_1333.c b/product/morello/module/dmc_bing/src/ddr_phy_values_1333.c new file mode 100644 index 000000000..3d3a49b91 --- /dev/null +++ b/product/morello/module/dmc_bing/src/ddr_phy_values_1333.c @@ -0,0 +1,1615 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Morello DDR-PHY register value configuration for 1333MHz speed. + */ + +#include + +#include + +#include + +#include + +#include +#include + +static uint8_t PHY_WRITE_PATH_LAT_ADD_2667[9] = { 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +static uint16_t PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[9] = { + 0x1A0, 0x120, 0x100, 0, 0, 0, 0x100, 0x100, 0 +}; +static uint8_t PHY_WRLVL_EARLY_FORCE_ZERO_2667[9] = { + 0, 0, 0, 0, 1, 0, 0, 0, 0 +}; +static uint32_t PHY_PAD_VREF_CTRL_DQ_2667; +static uint32_t VREF_TRAINING_CTRL_2667 = 0x00042520; +static uint16_t phy_dq_tsel_select_value; +static uint16_t phy_dqs_tsel_select_value; +static uint32_t phy_pad_data_drive_value = 0x2000073F; +static uint32_t phy_pad_clk_drive_value = 0x0006BF99; + +void ddr_phy_config_1333( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info, + int dmc_id) +{ + fwk_assert((ddr_phy != NULL) && (info != NULL)); + + if (info->number_of_ranks == 1) { + PHY_PAD_VREF_CTRL_DQ_2667 = 0x1234; + phy_dq_tsel_select_value = 0x9990; + phy_dqs_tsel_select_value = 0x9990; + } else { + PHY_PAD_VREF_CTRL_DQ_2667 = 0x1260; + phy_dq_tsel_select_value = 0x8890; + phy_dqs_tsel_select_value = 0x8890; + } + + ddr_phy->DENALI_PHY_00_DATA = 0x76543210; + ddr_phy->DENALI_PHY_01_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_02_DATA = 0x00000000; + ddr_phy->DENALI_PHY_03_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_04_DATA = 0x00000000; + ddr_phy->DENALI_PHY_05_DATA = 0x00000000; + ddr_phy->DENALI_PHY_06_DATA = 0x00010000; + ddr_phy->DENALI_PHY_07_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_08_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_09_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_10_DATA = 0x00010000; + ddr_phy->DENALI_PHY_11_DATA = 0x00000000; + ddr_phy->DENALI_PHY_12_DATA = 0x00000000; + ddr_phy->DENALI_PHY_13_DATA = 0x01000100; + ddr_phy->DENALI_PHY_14_DATA = 0x00000000; + ddr_phy->DENALI_PHY_15_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_16_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_17_DATA = 0x00000008; + ddr_phy->DENALI_PHY_18_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_19_DATA = 0x00005555; + ddr_phy->DENALI_PHY_20_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_21_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_22_DATA = 0x00005656; + ddr_phy->DENALI_PHY_23_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_24_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_25_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_26_DATA = 0x00000000; + ddr_phy->DENALI_PHY_27_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_28_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_29_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_30_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_31_DATA = 0x00000000; + ddr_phy->DENALI_PHY_32_DATA = 0x04080000; + ddr_phy->DENALI_PHY_33_DATA = 0x08040400; + ddr_phy->DENALI_PHY_34_DATA = 0x00000004; + ddr_phy->DENALI_PHY_35_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_36_DATA = 0x00000000; + ddr_phy->DENALI_PHY_37_DATA = 0x00000000; + ddr_phy->DENALI_PHY_38_DATA = 0x00000000; + ddr_phy->DENALI_PHY_39_DATA = 0x00000000; + ddr_phy->DENALI_PHY_40_DATA = 0x00000000; + ddr_phy->DENALI_PHY_41_DATA = 0x00000000; + ddr_phy->DENALI_PHY_42_DATA = 0x00000000; + ddr_phy->DENALI_PHY_43_DATA = 0x00000000; + ddr_phy->DENALI_PHY_44_DATA = 0x00000000; + ddr_phy->DENALI_PHY_45_DATA = 0x00000000; + ddr_phy->DENALI_PHY_46_DATA = 0x00000000; + ddr_phy->DENALI_PHY_47_DATA = 0x00000000; + ddr_phy->DENALI_PHY_48_DATA = 0x00000000; + ddr_phy->DENALI_PHY_49_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_50_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_50_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_51_DATA = 0x00000000; + ddr_phy->DENALI_PHY_52_DATA = 0x00000000; + ddr_phy->DENALI_PHY_53_DATA = 0x00000000; + ddr_phy->DENALI_PHY_54_DATA = 0x00000000; + ddr_phy->DENALI_PHY_55_DATA = 0x20000010; + ddr_phy->DENALI_PHY_56_DATA = 0x00000000; + ddr_phy->DENALI_PHY_57_DATA = 0x00000000; + ddr_phy->DENALI_PHY_58_DATA = 0x00000000; + ddr_phy->DENALI_PHY_59_DATA = 0x00000000; + ddr_phy->DENALI_PHY_60_DATA = 0x00000000; + ddr_phy->DENALI_PHY_61_DATA = 0x00000000; + ddr_phy->DENALI_PHY_62_DATA = 0x00000000; + ddr_phy->DENALI_PHY_63_DATA = 0x00000000; + ddr_phy->DENALI_PHY_64_DATA = 0x00000000; + ddr_phy->DENALI_PHY_65_DATA = 0x00000000; + ddr_phy->DENALI_PHY_66_DATA = 0x00000000; + ddr_phy->DENALI_PHY_67_DATA = 0x00000000; + ddr_phy->DENALI_PHY_68_DATA = 0x00000000; + ddr_phy->DENALI_PHY_69_DATA = 0x00000000; + ddr_phy->DENALI_PHY_70_DATA = 0x00000000; + ddr_phy->DENALI_PHY_71_DATA = 0x00000000; + ddr_phy->DENALI_PHY_72_DATA = 0x00000000; + ddr_phy->DENALI_PHY_73_DATA = 0x00000000; + ddr_phy->DENALI_PHY_74_DATA = 0x00000000; + ddr_phy->DENALI_PHY_75_DATA = 0x00000000; + ddr_phy->DENALI_PHY_76_DATA = 0x00000000; + ddr_phy->DENALI_PHY_77_DATA = 0x00000000; + ddr_phy->DENALI_PHY_78_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_79_DATA = 0x00000000; + ddr_phy->DENALI_PHY_80_DATA = 0x00000000; + ddr_phy->DENALI_PHY_81_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_82_DATA = 0x02400240; + ddr_phy->DENALI_PHY_83_DATA = 0x02400240; + ddr_phy->DENALI_PHY_84_DATA = 0x02400240; + ddr_phy->DENALI_PHY_85_DATA = 0x02400240; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_82_DATA = 0x02500250; + ddr_phy->DENALI_PHY_83_DATA = 0x02500250; + ddr_phy->DENALI_PHY_84_DATA = 0x02500250; + ddr_phy->DENALI_PHY_85_DATA = 0x02500250; + } + ddr_phy->DENALI_PHY_86_DATA = 0x00000280; + ddr_phy->DENALI_PHY_87_DATA = 0x00000000; + ddr_phy->DENALI_PHY_88_DATA = 0x00000000; + ddr_phy->DENALI_PHY_89_DATA = 0x00000000; + ddr_phy->DENALI_PHY_90_DATA = 0x00000000; + ddr_phy->DENALI_PHY_91_DATA = 0x00000000; + ddr_phy->DENALI_PHY_92_DATA = 0x00800080; + ddr_phy->DENALI_PHY_93_DATA = 0x00800080; + ddr_phy->DENALI_PHY_94_DATA = 0x00800080; + ddr_phy->DENALI_PHY_95_DATA = 0x00800080; + ddr_phy->DENALI_PHY_96_DATA = 0x00800080; + ddr_phy->DENALI_PHY_97_DATA = 0x00800080; + ddr_phy->DENALI_PHY_98_DATA = 0x00800080; + ddr_phy->DENALI_PHY_99_DATA = 0x00800080; + ddr_phy->DENALI_PHY_100_DATA = 0x00800080; + ddr_phy->DENALI_PHY_101_DATA = 0x00800080; + ddr_phy->DENALI_PHY_102_DATA = 0x00800080; + ddr_phy->DENALI_PHY_103_DATA = 0x00800080; + ddr_phy->DENALI_PHY_104_DATA = 0x00800080; + ddr_phy->DENALI_PHY_105_DATA = 0x00800080; + ddr_phy->DENALI_PHY_106_DATA = 0x00800080; + ddr_phy->DENALI_PHY_107_DATA = 0x00800080; + ddr_phy->DENALI_PHY_108_DATA = 0x00800080; + ddr_phy->DENALI_PHY_109_DATA = 0x00800080; + ddr_phy->DENALI_PHY_110_DATA = 0x10040001; + ddr_phy->DENALI_PHY_111_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_112_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_113_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_114_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[0]); + ddr_phy->DENALI_PHY_115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_116_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_117_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_118_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[0]); + ddr_phy->DENALI_PHY_119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_120_DATA = 0x00800802; + ddr_phy->DENALI_PHY_121_DATA = 0x00081020; + ddr_phy->DENALI_PHY_122_DATA = 0x04010000; + ddr_phy->DENALI_PHY_123_DATA = 0x61314042; + ddr_phy->DENALI_PHY_124_DATA = 0x00314000; + ddr_phy->DENALI_PHY_125_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_126_DATA = 0x05010080; + ddr_phy->DENALI_PHY_127_DATA = 0x00000400; + ddr_phy->DENALI_PHY_128_DATA = 0x42100010; + ddr_phy->DENALI_PHY_129_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_130_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_131_DATA = 0x40420100; + ddr_phy->DENALI_PHY_132_DATA = 0x40518031; + ddr_phy->DENALI_PHY_133_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_134_DATA = 0x00000233; + ddr_phy->DENALI_PHY_135_DATA = 0x00000203; + ddr_phy->DENALI_PHY_136_DATA = 0x03000100; + ddr_phy->DENALI_PHY_137_DATA = 0x20202000; + ddr_phy->DENALI_PHY_138_DATA = 0x20202020; + ddr_phy->DENALI_PHY_139_DATA = 0x80202020; + ddr_phy->DENALI_PHY_140_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_141_DATA = 0x00000000; + ddr_phy->DENALI_PHY_142_DATA = 0x00000000; + ddr_phy->DENALI_PHY_256_DATA = 0x76543210; + ddr_phy->DENALI_PHY_257_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_258_DATA = 0x00000000; + ddr_phy->DENALI_PHY_259_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_260_DATA = 0x00000000; + ddr_phy->DENALI_PHY_261_DATA = 0x00000000; + ddr_phy->DENALI_PHY_262_DATA = 0x00010000; + ddr_phy->DENALI_PHY_263_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_264_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_265_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_266_DATA = 0x00010000; + ddr_phy->DENALI_PHY_267_DATA = 0x00000000; + ddr_phy->DENALI_PHY_268_DATA = 0x00000000; + ddr_phy->DENALI_PHY_269_DATA = 0x01000100; + ddr_phy->DENALI_PHY_270_DATA = 0x00000000; + ddr_phy->DENALI_PHY_271_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_272_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_273_DATA = 0x00000008; + ddr_phy->DENALI_PHY_274_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_275_DATA = 0x00005555; + ddr_phy->DENALI_PHY_276_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_277_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_278_DATA = 0x00005656; + ddr_phy->DENALI_PHY_279_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_280_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_281_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_283_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_284_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_285_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_286_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_287_DATA = 0x00000000; + ddr_phy->DENALI_PHY_288_DATA = 0x04080000; + ddr_phy->DENALI_PHY_289_DATA = 0x08040400; + ddr_phy->DENALI_PHY_290_DATA = 0x00000004; + ddr_phy->DENALI_PHY_291_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_293_DATA = 0x00000000; + ddr_phy->DENALI_PHY_294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_295_DATA = 0x00000000; + ddr_phy->DENALI_PHY_296_DATA = 0x00000000; + ddr_phy->DENALI_PHY_297_DATA = 0x00000000; + ddr_phy->DENALI_PHY_298_DATA = 0x00000000; + ddr_phy->DENALI_PHY_299_DATA = 0x00000000; + ddr_phy->DENALI_PHY_300_DATA = 0x00000000; + ddr_phy->DENALI_PHY_301_DATA = 0x00000000; + ddr_phy->DENALI_PHY_302_DATA = 0x00000000; + ddr_phy->DENALI_PHY_303_DATA = 0x00000000; + ddr_phy->DENALI_PHY_304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_305_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_306_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_306_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_309_DATA = 0x00000000; + ddr_phy->DENALI_PHY_310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_311_DATA = 0x20000010; + ddr_phy->DENALI_PHY_312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_313_DATA = 0x00000000; + ddr_phy->DENALI_PHY_314_DATA = 0x00000000; + ddr_phy->DENALI_PHY_315_DATA = 0x00000000; + ddr_phy->DENALI_PHY_316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_329_DATA = 0x00000000; + ddr_phy->DENALI_PHY_330_DATA = 0x00000000; + ddr_phy->DENALI_PHY_331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_334_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_335_DATA = 0x00000000; + ddr_phy->DENALI_PHY_336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_337_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_338_DATA = 0x02800280; + ddr_phy->DENALI_PHY_339_DATA = 0x02800280; + ddr_phy->DENALI_PHY_340_DATA = 0x02800280; + ddr_phy->DENALI_PHY_341_DATA = 0x02800280; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_338_DATA = 0x02700270; + ddr_phy->DENALI_PHY_339_DATA = 0x02700270; + ddr_phy->DENALI_PHY_340_DATA = 0x02700270; + ddr_phy->DENALI_PHY_341_DATA = 0x02700270; + } + ddr_phy->DENALI_PHY_342_DATA = 0x00000280; + ddr_phy->DENALI_PHY_343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_348_DATA = 0x00800080; + ddr_phy->DENALI_PHY_349_DATA = 0x00800080; + ddr_phy->DENALI_PHY_350_DATA = 0x00800080; + ddr_phy->DENALI_PHY_351_DATA = 0x00800080; + ddr_phy->DENALI_PHY_352_DATA = 0x00800080; + ddr_phy->DENALI_PHY_353_DATA = 0x00800080; + ddr_phy->DENALI_PHY_354_DATA = 0x00800080; + ddr_phy->DENALI_PHY_355_DATA = 0x00800080; + ddr_phy->DENALI_PHY_356_DATA = 0x00800080; + ddr_phy->DENALI_PHY_357_DATA = 0x00800080; + ddr_phy->DENALI_PHY_358_DATA = 0x00800080; + ddr_phy->DENALI_PHY_359_DATA = 0x00800080; + ddr_phy->DENALI_PHY_360_DATA = 0x00800080; + ddr_phy->DENALI_PHY_361_DATA = 0x00800080; + ddr_phy->DENALI_PHY_362_DATA = 0x00800080; + ddr_phy->DENALI_PHY_363_DATA = 0x00800080; + ddr_phy->DENALI_PHY_364_DATA = 0x00800080; + ddr_phy->DENALI_PHY_365_DATA = 0x00800080; + ddr_phy->DENALI_PHY_366_DATA = 0x10040001; + ddr_phy->DENALI_PHY_367_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_368_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_369_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_370_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[1]); + ddr_phy->DENALI_PHY_371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_372_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_373_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_374_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[1]); + ddr_phy->DENALI_PHY_375_DATA = 0x00000000; + ddr_phy->DENALI_PHY_376_DATA = 0x00800802; + ddr_phy->DENALI_PHY_377_DATA = 0x00081020; + ddr_phy->DENALI_PHY_378_DATA = 0x04010000; + ddr_phy->DENALI_PHY_379_DATA = 0x61314042; + ddr_phy->DENALI_PHY_380_DATA = 0x00314000; + ddr_phy->DENALI_PHY_381_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_382_DATA = 0x05010080; + ddr_phy->DENALI_PHY_383_DATA = 0x00000400; + ddr_phy->DENALI_PHY_384_DATA = 0x42100010; + ddr_phy->DENALI_PHY_385_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_386_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_387_DATA = 0x40420100; + ddr_phy->DENALI_PHY_388_DATA = 0x40518031; + ddr_phy->DENALI_PHY_389_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_390_DATA = 0x00000233; + ddr_phy->DENALI_PHY_391_DATA = 0x00000203; + ddr_phy->DENALI_PHY_392_DATA = 0x03000100; + ddr_phy->DENALI_PHY_393_DATA = 0x20202000; + ddr_phy->DENALI_PHY_394_DATA = 0x20202020; + ddr_phy->DENALI_PHY_395_DATA = 0x80202020; + ddr_phy->DENALI_PHY_396_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_397_DATA = 0x00000000; + ddr_phy->DENALI_PHY_398_DATA = 0x00000000; + ddr_phy->DENALI_PHY_512_DATA = 0x76543210; + ddr_phy->DENALI_PHY_513_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_514_DATA = 0x00000000; + ddr_phy->DENALI_PHY_515_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_516_DATA = 0x00000000; + ddr_phy->DENALI_PHY_517_DATA = 0x00000000; + ddr_phy->DENALI_PHY_518_DATA = 0x00010000; + ddr_phy->DENALI_PHY_519_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_520_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_521_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_522_DATA = 0x00010000; + ddr_phy->DENALI_PHY_523_DATA = 0x00000000; + ddr_phy->DENALI_PHY_524_DATA = 0x00000000; + ddr_phy->DENALI_PHY_525_DATA = 0x01000100; + ddr_phy->DENALI_PHY_526_DATA = 0x00000000; + ddr_phy->DENALI_PHY_527_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_528_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_529_DATA = 0x00000008; + ddr_phy->DENALI_PHY_530_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_531_DATA = 0x00005555; + ddr_phy->DENALI_PHY_532_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_533_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_534_DATA = 0x00005656; + ddr_phy->DENALI_PHY_535_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_536_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_537_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_539_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_540_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_541_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_542_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_543_DATA = 0x00000000; + ddr_phy->DENALI_PHY_544_DATA = 0x04080000; + ddr_phy->DENALI_PHY_545_DATA = 0x08040400; + ddr_phy->DENALI_PHY_546_DATA = 0x00000004; + ddr_phy->DENALI_PHY_547_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_549_DATA = 0x00000000; + ddr_phy->DENALI_PHY_550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_551_DATA = 0x00000000; + ddr_phy->DENALI_PHY_552_DATA = 0x00000000; + ddr_phy->DENALI_PHY_553_DATA = 0x00000000; + ddr_phy->DENALI_PHY_554_DATA = 0x00000000; + ddr_phy->DENALI_PHY_555_DATA = 0x00000000; + ddr_phy->DENALI_PHY_556_DATA = 0x00000000; + ddr_phy->DENALI_PHY_557_DATA = 0x00000000; + ddr_phy->DENALI_PHY_558_DATA = 0x00000000; + ddr_phy->DENALI_PHY_559_DATA = 0x00000000; + ddr_phy->DENALI_PHY_560_DATA = 0x00000000; + ddr_phy->DENALI_PHY_561_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_562_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_562_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_563_DATA = 0x00000000; + ddr_phy->DENALI_PHY_564_DATA = 0x00000000; + ddr_phy->DENALI_PHY_565_DATA = 0x00000000; + ddr_phy->DENALI_PHY_566_DATA = 0x00000000; + ddr_phy->DENALI_PHY_567_DATA = 0x20000010; + ddr_phy->DENALI_PHY_568_DATA = 0x00000000; + ddr_phy->DENALI_PHY_569_DATA = 0x00000000; + ddr_phy->DENALI_PHY_570_DATA = 0x00000000; + ddr_phy->DENALI_PHY_571_DATA = 0x00000000; + ddr_phy->DENALI_PHY_572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_585_DATA = 0x00000000; + ddr_phy->DENALI_PHY_586_DATA = 0x00000000; + ddr_phy->DENALI_PHY_587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_590_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_591_DATA = 0x00000000; + ddr_phy->DENALI_PHY_592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_593_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_594_DATA = 0x02800280; + ddr_phy->DENALI_PHY_595_DATA = 0x02800280; + ddr_phy->DENALI_PHY_596_DATA = 0x02800280; + ddr_phy->DENALI_PHY_597_DATA = 0x02800280; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_594_DATA = 0x02700270; + ddr_phy->DENALI_PHY_595_DATA = 0x02700270; + ddr_phy->DENALI_PHY_596_DATA = 0x02700270; + ddr_phy->DENALI_PHY_597_DATA = 0x02700270; + } + ddr_phy->DENALI_PHY_598_DATA = 0x00000280; + ddr_phy->DENALI_PHY_599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_604_DATA = 0x00800080; + ddr_phy->DENALI_PHY_605_DATA = 0x00800080; + ddr_phy->DENALI_PHY_606_DATA = 0x00800080; + ddr_phy->DENALI_PHY_607_DATA = 0x00800080; + ddr_phy->DENALI_PHY_608_DATA = 0x00800080; + ddr_phy->DENALI_PHY_609_DATA = 0x00800080; + ddr_phy->DENALI_PHY_610_DATA = 0x00800080; + ddr_phy->DENALI_PHY_611_DATA = 0x00800080; + ddr_phy->DENALI_PHY_612_DATA = 0x00800080; + ddr_phy->DENALI_PHY_613_DATA = 0x00800080; + ddr_phy->DENALI_PHY_614_DATA = 0x00800080; + ddr_phy->DENALI_PHY_615_DATA = 0x00800080; + ddr_phy->DENALI_PHY_616_DATA = 0x00800080; + ddr_phy->DENALI_PHY_617_DATA = 0x00800080; + ddr_phy->DENALI_PHY_618_DATA = 0x00800080; + ddr_phy->DENALI_PHY_619_DATA = 0x00800080; + ddr_phy->DENALI_PHY_620_DATA = 0x00800080; + ddr_phy->DENALI_PHY_621_DATA = 0x00800080; + ddr_phy->DENALI_PHY_622_DATA = 0x10040001; + ddr_phy->DENALI_PHY_623_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_624_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_625_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_626_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[2]); + ddr_phy->DENALI_PHY_627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_628_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_629_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_630_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[2]); + ddr_phy->DENALI_PHY_631_DATA = 0x00000000; + ddr_phy->DENALI_PHY_632_DATA = 0x00800802; + ddr_phy->DENALI_PHY_633_DATA = 0x00081020; + ddr_phy->DENALI_PHY_634_DATA = 0x04010000; + ddr_phy->DENALI_PHY_635_DATA = 0x61314042; + ddr_phy->DENALI_PHY_636_DATA = 0x00314000; + ddr_phy->DENALI_PHY_637_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_638_DATA = 0x05010080; + ddr_phy->DENALI_PHY_639_DATA = 0x00000400; + ddr_phy->DENALI_PHY_640_DATA = 0x42100010; + ddr_phy->DENALI_PHY_641_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_642_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_643_DATA = 0x40420100; + ddr_phy->DENALI_PHY_644_DATA = 0x40518031; + ddr_phy->DENALI_PHY_645_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_646_DATA = 0x00000233; + ddr_phy->DENALI_PHY_647_DATA = 0x00000203; + ddr_phy->DENALI_PHY_648_DATA = 0x03000100; + ddr_phy->DENALI_PHY_649_DATA = 0x20202000; + ddr_phy->DENALI_PHY_650_DATA = 0x20202020; + ddr_phy->DENALI_PHY_651_DATA = 0x80202020; + ddr_phy->DENALI_PHY_652_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_653_DATA = 0x00000000; + ddr_phy->DENALI_PHY_654_DATA = 0x00000000; + ddr_phy->DENALI_PHY_768_DATA = 0x76543210; + ddr_phy->DENALI_PHY_769_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_770_DATA = 0x00000000; + ddr_phy->DENALI_PHY_771_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_772_DATA = 0x00000000; + ddr_phy->DENALI_PHY_773_DATA = 0x00000000; + ddr_phy->DENALI_PHY_774_DATA = 0x00010000; + ddr_phy->DENALI_PHY_775_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_776_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_777_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_778_DATA = 0x00010000; + ddr_phy->DENALI_PHY_779_DATA = 0x00000000; + ddr_phy->DENALI_PHY_780_DATA = 0x00000000; + ddr_phy->DENALI_PHY_781_DATA = 0x01000100; + ddr_phy->DENALI_PHY_782_DATA = 0x00000000; + ddr_phy->DENALI_PHY_783_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_784_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_785_DATA = 0x00000008; + ddr_phy->DENALI_PHY_786_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_787_DATA = 0x00005555; + ddr_phy->DENALI_PHY_788_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_789_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_790_DATA = 0x00005656; + ddr_phy->DENALI_PHY_791_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_792_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_793_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_795_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_796_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_797_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_798_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_799_DATA = 0x00000000; + ddr_phy->DENALI_PHY_800_DATA = 0x04080000; + ddr_phy->DENALI_PHY_801_DATA = 0x08040400; + ddr_phy->DENALI_PHY_802_DATA = 0x00000004; + ddr_phy->DENALI_PHY_803_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_805_DATA = 0x00000000; + ddr_phy->DENALI_PHY_806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_807_DATA = 0x00000000; + ddr_phy->DENALI_PHY_808_DATA = 0x00000000; + ddr_phy->DENALI_PHY_809_DATA = 0x00000000; + ddr_phy->DENALI_PHY_810_DATA = 0x00000000; + ddr_phy->DENALI_PHY_811_DATA = 0x00000000; + ddr_phy->DENALI_PHY_812_DATA = 0x00000000; + ddr_phy->DENALI_PHY_813_DATA = 0x00000000; + ddr_phy->DENALI_PHY_814_DATA = 0x00000000; + ddr_phy->DENALI_PHY_815_DATA = 0x00000000; + ddr_phy->DENALI_PHY_816_DATA = 0x00000000; + ddr_phy->DENALI_PHY_817_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_818_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_818_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_819_DATA = 0x00000000; + ddr_phy->DENALI_PHY_820_DATA = 0x00000000; + ddr_phy->DENALI_PHY_821_DATA = 0x00000000; + ddr_phy->DENALI_PHY_822_DATA = 0x00000000; + ddr_phy->DENALI_PHY_823_DATA = 0x20000010; + ddr_phy->DENALI_PHY_824_DATA = 0x00000000; + ddr_phy->DENALI_PHY_825_DATA = 0x00000000; + ddr_phy->DENALI_PHY_826_DATA = 0x00000000; + ddr_phy->DENALI_PHY_827_DATA = 0x00000000; + ddr_phy->DENALI_PHY_828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_841_DATA = 0x00000000; + ddr_phy->DENALI_PHY_842_DATA = 0x00000000; + ddr_phy->DENALI_PHY_843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_846_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_847_DATA = 0x00000000; + ddr_phy->DENALI_PHY_848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_849_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_850_DATA = 0x02700270; + ddr_phy->DENALI_PHY_851_DATA = 0x02700270; + ddr_phy->DENALI_PHY_852_DATA = 0x02700270; + ddr_phy->DENALI_PHY_853_DATA = 0x02700270; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_850_DATA = 0x02700270; + ddr_phy->DENALI_PHY_851_DATA = 0x02700270; + ddr_phy->DENALI_PHY_852_DATA = 0x02700270; + ddr_phy->DENALI_PHY_853_DATA = 0x02700270; + } + ddr_phy->DENALI_PHY_854_DATA = 0x00000280; + ddr_phy->DENALI_PHY_855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_860_DATA = 0x00800080; + ddr_phy->DENALI_PHY_861_DATA = 0x00800080; + ddr_phy->DENALI_PHY_862_DATA = 0x00800080; + ddr_phy->DENALI_PHY_863_DATA = 0x00800080; + ddr_phy->DENALI_PHY_864_DATA = 0x00800080; + ddr_phy->DENALI_PHY_865_DATA = 0x00800080; + ddr_phy->DENALI_PHY_866_DATA = 0x00800080; + ddr_phy->DENALI_PHY_867_DATA = 0x00800080; + ddr_phy->DENALI_PHY_868_DATA = 0x00800080; + ddr_phy->DENALI_PHY_869_DATA = 0x00800080; + ddr_phy->DENALI_PHY_870_DATA = 0x00800080; + ddr_phy->DENALI_PHY_871_DATA = 0x00800080; + ddr_phy->DENALI_PHY_872_DATA = 0x00800080; + ddr_phy->DENALI_PHY_873_DATA = 0x00800080; + ddr_phy->DENALI_PHY_874_DATA = 0x00800080; + ddr_phy->DENALI_PHY_875_DATA = 0x00800080; + ddr_phy->DENALI_PHY_876_DATA = 0x00800080; + ddr_phy->DENALI_PHY_877_DATA = 0x00800080; + ddr_phy->DENALI_PHY_878_DATA = 0x10040001; + ddr_phy->DENALI_PHY_879_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_880_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_881_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_882_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[3]); + ddr_phy->DENALI_PHY_883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_884_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_885_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_886_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[3]); + ddr_phy->DENALI_PHY_887_DATA = 0x00000000; + ddr_phy->DENALI_PHY_888_DATA = 0x00800802; + ddr_phy->DENALI_PHY_889_DATA = 0x00081020; + ddr_phy->DENALI_PHY_890_DATA = 0x04010000; + ddr_phy->DENALI_PHY_891_DATA = 0x61314042; + ddr_phy->DENALI_PHY_892_DATA = 0x00314000; + ddr_phy->DENALI_PHY_893_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_894_DATA = 0x05010080; + ddr_phy->DENALI_PHY_895_DATA = 0x00000400; + ddr_phy->DENALI_PHY_896_DATA = 0x42100010; + ddr_phy->DENALI_PHY_897_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_898_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_899_DATA = 0x40420100; + ddr_phy->DENALI_PHY_900_DATA = 0x40518031; + ddr_phy->DENALI_PHY_901_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_902_DATA = 0x00000233; + ddr_phy->DENALI_PHY_903_DATA = 0x00000203; + ddr_phy->DENALI_PHY_904_DATA = 0x03000100; + ddr_phy->DENALI_PHY_905_DATA = 0x20202000; + ddr_phy->DENALI_PHY_906_DATA = 0x20202020; + ddr_phy->DENALI_PHY_907_DATA = 0x80202020; + ddr_phy->DENALI_PHY_908_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_909_DATA = 0x00000000; + ddr_phy->DENALI_PHY_910_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1024_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1025_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1026_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1027_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1028_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1029_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1030_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1031_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1032_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1033_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1034_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1035_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1036_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1037_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1038_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1039_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_1040_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1041_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1042_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1043_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1044_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1045_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1046_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1047_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1048_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1049_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1051_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1052_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1053_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1054_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_1055_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1056_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1057_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1058_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1059_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1061_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1063_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1064_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1065_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1066_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1067_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1068_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1069_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1070_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1071_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1072_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1073_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1074_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1074_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1075_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1076_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1077_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1078_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1079_DATA = 0x20000010; + ddr_phy->DENALI_PHY_1080_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1081_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1082_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1083_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1097_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1098_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1102_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1103_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1105_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_1106_DATA = 0x02100210; + ddr_phy->DENALI_PHY_1107_DATA = 0x02100210; + ddr_phy->DENALI_PHY_1108_DATA = 0x02100210; + ddr_phy->DENALI_PHY_1109_DATA = 0x02100210; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_1106_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1107_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1108_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1109_DATA = 0x02500250; + } + ddr_phy->DENALI_PHY_1110_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1116_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1117_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1118_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1119_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1120_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1121_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1122_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1123_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1124_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1125_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1126_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1127_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1128_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1129_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1130_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1131_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1132_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1133_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1134_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1135_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1136_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1137_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[4] << 16) | 0x00000100; + ddr_phy->DENALI_PHY_1138_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[4]); + ddr_phy->DENALI_PHY_1139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1140_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1141_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[4] << 16) | 0x00000120; + ddr_phy->DENALI_PHY_1142_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[4]); + ddr_phy->DENALI_PHY_1143_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1144_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1145_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1146_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1147_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1148_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1149_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1150_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1151_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1152_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1153_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1154_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1155_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1156_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1157_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1158_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1159_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1160_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1161_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1162_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1163_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1164_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1165_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1166_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1280_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1281_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1283_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1284_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1285_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1286_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1287_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1288_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1289_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1290_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1291_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1293_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1295_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_1296_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1297_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1298_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1299_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1300_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1301_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1302_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1303_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1304_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1305_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1307_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1308_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1309_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1310_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_1311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1312_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1313_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1314_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1315_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1329_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1330_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1330_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1334_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1335_DATA = 0x20000010; + ddr_phy->DENALI_PHY_1336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1337_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1338_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1339_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1340_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1341_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1342_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1348_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1349_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1350_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1351_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1352_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1353_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1354_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1355_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1356_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1357_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1358_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1359_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1360_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1361_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_1362_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1363_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1364_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1365_DATA = 0x02600260; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_1362_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1363_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1364_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1365_DATA = 0x02500250; + } + ddr_phy->DENALI_PHY_1366_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1367_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1368_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1369_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1370_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1372_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1373_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1374_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1375_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1376_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1377_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1378_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1379_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1380_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1381_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1382_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1383_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1384_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1385_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1386_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1387_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1388_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1389_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1390_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1391_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1392_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1393_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1394_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[5]); + ddr_phy->DENALI_PHY_1395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1396_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1397_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1398_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[5]); + ddr_phy->DENALI_PHY_1399_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1400_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1401_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1402_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1403_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1404_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1405_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1406_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1407_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1408_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1409_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1410_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1411_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1412_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1413_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1414_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1415_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1416_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1417_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1418_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1419_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1420_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1536_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1537_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1539_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1540_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1541_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1542_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1543_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1544_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1545_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1546_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1547_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1549_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1551_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_1552_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1553_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1554_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1555_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1556_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1557_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1558_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1559_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1560_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1561_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1562_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1563_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1564_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1565_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1566_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_1567_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1568_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1569_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1570_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1571_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1585_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1586_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1586_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1590_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1591_DATA = 0x20000010; + ddr_phy->DENALI_PHY_1592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1593_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1594_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1595_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1596_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1597_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1598_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1604_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1605_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1606_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1607_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1608_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1609_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1610_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1611_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1612_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1613_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1614_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1615_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1616_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1617_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_1618_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1619_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1620_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1621_DATA = 0x02700270; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_1618_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1619_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1620_DATA = 0x02700270; + ddr_phy->DENALI_PHY_1621_DATA = 0x02700270; + } + ddr_phy->DENALI_PHY_1622_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1623_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1624_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1625_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1626_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1628_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1629_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1630_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1631_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1632_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1633_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1634_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1635_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1636_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1637_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1638_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1639_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1640_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1641_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1642_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1643_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1644_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1645_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1646_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1647_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1648_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1649_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1650_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[6]); + ddr_phy->DENALI_PHY_1651_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1652_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1653_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1654_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[6]); + ddr_phy->DENALI_PHY_1655_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1656_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1657_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1658_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1659_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1660_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1661_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1662_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1663_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1664_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1665_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1666_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1667_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1668_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1669_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1670_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1671_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1672_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1673_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1674_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1675_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1676_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1677_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1678_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1792_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1793_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1795_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1796_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1797_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1798_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1799_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1800_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1801_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1802_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1803_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1805_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1807_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_1808_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1809_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1810_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1811_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1812_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1813_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1814_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1815_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1816_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1817_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1818_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1819_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1820_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1821_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1822_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_1823_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1824_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1825_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1826_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1827_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1841_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1842_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1842_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1846_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1847_DATA = 0x20000010; + ddr_phy->DENALI_PHY_1848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1849_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1850_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1851_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1852_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1853_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1854_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1860_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1861_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1862_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1863_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1864_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1865_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1866_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1867_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1868_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1869_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1870_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1871_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1872_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1873_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_1874_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1875_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1876_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1877_DATA = 0x02800280; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_1874_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1875_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1876_DATA = 0x02500250; + ddr_phy->DENALI_PHY_1877_DATA = 0x02500250; + } + ddr_phy->DENALI_PHY_1878_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1879_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1880_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1881_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1882_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1884_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1885_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1886_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1887_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1888_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1889_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1890_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1891_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1892_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1893_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1894_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1895_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1896_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1897_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1898_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1899_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1900_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1901_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1902_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1903_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1904_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1905_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1906_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[7]); + ddr_phy->DENALI_PHY_1907_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1908_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1909_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1910_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[7]); + ddr_phy->DENALI_PHY_1911_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1912_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1913_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1914_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1915_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1916_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1917_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1918_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1919_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1920_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1921_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1922_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1923_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1924_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1925_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1926_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1927_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1928_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1929_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1930_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1931_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1932_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1933_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1934_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2048_DATA = 0x76543210; + ddr_phy->DENALI_PHY_2049_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_2050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2051_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_2052_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2053_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2054_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2055_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_2056_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_2057_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_2058_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2059_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2061_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2063_DATA = VREF_TRAINING_CTRL_2667; + ddr_phy->DENALI_PHY_2064_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_2065_DATA = 0x00000008; + ddr_phy->DENALI_PHY_2066_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_2067_DATA = 0x00005555; + ddr_phy->DENALI_PHY_2068_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2069_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_2070_DATA = 0x00005656; + ddr_phy->DENALI_PHY_2071_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2072_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2073_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2074_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2075_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_2076_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_2077_DATA = (PHY_PAD_VREF_CTRL_DQ_2667 << 16) | 0x0000; + ddr_phy->DENALI_PHY_2078_DATA = PHY_PAD_VREF_CTRL_DQ_2667; + ddr_phy->DENALI_PHY_2079_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2080_DATA = 0x04080000; + ddr_phy->DENALI_PHY_2081_DATA = 0x08040400; + ddr_phy->DENALI_PHY_2082_DATA = 0x00000004; + ddr_phy->DENALI_PHY_2083_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_2084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2097_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_2098_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_2098_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_2099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2102_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2103_DATA = 0x20000010; + ddr_phy->DENALI_PHY_2104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2105_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2106_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2107_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2108_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2109_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2110_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2116_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2117_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2118_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2120_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2121_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2122_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2123_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2124_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2125_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2126_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_2127_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2128_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2129_DATA = 0x04000000; + if (dmc_id == 0) { + ddr_phy->DENALI_PHY_2130_DATA = 0x02600260; + ddr_phy->DENALI_PHY_2131_DATA = 0x02600260; + ddr_phy->DENALI_PHY_2132_DATA = 0x02600260; + ddr_phy->DENALI_PHY_2133_DATA = 0x02600260; + } else if (dmc_id == 1) { + ddr_phy->DENALI_PHY_2130_DATA = 0x02700270; + ddr_phy->DENALI_PHY_2131_DATA = 0x02700270; + ddr_phy->DENALI_PHY_2132_DATA = 0x02700270; + ddr_phy->DENALI_PHY_2133_DATA = 0x02700270; + } + ddr_phy->DENALI_PHY_2134_DATA = 0x00000280; + ddr_phy->DENALI_PHY_2135_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2136_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2137_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2138_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2140_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2141_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2142_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2143_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2144_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2145_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2146_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2147_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2148_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2149_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2150_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2151_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2152_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2153_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2154_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2155_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2156_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2157_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2158_DATA = 0x10040001; + ddr_phy->DENALI_PHY_2159_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_2160_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2161_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2162_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[8]); + ddr_phy->DENALI_PHY_2163_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2164_DATA = + (PHY_WRITE_PATH_LAT_ADD_2667[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2165_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2667[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2166_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2667[8]); + ddr_phy->DENALI_PHY_2167_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2168_DATA = 0x00800802; + ddr_phy->DENALI_PHY_2169_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2170_DATA = 0x04010000; + ddr_phy->DENALI_PHY_2171_DATA = 0x61314042; + ddr_phy->DENALI_PHY_2172_DATA = 0x00314000; + ddr_phy->DENALI_PHY_2173_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_2174_DATA = 0x05010080; + ddr_phy->DENALI_PHY_2175_DATA = 0x00000400; + ddr_phy->DENALI_PHY_2176_DATA = 0x42100010; + ddr_phy->DENALI_PHY_2177_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_2178_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_2179_DATA = 0x40420100; + ddr_phy->DENALI_PHY_2180_DATA = 0x40518031; + ddr_phy->DENALI_PHY_2181_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_2182_DATA = 0x00000233; + ddr_phy->DENALI_PHY_2183_DATA = 0x00000203; + ddr_phy->DENALI_PHY_2184_DATA = 0x03000100; + ddr_phy->DENALI_PHY_2185_DATA = 0x20202000; + ddr_phy->DENALI_PHY_2186_DATA = 0x20202020; + ddr_phy->DENALI_PHY_2187_DATA = 0x80202020; + ddr_phy->DENALI_PHY_2188_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_2189_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2190_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2305_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2309_DATA = 0x00050000; + ddr_phy->DENALI_PHY_2310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2313_DATA = 0x02010000; + ddr_phy->DENALI_PHY_2314_DATA = 0x00008008; + ddr_phy->DENALI_PHY_2315_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2320_DATA = 0x00010100; + ddr_phy->DENALI_PHY_2321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2327_DATA = 0x64000000; + ddr_phy->DENALI_PHY_2328_DATA = 0x00000050; + ddr_phy->DENALI_PHY_2329_DATA = 0x014A114A; + ddr_phy->DENALI_PHY_2330_DATA = 0x0000014A; + ddr_phy->DENALI_PHY_2331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2332_DATA = 0x00163F00; + ddr_phy->DENALI_PHY_2333_DATA = 0x42080010; + ddr_phy->DENALI_PHY_2334_DATA = 0x0100003E; + ddr_phy->DENALI_PHY_2335_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2336_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2337_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2338_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2339_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2340_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2341_DATA = 0x80002020; + ddr_phy->DENALI_PHY_2342_DATA = 0x00124924; + ddr_phy->DENALI_PHY_2343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2347_DATA = 0x070A0707; + ddr_phy->DENALI_PHY_2348_DATA = 0x00005400; + ddr_phy->DENALI_PHY_2349_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2350_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2351_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2352_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2353_DATA = phy_pad_data_drive_value; + ddr_phy->DENALI_PHY_2354_DATA = 0x0000073F; + ddr_phy->DENALI_PHY_2355_DATA = 0x0006BF00; + ddr_phy->DENALI_PHY_2356_DATA = 0x013200E0; + ddr_phy->DENALI_PHY_2357_DATA = phy_pad_clk_drive_value; + ddr_phy->DENALI_PHY_2358_DATA = 0x00007000; + ddr_phy->DENALI_PHY_2359_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2360_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2361_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2362_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2363_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2364_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2365_DATA = 0x00073F10; + ddr_phy->DENALI_PHY_2366_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2367_DATA = 0x00024410; + ddr_phy->DENALI_PHY_2368_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2369_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2370_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2371_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2372_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2373_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2374_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2375_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2376_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2377_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2378_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2379_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2380_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2381_DATA = 0x04102089; + ddr_phy->DENALI_PHY_2382_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2383_DATA = 0x00020011; + ddr_phy->DENALI_PHY_2384_DATA = 0x00021000; + ddr_phy->DENALI_PHY_2385_DATA = 0x00000448; + ddr_phy->DENALI_PHY_2386_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2387_DATA = 0x04000408; + ddr_phy->DENALI_PHY_2388_DATA = 0x00000020; + ddr_phy->DENALI_PHY_2389_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2390_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2391_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2392_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2393_DATA = 0x03000000; + ddr_phy->DENALI_PHY_2394_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2396_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2397_DATA = 0x04102035; + ddr_phy->DENALI_PHY_2398_DATA = 0x00041020; + ddr_phy->DENALI_PHY_2399_DATA = 0x01C98C98; + ddr_phy->DENALI_PHY_2400_DATA = 0x3F400000; + ddr_phy->DENALI_PHY_2401_DATA = 0x3F3F1F3F; + ddr_phy->DENALI_PHY_2402_DATA = 0x1F3F3F1F; + ddr_phy->DENALI_PHY_2403_DATA = 0x001F3F3F; + ddr_phy->DENALI_PHY_2404_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2405_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2406_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2407_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2408_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2409_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2410_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2411_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2412_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2413_DATA = 0x00100700; + ddr_phy->DENALI_PHY_2414_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2415_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2416_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2417_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2418_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2419_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2420_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2423_DATA = 0x00000002; + ddr_phy->DENALI_PHY_2424_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2425_DATA = 0x0000000F; +} diff --git a/product/morello/module/dmc_bing/src/ddr_phy_values_800.c b/product/morello/module/dmc_bing/src/ddr_phy_values_800.c new file mode 100644 index 000000000..bb2d1b58f --- /dev/null +++ b/product/morello/module/dmc_bing/src/ddr_phy_values_800.c @@ -0,0 +1,1547 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Morello DDR-PHY register value configuration for 800MHz speed. + */ + +#include + +#include + +#include + +#include + +#include +#include + +static uint8_t PHY_WRITE_PATH_LAT_ADD_1600[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +static uint16_t PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[9] = { + 0x100, 0x100, 0x100, 0, 0, 0, 0x100, 0x100, 0 +}; +static uint8_t PHY_WRLVL_EARLY_FORCE_ZERO_1600[9] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; +static uint32_t PHY_PAD_VREF_CTRL_DQ_1600 = 0x1234; +static uint32_t VREF_TRAINING_CTRL_1600 = 0x00042520; +static uint16_t phy_dq_tsel_select_value = 0x9990; +static uint16_t phy_dqs_tsel_select_value = 0x9990; +static uint32_t phy_pad_data_drive_value = 0x2000073F; +static uint32_t phy_pad_clk_drive_value = 0x0006BF99; + +void ddr_phy_config_800( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info) +{ + fwk_assert((ddr_phy != NULL) && (info != NULL)); + + if (info->number_of_ranks == 1) { + PHY_PAD_VREF_CTRL_DQ_1600 = 0x1234; + } else { + PHY_PAD_VREF_CTRL_DQ_1600 = 0x1260; + } + + ddr_phy->DENALI_PHY_00_DATA = 0x76543210; + ddr_phy->DENALI_PHY_01_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_02_DATA = 0x00000000; + ddr_phy->DENALI_PHY_03_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_04_DATA = 0x00000000; + ddr_phy->DENALI_PHY_05_DATA = 0x00000000; + ddr_phy->DENALI_PHY_06_DATA = 0x00010000; + ddr_phy->DENALI_PHY_07_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_08_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_09_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_10_DATA = 0x00010000; + ddr_phy->DENALI_PHY_11_DATA = 0x00000000; + ddr_phy->DENALI_PHY_12_DATA = 0x00000000; + ddr_phy->DENALI_PHY_13_DATA = 0x01000100; + ddr_phy->DENALI_PHY_14_DATA = 0x00000000; + ddr_phy->DENALI_PHY_15_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_16_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_17_DATA = 0x00000008; + ddr_phy->DENALI_PHY_18_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_19_DATA = 0x00005555; + ddr_phy->DENALI_PHY_20_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_21_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_22_DATA = 0x00005656; + ddr_phy->DENALI_PHY_23_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_24_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_25_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_26_DATA = 0x00000000; + ddr_phy->DENALI_PHY_27_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_28_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_29_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_30_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_31_DATA = 0x00000000; + ddr_phy->DENALI_PHY_32_DATA = 0x04080000; + ddr_phy->DENALI_PHY_33_DATA = 0x08040400; + ddr_phy->DENALI_PHY_34_DATA = 0x00000004; + ddr_phy->DENALI_PHY_35_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_36_DATA = 0x00000000; + ddr_phy->DENALI_PHY_37_DATA = 0x00000000; + ddr_phy->DENALI_PHY_38_DATA = 0x00000000; + ddr_phy->DENALI_PHY_39_DATA = 0x00000000; + ddr_phy->DENALI_PHY_40_DATA = 0x00000000; + ddr_phy->DENALI_PHY_41_DATA = 0x00000000; + ddr_phy->DENALI_PHY_42_DATA = 0x00000000; + ddr_phy->DENALI_PHY_43_DATA = 0x00000000; + ddr_phy->DENALI_PHY_44_DATA = 0x00000000; + ddr_phy->DENALI_PHY_45_DATA = 0x00000000; + ddr_phy->DENALI_PHY_46_DATA = 0x00000000; + ddr_phy->DENALI_PHY_47_DATA = 0x00000000; + ddr_phy->DENALI_PHY_48_DATA = 0x00000000; + ddr_phy->DENALI_PHY_49_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_50_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_50_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_51_DATA = 0x00000000; + ddr_phy->DENALI_PHY_52_DATA = 0x00000000; + ddr_phy->DENALI_PHY_53_DATA = 0x00000000; + ddr_phy->DENALI_PHY_54_DATA = 0x00000000; + ddr_phy->DENALI_PHY_55_DATA = 0x20000004; + ddr_phy->DENALI_PHY_56_DATA = 0x00000000; + ddr_phy->DENALI_PHY_57_DATA = 0x00000000; + ddr_phy->DENALI_PHY_58_DATA = 0x00000000; + ddr_phy->DENALI_PHY_59_DATA = 0x00000000; + ddr_phy->DENALI_PHY_60_DATA = 0x00000000; + ddr_phy->DENALI_PHY_61_DATA = 0x00000000; + ddr_phy->DENALI_PHY_62_DATA = 0x00000000; + ddr_phy->DENALI_PHY_63_DATA = 0x00000000; + ddr_phy->DENALI_PHY_64_DATA = 0x00000000; + ddr_phy->DENALI_PHY_65_DATA = 0x00000000; + ddr_phy->DENALI_PHY_66_DATA = 0x00000000; + ddr_phy->DENALI_PHY_67_DATA = 0x00000000; + ddr_phy->DENALI_PHY_68_DATA = 0x00000000; + ddr_phy->DENALI_PHY_69_DATA = 0x00000000; + ddr_phy->DENALI_PHY_70_DATA = 0x00000000; + ddr_phy->DENALI_PHY_71_DATA = 0x00000000; + ddr_phy->DENALI_PHY_72_DATA = 0x00000000; + ddr_phy->DENALI_PHY_73_DATA = 0x00000000; + ddr_phy->DENALI_PHY_74_DATA = 0x00000000; + ddr_phy->DENALI_PHY_75_DATA = 0x00000000; + ddr_phy->DENALI_PHY_76_DATA = 0x00000000; + ddr_phy->DENALI_PHY_77_DATA = 0x00000000; + ddr_phy->DENALI_PHY_78_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_79_DATA = 0x00000000; + ddr_phy->DENALI_PHY_80_DATA = 0x00000000; + ddr_phy->DENALI_PHY_81_DATA = 0x04000000; + ddr_phy->DENALI_PHY_82_DATA = 0x02800280; + ddr_phy->DENALI_PHY_83_DATA = 0x02800280; + ddr_phy->DENALI_PHY_84_DATA = 0x02800280; + ddr_phy->DENALI_PHY_85_DATA = 0x02800280; + ddr_phy->DENALI_PHY_86_DATA = 0x00000280; + ddr_phy->DENALI_PHY_87_DATA = 0x00000000; + ddr_phy->DENALI_PHY_88_DATA = 0x00000000; + ddr_phy->DENALI_PHY_89_DATA = 0x00000000; + ddr_phy->DENALI_PHY_90_DATA = 0x00000000; + ddr_phy->DENALI_PHY_91_DATA = 0x00000000; + ddr_phy->DENALI_PHY_92_DATA = 0x00800080; + ddr_phy->DENALI_PHY_93_DATA = 0x00800080; + ddr_phy->DENALI_PHY_94_DATA = 0x00800080; + ddr_phy->DENALI_PHY_95_DATA = 0x00800080; + ddr_phy->DENALI_PHY_96_DATA = 0x00800080; + ddr_phy->DENALI_PHY_97_DATA = 0x00800080; + ddr_phy->DENALI_PHY_98_DATA = 0x00800080; + ddr_phy->DENALI_PHY_99_DATA = 0x00800080; + ddr_phy->DENALI_PHY_100_DATA = 0x00800080; + ddr_phy->DENALI_PHY_101_DATA = 0x00800080; + ddr_phy->DENALI_PHY_102_DATA = 0x00800080; + ddr_phy->DENALI_PHY_103_DATA = 0x00800080; + ddr_phy->DENALI_PHY_104_DATA = 0x00800080; + ddr_phy->DENALI_PHY_105_DATA = 0x00800080; + ddr_phy->DENALI_PHY_106_DATA = 0x00800080; + ddr_phy->DENALI_PHY_107_DATA = 0x00800080; + ddr_phy->DENALI_PHY_108_DATA = 0x00800080; + ddr_phy->DENALI_PHY_109_DATA = 0x00800080; + ddr_phy->DENALI_PHY_110_DATA = 0x10040001; + ddr_phy->DENALI_PHY_111_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_112_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_113_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_114_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[0]); + ddr_phy->DENALI_PHY_115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_116_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_117_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_118_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[0]); + ddr_phy->DENALI_PHY_119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_120_DATA = 0x00800802; + ddr_phy->DENALI_PHY_121_DATA = 0x00081020; + ddr_phy->DENALI_PHY_122_DATA = 0x04010000; + ddr_phy->DENALI_PHY_123_DATA = 0x61314042; + ddr_phy->DENALI_PHY_124_DATA = 0x00314000; + ddr_phy->DENALI_PHY_125_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_126_DATA = 0x03000080; + ddr_phy->DENALI_PHY_127_DATA = 0x00000200; + ddr_phy->DENALI_PHY_128_DATA = 0x42100010; + ddr_phy->DENALI_PHY_129_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_130_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_131_DATA = 0x40420100; + ddr_phy->DENALI_PHY_132_DATA = 0x40518031; + ddr_phy->DENALI_PHY_133_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_134_DATA = 0x00000233; + ddr_phy->DENALI_PHY_135_DATA = 0x00000203; + ddr_phy->DENALI_PHY_136_DATA = 0x03000100; + ddr_phy->DENALI_PHY_137_DATA = 0x20202000; + ddr_phy->DENALI_PHY_138_DATA = 0x20202020; + ddr_phy->DENALI_PHY_139_DATA = 0x80202020; + ddr_phy->DENALI_PHY_140_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_141_DATA = 0x00000000; + ddr_phy->DENALI_PHY_142_DATA = 0x00000000; + ddr_phy->DENALI_PHY_256_DATA = 0x76543210; + ddr_phy->DENALI_PHY_257_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_258_DATA = 0x00000000; + ddr_phy->DENALI_PHY_259_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_260_DATA = 0x00000000; + ddr_phy->DENALI_PHY_261_DATA = 0x00000000; + ddr_phy->DENALI_PHY_262_DATA = 0x00010000; + ddr_phy->DENALI_PHY_263_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_264_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_265_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_266_DATA = 0x00010000; + ddr_phy->DENALI_PHY_267_DATA = 0x00000000; + ddr_phy->DENALI_PHY_268_DATA = 0x00000000; + ddr_phy->DENALI_PHY_269_DATA = 0x01000100; + ddr_phy->DENALI_PHY_270_DATA = 0x00000000; + ddr_phy->DENALI_PHY_271_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_272_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_273_DATA = 0x00000008; + ddr_phy->DENALI_PHY_274_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_275_DATA = 0x00005555; + ddr_phy->DENALI_PHY_276_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_277_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_278_DATA = 0x00005656; + ddr_phy->DENALI_PHY_279_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_280_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_281_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_283_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_284_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_285_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_286_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_287_DATA = 0x00000000; + ddr_phy->DENALI_PHY_288_DATA = 0x04080000; + ddr_phy->DENALI_PHY_289_DATA = 0x08040400; + ddr_phy->DENALI_PHY_290_DATA = 0x00000004; + ddr_phy->DENALI_PHY_291_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_293_DATA = 0x00000000; + ddr_phy->DENALI_PHY_294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_295_DATA = 0x00000000; + ddr_phy->DENALI_PHY_296_DATA = 0x00000000; + ddr_phy->DENALI_PHY_297_DATA = 0x00000000; + ddr_phy->DENALI_PHY_298_DATA = 0x00000000; + ddr_phy->DENALI_PHY_299_DATA = 0x00000000; + ddr_phy->DENALI_PHY_300_DATA = 0x00000000; + ddr_phy->DENALI_PHY_301_DATA = 0x00000000; + ddr_phy->DENALI_PHY_302_DATA = 0x00000000; + ddr_phy->DENALI_PHY_303_DATA = 0x00000000; + ddr_phy->DENALI_PHY_304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_305_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_306_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_306_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_309_DATA = 0x00000000; + ddr_phy->DENALI_PHY_310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_311_DATA = 0x20000004; + ddr_phy->DENALI_PHY_312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_313_DATA = 0x00000000; + ddr_phy->DENALI_PHY_314_DATA = 0x00000000; + ddr_phy->DENALI_PHY_315_DATA = 0x00000000; + ddr_phy->DENALI_PHY_316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_329_DATA = 0x00000000; + ddr_phy->DENALI_PHY_330_DATA = 0x00000000; + ddr_phy->DENALI_PHY_331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_334_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_335_DATA = 0x00000000; + ddr_phy->DENALI_PHY_336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_337_DATA = 0x04000000; + ddr_phy->DENALI_PHY_338_DATA = 0x02800280; + ddr_phy->DENALI_PHY_339_DATA = 0x02800280; + ddr_phy->DENALI_PHY_340_DATA = 0x02800280; + ddr_phy->DENALI_PHY_341_DATA = 0x02800280; + ddr_phy->DENALI_PHY_342_DATA = 0x00000280; + ddr_phy->DENALI_PHY_343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_348_DATA = 0x00800080; + ddr_phy->DENALI_PHY_349_DATA = 0x00800080; + ddr_phy->DENALI_PHY_350_DATA = 0x00800080; + ddr_phy->DENALI_PHY_351_DATA = 0x00800080; + ddr_phy->DENALI_PHY_352_DATA = 0x00800080; + ddr_phy->DENALI_PHY_353_DATA = 0x00800080; + ddr_phy->DENALI_PHY_354_DATA = 0x00800080; + ddr_phy->DENALI_PHY_355_DATA = 0x00800080; + ddr_phy->DENALI_PHY_356_DATA = 0x00800080; + ddr_phy->DENALI_PHY_357_DATA = 0x00800080; + ddr_phy->DENALI_PHY_358_DATA = 0x00800080; + ddr_phy->DENALI_PHY_359_DATA = 0x00800080; + ddr_phy->DENALI_PHY_360_DATA = 0x00800080; + ddr_phy->DENALI_PHY_361_DATA = 0x00800080; + ddr_phy->DENALI_PHY_362_DATA = 0x00800080; + ddr_phy->DENALI_PHY_363_DATA = 0x00800080; + ddr_phy->DENALI_PHY_364_DATA = 0x00800080; + ddr_phy->DENALI_PHY_365_DATA = 0x00800080; + ddr_phy->DENALI_PHY_366_DATA = 0x10040001; + ddr_phy->DENALI_PHY_367_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_368_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_369_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_370_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[1]); + ddr_phy->DENALI_PHY_371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_372_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_373_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_374_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[1]); + ddr_phy->DENALI_PHY_375_DATA = 0x00000000; + ddr_phy->DENALI_PHY_376_DATA = 0x00800802; + ddr_phy->DENALI_PHY_377_DATA = 0x00081020; + ddr_phy->DENALI_PHY_378_DATA = 0x04010000; + ddr_phy->DENALI_PHY_379_DATA = 0x61314042; + ddr_phy->DENALI_PHY_380_DATA = 0x00314000; + ddr_phy->DENALI_PHY_381_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_382_DATA = 0x03000080; + ddr_phy->DENALI_PHY_383_DATA = 0x00000200; + ddr_phy->DENALI_PHY_384_DATA = 0x42100010; + ddr_phy->DENALI_PHY_385_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_386_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_387_DATA = 0x40420100; + ddr_phy->DENALI_PHY_388_DATA = 0x40518031; + ddr_phy->DENALI_PHY_389_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_390_DATA = 0x00000233; + ddr_phy->DENALI_PHY_391_DATA = 0x00000203; + ddr_phy->DENALI_PHY_392_DATA = 0x03000100; + ddr_phy->DENALI_PHY_393_DATA = 0x20202000; + ddr_phy->DENALI_PHY_394_DATA = 0x20202020; + ddr_phy->DENALI_PHY_395_DATA = 0x80202020; + ddr_phy->DENALI_PHY_396_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_397_DATA = 0x00000000; + ddr_phy->DENALI_PHY_398_DATA = 0x00000000; + ddr_phy->DENALI_PHY_512_DATA = 0x76543210; + ddr_phy->DENALI_PHY_513_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_514_DATA = 0x00000000; + ddr_phy->DENALI_PHY_515_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_516_DATA = 0x00000000; + ddr_phy->DENALI_PHY_517_DATA = 0x00000000; + ddr_phy->DENALI_PHY_518_DATA = 0x00010000; + ddr_phy->DENALI_PHY_519_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_520_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_521_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_522_DATA = 0x00010000; + ddr_phy->DENALI_PHY_523_DATA = 0x00000000; + ddr_phy->DENALI_PHY_524_DATA = 0x00000000; + ddr_phy->DENALI_PHY_525_DATA = 0x01000100; + ddr_phy->DENALI_PHY_526_DATA = 0x00000000; + ddr_phy->DENALI_PHY_527_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_528_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_529_DATA = 0x00000008; + ddr_phy->DENALI_PHY_530_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_531_DATA = 0x00005555; + ddr_phy->DENALI_PHY_532_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_533_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_534_DATA = 0x00005656; + ddr_phy->DENALI_PHY_535_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_536_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_537_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_539_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_540_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_541_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_542_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_543_DATA = 0x00000000; + ddr_phy->DENALI_PHY_544_DATA = 0x04080000; + ddr_phy->DENALI_PHY_545_DATA = 0x08040400; + ddr_phy->DENALI_PHY_546_DATA = 0x00000004; + ddr_phy->DENALI_PHY_547_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_549_DATA = 0x00000000; + ddr_phy->DENALI_PHY_550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_551_DATA = 0x00000000; + ddr_phy->DENALI_PHY_552_DATA = 0x00000000; + ddr_phy->DENALI_PHY_553_DATA = 0x00000000; + ddr_phy->DENALI_PHY_554_DATA = 0x00000000; + ddr_phy->DENALI_PHY_555_DATA = 0x00000000; + ddr_phy->DENALI_PHY_556_DATA = 0x00000000; + ddr_phy->DENALI_PHY_557_DATA = 0x00000000; + ddr_phy->DENALI_PHY_558_DATA = 0x00000000; + ddr_phy->DENALI_PHY_559_DATA = 0x00000000; + ddr_phy->DENALI_PHY_560_DATA = 0x00000000; + ddr_phy->DENALI_PHY_561_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_562_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_562_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_563_DATA = 0x00000000; + ddr_phy->DENALI_PHY_564_DATA = 0x00000000; + ddr_phy->DENALI_PHY_565_DATA = 0x00000000; + ddr_phy->DENALI_PHY_566_DATA = 0x00000000; + ddr_phy->DENALI_PHY_567_DATA = 0x20000004; + ddr_phy->DENALI_PHY_568_DATA = 0x00000000; + ddr_phy->DENALI_PHY_569_DATA = 0x00000000; + ddr_phy->DENALI_PHY_570_DATA = 0x00000000; + ddr_phy->DENALI_PHY_571_DATA = 0x00000000; + ddr_phy->DENALI_PHY_572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_585_DATA = 0x00000000; + ddr_phy->DENALI_PHY_586_DATA = 0x00000000; + ddr_phy->DENALI_PHY_587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_590_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_591_DATA = 0x00000000; + ddr_phy->DENALI_PHY_592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_593_DATA = 0x04000000; + ddr_phy->DENALI_PHY_594_DATA = 0x02800280; + ddr_phy->DENALI_PHY_595_DATA = 0x02800280; + ddr_phy->DENALI_PHY_596_DATA = 0x02800280; + ddr_phy->DENALI_PHY_597_DATA = 0x02800280; + ddr_phy->DENALI_PHY_598_DATA = 0x00000280; + ddr_phy->DENALI_PHY_599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_604_DATA = 0x00800080; + ddr_phy->DENALI_PHY_605_DATA = 0x00800080; + ddr_phy->DENALI_PHY_606_DATA = 0x00800080; + ddr_phy->DENALI_PHY_607_DATA = 0x00800080; + ddr_phy->DENALI_PHY_608_DATA = 0x00800080; + ddr_phy->DENALI_PHY_609_DATA = 0x00800080; + ddr_phy->DENALI_PHY_610_DATA = 0x00800080; + ddr_phy->DENALI_PHY_611_DATA = 0x00800080; + ddr_phy->DENALI_PHY_612_DATA = 0x00800080; + ddr_phy->DENALI_PHY_613_DATA = 0x00800080; + ddr_phy->DENALI_PHY_614_DATA = 0x00800080; + ddr_phy->DENALI_PHY_615_DATA = 0x00800080; + ddr_phy->DENALI_PHY_616_DATA = 0x00800080; + ddr_phy->DENALI_PHY_617_DATA = 0x00800080; + ddr_phy->DENALI_PHY_618_DATA = 0x00800080; + ddr_phy->DENALI_PHY_619_DATA = 0x00800080; + ddr_phy->DENALI_PHY_620_DATA = 0x00800080; + ddr_phy->DENALI_PHY_621_DATA = 0x00800080; + ddr_phy->DENALI_PHY_622_DATA = 0x10040001; + ddr_phy->DENALI_PHY_623_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_624_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_625_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_626_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[2]); + ddr_phy->DENALI_PHY_627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_628_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_629_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_630_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[2]); + ddr_phy->DENALI_PHY_631_DATA = 0x00000000; + ddr_phy->DENALI_PHY_632_DATA = 0x00800802; + ddr_phy->DENALI_PHY_633_DATA = 0x00081020; + ddr_phy->DENALI_PHY_634_DATA = 0x04010000; + ddr_phy->DENALI_PHY_635_DATA = 0x61314042; + ddr_phy->DENALI_PHY_636_DATA = 0x00314000; + ddr_phy->DENALI_PHY_637_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_638_DATA = 0x03000080; + ddr_phy->DENALI_PHY_639_DATA = 0x00000200; + ddr_phy->DENALI_PHY_640_DATA = 0x42100010; + ddr_phy->DENALI_PHY_641_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_642_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_643_DATA = 0x40420100; + ddr_phy->DENALI_PHY_644_DATA = 0x40518031; + ddr_phy->DENALI_PHY_645_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_646_DATA = 0x00000233; + ddr_phy->DENALI_PHY_647_DATA = 0x00000203; + ddr_phy->DENALI_PHY_648_DATA = 0x03000100; + ddr_phy->DENALI_PHY_649_DATA = 0x20202000; + ddr_phy->DENALI_PHY_650_DATA = 0x20202020; + ddr_phy->DENALI_PHY_651_DATA = 0x80202020; + ddr_phy->DENALI_PHY_652_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_653_DATA = 0x00000000; + ddr_phy->DENALI_PHY_654_DATA = 0x00000000; + ddr_phy->DENALI_PHY_768_DATA = 0x76543210; + ddr_phy->DENALI_PHY_769_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_770_DATA = 0x00000000; + ddr_phy->DENALI_PHY_771_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_772_DATA = 0x00000000; + ddr_phy->DENALI_PHY_773_DATA = 0x00000000; + ddr_phy->DENALI_PHY_774_DATA = 0x00010000; + ddr_phy->DENALI_PHY_775_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_776_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_777_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_778_DATA = 0x00010000; + ddr_phy->DENALI_PHY_779_DATA = 0x00000000; + ddr_phy->DENALI_PHY_780_DATA = 0x00000000; + ddr_phy->DENALI_PHY_781_DATA = 0x01000100; + ddr_phy->DENALI_PHY_782_DATA = 0x00000000; + ddr_phy->DENALI_PHY_783_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_784_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_785_DATA = 0x00000008; + ddr_phy->DENALI_PHY_786_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_787_DATA = 0x00005555; + ddr_phy->DENALI_PHY_788_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_789_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_790_DATA = 0x00005656; + ddr_phy->DENALI_PHY_791_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_792_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_793_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_795_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_796_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_797_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_798_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_799_DATA = 0x00000000; + ddr_phy->DENALI_PHY_800_DATA = 0x04080000; + ddr_phy->DENALI_PHY_801_DATA = 0x08040400; + ddr_phy->DENALI_PHY_802_DATA = 0x00000004; + ddr_phy->DENALI_PHY_803_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_805_DATA = 0x00000000; + ddr_phy->DENALI_PHY_806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_807_DATA = 0x00000000; + ddr_phy->DENALI_PHY_808_DATA = 0x00000000; + ddr_phy->DENALI_PHY_809_DATA = 0x00000000; + ddr_phy->DENALI_PHY_810_DATA = 0x00000000; + ddr_phy->DENALI_PHY_811_DATA = 0x00000000; + ddr_phy->DENALI_PHY_812_DATA = 0x00000000; + ddr_phy->DENALI_PHY_813_DATA = 0x00000000; + ddr_phy->DENALI_PHY_814_DATA = 0x00000000; + ddr_phy->DENALI_PHY_815_DATA = 0x00000000; + ddr_phy->DENALI_PHY_816_DATA = 0x00000000; + ddr_phy->DENALI_PHY_817_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_818_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_818_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_819_DATA = 0x00000000; + ddr_phy->DENALI_PHY_820_DATA = 0x00000000; + ddr_phy->DENALI_PHY_821_DATA = 0x00000000; + ddr_phy->DENALI_PHY_822_DATA = 0x00000000; + ddr_phy->DENALI_PHY_823_DATA = 0x20000004; + ddr_phy->DENALI_PHY_824_DATA = 0x00000000; + ddr_phy->DENALI_PHY_825_DATA = 0x00000000; + ddr_phy->DENALI_PHY_826_DATA = 0x00000000; + ddr_phy->DENALI_PHY_827_DATA = 0x00000000; + ddr_phy->DENALI_PHY_828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_841_DATA = 0x00000000; + ddr_phy->DENALI_PHY_842_DATA = 0x00000000; + ddr_phy->DENALI_PHY_843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_846_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_847_DATA = 0x00000000; + ddr_phy->DENALI_PHY_848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_849_DATA = 0x04000000; + ddr_phy->DENALI_PHY_850_DATA = 0x02800280; + ddr_phy->DENALI_PHY_851_DATA = 0x02800280; + ddr_phy->DENALI_PHY_852_DATA = 0x02800280; + ddr_phy->DENALI_PHY_853_DATA = 0x02800280; + ddr_phy->DENALI_PHY_854_DATA = 0x00000280; + ddr_phy->DENALI_PHY_855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_860_DATA = 0x00800080; + ddr_phy->DENALI_PHY_861_DATA = 0x00800080; + ddr_phy->DENALI_PHY_862_DATA = 0x00800080; + ddr_phy->DENALI_PHY_863_DATA = 0x00800080; + ddr_phy->DENALI_PHY_864_DATA = 0x00800080; + ddr_phy->DENALI_PHY_865_DATA = 0x00800080; + ddr_phy->DENALI_PHY_866_DATA = 0x00800080; + ddr_phy->DENALI_PHY_867_DATA = 0x00800080; + ddr_phy->DENALI_PHY_868_DATA = 0x00800080; + ddr_phy->DENALI_PHY_869_DATA = 0x00800080; + ddr_phy->DENALI_PHY_870_DATA = 0x00800080; + ddr_phy->DENALI_PHY_871_DATA = 0x00800080; + ddr_phy->DENALI_PHY_872_DATA = 0x00800080; + ddr_phy->DENALI_PHY_873_DATA = 0x00800080; + ddr_phy->DENALI_PHY_874_DATA = 0x00800080; + ddr_phy->DENALI_PHY_875_DATA = 0x00800080; + ddr_phy->DENALI_PHY_876_DATA = 0x00800080; + ddr_phy->DENALI_PHY_877_DATA = 0x00800080; + ddr_phy->DENALI_PHY_878_DATA = 0x10040001; + ddr_phy->DENALI_PHY_879_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_880_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_881_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_882_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[3]); + ddr_phy->DENALI_PHY_883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_884_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_885_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_886_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[3]); + ddr_phy->DENALI_PHY_887_DATA = 0x00000000; + ddr_phy->DENALI_PHY_888_DATA = 0x00800802; + ddr_phy->DENALI_PHY_889_DATA = 0x00081020; + ddr_phy->DENALI_PHY_890_DATA = 0x04010000; + ddr_phy->DENALI_PHY_891_DATA = 0x61314042; + ddr_phy->DENALI_PHY_892_DATA = 0x00314000; + ddr_phy->DENALI_PHY_893_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_894_DATA = 0x03000080; + ddr_phy->DENALI_PHY_895_DATA = 0x00000200; + ddr_phy->DENALI_PHY_896_DATA = 0x42100010; + ddr_phy->DENALI_PHY_897_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_898_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_899_DATA = 0x40420100; + ddr_phy->DENALI_PHY_900_DATA = 0x40518031; + ddr_phy->DENALI_PHY_901_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_902_DATA = 0x00000233; + ddr_phy->DENALI_PHY_903_DATA = 0x00000203; + ddr_phy->DENALI_PHY_904_DATA = 0x03000100; + ddr_phy->DENALI_PHY_905_DATA = 0x20202000; + ddr_phy->DENALI_PHY_906_DATA = 0x20202020; + ddr_phy->DENALI_PHY_907_DATA = 0x80202020; + ddr_phy->DENALI_PHY_908_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_909_DATA = 0x00000000; + ddr_phy->DENALI_PHY_910_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1024_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1025_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1026_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1027_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1028_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1029_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1030_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1031_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1032_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1033_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1034_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1035_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1036_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1037_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1038_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1039_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1040_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1041_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1042_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1043_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1044_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1045_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1046_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1047_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1048_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1049_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1051_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1052_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1053_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1054_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1055_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1056_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1057_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1058_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1059_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1061_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1063_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1064_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1065_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1066_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1067_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1068_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1069_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1070_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1071_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1072_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1073_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1074_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1074_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1075_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1076_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1077_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1078_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1079_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1080_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1081_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1082_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1083_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1097_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1098_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1102_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1103_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1105_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1106_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1107_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1108_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1109_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1110_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1116_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1117_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1118_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1119_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1120_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1121_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1122_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1123_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1124_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1125_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1126_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1127_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1128_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1129_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1130_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1131_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1132_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1133_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1134_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1135_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1136_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1137_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[4] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1138_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[4]); + ddr_phy->DENALI_PHY_1139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1140_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1141_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[4] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1142_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[4]); + ddr_phy->DENALI_PHY_1143_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1144_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1145_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1146_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1147_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1148_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1149_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1150_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1151_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1152_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1153_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1154_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1155_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1156_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1157_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1158_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1159_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1160_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1161_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1162_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1163_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1164_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1165_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1166_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1280_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1281_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1283_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1284_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1285_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1286_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1287_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1288_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1289_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1290_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1291_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1293_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1295_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1296_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1297_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1298_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1299_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1300_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1301_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1302_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1303_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1304_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1305_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1307_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1308_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1309_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1310_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1312_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1313_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1314_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1315_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1329_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1330_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1330_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1334_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1335_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1337_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1338_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1339_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1340_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1341_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1342_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1348_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1349_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1350_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1351_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1352_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1353_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1354_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1355_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1356_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1357_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1358_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1359_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1360_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1361_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1362_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1363_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1364_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1365_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1366_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1367_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1368_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1369_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1370_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1372_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1373_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1374_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1375_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1376_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1377_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1378_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1379_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1380_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1381_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1382_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1383_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1384_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1385_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1386_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1387_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1388_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1389_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1390_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1391_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1392_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1393_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1394_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[5]); + ddr_phy->DENALI_PHY_1395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1396_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1397_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1398_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[5]); + ddr_phy->DENALI_PHY_1399_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1400_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1401_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1402_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1403_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1404_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1405_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1406_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1407_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1408_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1409_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1410_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1411_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1412_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1413_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1414_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1415_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1416_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1417_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1418_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1419_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1420_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1536_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1537_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1539_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1540_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1541_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1542_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1543_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1544_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1545_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1546_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1547_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1549_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1551_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1552_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1553_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1554_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1555_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1556_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1557_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1558_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1559_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1560_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1561_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1562_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1563_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1564_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1565_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1566_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1567_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1568_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1569_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1570_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1571_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1585_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1586_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1586_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1590_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1591_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1593_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1594_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1595_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1596_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1597_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1598_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1604_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1605_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1606_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1607_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1608_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1609_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1610_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1611_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1612_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1613_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1614_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1615_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1616_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1617_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1618_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1619_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1620_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1621_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1622_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1623_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1624_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1625_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1626_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1628_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1629_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1630_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1631_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1632_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1633_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1634_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1635_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1636_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1637_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1638_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1639_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1640_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1641_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1642_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1643_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1644_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1645_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1646_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1647_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1648_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1649_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1650_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[6]); + ddr_phy->DENALI_PHY_1651_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1652_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1653_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1654_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[6]); + ddr_phy->DENALI_PHY_1655_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1656_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1657_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1658_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1659_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1660_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1661_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1662_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1663_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1664_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1665_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1666_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1667_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1668_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1669_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1670_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1671_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1672_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1673_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1674_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1675_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1676_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1677_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1678_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1792_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1793_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1795_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1796_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1797_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1798_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1799_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1800_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1801_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1802_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1803_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1805_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1807_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_1808_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1809_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1810_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1811_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1812_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1813_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1814_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1815_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1816_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1817_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1818_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1819_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1820_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1821_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1822_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_1823_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1824_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1825_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1826_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1827_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1841_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1842_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1842_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1846_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1847_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1849_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1850_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1851_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1852_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1853_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1854_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1860_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1861_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1862_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1863_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1864_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1865_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1866_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1867_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1868_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1869_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1870_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1871_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1872_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1873_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1874_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1875_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1876_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1877_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1878_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1879_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1880_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1881_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1882_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1884_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1885_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1886_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1887_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1888_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1889_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1890_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1891_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1892_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1893_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1894_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1895_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1896_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1897_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1898_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1899_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1900_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1901_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1902_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1903_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1904_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1905_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1906_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[7]); + ddr_phy->DENALI_PHY_1907_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1908_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1909_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1910_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[7]); + ddr_phy->DENALI_PHY_1911_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1912_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1913_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1914_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1915_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1916_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1917_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1918_DATA = 0x03000080; + ddr_phy->DENALI_PHY_1919_DATA = 0x00000200; + ddr_phy->DENALI_PHY_1920_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1921_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1922_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1923_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1924_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1925_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1926_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1927_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1928_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1929_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1930_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1931_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1932_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1933_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1934_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2048_DATA = 0x76543210; + ddr_phy->DENALI_PHY_2049_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_2050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2051_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_2052_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2053_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2054_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2055_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_2056_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_2057_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_2058_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2059_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2061_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2063_DATA = VREF_TRAINING_CTRL_1600; + ddr_phy->DENALI_PHY_2064_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_2065_DATA = 0x00000008; + ddr_phy->DENALI_PHY_2066_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_2067_DATA = 0x00005555; + ddr_phy->DENALI_PHY_2068_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2069_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_2070_DATA = 0x00005656; + ddr_phy->DENALI_PHY_2071_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2072_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2073_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2074_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2075_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_2076_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_2077_DATA = (PHY_PAD_VREF_CTRL_DQ_1600 << 16) | 0x0000; + ddr_phy->DENALI_PHY_2078_DATA = PHY_PAD_VREF_CTRL_DQ_1600; + ddr_phy->DENALI_PHY_2079_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2080_DATA = 0x04080000; + ddr_phy->DENALI_PHY_2081_DATA = 0x08040400; + ddr_phy->DENALI_PHY_2082_DATA = 0x00000004; + ddr_phy->DENALI_PHY_2083_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_2084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2097_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_2098_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_2098_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_2099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2102_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2103_DATA = 0x20000004; + ddr_phy->DENALI_PHY_2104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2105_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2106_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2107_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2108_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2109_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2110_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2116_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2117_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2118_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2120_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2121_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2122_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2123_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2124_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2125_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2126_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_2127_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2128_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2129_DATA = 0x04000000; + ddr_phy->DENALI_PHY_2130_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2131_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2132_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2133_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2134_DATA = 0x00000280; + ddr_phy->DENALI_PHY_2135_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2136_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2137_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2138_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2140_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2141_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2142_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2143_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2144_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2145_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2146_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2147_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2148_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2149_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2150_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2151_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2152_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2153_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2154_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2155_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2156_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2157_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2158_DATA = 0x10040001; + ddr_phy->DENALI_PHY_2159_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_2160_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2161_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2162_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[8]); + ddr_phy->DENALI_PHY_2163_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2164_DATA = + (PHY_WRITE_PATH_LAT_ADD_1600[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2165_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1600[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2166_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_1600[8]); + ddr_phy->DENALI_PHY_2167_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2168_DATA = 0x00800802; + ddr_phy->DENALI_PHY_2169_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2170_DATA = 0x04010000; + ddr_phy->DENALI_PHY_2171_DATA = 0x61314042; + ddr_phy->DENALI_PHY_2172_DATA = 0x00314000; + ddr_phy->DENALI_PHY_2173_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_2174_DATA = 0x03000080; + ddr_phy->DENALI_PHY_2175_DATA = 0x00000200; + ddr_phy->DENALI_PHY_2176_DATA = 0x42100010; + ddr_phy->DENALI_PHY_2177_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_2178_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_2179_DATA = 0x40420100; + ddr_phy->DENALI_PHY_2180_DATA = 0x40518031; + ddr_phy->DENALI_PHY_2181_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_2182_DATA = 0x00000233; + ddr_phy->DENALI_PHY_2183_DATA = 0x00000203; + ddr_phy->DENALI_PHY_2184_DATA = 0x03000100; + ddr_phy->DENALI_PHY_2185_DATA = 0x20202000; + ddr_phy->DENALI_PHY_2186_DATA = 0x20202020; + ddr_phy->DENALI_PHY_2187_DATA = 0x80202020; + ddr_phy->DENALI_PHY_2188_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_2189_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2190_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2305_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2309_DATA = 0x00050000; + ddr_phy->DENALI_PHY_2310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2313_DATA = 0x02010000; + ddr_phy->DENALI_PHY_2314_DATA = 0x00008008; + ddr_phy->DENALI_PHY_2315_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2320_DATA = 0x00010100; + ddr_phy->DENALI_PHY_2321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2327_DATA = 0x64000000; + ddr_phy->DENALI_PHY_2328_DATA = 0x00000050; + ddr_phy->DENALI_PHY_2329_DATA = 0x014A114A; + ddr_phy->DENALI_PHY_2330_DATA = 0x0000014A; + ddr_phy->DENALI_PHY_2331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2332_DATA = 0x00163F00; + ddr_phy->DENALI_PHY_2333_DATA = 0x42080010; + ddr_phy->DENALI_PHY_2334_DATA = 0x0100003E; + ddr_phy->DENALI_PHY_2335_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2336_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2337_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2338_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2339_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2340_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2341_DATA = 0x80002020; + ddr_phy->DENALI_PHY_2342_DATA = 0x00124924; + ddr_phy->DENALI_PHY_2343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2347_DATA = 0x070A0707; + ddr_phy->DENALI_PHY_2348_DATA = 0x00005400; + ddr_phy->DENALI_PHY_2349_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2350_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2351_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2352_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2353_DATA = phy_pad_data_drive_value; + ddr_phy->DENALI_PHY_2354_DATA = 0x0000073F; + ddr_phy->DENALI_PHY_2355_DATA = 0x0006BF00; + ddr_phy->DENALI_PHY_2356_DATA = 0x013200E0; + ddr_phy->DENALI_PHY_2357_DATA = phy_pad_clk_drive_value; + ddr_phy->DENALI_PHY_2358_DATA = 0x00007000; + ddr_phy->DENALI_PHY_2359_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2360_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2361_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2362_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2363_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2364_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2365_DATA = 0x00073F10; + ddr_phy->DENALI_PHY_2366_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2367_DATA = 0x00024410; + ddr_phy->DENALI_PHY_2368_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2369_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2370_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2371_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2372_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2373_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2374_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2375_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2376_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2377_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2378_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2379_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2380_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2381_DATA = 0x04102089; + ddr_phy->DENALI_PHY_2382_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2383_DATA = 0x00020011; + ddr_phy->DENALI_PHY_2384_DATA = 0x00021000; + ddr_phy->DENALI_PHY_2385_DATA = 0x00000448; + ddr_phy->DENALI_PHY_2386_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2387_DATA = 0x04000408; + ddr_phy->DENALI_PHY_2388_DATA = 0x00000020; + ddr_phy->DENALI_PHY_2389_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2390_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2391_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2392_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2393_DATA = 0x03000000; + ddr_phy->DENALI_PHY_2394_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2396_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2397_DATA = 0x04102035; + ddr_phy->DENALI_PHY_2398_DATA = 0x00041020; + ddr_phy->DENALI_PHY_2399_DATA = 0x01C98C98; + ddr_phy->DENALI_PHY_2400_DATA = 0x3F400000; + ddr_phy->DENALI_PHY_2401_DATA = 0x3F3F1F3F; + ddr_phy->DENALI_PHY_2402_DATA = 0x1F3F3F1F; + ddr_phy->DENALI_PHY_2403_DATA = 0x001F3F3F; + ddr_phy->DENALI_PHY_2404_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2405_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2406_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2407_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2408_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2409_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2410_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2411_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2412_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2413_DATA = 0x00040700; + ddr_phy->DENALI_PHY_2414_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2415_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2416_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2417_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2418_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2419_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2420_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2423_DATA = 0x00000002; + ddr_phy->DENALI_PHY_2424_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2425_DATA = 0x0000000F; +} diff --git a/product/morello/module/dmc_bing/src/dimm_spd.c b/product/morello/module/dmc_bing/src/dimm_spd.c new file mode 100644 index 000000000..fbacb9054 --- /dev/null +++ b/product/morello/module/dmc_bing/src/dimm_spd.c @@ -0,0 +1,880 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static bool multi_rank; +static float t_refi = .0000078; +static uint32_t dmc_clk_freq; +static float dmc_clk_period; +static float dmc_clk_period_ps; + +struct ddr4_spd ddr4_dimm0; +struct ddr4_spd ddr4_dimm1; + +/* + * Internal APIs used by SPD functions + */ + +static int spd_read( + struct mod_cdns_i2c_master_api_polled *i2c_api, + int address, + uint8_t *spd_data) +{ + char data[2] = { 0 }; + int i; + int status; + + status = i2c_api->write( + (FWK_ID_ELEMENT(FWK_MODULE_IDX_CDNS_I2C, 0)), + WRITE_PAGE0, + data, + SPD_W_TRANSFER_SIZE, + SPD_STOP); + if (status != FWK_SUCCESS) { + return status; + } + + for (i = SPD_PAGE0_START; i <= MAX_SPD_PAGE0; i++) { + status = i2c_api->read( + (FWK_ID_ELEMENT(FWK_MODULE_IDX_CDNS_I2C, 0)), + address, + (char *)&spd_data[i], + SPD_R_TRANSFER_SIZE); + if (status != FWK_SUCCESS) { + return status; + } + } + + status = i2c_api->write( + (FWK_ID_ELEMENT(FWK_MODULE_IDX_CDNS_I2C, 0)), + WRITE_PAGE1, + data, + SPD_W_TRANSFER_SIZE, + SPD_STOP); + if (status != FWK_SUCCESS) { + return status; + } + + for (i = SPD_PAGE1_START; i <= MAX_SPD_PAGE1; i++) { + status = i2c_api->read( + (FWK_ID_ELEMENT(FWK_MODULE_IDX_CDNS_I2C, 0)), + address, + (char *)&spd_data[i], + SPD_R_TRANSFER_SIZE); + if (status != FWK_SUCCESS) { + return status; + } + } + + return FWK_SUCCESS; +} + +static int chk_ddr4_dimms( + unsigned int speed, + struct ddr4_spd *dimm0, + struct ddr4_spd *dimm1) +{ + int status = FWK_SUCCESS; + uint8_t *dimm0_dram_param; + uint8_t *dimm1_dram_param; + + fwk_assert((dimm0 != NULL) && (dimm1 != NULL)); + + dimm0_dram_param = (uint8_t *)dimm0; + dimm1_dram_param = (uint8_t *)dimm1; + + if (memcmp(dimm0_dram_param, dimm1_dram_param, 125) != 0) { + return FWK_E_DATA; + } + + switch (speed) { + case 800: + if ((dimm0_dram_param[18] > 0x0A) || (dimm1_dram_param[18] > 0x0A)) { + status = FWK_E_DATA; + } + break; + case 1200: + if ((dimm0_dram_param[18] > 0x07) || (dimm1_dram_param[18] > 0x07)) { + status = FWK_E_DATA; + } + break; + case 1333: + if ((dimm0_dram_param[18] > 0x06) || (dimm1_dram_param[18] > 0x06)) { + status = FWK_E_DATA; + } + break; + default: + fwk_unexpected(); + break; + } + + return status; +} + +static void dimm_device_data(uint8_t *spd_data, uint8_t dimm_id) +{ + unsigned int i, j; + char part_num[20]; + + (void)part_num; + + if (spd_data[2] == 0x0C) { + FWK_LOG_INFO(" DIMM %d information:", dimm_id); + FWK_LOG_INFO( + " Manufacturer ID = 0x%x 0x%x", spd_data[320], spd_data[321]); + + j = 0; + for (i = 329; i <= 348; i++) { + part_num[j++] = spd_data[i]; + } + + FWK_LOG_INFO(" Module part number = %s", part_num); + + FWK_LOG_INFO( + " Module serial number = 0x%x 0x%x 0x%x 0x%x", + spd_data[325], + spd_data[326], + spd_data[327], + spd_data[328]); + + FWK_LOG_INFO( + " Module manufacturing week %d%d year %d%d", + 0xF & (spd_data[324] >> 4), + 0xF & spd_data[324], + 0xF & (spd_data[323] >> 4), + 0xF & spd_data[323]); + } else { + FWK_LOG_ERR("[DDR] ERROR! DDR4 SPD EEPROM Not Detected"); + fwk_unexpected(); + } +} + +static int get_dimm_rank_bits( + uint8_t element, + uint32_t *temp_reg, + struct dimm_info *ddr) +{ + int status; + uint8_t pkg_rank = + (element & SPD_PKG_RANK_BITS_MASK) >> SPD_PKG_RANK_BITS_OFFSET; + + *temp_reg &= ~RANK_BITS_NEXT_MASK; + + switch (pkg_rank) { + case SPD_PKG_RANK1: + *temp_reg |= RANK_BITS_NEXT_0; + multi_rank = false; + ddr->ranks_to_train = 0x01; + ddr->number_of_ranks = 1; + status = FWK_SUCCESS; + break; + case SPD_PKG_RANK2: + *temp_reg |= RANK_BITS_NEXT_1; + multi_rank = true; + ddr->ranks_to_train = 0x03; + ddr->number_of_ranks = 2; + status = FWK_SUCCESS; + break; + case SPD_PKG_RANK4: + *temp_reg |= RANK_BITS_NEXT_2; + multi_rank = true; + ddr->ranks_to_train = 0x0F; + ddr->number_of_ranks = 4; + status = FWK_SUCCESS; + break; + case SPD_PKG_RANK8: + *temp_reg |= RANK_BITS_NEXT_3; + multi_rank = true; + ddr->ranks_to_train = 0xFF; + ddr->number_of_ranks = 8; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_col_bits(uint8_t element, uint32_t *temp_reg) +{ + int status; + *temp_reg &= ~COL_BITS_NEXT_MASK; + + switch ((element & SPD_COL_ADDR_BITS_MASK)) { + case SPD_COL_ADDR_BITS_10: + *temp_reg |= COL_BITS_NEXT_10_BITS; + status = FWK_SUCCESS; + break; + case SPD_COL_ADDR_BITS_11: + *temp_reg |= COL_BITS_NEXT_11_BITS; + status = FWK_SUCCESS; + break; + case SPD_COL_ADDR_BITS_12: + *temp_reg |= COL_BITS_NEXT_12_BITS; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_row_bits(uint8_t element, uint32_t *temp_reg) +{ + int status; + *temp_reg &= ~ROW_BITS_NEXT_MASK; + + switch ((element & SPD_ROW_ADDR_BITS_MASK)) { + case SPD_ROW_ADDR_BITS_12: + *temp_reg |= ROW_BITS_NEXT_12_BITS; + status = FWK_SUCCESS; + break; + case SPD_ROW_ADDR_BITS_13: + *temp_reg |= ROW_BITS_NEXT_13_BITS; + status = FWK_SUCCESS; + break; + case SPD_ROW_ADDR_BITS_14: + *temp_reg |= ROW_BITS_NEXT_14_BITS; + status = FWK_SUCCESS; + break; + case SPD_ROW_ADDR_BITS_15: + *temp_reg |= ROW_BITS_NEXT_15_BITS; + status = FWK_SUCCESS; + break; + case SPD_ROW_ADDR_BITS_16: + *temp_reg |= ROW_BITS_NEXT_16_BITS; + status = FWK_SUCCESS; + break; + case SPD_ROW_ADDR_BITS_17: + *temp_reg |= ROW_BITS_NEXT_17_BITS; + status = FWK_SUCCESS; + break; + case SPD_ROW_ADDR_BITS_18: + *temp_reg |= ROW_BITS_NEXT_18_BITS; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_bank_addr_grp_bits(uint8_t element, uint32_t *temp_reg) +{ + int status; + uint8_t bank_addr = element & SPD_BANK_BITS_MASK; + uint8_t bank_group = element & SPD_BANK_GROUP_BITS_MASK; + + *temp_reg &= ~BANK_BITS_NEXT_MASK; + + switch (bank_group) { + case SPD_BANK_GROUP_BITS_0: + switch (bank_addr) { + case SPD_BANK_BITS_3: + *temp_reg |= BANK_BITS_NEXT_8_BANKS; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + break; + case SPD_BANK_GROUP_BITS_2: + switch (bank_addr) { + case SPD_BANK_BITS_2: + *temp_reg |= BANK_BITS_NEXT_8_BANKS; + status = FWK_SUCCESS; + break; + case SPD_BANK_BITS_3: + *temp_reg |= BANK_BITS_NEXT_16_BANKS; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + break; + case SPD_BANK_GROUP_BITS_4: + switch (bank_addr) { + case SPD_BANK_BITS_2: + *temp_reg |= BANK_BITS_NEXT_16_BANKS; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_memory_device_width_next_bits( + uint8_t element, + uint32_t *temp_reg, + struct dimm_info *ddr) +{ + int status; + uint8_t sdram_device_width = (element & SDRAM_DEVICE_WIDTH_MASK); + + *temp_reg &= ~MEM_DEV_WIDTH_NEXT_MASK; + + switch (sdram_device_width) { + case SDRAM_DEVICE_WIDTH_0: + *temp_reg |= MEM_DEV_WIDTH_NEXT_4; + ddr->dimm_mem_width = 4; + status = FWK_SUCCESS; + break; + case SDRAM_DEVICE_WIDTH_1: + *temp_reg |= MEM_DEV_WIDTH_NEXT_8; + ddr->dimm_mem_width = 8; + status = FWK_SUCCESS; + break; + case SDRAM_DEVICE_WIDTH_2: + *temp_reg |= MEM_DEV_WIDTH_NEXT_16; + ddr->dimm_mem_width = 16; + status = FWK_SUCCESS; + break; + default: + ddr->dimm_mem_width = 0; + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_cid_bits(uint8_t element, uint32_t *temp_reg) +{ + int status; + uint8_t pkg_type = element & SPD_PKG_TYPE_BITS_MASK; + uint8_t die_cnt = element & SPD_DIE_CNT_BITS_MASK; + uint8_t sig_ld = element & SPD_SIG_LOAD_BITS_MASK; + + *temp_reg &= ~CID_BITS_NEXT_MASK; + + switch (pkg_type) { + case SPD_PKG_TYPE_BITS_0: + switch (die_cnt) { + case SPD_DIE_CNT_BITS_0: + switch (sig_ld) { + case SPD_SIG_LOAD_BITS_0: + status = FWK_SUCCESS; + *temp_reg |= CID_BITS_NEXT_0_CID; + break; + default: + status = FWK_E_PARAM; + break; + } + break; + default: + status = FWK_E_PARAM; + break; + } + break; + case SPD_PKG_TYPE_BITS_1: + switch (sig_ld) { + case SPD_SIG_LOAD_BITS_1: + *temp_reg |= CID_BITS_NEXT_0_CID; + status = FWK_SUCCESS; + break; + case SPD_SIG_LOAD_BITS_2: + switch (die_cnt) { + case SPD_DIE_CNT_BITS_2: + *temp_reg |= CID_BITS_NEXT_1_CID; + status = FWK_SUCCESS; + break; + case SPD_DIE_CNT_BITS_4: + *temp_reg |= CID_BITS_NEXT_2_CID; + status = FWK_SUCCESS; + break; + case SPD_DIE_CNT_BITS_8: + *temp_reg |= CID_BITS_NEXT_3_CID; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + break; + default: + status = FWK_E_PARAM; + break; + } + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_memory_type_nxt(uint8_t element, uint32_t *temp_reg) +{ + int status; + uint8_t mem_type = element; + + *temp_reg &= ~DMC620_MEM_TYPE_MASK; + + switch (mem_type) { + case SPD_DDR4_SDRAM: + *temp_reg |= DMC620_MEM_TYPE_DDR4; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_memory_width(uint8_t element, uint32_t *temp_reg) +{ + int status; + uint8_t pri_bus_width = element & SPD_PRI_BUS_WIDTH_BITS_MASK; + + *temp_reg &= ~MEM_WIDTH_MASK; + + switch (pri_bus_width) { + case SPD_PRI_BUS_WIDTH_BITS_32: + *temp_reg |= MEM_WIDTH_64; + status = FWK_SUCCESS; + break; + case SPD_PRI_BUS_WIDTH_BITS_64: + *temp_reg |= MEM_WIDTH_128; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static int get_dimm_bank_grp_bits(uint8_t element, uint32_t *temp_reg) +{ + int status; + uint8_t bank_group = element & SPD_BANK_GROUP_BITS_MASK; + + *temp_reg &= ~MEM_BANK_GROUPS_NEXT_MASK; + + switch (bank_group) { + case SPD_BANK_GROUP_BITS_0: + *temp_reg |= MEM_BANK_GROUPS_NEXT_0; + status = FWK_SUCCESS; + break; + case SPD_BANK_GROUP_BITS_2: + *temp_reg |= MEM_BANK_GROUPS_NEXT_2; + status = FWK_SUCCESS; + break; + case SPD_BANK_GROUP_BITS_4: + *temp_reg |= MEM_BANK_GROUPS_NEXT_4; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +static uint32_t cal_dly_wth_rounding(int32_t spd_val, int32_t spd_val_fine) +{ + int32_t tDLY = 0; + int32_t tempNck = 0; + int32_t tDLY_int_nck = 0; + + tDLY = ((spd_val * MTB) + (spd_val_fine * FTB)); + tempNck = (tDLY * 1000) / dmc_clk_period_ps; + tempNck = tempNck + 974; + tDLY_int_nck = (int32_t)(tempNck / 1000); + + return tDLY_int_nck; +} + +/* + * APIs invoked by DMC-620 core functions + */ +int dimm_spd_init_check( + struct mod_cdns_i2c_master_api_polled *i2c_api, + struct dimm_info *ddr) +{ + int status; + + spd_read(i2c_api, DIMM0_SPD_SLAVE, (uint8_t *)&ddr4_dimm0); + spd_read(i2c_api, DIMM1_SPD_SLAVE, (uint8_t *)&ddr4_dimm1); + + status = chk_ddr4_dimms(ddr->speed, &ddr4_dimm0, &ddr4_dimm1); + if (status != FWK_SUCCESS) { + return status; + } + + dmc_clk_freq = ddr->speed * UINT32_C(1000000); + dmc_clk_period = 1.0f / dmc_clk_freq; + dmc_clk_period_ps = dmc_clk_period * 1000000000000.0f; + + return FWK_SUCCESS; +} + +void dimm_spd_mem_info(void) +{ + dimm_device_data((uint8_t *)&ddr4_dimm0, 0); + dimm_device_data((uint8_t *)&ddr4_dimm1, 1); +} + +int dimm_spd_address_control(uint32_t *temp_reg, struct dimm_info *ddr) +{ + int status; + + status = get_dimm_col_bits(ddr4_dimm0.dram_param.sdram_addr, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + status = get_dimm_row_bits(ddr4_dimm0.dram_param.sdram_addr, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + status = get_dimm_bank_addr_grp_bits( + ddr4_dimm0.dram_param.sdram_density_banks, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + status = get_dimm_rank_bits(ddr4_dimm0.dram_param.mod_org, temp_reg, ddr); + if (status != FWK_SUCCESS) { + return status; + } + + status = get_dimm_cid_bits(ddr4_dimm0.dram_param.sdram_pkg_type, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + return FWK_SUCCESS; +} + +int dimm_spd_format_control(uint32_t *temp_reg) +{ + uint32_t status; + + status = get_dimm_memory_width( + ddr4_dimm0.dram_param.mod_mem_bus_width, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + return FWK_SUCCESS; +} + +int dimm_spd_memory_type(uint32_t *temp_reg, struct dimm_info *ddr) +{ + uint32_t status; + + status = + get_dimm_memory_type_nxt(ddr4_dimm0.dram_param.kb_dram_type, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + status = get_dimm_row_bits(ddr4_dimm0.dram_param.kb_dram_type, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + status = get_dimm_bank_grp_bits( + ddr4_dimm0.dram_param.sdram_density_banks, temp_reg); + if (status != FWK_SUCCESS) { + return status; + } + + status = get_dimm_memory_device_width_next_bits( + ddr4_dimm0.dram_param.mod_org, temp_reg, ddr); + if (status != FWK_SUCCESS) { + return status; + } + + return FWK_SUCCESS; +} + +void dimm_spd_t_refi(uint32_t *temp_reg) +{ + float refi_tmp = t_refi / 8; + uint32_t tmp_refi_now = 0; + + *temp_reg &= ~T_REFI_NEXT_MASK; + + tmp_refi_now = (uint32_t)(refi_tmp / dmc_clk_period); + *temp_reg = (T_REFI_NEXT_MASK & tmp_refi_now); + + fwk_assert(*temp_reg != 0); +} + +void dimm_spd_t_rfc(uint32_t *temp_reg) +{ + uint32_t tmp_value = 0; + uint32_t rfc_tmp = 0; + + *temp_reg &= ~T_RFC_NEXT_MASK; + rfc_tmp = (uint32_t)ddr4_dimm0.dram_param.trfc1min_msb; + + rfc_tmp = rfc_tmp << 8; + rfc_tmp |= (uint32_t)ddr4_dimm0.dram_param.trfc1min_lsb; + + tmp_value = cal_dly_wth_rounding(rfc_tmp, 0); + *temp_reg |= (T_RFC_NEXT_MASK & tmp_value); + *temp_reg &= ~T_RFCFG_NEXT_MASK; + *temp_reg |= (T_RFCFG_NEXT_MASK & (tmp_value << 10)); + *temp_reg &= ~T_RFCFC_NEXT_MASK; + + if (multi_rank == true) { + dimm_spd_t_refi(&tmp_value); + *temp_reg |= + (T_RFCFC_NEXT_MASK & ((uint32_t)((float)tmp_value / t_refi) << 20)); + } + + fwk_assert(*temp_reg != 0); +} + +void dimm_spd_t_rcd(uint32_t *temp_reg) +{ + uint8_t spd_tmp = 0; + uint8_t spd_tmp2 = 0; + uint32_t tmp_value = 0; + + *temp_reg &= ~T_RCD_NEXT_MASK; + + spd_tmp = ddr4_dimm0.dram_param.trcdmin; + spd_tmp2 = ddr4_dimm0.dram_param.trcdmin_fine; + + tmp_value = cal_dly_wth_rounding((int32_t)spd_tmp, (int32_t)spd_tmp2); + *temp_reg = T_RCD_NEXT_MASK & tmp_value; + + fwk_assert(*temp_reg != 0); +} + +void dimm_spd_t_ras(uint32_t *temp_reg) +{ + uint8_t temp = 0; + uint32_t tras_tmp = 0; + uint32_t tmp_value = 0; + + *temp_reg &= ~T_RAS_NEXT_MASK; + tras_tmp = (uint32_t)ddr4_dimm0.dram_param.uppr_nbls_trasmin_trcmin; + + tras_tmp &= (uint32_t)LWR_NBBL_MASK; + tras_tmp = tras_tmp << 8; + + temp = ddr4_dimm0.dram_param.trasmin_lsb; + tras_tmp |= (uint32_t)temp; + + tmp_value = cal_dly_wth_rounding(tras_tmp, 0); + *temp_reg = (T_RAS_NEXT_MASK & tmp_value); + + fwk_assert(*temp_reg != 0); +} + +void dimm_spd_t_rp(uint32_t *temp_reg) +{ + uint8_t spd_tmp = 0; + uint8_t spd_tmp2 = 0; + uint32_t tmp_value = 0; + + *temp_reg &= ~T_RP_NEXT_MASK; + + spd_tmp = ddr4_dimm0.dram_param.trpmin; + spd_tmp2 = ddr4_dimm0.dram_param.trpmin_fine; + + tmp_value = cal_dly_wth_rounding((int32_t)spd_tmp, (int32_t)spd_tmp2); + *temp_reg = T_RP_NEXT_MASK & tmp_value; + + fwk_assert(*temp_reg != 0); +} + +void dimm_spd_t_rrd(uint32_t *temp_reg) +{ + uint8_t spd_tmp = 0; + uint8_t spd_tmp2 = 0; + uint32_t tmp_value = 0; + + *temp_reg &= ~T_RRD_S_NEXT_MASK; + + spd_tmp = ddr4_dimm0.dram_param.trrd_smin; + spd_tmp2 = ddr4_dimm0.dram_param.trrd_smin_fine; + + tmp_value = cal_dly_wth_rounding((int32_t)spd_tmp, (int32_t)spd_tmp2); + *temp_reg = T_RRD_S_NEXT_MASK & tmp_value; + *temp_reg &= ~T_RRD_L_NEXT_MASK; + + spd_tmp = ddr4_dimm0.dram_param.trrd_lmin; + spd_tmp2 = ddr4_dimm0.dram_param.trrd_lmin_fine; + + tmp_value = 0; + tmp_value = cal_dly_wth_rounding((int32_t)spd_tmp, (int32_t)spd_tmp2); + tmp_value = tmp_value << 8; + + *temp_reg |= (T_RRD_L_NEXT_MASK & tmp_value); + tmp_value = 0x04000000; + *temp_reg |= (T_RRD_DLR_NEXT_MASK & tmp_value); + + fwk_assert(*temp_reg != 0); +} + +void dimm_spd_t_wtr(uint32_t *temp_reg, struct dimm_info *ddr) +{ + uint8_t spd_tmp1 = 0; + uint8_t spd_temp = 0; + uint32_t twtr_tmp = 0; + uint32_t tmp_value = 0; + uint32_t bl_value = 8; + + spd_temp = ddr4_dimm0.dram_param.twtrmin_un; + twtr_tmp = (uint32_t)(spd_temp & LWR_NBBL_MASK); + twtr_tmp = twtr_tmp << 8; + + spd_tmp1 = ddr4_dimm0.dram_param.twtr_smin; + twtr_tmp |= (uint32_t)spd_tmp1; + + tmp_value = cal_dly_wth_rounding(twtr_tmp, 0); + tmp_value = ddr->cwl_value + (bl_value / 2) + tmp_value; + *temp_reg = (T_WTR_S_NEXT_MASK & tmp_value); + + twtr_tmp = (uint32_t)(spd_temp & UPPR_NBBL_MASK); + twtr_tmp = twtr_tmp << 4; + + spd_tmp1 = ddr4_dimm0.dram_param.twtr_lmin; + twtr_tmp |= (uint32_t)spd_tmp1; + tmp_value = cal_dly_wth_rounding(twtr_tmp, 0); + tmp_value = ddr->cwl_value + (bl_value / 2) + tmp_value; + *temp_reg |= (T_WTR_L_NEXT_MASK & (tmp_value << 8)); + *temp_reg |= (T_WTR_CS_NEXT_MASK & (tmp_value << 16)); + + fwk_assert(*temp_reg != 0); +} + +int dimm_spd_t_act_window(uint32_t *temp_reg) +{ + uint8_t temp = 0; + uint32_t tfawmin = 0; + uint32_t tmp_value = 0; + uint8_t tmp_mac = 0; + int status = FWK_SUCCESS; + + *temp_reg &= ~T_FAW_NEXT_MASK; + + tfawmin = (uint32_t)ddr4_dimm0.dram_param.tfawmin_msn; + tfawmin &= (uint32_t)LWR_NBBL_MASK; + tfawmin = tfawmin << 8; + temp = ddr4_dimm0.dram_param.tfawmin_lsb; + + tfawmin |= temp; + tmp_value = cal_dly_wth_rounding(tfawmin, 0); + *temp_reg = (T_FAW_NEXT_MASK & tmp_value); + *temp_reg &= ~T_FAW_DLR_NEXT_MASK; + *temp_reg |= (T_FAW_DLR_NEXT_MASK & (tmp_value << 8)); + + temp = ddr4_dimm0.dram_param.sdram_opt_features; + tmp_mac = ~SPD_T_MAC_MASK & temp; + + switch (tmp_mac) { + case SPD_T_MAC_0: + case SPD_T_MAC_1: + case SPD_T_MAC_2: + case SPD_T_MAC_3: + case SPD_T_MAC_4: + case SPD_T_MAC_5: + case SPD_T_MAC_6: + case SPD_T_MAC_7: + case SPD_T_MAC_8: + *temp_reg &= ~T_MAWI_NEXT_MASK; + status = FWK_SUCCESS; + break; + default: + status = FWK_E_PARAM; + break; + } + + return status; +} + +int dimm_spd_calculate_dimm_size_gb(uint32_t *size_gb) +{ + uint64_t size; + uint8_t temp; + + size = 0; + temp = ddr4_dimm0.dram_param.sdram_density_banks; + temp = (temp & SPD_SDRAM_DENSITY_MASK) >> SPD_SDRAM_DENSITY_POS; + + if (temp <= 7) { + size = (uint64_t)(1 << temp) * 256UL * FWK_MIB; + } else if (temp == 0x8) { + size = 12UL * FWK_GIB; + } else if (temp == 0x9) { + size = 24UL * FWK_GIB; + } else { + return FWK_E_DEVICE; + } + + size = size / 8UL; + temp = ddr4_dimm0.dram_param.mod_mem_bus_width; + temp = (temp & SPD_PRI_BUS_WIDTH_BITS_MASK) >> SPD_PRI_BUS_WIDTH_BITS_POS; + if (temp <= 3) { + size = size * (uint64_t)((1 << temp) * 8UL); + } else { + return FWK_E_DEVICE; + } + + temp = ddr4_dimm0.dram_param.mod_org; + temp = (temp & SDRAM_DEVICE_WIDTH_MASK) >> SDRAM_DEVICE_WIDTH_POS; + if (temp <= 3) { + size = size / (uint64_t)((1 << temp) * 4); + } else { + return FWK_E_DEVICE; + } + + temp = ddr4_dimm0.dram_param.mod_org; + temp = (temp & SPD_PKG_RANK_BITS_MASK) >> SPD_PKG_RANK_BITS_OFFSET; + if (temp <= 7) { + size = size * (uint64_t)(temp + 1); + } else { + return FWK_E_DEVICE; + } + + *size_gb = size / FWK_GIB; + return FWK_SUCCESS; +} diff --git a/product/morello/module/dmc_bing/src/dimm_spd.h b/product/morello/module/dmc_bing/src/dimm_spd.h new file mode 100644 index 000000000..45f73e73f --- /dev/null +++ b/product/morello/module/dmc_bing/src/dimm_spd.h @@ -0,0 +1,492 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DIMM_SPD_H +#define DIMM_SPD_H + +#include +#include + +#include + +#include + +/* + * DMC-Bing ADDRESS_CONTROL register bit field values + */ +#define COL_BITS_NEXT_MASK UINT32_C(0x00000003) +#define COL_BITS_NEXT_10_BITS UINT32_C(0x00000002) +#define COL_BITS_NEXT_11_BITS UINT32_C(0x00000003) +#define COL_BITS_NEXT_12_BITS UINT32_C(0x00000004) + +#define ROW_BITS_NEXT_MASK UINT32_C(0x00000700) +#define ROW_BITS_NEXT_12_BITS UINT32_C(0x00000100) +#define ROW_BITS_NEXT_13_BITS UINT32_C(0x00000200) +#define ROW_BITS_NEXT_14_BITS UINT32_C(0x00000300) +#define ROW_BITS_NEXT_15_BITS UINT32_C(0x00000400) +#define ROW_BITS_NEXT_16_BITS UINT32_C(0x00000500) +#define ROW_BITS_NEXT_17_BITS UINT32_C(0x00000600) +#define ROW_BITS_NEXT_18_BITS UINT32_C(0x00000700) + +#define CID_BITS_NEXT_MASK UINT32_C(0x60000000) +#define CID_BITS_NEXT_0_CID UINT32_C(0x00000000) +#define CID_BITS_NEXT_1_CID UINT32_C(0x20000000) +#define CID_BITS_NEXT_2_CID UINT32_C(0x40000000) +#define CID_BITS_NEXT_3_CID UINT32_C(0x60000000) + +#define BANK_BITS_NEXT_MASK UINT32_C(0x00070000) +#define BANK_BITS_NEXT_8_BANKS UINT32_C(0x00030000) +#define BANK_BITS_NEXT_16_BANKS UINT32_C(0x00040000) + +#define RANK_BITS_NEXT_MASK UINT32_C(0x03000000) +#define RANK_BITS_NEXT_0 UINT32_C(0x00000000) +#define RANK_BITS_NEXT_1 UINT32_C(0x01000000) +#define RANK_BITS_NEXT_2 UINT32_C(0x02000000) +#define RANK_BITS_NEXT_3 UINT32_C(0x03000000) + +/* + * DMC Bing FORMAT_CONTROL register bit field values + */ +#define MEM_WIDTH_MASK UINT32_C(0x00000003) +#define MEM_WIDTH_64 UINT32_C(0x00000002) +#define MEM_WIDTH_128 UINT32_C(0x00000003) + +/* + * DMC-Bing MEMORY_TYPE register bit field values + */ +#define DMC620_MEM_TYPE_MASK UINT32_C(0x00000003) +#define DMC620_MEM_TYPE_DDR4 UINT32_C(0x00000002) + +#define MEM_BANK_GROUPS_NEXT_MASK UINT32_C(0x00030000) +#define MEM_BANK_GROUPS_NEXT_0 UINT32_C(0x00000000) +#define MEM_BANK_GROUPS_NEXT_2 UINT32_C(0x00010000) +#define MEM_BANK_GROUPS_NEXT_4 UINT32_C(0x00030000) + +#define MEM_DEV_WIDTH_NEXT_MASK UINT32_C(0x00000300) +#define MEM_DEV_WIDTH_NEXT_4 UINT32_C(0x00000000) +#define MEM_DEV_WIDTH_NEXT_8 UINT32_C(0x00000100) +#define MEM_DEV_WIDTH_NEXT_16 UINT32_C(0x00000200) + +#define T_REFI_NEXT_MASK UINT32_C(0x00000FFF) +#define T_RFC_NEXT_MASK UINT32_C(0x000003FF) +#define T_RFCFG_NEXT_MASK UINT32_C(0x000FFC00) +#define T_RFCFC_NEXT_MASK UINT32_C(0x0FF00000) +#define T_RCD_NEXT_MASK UINT32_C(0x000001FF) +#define T_RAS_NEXT_MASK UINT32_C(0x000003FF) +#define T_RP_NEXT_MASK UINT32_C(0x000001FF) +#define T_WTW_L_NEXT_MASK UINT32_C(0x00003F00) +#define T_WTW_S_NEXT_MASK UINT32_C(0x0000003F) +#define T_WTW_DLR_NEXT_MASK UINT32_C(0xF6000000) +#define T_RRD_S_NEXT_MASK UINT32_C(0x0000000F) +#define T_RRD_L_NEXT_MASK UINT32_C(0x00000F00) +#define T_RRD_DLR_NEXT_MASK UINT32_C(0x0F000000) +#define T_FAW_NEXT_MASK UINT32_C(0x0000003F) +#define T_FAW_DLR_NEXT_MASK UINT32_C(0x00003F00) +#define T_MAWI_NEXT_MASK UINT32_C(0x03FF0000) +#define T_WTR_S_NEXT_MASK UINT32_C(0x0000003F) +#define T_WTR_L_NEXT_MASK UINT32_C(0x00003F00) +#define T_WTR_CS_NEXT_MASK UINT32_C(0x003F0000) +#define T_WR_NEXT_MASK UINT32_C(0x0000003F) + +#define LWR_NBBL_MASK 0x0F +#define UPPR_NBBL_MASK 0xF0 + +/* + * SPD definitions + */ + +/* SPD DRAM Device Type supported */ +#define SPD_DDR4_SDRAM 0x0C + +/* Column Address Bits */ +#define SPD_COL_ADDR_BITS_MASK 0x07 +#define SPD_COL_ADDR_BITS_9 0x00 +#define SPD_COL_ADDR_BITS_10 0x01 +#define SPD_COL_ADDR_BITS_11 0x02 +#define SPD_COL_ADDR_BITS_12 0x03 + +/* Row Address Bits */ +#define SPD_ROW_ADDR_BITS_MASK 0x38 +#define SPD_ROW_ADDR_BITS_12 0x00 +#define SPD_ROW_ADDR_BITS_13 0x08 +#define SPD_ROW_ADDR_BITS_14 0x10 +#define SPD_ROW_ADDR_BITS_15 0x18 +#define SPD_ROW_ADDR_BITS_16 0x20 +#define SPD_ROW_ADDR_BITS_17 0x28 +#define SPD_ROW_ADDR_BITS_18 0x30 + +/* Bank Group bits */ +#define SPD_BANK_GROUP_BITS_MASK 0xC0 +#define SPD_BANK_GROUP_BITS_0 0x00 +#define SPD_BANK_GROUP_BITS_2 0x40 +#define SPD_BANK_GROUP_BITS_4 0x80 + +/* Bank Address bits on each chip-select */ +#define SPD_BANK_BITS_MASK 0x30 +#define SPD_BANK_BITS_2 0x00 +#define SPD_BANK_BITS_3 0x10 + +/* SDRAM die capacity definition */ +#define SPD_SDRAM_DENSITY_MASK 0xF +#define SPD_SDRAM_DENSITY_POS 0 + +/* Number of Package Ranks per DIMM supported */ +#define SPD_PKG_RANK_BITS_MASK 0x38 +#define SPD_PKG_RANK_BITS_OFFSET 3 +#define SPD_PKG_RANK1 0x00 +#define SPD_PKG_RANK2 0x01 +#define SPD_PKG_RANK4 0x03 +#define SPD_PKG_RANK8 0x07 + +/* SDRAM Package Type bits - SDRAM Package Type */ +#define SPD_PKG_TYPE_BITS_MASK 0x80 +#define SPD_PKG_TYPE_BITS_0 0x00 +#define SPD_PKG_TYPE_BITS_1 0x80 + +/* Die Count bits - SDRAM Package Type */ +#define SPD_DIE_CNT_BITS_MASK 0x70 +#define SPD_DIE_CNT_BITS_0 0x00 +#define SPD_DIE_CNT_BITS_2 0x10 +#define SPD_DIE_CNT_BITS_4 0x30 +#define SPD_DIE_CNT_BITS_8 0x70 + +/* Signal Loading bits - SDRAM Package Type */ +#define SPD_SIG_LOAD_BITS_MASK 0x03 +#define SPD_SIG_LOAD_BITS_0 0x00 +#define SPD_SIG_LOAD_BITS_1 0x03 +#define SPD_SIG_LOAD_BITS_2 0x01 + +/* SDRAM Primary bus width */ +#define SPD_PRI_BUS_WIDTH_BITS_MASK 0x07 +#define SPD_PRI_BUS_WIDTH_BITS_POS 0 +#define SPD_PRI_BUS_WIDTH_BITS_8 0x00 +#define SPD_PRI_BUS_WIDTH_BITS_16 0x01 +#define SPD_PRI_BUS_WIDTH_BITS_32 0x02 +#define SPD_PRI_BUS_WIDTH_BITS_64 0x03 + +/* SDRAM Device width */ +#define SDRAM_DEVICE_WIDTH_MASK 0x07 +#define SDRAM_DEVICE_WIDTH_POS 0 +#define SDRAM_DEVICE_WIDTH_0 0x00 +#define SDRAM_DEVICE_WIDTH_1 0x01 +#define SDRAM_DEVICE_WIDTH_2 0x02 +#define SDRAM_DEVICE_WIDTH_3 0x03 + +#define SPD_T_MAC_MASK 0x0F +#define SPD_T_MAC_0 0x00 +#define SPD_T_MAC_1 0x01 +#define SPD_T_MAC_2 0x02 +#define SPD_T_MAC_3 0x03 +#define SPD_T_MAC_4 0x04 +#define SPD_T_MAC_5 0x05 +#define SPD_T_MAC_6 0x06 +#define SPD_T_MAC_7 0x07 +#define SPD_T_MAC_8 0x08 + +#define FTB 1U +#define MTB 125U +#define DIMM0_SPD_SLAVE 0x50 +#define DIMM1_SPD_SLAVE 0x51 +#define WRITE_PAGE0 0x36 +#define WRITE_PAGE1 0x37 + +#define SPD_PAGE0_START 0 +#define SPD_PAGE1_START 256 +#define MAX_SPD_PAGE0 255 +#define MAX_SPD_PAGE1 511 + +#define SPD_W_TRANSFER_SIZE 2 +#define SPD_R_TRANSFER_SIZE 1 +#define SPD_STOP 1 + +/* + * SPD - Base Configuration and DRAM Parameter structure + * Block 0 + * Bytes 0 - 127 + * Address 0x000 - 0x07F + * This section defines parameters that are common to all DDR4 module types + */ +struct ddr4_dram_param { + /* Number of Bytes used */ + uint8_t num_bytes; + /* SPD Revision */ + uint8_t spd_rev; + /* Key Byte / DRAM Device Type */ + uint8_t kb_dram_type; + /* Key Byte / Module Type */ + uint8_t kb_mod_type; + /* SDRAM Density and Banks */ + uint8_t sdram_density_banks; + /* SDRAM Addressing */ + uint8_t sdram_addr; + /* SDRAM Package Type */ + uint8_t sdram_pkg_type; + /* SDRAM Optional Features */ + uint8_t sdram_opt_features; + /* SDRAM Thermal and Refresh Options */ + uint8_t sdram_temp_refresh; + /* Other SDRAM Optional Features */ + uint8_t sdram_other_features; + /* Secondary SDRAM Package Type */ + uint8_t secdry_sdram_pck_type; + /* Module Nominal Voltage, VDD */ + uint8_t mod_nom_volt; + /* Module Organization */ + uint8_t mod_org; + /* Module Memory Bus Width */ + uint8_t mod_mem_bus_width; + /* Module Thermal Sensor */ + uint8_t mod_temp_sensor; + /* Extended module type */ + uint8_t extnded_mod_type; + /* Reserved */ + uint8_t reserved_byte16; + /* Timebases */ + uint8_t timebases; + /* SDRAM Minimum Cycle Time (tCKAVGmin) */ + uint8_t tckavgmin; + /* SDRAM Maximum Cycle Time (C) */ + uint8_t tckavgmax; + /* CAS Latencies Supported, First Byte */ + uint8_t cas_lat_sup_1; + /* CAS Latencies Supported, Second Byte */ + uint8_t cas_lat_sup_2; + /* CAS Latencies Supported, Third Byte */ + uint8_t cas_lat_sup_3; + /* CAS Latencies Supported, Fourth Byte */ + uint8_t cas_lat_sup_4; + /* Minimum CAS Latency Time (tAAmin) */ + uint8_t taamin; + /* Minimum RAS to CAS Delay Time (tRCDmin)*/ + uint8_t trcdmin; + /* Minimum Row Precharge Delay Time (tRPmin) */ + uint8_t trpmin; + /* Upper Nibbles for tRASmin and tRCmin */ + uint8_t uppr_nbls_trasmin_trcmin; + /* Minimum Active to Precharge Delay Time(tRASmin), LSB */ + uint8_t trasmin_lsb; + /* Minimum Active to Active/Refresh Delay Time (tRCmin), LSB */ + uint8_t trcmin_lsb; + /* Minimum Refresh Recovery Delay Time (tRFC1min), LSB */ + uint8_t trfc1min_lsb; + /* Minimum Refresh Recovery Delay Time (tRFC1min), MSB */ + uint8_t trfc1min_msb; + /* Minimum Refresh Recovery Delay Time (tRFC2min), LSB */ + uint8_t trfc2min_lsb; + /* Minimum Refresh Recovery Delay Time (tRFC2min), MSB */ + uint8_t trfc2min_msb; + /* Minimum Refresh Recovery Delay Time (tRFC4min), LSB */ + uint8_t trfc4min_lsb; + /* Minimum Refresh Recovery Delay Time (tRFC4min), MSB */ + uint8_t trfc4min_msb; + /* Minimum Four Activate Window Time(tFAWmin), Most Significant Nibble */ + uint8_t tfawmin_msn; + /* Minimum Four Activate Window Delay Time (tFAWmin), LSB */ + uint8_t tfawmin_lsb; + /* Minimum Activate to Activate Delay Time(tRRD_Smin), diff bank group */ + uint8_t trrd_smin; + /* Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group */ + uint8_t trrd_lmin; + /* Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group */ + uint8_t tccd_lmin; + /* Upper Nibble for tWRmin */ + uint8_t twrmin_un; + /* Minimum Write Recovery Time (tWRmin) */ + uint8_t twrmin; + /* Upper Nibble for tWTRmin */ + uint8_t twtrmin_un; + /* Minimum Write to Read Time (tWTR_Smin), different bank group */ + uint8_t twtr_smin; + /* Minimum Write to Read Time (tWTR_Lmin), same bank group */ + uint8_t twtr_lmin; + /* Reserved */ + uint8_t reserved_byte46_59[14]; + /* Connector to SDRAM Bit Mapping, Bytes 60 - 77*/ + uint8_t conn_sdram_bit_map_60_77[18]; + /* Reserved */ + uint8_t reserved_byte78_116[39]; + /* Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank */ + uint8_t tccd_lmin_fine; + /* + * Fine Offset for Minimum Activate to Activate Delay Time(tRRD_Lmin), + * same bank + */ + uint8_t trrd_lmin_fine; + /* + * Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), + * different bank group + */ + uint8_t trrd_smin_fine; + /* Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) */ + uint8_t trcmin_fine; + /* Fine Offset for Minimum Row Precharge Delay Time (tRPmin) */ + uint8_t trpmin_fine; + /* Fine Offset for Minimum RAS to CAS Delay Time (tRCDmin) */ + uint8_t trcdmin_fine; + /* Fine Offset for Minimum CAS Latency Time (tAAmin) */ + uint8_t taamin_fine; + /* Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax) */ + uint8_t tckavgmax_fine; + /* Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) */ + uint8_t tckavgmin_fine; + /* Cyclical Redundancy Code (CRC) for Base Configuration Section, LSB */ + uint8_t crc_lsb; + /* Cyclical Redundancy Code (CRC) for Base Configuration Section, MSB */ + uint8_t crc_msb; +} __attribute__((packed)); + +struct ddr4_spd { + struct ddr4_dram_param dram_param; + uint8_t standard_mod[64]; + uint8_t hybrid_mod[64]; + uint8_t hybrid_ext_func[64]; + uint8_t mfg_info[64]; + uint8_t end_usr[128]; +} __attribute__((packed)); + +/* + * SPD API function prototypes + */ + +/* + * Brief - Function to initialize and check DIMM SPD values + * + * param - i2c_api - Pointer to I2C master APIs + * param - ddr - Pointer to DIMM information structure + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DATA - if the SPD data is wrong + */ +int dimm_spd_init_check( + struct mod_cdns_i2c_master_api_polled *i2c_api, + struct dimm_info *ddr); + +/* + * Brief - Function to print the DIMM card information + * + * retval - NONE + */ +void dimm_spd_mem_info(void); + +/* + * Brief - Function to calculate DMC-620 ADDRESS_CONTROL register value + * + * param - value - Pointer to variable where calculated value is saved + * param - info - Pointer to DIMM information structure + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DATA - if the value cannot be calculated + */ +int dimm_spd_address_control(uint32_t *value, struct dimm_info *info); + +/* + * Brief - Function to calculate DMC-620 FORMAT_CONTROL register value + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DATA - if the value cannot be calculated + */ +int dimm_spd_format_control(uint32_t *value); + +/* + * Brief - Function to calculate DMC-620 MEMORY_TYPE register value + * + * param - value - Pointer to variable where calculated value is saved + * param - info - Pointer to DIMM information structure + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DATA - if the value cannot be calculated + */ +int dimm_spd_memory_type(uint32_t *value, struct dimm_info *info); + +/* + * Brief - Function to calculate tREFI timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DATA - if the value cannot be calculated + */ +void dimm_spd_t_refi(uint32_t *value); + +/* + * Brief - Function to calculate tRFC timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - NONE + */ +void dimm_spd_t_rfc(uint32_t *value); + +/* + * Brief - Function to calculate tRCD timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - NONE + */ +void dimm_spd_t_rcd(uint32_t *value); + +/* + * Brief - Function to calculate tRAS timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - NONE + */ +void dimm_spd_t_ras(uint32_t *value); + +/* + * Brief - Function to calculate tRP timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - NONE + */ +void dimm_spd_t_rp(uint32_t *value); + +/* + * Brief - Function to calculate tRRD timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - NONE + */ +void dimm_spd_t_rrd(uint32_t *value); + +/* + * Brief - Function to calculate tWTR timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * param - info - Pointer to DIMM information structure + * + * retval - NONE + */ +void dimm_spd_t_wtr(uint32_t *value, struct dimm_info *info); + +/* + * Brief - Function to calculate tACT_WINDOW timing parameter + * + * param - value - Pointer to variable where calculated value is saved + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DATA - if the value cannot be calculated + */ +int dimm_spd_t_act_window(uint32_t *value); + +/* + * Brief - Function to calculate total DIMM size + * + * param - size_gb - Pointer to variable where calculated value is saved + * + * retval - FWK_SUCCESS - if the operation is succeeded + * FWK_E_DEVICE - if the SPD value is invalid + */ +int dimm_spd_calculate_dimm_size_gb(uint32_t *size_gb); + +#endif /* DIMM_SPD_H */ diff --git a/product/morello/module/dmc_bing/src/mod_dmc_bing.c b/product/morello/module/dmc_bing/src/mod_dmc_bing.c index ad467ac51..26ec472a8 100644 --- a/product/morello/module/dmc_bing/src/mod_dmc_bing.c +++ b/product/morello/module/dmc_bing/src/mod_dmc_bing.c @@ -11,6 +11,15 @@ #include "morello_pik_system.h" #include "morello_scp_pik.h" +#if !defined(PLAT_FVP) +# include +# include + +# include + +# include +#endif + #include #include #include @@ -31,21 +40,40 @@ #include #include +#define DECODE_CTRL_ROW_POS 10 +#define DECODE_CTRL_BANK_POS 13 +#define DECODE_CTRL_CID_POS 16 +#define DECODE_CTRL_RANK_POS 19 + +/* DMC-Bing register specific definitions */ +#define DDR_TRAIN_TWO_RANKS 0 + static struct mod_timer_api *timer_api; -static uint64_t usable_mem_size; -static int ddr_get_dimm_size(uint64_t *size) +#if !defined(PLAT_FVP) +struct mod_cdns_i2c_master_api_polled *i2c_api; +#endif +struct dimm_info ddr_info; + +static int ddr_get_mem_size(uint64_t *size) { +#if defined(PLAT_FVP) /* FVP has fixed memory size of 8GB */ *size = 0x200000000ULL; - return FWK_SUCCESS; -} +#else + uint32_t size_gb = 0; + int status; -/* Memory Information API */ + fwk_assert(size != NULL); + + status = dimm_spd_calculate_dimm_size_gb(&size_gb); + if (status != FWK_SUCCESS) { + return status; + } + + *size = (uint64_t)size_gb * 2ULL * FWK_GIB; +#endif -static int ddr_get_mem_size(uint64_t *size) -{ - *size = usable_mem_size; return FWK_SUCCESS; } @@ -80,8 +108,9 @@ static void dmc_bing_abort_recover(struct mod_dmc_bing_reg *dmc) /* Wait for DMC to enter aborted state */ FWK_LOG_INFO("[DDR] Waiting for DMC to enter abort state..."); while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS) != - DMC_BING_ABORTED_STATE) + DMC_BING_ABORTED_STATE) { continue; + } FWK_LOG_INFO("[DDR] DONE"); @@ -96,8 +125,9 @@ static void dmc_bing_abort_recover(struct mod_dmc_bing_reg *dmc) /* Wait for state transition to complete */ FWK_LOG_INFO("[DDR] Waiting for DMC state transition..."); while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS) != - DMC_BING_RECOVER_STATE) + DMC_BING_RECOVER_STATE) { continue; + } FWK_LOG_INFO("[DDR] DONE"); @@ -107,8 +137,9 @@ static void dmc_bing_abort_recover(struct mod_dmc_bing_reg *dmc) /* Wait for state transition to complete */ FWK_LOG_INFO("[DDR] Waiting for DMC state transition..."); - while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS) != current_state) + while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS) != current_state) { continue; + } FWK_LOG_INFO("[DDR] DONE"); @@ -367,7 +398,224 @@ static int enable_dimm_refresh(struct mod_dmc_bing_reg *dmc) return ddr_poll_training_status(dmc); } -static void delay_ms(uint32_t ms) +#if !defined(PLAT_FVP) +static int ddr_training( + struct mod_dmc_bing_reg *dmc, + fwk_id_t ddr_id, + struct dimm_info *info) +{ + uint32_t value; + int i; + int j; + int status; + + FWK_LOG_INFO("[DDR] Training DDR memories..."); + + for (i = 1; i <= ddr_info.number_of_ranks; i++) { + FWK_LOG_INFO("[DDR] Write leveling rank %d... ", i); + + /* Clear interrupt status if any */ + if (dmc->INTERRUPT_STATUS != 0) { + dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } + + /* Set training command */ + dmc->DIRECT_ADDR = DDR_ADDR_TRAIN_TYPE_WR_LVL; + if (dmc->DIRECT_ADDR != DDR_ADDR_TRAIN_TYPE_WR_LVL) { + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_wrlvl_phy_obs_regs(ddr_id, j, info); + } + return FWK_E_DEVICE; + } + dmc->DIRECT_CMD = ((1 << (i + 15)) | 0x000A); + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) { + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_wrlvl_phy_obs_regs(ddr_id, j, info); + } + return status; + } + morello_wrlvl_phy_obs_regs(ddr_id, i, info); + } + morello_verify_phy_status(ddr_id, DDR_ADDR_TRAIN_TYPE_WR_LVL, info); + + FWK_LOG_INFO("[DDR] Read gate training"); + /* Clear interrupt status if any */ + if (dmc->INTERRUPT_STATUS != 0) { + dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } + + FWK_LOG_INFO("[DDR] A side..."); + + /* Set read level control parameter */ + value = dmc->RDLVL_CONTROL_NEXT; + value = (value & 0xFFFFF9FF) | (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + /* Update */ + dmc->DIRECT_ADDR = 0; + value = ((ddr_info.ranks_to_train << 16) | 0x000C); + dmc->DIRECT_CMD = value; + + /* Run training on slices 0-9 */ + dmc->DIRECT_ADDR = + (DDR_ADDR_TRAIN_TYPE_RD_GATE | (0x3FFFF << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x000A); + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) { + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_read_gate_phy_obs_regs(ddr_id, j, info); + } + return status; + } + + /* Clear interrupt status if any */ + if (dmc->INTERRUPT_STATUS != 0) { + dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } + +# if DDR_TRAIN_TWO_RANKS + FWK_LOG_INFO("[DDR] B side..."); + + /* Set write leveling parameters */ + value = dmc->RDLVL_CONTROL_NEXT; + value |= (0x03 << 9) | (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + /* Update */ + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = 0x0001000C; + + /* Run training on slices 10-17 */ + dmc->DIRECT_ADDR = + (DDR_ADDR_TRAIN_TYPE_RD_GATE | (0x3FFFF << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = DDR_CMD_TRAIN_RANK_1; + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) { + return status; + } +# endif + + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_read_gate_phy_obs_regs(ddr_id, j, info); + } + + FWK_LOG_INFO("[DDR] Read eye training"); + + /* Clear interrupt status if any */ + if (dmc->INTERRUPT_STATUS != 0) { + dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } + + FWK_LOG_INFO("[DDR] A side..."); + + /* Set write leveling parameters */ + value = dmc->RDLVL_CONTROL_NEXT; + value = (value & 0xFFFFF9FF) | (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + + /* Update */ + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x000C); + + /* Run training on slices 0-9 */ + dmc->DIRECT_ADDR = + (DDR_ADDR_TRAIN_TYPE_RD_EYE | (0x300FF << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x000A); + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) { + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_phy_obs_regs(ddr_id, j, info); + } + return status; + } + + /* Clear interrupt status if any */ + if (dmc->INTERRUPT_STATUS != 0) { + dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } + + FWK_LOG_INFO("[DDR] B side..."); + + /* Set write leveling parameters */ + value = dmc->RDLVL_CONTROL_NEXT; + value |= (0x03 << 9) | (0 << 16); + dmc->RDLVL_CONTROL_NEXT = value; + /* Update */ + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x000C); + + /* Run training on slices 10-17 */ + dmc->DIRECT_ADDR = + (DDR_ADDR_TRAIN_TYPE_RD_EYE | (0xFF00 << DDR_ADDR_DATA_SLICES_POS)); + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x000A); + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) { + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_phy_obs_regs(ddr_id, j, info); + } + return status; + } + + /* Clear interrupt status if any */ + if (dmc->INTERRUPT_STATUS != 0) { + dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } + + FWK_LOG_INFO("[DDR] MC initiated update..."); + + dmc->DIRECT_ADDR = 0; + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x000A); + + status = ddr_poll_training_status(dmc); + if (status != FWK_SUCCESS) { + return status; + } + + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x000C); + + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_phy_obs_regs(ddr_id, j, info); + } + + return FWK_SUCCESS; +} + +static int dmc_bing_verify_phy_status(fwk_id_t ddr_id) +{ + int status; + + status = morello_verify_phy_status( + ddr_id, DDR_ADDR_TRAIN_TYPE_WR_LVL, &ddr_info); + if (status != FWK_SUCCESS) { + return status; + } + + status = morello_verify_phy_status( + ddr_id, DDR_ADDR_TRAIN_TYPE_RD_GATE, &ddr_info); + if (status != FWK_SUCCESS) { + return status; + } + + status = morello_verify_phy_status( + ddr_id, DDR_ADDR_TRAIN_TYPE_RD_EYE, &ddr_info); + if (status != FWK_SUCCESS) { + return status; + } + + status = + morello_verify_phy_status(ddr_id, DDR_ADDR_TRAIN_TYPE_VREF, &ddr_info); + if (status != FWK_SUCCESS) { + return status; + } + + return FWK_SUCCESS; +} +#endif + +void delay_ms(uint32_t ms) { volatile uint32_t i; while (ms > 0) { @@ -388,8 +636,9 @@ static void execute_ddr_cmd( dmc->DIRECT_ADDR = addr; dmc->DIRECT_CMD = cmd; - if (ms != 0) + if (ms != 0) { delay_ms(ms); + } status = dmc_bing_poll_dmc_status(dmc); if (status != FWK_SUCCESS) { @@ -402,9 +651,11 @@ static void execute_ddr_cmd( static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) { +#if defined(PLAT_FVP) /* Clear interrupt status if any */ - if (dmc->INTERRUPT_STATUS != 0) + if (dmc->INTERRUPT_STATUS != 0) { dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } execute_ddr_cmd(dmc, 0x00000004, 0x0001000A, 0); execute_ddr_cmd(dmc, 0x00000006, 0x00ff0004, 0); @@ -430,19 +681,289 @@ static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) execute_ddr_cmd(dmc, 0x00000300, 0x0001000d, 0); execute_ddr_cmd(dmc, 0x00000400, 0x00ff0005, 0); execute_ddr_cmd(dmc, 0x00000000, 0x0001000d, 0); +#else + int count; + uint32_t addr; + int status; + + /* Clear interrupt status if any */ + if (dmc->INTERRUPT_STATUS != 0) { + dmc->INTERRUPT_CLR = 0xFFFFFFFF; + } + + execute_ddr_cmd(dmc, 0x00000004, 0x0001000A, 0); + execute_ddr_cmd( + dmc, 0x00000006, ((ddr_info.ranks_to_train << 16) | 0x0004), 0); + execute_ddr_cmd(dmc, 0x00000000, 0x0001000B, 0); + execute_ddr_cmd( + dmc, 0x00000001, ((ddr_info.ranks_to_train << 16) | 0x000B), 0); + execute_ddr_cmd(dmc, 0x000003E8, 0x0001000D, 0); + execute_ddr_cmd(dmc, 0x00000258, 0x0001000D, 1); + execute_ddr_cmd( + dmc, 0x00010001, ((ddr_info.ranks_to_train << 16) | 0x000B), 0); + execute_ddr_cmd(dmc, 0x0000002A, 0x0001000D, 0); + + for (count = 0; count < 12; count++) { + /* Wait for 0x200 cycles */ + execute_ddr_cmd(dmc, 0x00000200, 0x0001000D, 1); + } + + execute_ddr_cmd( + dmc, 0x00000000, ((ddr_info.ranks_to_train << 16) | 0x0000), 0); + + addr = 0; + switch (ddr_info.speed) { + case 800: + addr = 0x000000A0; + break; + case 1200: + addr = 0x000000A3; + break; + case 1333: + addr = 0x000000A4; + break; + default: + fwk_unexpected(); + break; + } + execute_ddr_cmd(dmc, addr, 0x0001070F, 5); + + addr = 0; + switch (ddr_info.speed) { + case 800: + addr = 0x00000311; + break; + case 1200: + addr = 0x00000339; + break; + case 1333: + addr = 0x00000347; + break; + default: + fwk_unexpected(); + break; + } + execute_ddr_cmd(dmc, addr, 0x0001070F, 5); + + execute_ddr_cmd(dmc, 0x000000DC, 0x0001070F, 0); + execute_ddr_cmd(dmc, 0x000000EC, 0x0001070F, 0); + + addr = 0; + if (ddr_info.number_of_ranks == 1) { + if (ddr_info.dimm_mem_width == 4) { + addr = 0x00000035; + } else { + addr = 0x00000030; + } + } else { + if (ddr_info.dimm_mem_width == 4) { + addr = 0x0000003A; + } else { + addr = 0x00000035; + } + } + execute_ddr_cmd(dmc, addr, 0x0001070F, 5); + + addr = 0; + if (ddr_info.number_of_ranks == 1) { + if (ddr_info.dimm_mem_width == 4) { + addr = 0x00000045; + } else { + addr = 0x00000040; + } + } else { + if (ddr_info.dimm_mem_width == 4) { + addr = 0x0000004A; + } else { + addr = 0x00000045; + } + } + execute_ddr_cmd(dmc, addr, 0x0001070F, 5); + + addr = 0; + if (ddr_info.number_of_ranks == 1) { + if (ddr_info.dimm_mem_width == 4) { + addr = 0x00000055; + } else { + addr = 0x00000050; + } + } else { + if (ddr_info.dimm_mem_width == 4) { + addr = 0x0000005A; + } else { + addr = 0x00000055; + } + } + execute_ddr_cmd(dmc, addr, 0x0001070F, 5); + execute_ddr_cmd( + dmc, 0x00000220, ((ddr_info.ranks_to_train << 16) | 0x0301), 0); + + /* MRS6 */ + addr = 0; + switch (ddr_info.speed) { + case 800: + if (ddr_info.number_of_ranks == 1) { + addr = 0x00000497; + } else { + addr = 0x000004A3; + } + break; + case 1200: + if (ddr_info.number_of_ranks == 1) { + addr = 0x00000894; + } else { + addr = 0x000008A3; + } + break; + case 1333: + if (ddr_info.number_of_ranks == 1) { + addr = 0x00000C95; + } else { + addr = 0x00000CA3; + } + break; + default: + fwk_unexpected(); + break; + } + + addr = addr | 0x00000080; + execute_ddr_cmd(dmc, addr, ((ddr_info.ranks_to_train << 16) | 0x0601), 0); + delay_ms(1); + dmc->DIRECT_CMD = ((ddr_info.ranks_to_train << 16) | 0x0601); + status = dmc_bing_poll_dmc_status(dmc); + if (status != FWK_SUCCESS) { + return status; + } + + addr = addr & 0xFFFFFF7F; + execute_ddr_cmd(dmc, addr, ((ddr_info.ranks_to_train << 16) | 0x0601), 1); + execute_ddr_cmd( + dmc, 0x00000180, ((ddr_info.ranks_to_train << 16) | 0x0501), 0); + execute_ddr_cmd( + dmc, 0x00000000, ((ddr_info.ranks_to_train << 16) | 0x0401), 0); + + addr = 0; + switch (ddr_info.speed) { + case 800: + addr = 0x00000800; + ddr_info.cwl_value = 9; + break; + case 1200: + addr = 0x00000818; + ddr_info.cwl_value = 12; + break; + case 1333: + addr = 0x00000820; + ddr_info.cwl_value = 14; + break; + default: + fwk_unexpected(); + break; + } + execute_ddr_cmd(dmc, addr, ((ddr_info.ranks_to_train << 16) | 0x0201), 0); + execute_ddr_cmd( + dmc, 0x00000003, ((ddr_info.ranks_to_train << 16) | 0x0101), 0); + + addr = 0; + switch (ddr_info.speed) { + case 800: + addr = 0x00000B10; + break; + case 1200: + addr = 0x00000B40; + break; + case 1333: + addr = 0x00000B44; + break; + default: + fwk_unexpected(); + break; + } + execute_ddr_cmd(dmc, addr, ((ddr_info.ranks_to_train << 16) | 0x0001), 0); + + addr = 0; + dimm_spd_t_wtr(&addr, &ddr_info); + dmc->T_WTR_NEXT = addr; + + for (count = 0; count < 12; count++) { + execute_ddr_cmd(dmc, 0x00000200, 0x0001000D, 0); + } + + execute_ddr_cmd( + dmc, 0x00000400, ((ddr_info.ranks_to_train << 16) | 0x0005), 0); + for (count = 0; count < 12; count++) { + execute_ddr_cmd(dmc, 0x00000200, 0x0001000D, 0); + } +#endif return FWK_SUCCESS; } -static int dmc_bing_config(struct mod_dmc_bing_reg *dmc, fwk_id_t ddr_id) +static int dmc_bing_pre_init(void) { - uint64_t mem_size; +#if defined(PLAT_FVP) + /* Fill fixed values for FVP */ + ddr_info.speed = 1333; + ddr_info.number_of_ranks = 1; + ddr_info.ranks_to_train = 1; + ddr_info.dimm_mem_width = 8; + ddr_info.cwl_value = 19; +#else int status; - FWK_LOG_INFO("[DDR] Initialising DMC-Bing at 0x%x", (uintptr_t)dmc); + FWK_LOG_INFO( + "[DDR] Starting DDR subsystem initialization at %d MHz", + ddr_info.speed); - dmc_bing_config_interrupt(ddr_id); + FWK_LOG_INFO("[DDR] Identifying connected DIMM cards..."); + status = dimm_spd_init_check(i2c_api, &ddr_info); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[DDR] Error checking DIMM SPD data: %d", status); + return status; + } + + dimm_spd_mem_info(); +#endif + return FWK_SUCCESS; +} + +#if !defined(PLAT_FVP) +static int dmc_bing_post_init(void) +{ + int status; + int i; + int j; + int count; + fwk_id_t id; + + count = + fwk_module_get_element_count(FWK_ID_MODULE(FWK_MODULE_IDX_DMC_BING)); + for (i = 0; i < count; i++) { + id = FWK_ID_ELEMENT(FWK_MODULE_IDX_DMC_BING, i); + + FWK_LOG_INFO("[DDR] Verifying PHY status for DMC %d...", i); + status = dmc_bing_verify_phy_status(id); + if (status != FWK_SUCCESS) { + return status; + } + FWK_LOG_INFO("[DDR] Done"); + } + for (i = 0; i < count; i++) { + id = FWK_ID_ELEMENT(FWK_MODULE_IDX_DMC_BING, i); + for (j = 1; j <= ddr_info.number_of_ranks; j++) { + morello_phy_obs_regs(id, j, &ddr_info); + } + } + + return FWK_SUCCESS; +} +#endif + +#if defined(PLAT_FVP) +int dmc_bing_pre_phy_init(struct mod_dmc_bing_reg *dmc) +{ FWK_LOG_INFO("[DDR] Writing functional settings"); dmc->ADDRESS_CONTROL_NEXT = 0x11040202; @@ -517,7 +1038,6 @@ static int dmc_bing_config(struct mod_dmc_bing_reg *dmc, fwk_id_t ddr_id) dmc->T_WDQLVL_RW_NEXT = 0x0000000C; dmc->RANK_REMAP_CONTROL_NEXT = 0x76543210; dmc->PHY_REQUEST_CS_REMAP = 0x76543210; - dmc->T_ODTH_NEXT = 0x00000006; dmc->ODT_TIMING_NEXT = 0x06000600; dmc->T_RW_ODT_CLR_NEXT = 0x00000010; dmc->T_CMD_NEXT = 0x00000000; @@ -546,38 +1066,290 @@ static int dmc_bing_config(struct mod_dmc_bing_reg *dmc, fwk_id_t ddr_id) dmc->ERR0CTLR0 = 0x00000400; dmc->ERR0CTLR1 = 0x000000C0; - ddr_get_dimm_size(&mem_size); + dmc->DIRECT_CMD = (ddr_info.ranks_to_train << 16) | 0x000C; + return FWK_SUCCESS; +} +#else +int dmc_bing_pre_phy_init(struct mod_dmc_bing_reg *dmc) +{ + int status = FWK_SUCCESS; + uint32_t value; + + FWK_LOG_INFO("[DDR] Writing functional settings"); - dmc->DIRECT_CMD = 0x0001000C; + value = 0; + status = dimm_spd_address_control(&value, &ddr_info); + if (status != FWK_SUCCESS) { + FWK_LOG_INFO( + "[DDR] Error code %d getting address control value from SPD", + status); + return status; + } + dmc->ADDRESS_CONTROL_NEXT = value; + /* CID, Rank, Row, Bank */ + dmc->DECODE_CONTROL_NEXT = 0x001C2800; + + value = 0; + status = dimm_spd_format_control(&value); + if (status != FWK_SUCCESS) { + FWK_LOG_INFO( + "[DDR] Error code %d getting format control value from SPD", + status); + return status; + } + dmc->FORMAT_CONTROL = value; + dmc->ADDRESS_MAP_NEXT = 0x00000002; + dmc->ADDRESS_SHUTTER_31_00_NEXT = 0x11111110; + dmc->ADDRESS_SHUTTER_63_32_NEXT = 0x11111111; + dmc->ADDRESS_SHUTTER_95_64_NEXT = 0x11111111; + dmc->ADDRESS_SHUTTER_127_96_NEXT = 0x11111111; + dmc->ADDRESS_SHUTTER_159_128_NEXT = 0x11111111; + dmc->ADDRESS_SHUTTER_191_160_NEXT = 0x00000011; + dmc->LOW_POWER_CONTROL_NEXT = 0x00000010; + dmc->MEMORY_ADDRESS_MAX_31_00_NEXT = 0xffff001f; + dmc->MEMORY_ADDRESS_MAX_43_32_NEXT = 0x0000ffff; + dmc->ACCESS_ADDRESS_NEXT[0].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[1].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[2].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[3].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[4].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[5].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[6].MIN_31_00 = 0x0000000F; + dmc->ACCESS_ADDRESS_NEXT[7].MIN_31_00 = 0x0000000F; + dmc->DCI_REPLAY_TYPE_NEXT = 0x00000000; + dmc->DIRECT_CONTROL_NEXT = 0x00000000; + dmc->DCI_STRB = 0x00000000; + + value = 0; + status = dimm_spd_memory_type(&value, &ddr_info); + if (status != FWK_SUCCESS) { + FWK_LOG_INFO( + "[DDR] Error code %d getting memory type value from SPD", status); + return status; + } + dmc->MEMORY_TYPE_NEXT = value; + dmc->FEATURE_CONFIG = 0x00001820; + + value = 0; + dimm_spd_t_refi(&value); + dmc->T_REFI_NEXT = value; + + value = 0; + dimm_spd_t_rfc(&value); + dmc->T_RFC_NEXT = value; + dmc->T_MRR_NEXT = 0x00000001; + dmc->T_MRW_NEXT = 0x00080030; + + value = 0; + dimm_spd_t_rcd(&value); + dmc->T_RCD_NEXT = value; + + value = 0; + dimm_spd_t_ras(&value); + dmc->T_RAS_NEXT = value; + + value = 0; + dimm_spd_t_rp(&value); + dmc->T_RP_NEXT = value; + dmc->T_RPALL_NEXT = 0x00000013; + + value = 0; + dimm_spd_t_rrd(&value); + dmc->T_RRD_NEXT = value; + + value = 0; + dimm_spd_t_act_window(&value); + dmc->T_ACT_WINDOW_NEXT = value; + + if ((ddr_info.speed == 1333) || (ddr_info.speed == 1200)) { + dmc->T_RTR_NEXT = 0x24090704; + } else { + dmc->T_RTR_NEXT = 0x14060604; + } + + dmc->T_RTW_NEXT = 0x001B1B1B; + dmc->T_RTP_NEXT = 0x00000008; + dmc->T_WR_NEXT = 0x00000029; + dmc->T_WTR_NEXT = 0x001B1B1B; + + if ((ddr_info.speed == 1333) || (ddr_info.speed == 1200)) { + dmc->T_WTW_NEXT = 0x24090704; + } else { + dmc->T_WTW_NEXT = 0x14060604; + } + + dmc->T_XMPD_NEXT = 0x00000480; + dmc->T_EP_NEXT = 0x00000006; + dmc->T_XP_NEXT = 0x000e0007; + dmc->T_ESR_NEXT = 0x00000007; + dmc->T_XSR_NEXT = 0x03000384; + dmc->T_ESRCK_NEXT = 0x0000000a; + dmc->T_CKXSR_NEXT = 0x0000000a; + dmc->T_PARITY_NEXT = 0x00001100; + dmc->T_ZQCS_NEXT = 0x00000090; + + switch (ddr_info.speed) { + case 800: + dmc->T_RDDATA_EN_NEXT = 0x00070007; + break; + case 1200: + dmc->T_RDDATA_EN_NEXT = 0x000E000E; + break; + case 1333: + dmc->T_RDDATA_EN_NEXT = 0x000E000E; + break; + default: + fwk_unexpected(); + break; + } + + dmc->T_PHYRDLAT_NEXT = 0x00000046; + + switch (ddr_info.speed) { + case 800: + dmc->T_PHYWRLAT_NEXT = 0x01050009; + break; + case 1200: + dmc->T_PHYWRLAT_NEXT = 0x0105000C; + break; + case 1333: + dmc->T_PHYWRLAT_NEXT = 0x010A000E; + break; + default: + fwk_unexpected(); + break; + } + + dmc->RDLVL_CONTROL_NEXT = 0x01000000; + dmc->RDLVL_MRS_NEXT = 0x00000224; + dmc->T_RDLVL_RR_NEXT = 0x0000003E; + dmc->WRLVL_CONTROL_NEXT = 0x00100000; + dmc->WRLVL_MRS_NEXT = 0x00000083; + dmc->T_WRLVL_EN_NEXT = 0x0000003E; + dmc->PHY_UPDATE_CONTROL_NEXT = 0x01401111; + dmc->T_LVL_DISCONNECT_NEXT = 0x00000001; + dmc->WDQLVL_CONTROL_NEXT = 0x00000080; + dmc->T_WDQLVL_EN_NEXT = 0x00000024; + dmc->T_WDQLVL_WW_NEXT = 0x00000006; + dmc->T_WDQLVL_RW_NEXT = 0x00000009; + dmc->ERR0CTLR1 = 0x000000D1; + dmc->RANK_REMAP_CONTROL_NEXT = 0x76543210; + dmc->PHY_REQUEST_CS_REMAP = 0x76543210; + dmc->T_ODTH_NEXT = 0x00000006; + dmc->ODT_TIMING_NEXT = 0x06000600; + dmc->T_RW_ODT_CLR_NEXT = 0x0000000f; + dmc->T_CMD_NEXT = 0x00000000; + dmc->T_RDLVL_EN_NEXT = 0x0000003E; + dmc->T_WRLVL_WW_NEXT = 0x0000003E; + dmc->PHYMSTR_CONTROL_NEXT = 0x00000000; + dmc->T_LPRESP_NEXT = 0x00000005; + dmc->ODT_WR_CONTROL_31_00_NEXT = 0x08040201; + dmc->ODT_WR_CONTROL_63_32_NEXT = 0x08040201; + dmc->ODT_RD_CONTROL_31_00_NEXT = 0x00000000; + dmc->ODT_RD_CONTROL_63_32_NEXT = 0x00000000; + dmc->ODT_CP_CONTROL_31_00_NEXT = 0x08040201; + dmc->ODT_CP_CONTROL_63_32_NEXT = 0x80402010; + dmc->CS_REMAP_CONTROL_31_00_NEXT = 0x00020001; + dmc->CS_REMAP_CONTROL_63_32_NEXT = 0x00080004; + dmc->CS_REMAP_CONTROL_95_64_NEXT = 0x00200010; + dmc->CS_REMAP_CONTROL_127_96_NEXT = 0x00800040; + dmc->CID_REMAP_CONTROL_31_00_NEXT = 0x00000000; + dmc->CID_REMAP_CONTROL_63_32_NEXT = 0x00000000; + dmc->POWER_GROUP_CONTROL_31_00_NEXT = 0x00020001; + dmc->POWER_GROUP_CONTROL_63_32_NEXT = 0x00080004; + dmc->POWER_GROUP_CONTROL_95_64_NEXT = 0x00200010; + dmc->POWER_GROUP_CONTROL_127_96_NEXT = 0x00800040; + dmc->REFRESH_CONTROL_NEXT = 0x00000000; + dmc->T_DB_TRAIN_RESP_NEXT = 0x00000004; + dmc->FEATURE_CONTROL_NEXT = 0x0aa30000; + dmc->MUX_CONTROL_NEXT = 0x00000000; + dmc->LOW_POWER_CONTROL_NEXT = 0x00000010; + dmc->MEMORY_ADDRESS_MAX_31_00_NEXT = 0xffff001f; + dmc->INTERRUPT_CONTROL = 0x00000070; + dmc->ERR0CTLR0 = 0x00000000; + dmc->ERR0CTLR1 = 0x000000D1; + dmc->CAPABILITY_CTRL = 0; + + dmc->DIRECT_CMD = (ddr_info.ranks_to_train << 16) | 0x000C; + return status; +} +#endif + +static int dmc_bing_config(struct mod_dmc_bing_reg *dmc, fwk_id_t ddr_id) +{ + int status; + int dmc_id; + + dmc_id = fwk_id_get_element_idx(ddr_id); + if (dmc_id == 0) { + status = dmc_bing_pre_init(); + if (status != FWK_SUCCESS) { + return status; + } + } + + FWK_LOG_INFO("[DDR] Initialising DMC-Bing at 0x%x", (uintptr_t)dmc); + + dmc_bing_config_interrupt(ddr_id); + dmc_bing_pre_phy_init(dmc); dmc->USER_CONFIG0_NEXT = 0x1; dmc->MEMC_CMD = MOD_DMC_BING_MEMC_CMD_GO; while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_CMD) != - MOD_DMC_BING_MEMC_CMD_GO) + MOD_DMC_BING_MEMC_CMD_GO) { continue; + } + +#if !defined(PLAT_FVP) + status = morello_ddr_phy_config(ddr_id, &ddr_info); + if (status != FWK_SUCCESS) { + return status; + } +#endif dmc->MEMC_CMD = MOD_DMC_BING_MEMC_CMD_CONFIG; while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_CMD) != - MOD_DMC_BING_MEMC_CMD_CONFIG) + MOD_DMC_BING_MEMC_CMD_CONFIG) { continue; + } + dmc->USER_CONFIG0_NEXT = 0x3; dmc->MEMC_CMD = MOD_DMC_BING_MEMC_CMD_GO; while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_CMD) != - MOD_DMC_BING_MEMC_CMD_GO) + MOD_DMC_BING_MEMC_CMD_GO) { continue; + } + dmc->MEMC_CMD = MOD_DMC_BING_MEMC_CMD_CONFIG; while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_CMD) != - MOD_DMC_BING_MEMC_CMD_CONFIG) + MOD_DMC_BING_MEMC_CMD_CONFIG) { continue; + } FWK_LOG_INFO("[DDR] Sending direct DDR commands"); - direct_ddr_cmd(dmc); + status = direct_ddr_cmd(dmc); + if (status != FWK_SUCCESS) { + return status; + } + +#if !defined(PLAT_FVP) + status = ddr_training(dmc, ddr_id, &ddr_info); + if (status != FWK_SUCCESS) { + return status; + } + + status = morello_ddr_phy_post_training_configure(ddr_id, &ddr_info); + if (status != FWK_SUCCESS) { + return status; + } +#endif FWK_LOG_INFO("[DDR] Enable DIMM refresh..."); status = enable_dimm_refresh(dmc); - if (status != FWK_SUCCESS) + if (status != FWK_SUCCESS) { return status; + } /* Switch to READY */ FWK_LOG_INFO("[DDR] Setting DMC to READY mode"); @@ -585,11 +1357,21 @@ static int dmc_bing_config(struct mod_dmc_bing_reg *dmc, fwk_id_t ddr_id) dmc->MEMC_CMD = MOD_DMC_BING_MEMC_CMD_GO; while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_CMD) != - MOD_DMC_BING_MEMC_CMD_GO) + MOD_DMC_BING_MEMC_CMD_GO) { continue; + } FWK_LOG_INFO("[DDR] DMC init done."); +#if !defined(PLAT_FVP) + if (dmc_id == 1) { + status = dmc_bing_post_init(); + if (status != FWK_SUCCESS) { + return status; + } + } +#endif + return FWK_SUCCESS; } @@ -599,6 +1381,13 @@ static int mod_dmc_bing_init( unsigned int element_count, const void *config) { +#if !defined(PLAT_FVP) + struct mod_dmc_bing_module_config *mod_config = + (struct mod_dmc_bing_module_config *)config; + + ddr_info.speed = mod_config->ddr_speed; +#endif + return FWK_SUCCESS; } @@ -614,18 +1403,36 @@ static int mod_dmc_bing_element_init( static int mod_dmc_bing_bind(fwk_id_t id, unsigned int round) { + int status; + /* Nothing to do in the second round of calls. */ - if (round == 1) + if (round == 1) { return FWK_SUCCESS; + } /* Nothing to do in case of elements. */ - if (fwk_module_is_valid_element_id(id)) + if (fwk_module_is_valid_element_id(id)) { return FWK_SUCCESS; + } - return fwk_module_bind( + status = fwk_module_bind( FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), FWK_ID_API(FWK_MODULE_IDX_TIMER, MOD_TIMER_API_IDX_TIMER), &timer_api); + if (status != FWK_SUCCESS) { + return status; + } + +#if !defined(PLAT_FVP) + status = fwk_module_bind( + FWK_ID_MODULE(FWK_MODULE_IDX_CDNS_I2C), + FWK_ID_API(FWK_MODULE_IDX_CDNS_I2C, MOD_CDNS_I2C_API_MASTER_POLLED), + &i2c_api); + if (status != FWK_SUCCESS) { + return status; + } +#endif + return FWK_SUCCESS; } static int mod_dmc_bing_process_bind_request( @@ -685,8 +1492,9 @@ static int mod_dmc_bing_process_notification( params = (struct clock_notification_params *)event->params; - if (params->new_state == MOD_CLOCK_STATE_RUNNING) + if (params->new_state == MOD_CLOCK_STATE_RUNNING) { return dmc_bing_notify_system_state_transition_resume(event->target_id); + } return FWK_SUCCESS; } diff --git a/product/morello/module/dmc_bing/src/morello_ddr_phy.c b/product/morello/module/dmc_bing/src/morello_ddr_phy.c new file mode 100644 index 000000000..5d39daf27 --- /dev/null +++ b/product/morello/module/dmc_bing/src/morello_ddr_phy.c @@ -0,0 +1,998 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Morello DDR-PHY driver + */ + +#include "morello_scp_mmap.h" + +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define NUM_SLICES 9 +#define NUM_BITS_PER_SLICE 8 +#define NUM_DATA_PATTERNS 5 +#define DCI_FIFO_SIZE 20 + +#define NUM_DQ_BITS (NUM_SLICES) * (NUM_BITS_PER_SLICE) +#define NUM_DFI_BEATS_TO_CHECK UINT32_C(4) + +#define SLICE_MASK (~(UINT32_C(0xFFFFFFFF) << (NUM_BITS_PER_SLICE))) + +#define NUM_WORDS_IN_DFI_BEAT UINT32_C(5) + +#define BIT_WRRD_SUCCESS ((NUM_DATA_PATTERNS) * (NUM_DFI_BEATS_TO_CHECK)*2) + +#define PHY_PER_CS_TRAINING_INDEX_0_REG_IDX UINT32_C(9) +#define PHY_CLK_WRDQ0_SLAVE_DELAY_0_REG_IDX UINT32_C(82) +#define SC_PHY_MANUAL_UPDATE_REG_IDX UINT32_C(2310) + +struct wrdq_eye { + uint16_t min; + uint8_t min_found; + uint16_t max; + uint8_t max_found; + uint16_t mid; + uint16_t width; +}; + +uint32_t wr_data_all[NUM_DATA_PATTERNS][DCI_FIFO_SIZE] = { + { + 0x0, 0x0, 0x0, 0x0, 0x0000, 0x0, 0x0, 0x0, 0x0, 0x0000, + 0x0, 0x0, 0x0, 0x0, 0x0000, 0x0, 0x0, 0x0, 0x0, 0x0000, + }, + { + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF, + }, + { + 0x0, 0x0, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF00, + 0x0, 0x0, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF00, + 0x0, 0x0, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF00, + 0x0, 0x0, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF00, + }, + { + 0xFFFFFFFF, 0xFFFFFFFF, 0x0, 0x0, 0x00FF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x0, 0x0, 0x00FF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x0, 0x0, 0x00FF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x0, 0x0, 0x00FF, + }, + { + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0x5AA5, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0x5AA5, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0x5AA5, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0x5AA5, + } +}; + +struct slice_eye_stat { + uint16_t min_width; + int16_t median_mid; +}; + +struct wrdq_eye wrdq_eyes[NUM_SLICES][NUM_BITS_PER_SLICE]; +struct wrdq_eye best_wrdq_eyes[NUM_SLICES][NUM_BITS_PER_SLICE]; +uint16_t cur_wrdq_delays[NUM_SLICES][NUM_BITS_PER_SLICE]; + +struct slice_eye_stat slice_eye_stats[NUM_SLICES]; +struct slice_eye_stat best_slice_eye_stats[NUM_SLICES]; +int16_t sorted_mids[NUM_BITS_PER_SLICE]; +uint32_t *wr_data; +uint32_t rd_data[DCI_FIFO_SIZE]; +uint8_t wrrd_passes[NUM_SLICES][NUM_BITS_PER_SLICE]; +uint16_t DEFAULT_DELAY_V2 = 0x240; + +/* + * Functions fulfilling this module's interface + */ +int morello_ddr_phy_config(fwk_id_t element_id, struct dimm_info *info) +{ + int element_idx; + struct mod_morello_ddr_phy_reg *ddr_phy; + const struct mod_dmc_bing_element_config *element_config; + + fwk_assert(info != NULL); + + element_idx = fwk_id_get_element_idx(element_id); + element_config = fwk_module_get_data(element_id); + + ddr_phy = (struct mod_morello_ddr_phy_reg *)element_config->ddr_phy_base; + + FWK_LOG_INFO( + "[DDR-PHY] Initializing PHY at 0x%p for %" PRIu16 " MHz speed", + (const void *)ddr_phy, + info->speed); + + switch (info->speed) { + case 1333: + ddr_phy_config_1333(ddr_phy, info, element_idx); + break; + case 1200: + ddr_phy_config_1200(ddr_phy, info, element_idx); + break; + case 800: + ddr_phy_config_800(ddr_phy, info); + break; + default: + FWK_LOG_INFO("[DDR-PHY] Unsupported frequency!"); + break; + } + + return FWK_SUCCESS; +} + +uint32_t dci_write_dram( + struct mod_dmc_bing_reg *dmc, + uint32_t *scp_address, + uint32_t size_32, + uint32_t rank, + uint32_t bank) +{ + uint32_t count; + uint8_t rank_1_hot = (1 << rank); + + /* Confirm that DMC is in config state */ + if ((dmc->MEMC_STATUS & 0x7) != 0x0) { + FWK_LOG_ERR("DMC needs to be in config state"); + return FWK_E_STATE; + } + + /* Clear DCI write FIFO */ + dmc->DIRECT_ADDR = 0x00000002; + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x000B; + + while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS_MGR_ACTIVE) != 0) { + ; + } + + /* Set DCI_STRB */ + dmc->DCI_STRB = 0x0000000F; + + /* Issue precharge direct command */ + dmc->DIRECT_ADDR = 0x00000010; + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x0002; + dmc->DIRECT_ADDR = 0x00000000; + + /* Fill the write buffer */ + for (count = 0; count < size_32; count++) { + dmc->DCI_DATA = scp_address[count]; + } + + /* Set the column address to 0 */ + dmc->DIRECT_ADDR = 0x00000000; + + /* Issue ACTIVATE command */ + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x0009; + + /* Issue WRITE command */ + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x0008; + + while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS_MGR_ACTIVE) != 0) { + ; + } + + /* Issue precharge direct command */ + dmc->DIRECT_ADDR = 0x00000010; + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x0002; + dmc->DIRECT_ADDR = 0x00000000; + + while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS_MGR_ACTIVE) != 0) { + ; + } + + return FWK_SUCCESS; +} + +uint32_t dci_read_dram( + struct mod_dmc_bing_reg *dmc, + uint32_t *scp_address, + uint32_t size_32, + uint32_t rank, + uint32_t bank) +{ + uint32_t count = 0; + uint8_t rank_1_hot = (1 << rank); + + /* Confirm that DMC is in config state */ + if ((dmc->MEMC_STATUS & 0x7) != 0x0) { + FWK_LOG_INFO("DMC needs to be in config state"); + return FWK_E_PARAM; + } + + /* Clear DCI read FIFO */ + dmc->DIRECT_ADDR = 0x00000004; + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x000B; + + /* Issue ACTIVATE command */ + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x0009; + + /* Issue READ command */ + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x0007; + + while ((dmc->MEMC_STATUS & MOD_DMC_BING_MEMC_STATUS_MGR_ACTIVE) != 0) { + ; + } + + /* Copy read data back to buffer */ + for (count = 0; count < size_32; count++) { + scp_address[count] = dmc->DCI_DATA; + } + + /* Issue precharge direct command */ + dmc->DIRECT_ADDR = 0x00000010; + dmc->DIRECT_CMD = (rank_1_hot << 16) | 0x0002; + dmc->DIRECT_ADDR = 0x00000000; + + return FWK_SUCCESS; +} + +int write_eye_detect_single_rank( + fwk_id_t element_id, + struct dimm_info *info, + uint32_t rank, + uint32_t delay_increment, + uint32_t vrefdq_increment, + uint32_t dbg_level) +{ + const uint16_t DELAY_MIN = 0x0; + const uint16_t DELAY_MAX = 0x7FF; + uint16_t DELAY_INCR = delay_increment; + + uint32_t orig_training_idx_vals[NUM_SLICES]; + + bool sweep_vrefdq = (vrefdq_increment != 0); + bool no_bits_pass; + + uint32_t ret_code = FWK_SUCCESS; + uint32_t analysis_ret_code = FWK_SUCCESS; + uint32_t denali_index = 0; + uint32_t sc_phy_manual_update_reg_val = 0; + uint32_t reg_val = 0; + uint32_t wait_ms = 1; + + const int16_t MIN_VREFDQ_MR6 = 0x0; + const int16_t MAX_VREFDQ_MR6 = 0x32; + int16_t best_vrefdq_mr6 = -1; + int32_t direction; + uint32_t num_completed; + int32_t delay; + uint32_t data_pattern; + uint32_t i; + uint32_t dfi_beat; + uint32_t dfi_beat_word_offset; + uint32_t dqs_edge; + int16_t vrefdq_mr6; + uint32_t slice; + uint32_t bit; + uint32_t rd_val; + uint32_t wr_val; + uint32_t eye_a_mid; + uint32_t eye_b_mid; + struct wrdq_eye *eye = NULL; + struct wrdq_eye *eye_b = NULL; + uint32_t wr_slice_data; + uint32_t rd_slice_data; + uint32_t start_bit; + uint32_t word_num; + uint32_t wr_bit; + uint32_t rd_bit; + uint16_t min_width; + uint32_t num_good_eyes_in_slice; + uint32_t better_slices; + + uint32_t speed; + uint32_t range; + uint32_t tccd_l; + uint32_t direct_addr; + uint32_t direct_cmd; + int dmc_id; + int s; + int t; + struct mod_dmc_bing_reg *dmc = NULL; + uint32_t ddr_phy_base = 0; + + fwk_assert(rank < 2); + dmc_id = fwk_id_get_element_idx(element_id); + if (dmc_id == 0) { + dmc = (struct mod_dmc_bing_reg *)SCP_DMC0; + ddr_phy_base = SCP_DDR_PHY0; + } else if (dmc_id == 1) { + dmc = (struct mod_dmc_bing_reg *)SCP_DMC1; + ddr_phy_base = SCP_DDR_PHY1; + } else { + fwk_unexpected(); + } + + best_vrefdq_mr6 = -1; + for (slice = 0; slice < NUM_SLICES; slice++) { + best_slice_eye_stats[slice].min_width = 0; + best_slice_eye_stats[slice].median_mid = 0; + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { + best_wrdq_eyes[slice][bit].min = DELAY_MAX; + best_wrdq_eyes[slice][bit].min_found = 0; + best_wrdq_eyes[slice][bit].max = DELAY_MIN; + best_wrdq_eyes[slice][bit].max_found = 0; + best_wrdq_eyes[slice][bit].mid = 0; + best_wrdq_eyes[slice][bit].width = 0; + } + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + rd_val = 0; + wr_val = 0; + denali_index = PHY_PER_CS_TRAINING_INDEX_0_REG_IDX + (slice * 256); + rd_val = *(uint32_t *)(ddr_phy_base + (4 * denali_index)); + orig_training_idx_vals[slice] = rd_val; + wr_val = (rank << 16) | (rd_val & 0xFFFFCFEFF); + *(uint32_t *)(ddr_phy_base + (4 * denali_index)) = wr_val; + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit += 2) { + rd_val = 0; + denali_index = (PHY_CLK_WRDQ0_SLAVE_DELAY_0_REG_IDX + (bit / 2)) + + (slice * 256); + rd_val = *(uint32_t *)(ddr_phy_base + (4 * denali_index)); + } + } + + sc_phy_manual_update_reg_val = + *(uint32_t *)(ddr_phy_base + (4 * SC_PHY_MANUAL_UPDATE_REG_IDX)); + + speed = info->speed; + range = 1; + tccd_l = (speed == 800) ? 1 : (speed == 1200) ? 2 : 3; + direct_addr = (tccd_l << 10) | (1 << 7) | (range - 1) << 6; + direct_cmd = ((1 << rank) << 16) | (0x6 << 8) | 1; + + if (sweep_vrefdq) { + dmc->DIRECT_ADDR = direct_addr; + dmc->DIRECT_CMD = direct_cmd; + delay_ms(wait_ms); + } + + for (vrefdq_mr6 = MIN_VREFDQ_MR6; vrefdq_mr6 <= MAX_VREFDQ_MR6; + vrefdq_mr6 += vrefdq_increment) { + if (sweep_vrefdq) { + direct_addr = (direct_addr & 0xFFFFFFC0) | vrefdq_mr6; + dmc->DIRECT_ADDR = direct_addr; + dmc->DIRECT_CMD = direct_cmd; + delay_ms(wait_ms); + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { + wrdq_eyes[slice][bit].min = DELAY_MAX; + wrdq_eyes[slice][bit].min_found = 0; + wrdq_eyes[slice][bit].max = DELAY_MIN; + wrdq_eyes[slice][bit].max_found = 0; + wrdq_eyes[slice][bit].mid = 0; + wrdq_eyes[slice][bit].width = 0; + } + } + + for (direction = -1; direction < 2; direction += 2) { + num_completed = 0; + delay = DEFAULT_DELAY_V2; + while (num_completed != NUM_DQ_BITS) { + if ((delay < DELAY_MIN) || (delay > DELAY_MAX)) { + break; + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { + cur_wrdq_delays[slice][bit] = delay; + if (bit % 2 == 1) { + reg_val = (cur_wrdq_delays[slice][bit] & 0x7FF) + << 16; + reg_val |= + (cur_wrdq_delays[slice][bit - 1] & 0x7FF); + denali_index = + (PHY_CLK_WRDQ0_SLAVE_DELAY_0_REG_IDX + + (bit / 2)) + + (slice * 256); + *(uint32_t *)(ddr_phy_base + (4 * denali_index)) = + reg_val; + } + } + } + + delay_ms(wait_ms); + sc_phy_manual_update_reg_val |= 1; + *(uint32_t + *)(ddr_phy_base + (4 * SC_PHY_MANUAL_UPDATE_REG_IDX)) = + sc_phy_manual_update_reg_val; + + (void)memset(wrrd_passes, 0, sizeof(uint8_t) * NUM_DQ_BITS); + + for (data_pattern = 0; data_pattern < NUM_DATA_PATTERNS; + data_pattern++) { + wr_data = wr_data_all[data_pattern]; + ret_code = + dci_write_dram(dmc, wr_data, DCI_FIFO_SIZE, rank, 0); + if (ret_code != FWK_SUCCESS) { + return ret_code; + } + ret_code = + dci_read_dram(dmc, rd_data, DCI_FIFO_SIZE, rank, 0); + if (ret_code != FWK_SUCCESS) { + return ret_code; + } + + for (dfi_beat = 0; dfi_beat < NUM_DFI_BEATS_TO_CHECK; + dfi_beat++) { + dfi_beat_word_offset = + (dfi_beat * NUM_WORDS_IN_DFI_BEAT); + for (dqs_edge = 0; dqs_edge < 2; dqs_edge++) { + no_bits_pass = true; + for (slice = 0; slice < NUM_SLICES; slice++) { + start_bit = (dqs_edge * 64) + + (slice * NUM_BITS_PER_SLICE); + + if (slice == NUM_SLICES - 1) { + start_bit += (dqs_edge % 2 == 0) ? 64 : 8; + } + + word_num = + (start_bit / 32) + dfi_beat_word_offset; + wr_slice_data = + (wr_data[word_num] >> (start_bit % 32)) & + SLICE_MASK; + rd_slice_data = + (rd_data[word_num] >> (start_bit % 32)) & + SLICE_MASK; + + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { + wr_bit = (wr_slice_data >> bit) & 0x1; + rd_bit = (rd_slice_data >> bit) & 0x1; + if (wr_bit == rd_bit) { + wrrd_passes[slice][bit]++; + no_bits_pass = false; + } + } + } + + if (dbg_level == 0 && no_bits_pass) { + dqs_edge = 2; + dfi_beat = NUM_DFI_BEATS_TO_CHECK; + data_pattern = NUM_DATA_PATTERNS; + break; + } + } + } + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { + if (((direction < 0) && + (wrdq_eyes[slice][bit].min_found == 1)) || + ((direction > 0) && + (wrdq_eyes[slice][bit].max_found == 1))) { + continue; + } + + if (wrrd_passes[slice][bit] == BIT_WRRD_SUCCESS) { + if (direction < 0) { + if (cur_wrdq_delays[slice][bit] < + wrdq_eyes[slice][bit].min) { + wrdq_eyes[slice][bit].min = + cur_wrdq_delays[slice][bit]; + } + } else if (direction > 0) { + if (cur_wrdq_delays[slice][bit] > + wrdq_eyes[slice][bit].max) { + wrdq_eyes[slice][bit].max = + cur_wrdq_delays[slice][bit]; + } + } + } else { + if ((direction < 0) && + (wrdq_eyes[slice][bit].min != DELAY_MAX)) { + wrdq_eyes[slice][bit].min_found = 1; + num_completed++; + } + if ((direction > 0) && + (wrdq_eyes[slice][bit].max != DELAY_MIN)) { + wrdq_eyes[slice][bit].max_found = 1; + num_completed++; + } + } + } + } + delay += (direction * DELAY_INCR); + } + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + min_width = DELAY_MAX; + num_good_eyes_in_slice = 0; + for (i = 0; i < NUM_BITS_PER_SLICE; i++) { + sorted_mids[i] = DELAY_MAX; + } + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { + eye = &wrdq_eyes[slice][bit]; + if (!eye->min_found && !eye->max_found) { + break; + } + eye->width = eye->max - eye->min; + if (eye->width < min_width) { + min_width = eye->width; + } + + eye->mid = (eye->min + eye->max) / 2; + for (s = 0; s < (int)NUM_BITS_PER_SLICE; s++) { + if (eye->mid < sorted_mids[s]) { + for (t = num_good_eyes_in_slice - 1; t >= 0; t--) { + sorted_mids[t + 1] = sorted_mids[t]; + } + sorted_mids[s] = eye->mid; + break; + } + } + num_good_eyes_in_slice++; + } + slice_eye_stats[slice].min_width = + (min_width == DELAY_MAX) ? 0 : min_width; + slice_eye_stats[slice].median_mid = + sorted_mids[(num_good_eyes_in_slice + 1) / 2]; + } + + better_slices = 0; + for (slice = 0; slice < NUM_SLICES; slice++) { + if (slice_eye_stats[slice].min_width > + best_slice_eye_stats[slice].min_width) { + better_slices++; + } + } + if (better_slices == NUM_SLICES) { + best_vrefdq_mr6 = vrefdq_mr6; + (void)memcpy( + best_wrdq_eyes, + wrdq_eyes, + sizeof(struct wrdq_eye) * NUM_SLICES * NUM_BITS_PER_SLICE); + (void)memcpy( + best_slice_eye_stats, + slice_eye_stats, + sizeof(struct slice_eye_stat) * NUM_SLICES); + } + if (!sweep_vrefdq) { + break; + } + } + + if (best_vrefdq_mr6 != -1) { + for (slice = 0; slice < NUM_SLICES; slice++) { + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { + eye = &best_wrdq_eyes[slice][bit]; + if (eye->max == 0) { + analysis_ret_code = FWK_E_RANGE; + } + } + } + } + + if (best_vrefdq_mr6 == -1) { + analysis_ret_code = FWK_E_RANGE; + direct_addr &= 0xFFFFFF7F; + dmc->DIRECT_ADDR = direct_addr; + dmc->DIRECT_CMD = direct_cmd; + delay_ms(wait_ms); + } else { + if (sweep_vrefdq) { + direct_addr = (direct_addr & 0xFFFFFFC0) | best_vrefdq_mr6; + dmc->DIRECT_ADDR = direct_addr; + dmc->DIRECT_CMD = direct_cmd; + delay_ms(wait_ms); + direct_addr &= 0xFFFFFF7F; + dmc->DIRECT_ADDR = direct_addr; + dmc->DIRECT_CMD = direct_cmd; + delay_ms(wait_ms); + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + for (bit = 0; bit < NUM_BITS_PER_SLICE; bit += 2) { + eye = &best_wrdq_eyes[slice][bit]; + eye_a_mid = eye->mid; + eye_b = &best_wrdq_eyes[slice][bit + 1]; + eye_b_mid = eye_b->mid; + reg_val = (eye_b_mid << 16) | eye_a_mid; + denali_index = + (PHY_CLK_WRDQ0_SLAVE_DELAY_0_REG_IDX + (bit / 2)) + + (slice * 256); + *(uint32_t *)(ddr_phy_base + (4 * denali_index)) = reg_val; + } + } + + delay_ms(wait_ms); + sc_phy_manual_update_reg_val |= 1; + *(uint32_t *)(ddr_phy_base + (4 * SC_PHY_MANUAL_UPDATE_REG_IDX)) = + sc_phy_manual_update_reg_val; + } + + for (slice = 0; slice < NUM_SLICES; slice++) { + wr_val = 0; + denali_index = PHY_PER_CS_TRAINING_INDEX_0_REG_IDX + (slice * 256); + wr_val = orig_training_idx_vals[slice]; + *(uint32_t *)(ddr_phy_base + (4 * denali_index)) = wr_val; + } + + if (ret_code != FWK_SUCCESS) { + return ret_code; + } + + return analysis_ret_code; +} + +int write_eye_detect( + fwk_id_t element_id, + struct dimm_info *info, + uint32_t rank_sel, + uint32_t delay_increment, + uint32_t vrefdq_increment, + uint32_t dbg_level) +{ + uint32_t start_rank; + uint32_t stop_rank; + uint32_t rank; + int status = FWK_SUCCESS; + + if (((int)rank_sel > (info->number_of_ranks - 1)) && (rank_sel != 0xF)) { + FWK_LOG_INFO("[DDR-PHY] Invalid rank parameter %" PRIu32, rank_sel); + return FWK_E_PARAM; + } + + if (rank_sel == 0xF) { + start_rank = 0; + stop_rank = info->number_of_ranks - 1; + } else { + start_rank = rank_sel; + stop_rank = rank_sel; + } + + for (rank = start_rank; rank <= stop_rank; rank++) { + status = write_eye_detect_single_rank( + element_id, + info, + rank, + delay_increment, + vrefdq_increment, + dbg_level); + if (status != FWK_SUCCESS) { + FWK_LOG_INFO( + "[DDR-PHY] WET single rank failed with error %d", status); + break; + } + } + + return status; +} + +int morello_ddr_phy_post_training_configure( + fwk_id_t element_id, + struct dimm_info *info) +{ + int status; + const struct mod_dmc_bing_element_config *element_config; + uint32_t phy_addr; + + fwk_assert(info != NULL); + + element_config = fwk_module_get_data(element_id); + phy_addr = (uint32_t)element_config->ddr_phy_base; + + (void)(phy_addr); + FWK_LOG_INFO("[DDR-PHY] Post training PHY setting at 0x%" PRIX32, phy_addr); + + if (info->speed >= 1333) { + FWK_LOG_INFO("[DDR-PHY] Performing write eye training..."); + status = write_eye_detect(element_id, info, 0xF, 0x4, 0x2, 0); + if (status != FWK_SUCCESS) { + FWK_LOG_INFO("[DDR-PHY] FAIL!"); + return status; + } + FWK_LOG_INFO("[DDR-PHY] PASS!"); + } + + return FWK_SUCCESS; +} + +int morello_verify_phy_status( + fwk_id_t element_id, + uint8_t training_type, + struct dimm_info *info) +{ + const struct mod_dmc_bing_element_config *element_config; + uint32_t i; + uint32_t j; + uint32_t h; + uint32_t phy_base; + uint32_t value1; + uint32_t value2; + uint32_t num_slices; + + fwk_assert(info != NULL); + + element_config = fwk_module_get_data(element_id); + phy_base = (uint32_t)element_config->ddr_phy_base; + num_slices = 18; + + for (h = 0; h < info->number_of_ranks; h++) { + switch (training_type) { + case DDR_ADDR_TRAIN_TYPE_WR_LVL: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))); + value1 = (value1 & 0xFFFCFFFF) | (h << 16); + *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (41 + (i * 256)))); + value2 = *(uint32_t *)(phy_base + (4 * (42 + (i * 256)))); + if (((value1 >> 16) >= 0x0200) || + ((value2 & 0x0000FFFF) >= 0x200)) { + FWK_LOG_INFO( + "[DDR-PHY] PHY 0x%" PRIX32 + " : Invalid Hard0/Hard 1 " + "value found for slice %" PRIu32, + phy_base, + i); + } + } + break; + case DDR_ADDR_TRAIN_TYPE_RD_GATE: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))); + value1 = (value1 & 0xFFFCFFFF) | (h << 16); + *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (46 + (i * 256)))); + if ((value1 != 0x003C) && + ((info->dimm_mem_width == 4) && (value1 != 0x13C))) { + FWK_LOG_INFO( + "[DDR-PHY] PHY 0x%" PRIX32 + " : Final read gate training" + " status != 0x003C for slice %" PRIu32, + phy_base, + i); + } + } + break; + case DDR_ADDR_TRAIN_TYPE_RD_EYE: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))); + value1 = (value1 & 0xFFFCFFFF) | (h << 16); + *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + for (j = 0; j < num_slices; j++) { + value1 = *(uint32_t *)(phy_base + (4 * (34 + (i * 256)))); + if (j <= 16) { + value1 = (value1 & 0xFF00FFFF) | (j << 16); + } else { + value1 = (value1 & 0xFF00FFFF) | (0x18 << 16); + } + + *(uint32_t *)(phy_base + (4 * (34 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (47 + (i * 256)))); + if ((value1 & 0x0000FFFF) > 0x0180) { + FWK_LOG_INFO( + "[DDR-PHY] PHY 0x%" PRIX32 " : slice %" PRIu32 + " phy_rdlvl_rddqs_dq_le_dly_obs_%" PRIu32 + " is > 0x180", + phy_base, + j, + i); + } + if ((value1 >> 16) > 0x0180) { + FWK_LOG_INFO( + "[DDR-PHY] PHY 0x%" PRIX32 " : slice %" PRIu32 + " phy_rdlvl_rddqs_dq_te_dly_obs_%" PRIu32 + " is > 0x180", + phy_base, + j, + i); + } + value1 = *(uint32_t *)(phy_base + (4 * (49 + (i * 256)))); + if ((value1 >> 16) != 0x0C00) { + FWK_LOG_INFO( + "[DDR-PHY] PHY 0x%" PRIX32 + " : Final read data eye " + "training " + "status != 0x0C00 for slice %" PRIu32, + phy_base, + i); + } + } + } + break; + case DDR_ADDR_TRAIN_TYPE_VREF: + for (i = 0; i < 9; i++) { + value1 = *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))); + value1 = (value1 & 0xFFFCFFFF) | (h << 16); + *(uint32_t *)(phy_base + (4 * (9 + (i * 256)))) = value1; + value1 = *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))); + value1 = (value1 & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_base + (4 * (17 + (i * 256)))) = value1; + } + break; + default: + return FWK_E_STATE; + break; + } + } + return FWK_SUCCESS; +} + +int morello_wrlvl_phy_obs_regs( + fwk_id_t element_id, + uint32_t rank, + struct dimm_info *info) +{ + const struct mod_dmc_bing_element_config *element_config; + uint32_t i; + uint32_t j; + uint32_t h; + uint32_t phy_addr; + uint32_t value; + uint32_t rank_start; + uint32_t rank_end; + + fwk_assert(info != NULL); + + element_config = fwk_module_get_data(element_id); + phy_addr = (uint32_t)element_config->ddr_phy_base; + + if (rank == 0) { + rank_start = 0; + rank_end = info->number_of_ranks; + } else { + rank_start = rank - 1; + rank_end = rank; + } + + for (h = rank_start; h < rank_end; h++) { + for (i = 0; i < 9; i++) { + value = *(uint32_t *)(phy_addr + (4 * (9 + (i * 256)))); + value = (value & 0xFFFCFFFF) | (h << 16); + *(uint32_t *)(phy_addr + (4 * (9 + (i * 256)))) = value; + value = *(uint32_t *)(phy_addr + (4 * (17 + (i * 256)))); + value = (value & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_addr + (4 * (17 + (i * 256)))) = value; + + for (j = 0; j < 10; j++) { + value = *(uint32_t *)(phy_addr + (4 * (31 + (i * 256)))); + value = (value & 0xFFFF00FF) | (j << 8); + *(uint32_t *)(phy_addr + (4 * (31 + (i * 256)))) = value; + } + for (j = 0; j < 10; j++) { + value = *(uint32_t *)(phy_addr + (4 * (31 + (i * 256)))); + value = (value & 0xFFF0FFFF) | (j << 16); + *(uint32_t *)(phy_addr + (4 * (31 + (i * 256)))) = value; + } + } + } + return FWK_SUCCESS; +} + +int morello_read_gate_phy_obs_regs( + fwk_id_t element_id, + uint32_t rank, + struct dimm_info *info) +{ + const struct mod_dmc_bing_element_config *element_config; + uint32_t i; + uint32_t h; + uint32_t phy_addr; + uint32_t value; + uint32_t rank_start; + uint32_t rank_end; + + fwk_assert(info != NULL); + + element_config = fwk_module_get_data(element_id); + phy_addr = (uint32_t)element_config->ddr_phy_base; + + if (rank == 0) { + rank_start = 0; + rank_end = info->number_of_ranks; + } else { + rank_start = rank - 1; + rank_end = rank; + } + + for (h = rank_start; h < rank_end; h++) { + for (i = 0; i < 9; i++) { + value = *(uint32_t *)(phy_addr + (4 * (9 + (i * 256)))); + value = (value & 0xFFFCFFFF) | (h << 16); + *(uint32_t *)(phy_addr + (4 * (9 + (i * 256)))) = value; + value = *(uint32_t *)(phy_addr + (4 * (17 + (i * 256)))); + value = (value & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_addr + (4 * (17 + (i * 256)))) = value; + } + } + return FWK_SUCCESS; +} + +int morello_read_eye_phy_obs_regs(fwk_id_t element_id, struct dimm_info *info) +{ + const struct mod_dmc_bing_element_config *element_config; + uint32_t i; + uint32_t j; + uint32_t h; + uint32_t phy_addr; + uint32_t value; + uint32_t num_dq_slices = 18; + + fwk_assert(info != NULL); + + element_config = fwk_module_get_data(element_id); + phy_addr = (uint32_t)element_config->ddr_phy_base; + + for (h = 0; h < info->number_of_ranks; h++) { + for (i = 0; i < 9; i++) { + value = *(uint32_t *)(phy_addr + (4 * (9 + (i * 256)))); + value = (value & 0xFFFCFFFF) | (h << 16); + *(uint32_t *)(phy_addr + (4 * (9 + (i * 256)))) = value; + value = *(uint32_t *)(phy_addr + (4 * (17 + (i * 256)))); + value = (value & 0xFFFF00FF) | 0x100; + *(uint32_t *)(phy_addr + (4 * (17 + (i * 256)))) = value; + for (j = 0; j < num_dq_slices; j++) { + value = *(uint32_t *)(phy_addr + (4 * (34 + (i * 256)))); + if (j <= 16) { + value = (value & 0xFF00FFFF) | (j << 16); + } else { + value = (value & 0xFF00FFFF) | (0x18 << 16); + } + + *(uint32_t *)(phy_addr + (4 * (34 + (i * 256)))) = value; + } + } + } + return FWK_SUCCESS; +} + +int morello_phy_obs_regs( + fwk_id_t element_id, + uint32_t rank, + struct dimm_info *info) +{ + int status; + + status = morello_wrlvl_phy_obs_regs(element_id, rank, info); + if (status != FWK_SUCCESS) { + return status; + } + + status = morello_read_gate_phy_obs_regs(element_id, rank, info); + if (status != FWK_SUCCESS) { + return status; + } + + return morello_read_eye_phy_obs_regs(element_id, info); +} diff --git a/product/morello/module/dmc_bing/src/morello_ddr_phy.h b/product/morello/module/dmc_bing/src/morello_ddr_phy.h new file mode 100644 index 000000000..52ab6b4ee --- /dev/null +++ b/product/morello/module/dmc_bing/src/morello_ddr_phy.h @@ -0,0 +1,143 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Morello DDR-PHY driver + */ +#ifndef MORELLO_DDR_PHY_H +#define MORELLO_DDR_PHY_H + +#include + +#include + +#include + +/* + * \brief Function to configure and run DDR PHY at 800MHz frequency. + * + * \param ddr_phy Pointer to DDR PHY register space. + * \param info Pointer to DIMM information. + * + * \retval NONE + */ +void ddr_phy_config_800( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info); + +/* + * \brief Function to configure and run DDR PHY at 1200MHz frequency. + * + * \param ddr_phy Pointer to DDR PHY register space. + * \param info Pointer to DIMM information. + * \param dmc_id Identifier of the DMC instance. + * + * \retval NONE + */ +void ddr_phy_config_1200( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info, + int dmc_id); + +/* + * \brief Function to configure and run DDR PHY at 1333MHz frequency. + * + * \param ddr_phy Pointer to DDR PHY register space. + * \param info Pointer to DIMM information. + * \param dmc_id Identifier of the DMC instance. + * + * \retval NONE + */ +void ddr_phy_config_1333( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info, + int dmc_id); + +/*! + * \brief Configure a DDR physical device + * + * \param element_id Element identifier corresponding to the device to + * configure. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ +int morello_ddr_phy_config(fwk_id_t element_id, struct dimm_info *info); + +/*! + * \brief Post training setting for DDR physical device + * + * \param element_id Element identifier corresponding to the device to + * configure. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ +int morello_ddr_phy_post_training_configure( + fwk_id_t element_id, + struct dimm_info *info); + +/*! + * \brief API to verify DDR PHY status at different training stage + * + * \param element_id Element identifier corresponding to the device to + * configure. + * \param training_type Training type for which PHY status to be verified. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ +int morello_verify_phy_status( + fwk_id_t element_id, + uint8_t training_type, + struct dimm_info *info); + +/*! + * \brief API to tune write leveling registers + * + * \param element_id Element identifier corresponding to the device to + * configure. + * \param rank The rank number to perform the tuning. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ +int morello_wrlvl_phy_obs_regs( + fwk_id_t element_id, + uint32_t rank, + struct dimm_info *info); + +/*! + * \brief API to tune read leveling registers + * + * \param element_id Element identifier corresponding to the device to + * configure. + * \param rank The rank number to perform the tuning. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ +int morello_read_gate_phy_obs_regs( + fwk_id_t element_id, + uint32_t rank, + struct dimm_info *info); + +/*! + * \brief API to tune PHY training registers + * + * \param element_id Element identifier corresponding to the device to + * configure. + * \param rank The rank number to perform the tuning. + * + * \retval FWK_SUCCESS if the operation succeed. + * \return one of the error code otherwise. + */ +int morello_phy_obs_regs( + fwk_id_t element_id, + uint32_t rank, + struct dimm_info *info); + +#endif /* MORELLO_DDR_PHY_H */ diff --git a/tools/cppcheck_suppress_list.txt b/tools/cppcheck_suppress_list.txt index e82ba0026..ea70c1a12 100755 --- a/tools/cppcheck_suppress_list.txt +++ b/tools/cppcheck_suppress_list.txt @@ -181,7 +181,7 @@ objectIndex:*product/n1sdp/module/n1sdp_pcie/src/n1sdp_pcie.c:438 objectIndex:*product/morello/module/morello_pcie/src/morello_pcie.c:390 knownConditionTrueFalse:*product/n1sdp/module/n1sdp_dmc620/src/mod_n1sdp_dmc620.c:85 syntaxError:*product/morello/scp_ramfw_soc/config_resource_perms.c:54 -syntaxError:*product/morello/module/dmc_bing/include/mod_dmc_bing.h:787 +syntaxError:*product/morello/module/dmc_bing/include/mod_dmc_bing.h:789 // Suppress CMSIS errors *:*/CMSIS*/* -- GitLab From 1c000f07934df62209a1f0e957d9206b92f30345 Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Thu, 21 Oct 2021 19:50:57 +0530 Subject: [PATCH 35/41] morello: minor fix in the log Account for tag bit storage size in the DDR and print total 'usable' DDR Size - in a more human-readable form. Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul Change-Id: Ibf216df07bb177248ab1a315b22ae8cbfbad7abf --- .../module/morello_system/src/mod_morello_system.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/product/morello/module/morello_system/src/mod_morello_system.c b/product/morello/module/morello_system/src/mod_morello_system.c index 19943bf3e..25b72cd3c 100644 --- a/product/morello/module/morello_system/src/mod_morello_system.c +++ b/product/morello/module/morello_system/src/mod_morello_system.c @@ -264,11 +264,16 @@ static int morello_system_fill_platform_info(void) sds_platform_info.local_ddr_size = size; size = sds_platform_info.local_ddr_size + sds_platform_info.remote_ddr_size; + + /* Account for size reserved for tag bits storage in dmc-bing client mode */ + if (SCC->BOOT_GPR1 & 0x1) { + size -= (size / UINT64_C(128)); + } + (void)size; FWK_LOG_INFO( - "[MORELLO SYSTEM] Total DDR Size in Bytes: 0x%" PRIX32 "%08" PRIX32, - (uint32_t)(size >> 32), - (uint32_t)size); + "[MORELLO SYSTEM] Total Usable DDR Size in Megabytes: %llu", + (size / (1024 * 1024))); sds_platform_info.scc_config = SCC->BOOT_GPR1; -- GitLab From 58cd83253319411abf65798994aa27e50458d252 Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Tue, 5 Oct 2021 10:43:13 +0530 Subject: [PATCH 36/41] morello: Add SCP to PCC communication module This is a simple protocol for sending and receiving messages between SCP and PCC using shared memory. The buffer sizes must be defined to be identical in size. Payload sizes must be identical as well. The protocol works by having two FIFO-style buffers in shared memory, each processors TX buffer is mapped as the others RX buffer and vice versa. Since it's a simple FIFO implementation, no mutexes or other access control methods are necessary as for a given buffer, there is only one producer and one consumer. This guarantees that messages are processed in the order that they are received. Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul Change-Id: I73bc46dd9db2eecd183b5c13e29d9e034fc76da8 --- .../module/morello_scp2pcc/CMakeLists.txt | 13 ++ .../module/morello_scp2pcc/Module.cmake | 10 + .../include/internal/morello_scp2pcc.h | 36 ++++ .../include/mod_morello_scp2pcc.h | 73 ++++++++ .../module/morello_scp2pcc/src/Makefile | 11 ++ .../morello_scp2pcc/src/mod_morello_scp2pcc.c | 176 ++++++++++++++++++ 6 files changed, 319 insertions(+) create mode 100644 product/morello/module/morello_scp2pcc/CMakeLists.txt create mode 100644 product/morello/module/morello_scp2pcc/Module.cmake create mode 100644 product/morello/module/morello_scp2pcc/include/internal/morello_scp2pcc.h create mode 100644 product/morello/module/morello_scp2pcc/include/mod_morello_scp2pcc.h create mode 100644 product/morello/module/morello_scp2pcc/src/Makefile create mode 100644 product/morello/module/morello_scp2pcc/src/mod_morello_scp2pcc.c diff --git a/product/morello/module/morello_scp2pcc/CMakeLists.txt b/product/morello/module/morello_scp2pcc/CMakeLists.txt new file mode 100644 index 000000000..da5538d4a --- /dev/null +++ b/product/morello/module/morello_scp2pcc/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_morello_scp2pcc.c") diff --git a/product/morello/module/morello_scp2pcc/Module.cmake b/product/morello/module/morello_scp2pcc/Module.cmake new file mode 100644 index 000000000..0c48a3aa3 --- /dev/null +++ b/product/morello/module/morello_scp2pcc/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "morello-scp2pcc") + +set(SCP_MODULE_TARGET "module-morello-scp2pcc") diff --git a/product/morello/module/morello_scp2pcc/include/internal/morello_scp2pcc.h b/product/morello/module/morello_scp2pcc/include/internal/morello_scp2pcc.h new file mode 100644 index 000000000..ddffcb279 --- /dev/null +++ b/product/morello/module/morello_scp2pcc/include/internal/morello_scp2pcc.h @@ -0,0 +1,36 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MORELLO SCP to PCC message transfer prototypes. + */ + +#ifndef INTERNAL_MORELLO_SCP2PCC_H +#define INTERNAL_MORELLO_SCP2PCC_H + +#include + +#include + +#define MSG_PAYLOAD_SIZE 16 +#define MSG_UNUSED_MESSAGE_TYPE 0xFFFF +#define MSG_ALIVE_VALUE 0xDEADBEEF + +#define SCP2PCC_TYPE_SHUTDOWN 0x0001 +#define SCP2PCC_TYPE_REBOOT 0x0002 + +struct FWK_PACKED mem_msg_packet { + /* Message type, lower 16 bits only. */ + unsigned int type; + /* Valid payload size, lower 16 bits only. */ + unsigned int size; + /* Sequence field used to process packets in proper order. */ + unsigned int sequence; + /* Data payload. */ + uint8_t payload[MSG_PAYLOAD_SIZE]; +}; + +#endif /* INTERNAL_MORELLO_SCP2PCC_H */ diff --git a/product/morello/module/morello_scp2pcc/include/mod_morello_scp2pcc.h b/product/morello/module/morello_scp2pcc/include/mod_morello_scp2pcc.h new file mode 100644 index 000000000..86290d5bc --- /dev/null +++ b/product/morello/module/morello_scp2pcc/include/mod_morello_scp2pcc.h @@ -0,0 +1,73 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MORELLO SCP to PCC communication protocol module. + */ + +#ifndef MOD_MORELLO_SCP2PCC_H +#define MOD_MORELLO_SCP2PCC_H + +#include + +#include +/*! + * \addtogroup GroupMORELLOModule MORELLO Product Modules + * \{ + */ + +/*! + * \defgroup GroupMORELLOScp2pcc MORELLO SCP2PCC communication protocol + * + * \brief Driver support for MORELLO SCP2PCC. + * + * \details This module provides support for SCP to PCC communication. + * + * \{ + */ + +/*! + * \brief MORELLO SCP to PCC module configuration + */ +struct mem_msg_config { + /*! Pointer to memory location set at init. */ + unsigned volatile int *shared_alive_address; + /*! Pointer to TX buffer shared between SCP and PCC */ + uintptr_t shared_tx_buffer; + /*! Number of TX packets allocated */ + unsigned int shared_num_tx; + /*! Pointer to RX buffer shared between SCP and PCC */ + uintptr_t shared_rx_buffer; + /*! Number of RX packets allocated */ + unsigned int shared_num_rx; +}; + +/*! + * \brief API to transfer data between scp and pcc. + */ +struct mod_morello_scp2pcc_api { + /*! + * \brief Function to send data from SCP to PCC. + * + * \param data Data payload. + * \param size Size of the payload to be sent. + * \param type Indicates the type of payload sent. + * + * \retval ::FWK_SUCCESS Operation succeeded. + * \return One of the other specific error codes described by the framework. + */ + int (*send)(void *data, uint16_t size, uint16_t type); +}; + +/*! + * \} + */ + +/*! + * \} + */ + +#endif /* MOD_MORELLO_SCP2PCC_H */ diff --git a/product/morello/module/morello_scp2pcc/src/Makefile b/product/morello/module/morello_scp2pcc/src/Makefile new file mode 100644 index 000000000..e1932dbd3 --- /dev/null +++ b/product/morello/module/morello_scp2pcc/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := MORELLO_SCP2PCC +BS_LIB_SOURCES += mod_morello_scp2pcc.c + +include $(BS_DIR)/lib.mk diff --git a/product/morello/module/morello_scp2pcc/src/mod_morello_scp2pcc.c b/product/morello/module/morello_scp2pcc/src/mod_morello_scp2pcc.c new file mode 100644 index 000000000..ed136e41a --- /dev/null +++ b/product/morello/module/morello_scp2pcc/src/mod_morello_scp2pcc.c @@ -0,0 +1,176 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MORELLO SCP to PCC communications protocol driver + */ + +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +/* Module context */ +struct morello_scp2pcc_ctx { + /* Pointer to module configuration */ + struct mem_msg_config *config; + + /* Sequence variable */ + unsigned int sequence; +}; + +static struct morello_scp2pcc_ctx scp2pcc_ctx; + +static inline void wrdmemset(void *ptr, unsigned int value) +{ + ((unsigned int *)ptr)[0] = value; +} + +static void wrdmemcpy(void *destination, const void *source, unsigned int num) +{ + unsigned int index; + + for (index = 0; index < num; index++) { + ((unsigned int *)destination)[index] = ((unsigned int *)source)[index]; + } +} + +static void reset_shared_memory(void) +{ + unsigned int index; + struct mem_msg_packet *packet = NULL; + size_t offset; + + for (index = 0; index < scp2pcc_ctx.config->shared_num_rx; index++) { + offset = index * sizeof(struct mem_msg_packet); + packet = (struct mem_msg_packet + *)(scp2pcc_ctx.config->shared_rx_buffer + offset); + + wrdmemset(&packet->type, MSG_UNUSED_MESSAGE_TYPE); + } + + for (index = 0; index < scp2pcc_ctx.config->shared_num_tx; index++) { + offset = index * sizeof(struct mem_msg_packet); + packet = (struct mem_msg_packet + *)(scp2pcc_ctx.config->shared_tx_buffer + offset); + + wrdmemset(&packet->type, MSG_UNUSED_MESSAGE_TYPE); + } +} + +static int mem_msg_send_message(void *data, uint16_t size, uint16_t type) +{ + unsigned int index; + struct mem_msg_packet *packet = NULL; + size_t offset; + + if (type == SCP2PCC_TYPE_SHUTDOWN) { + FWK_LOG_INFO("Shutdown request to PCC"); + } + + /* Check parameters. */ + if ((size > MSG_PAYLOAD_SIZE) || (type == MSG_UNUSED_MESSAGE_TYPE)) { + FWK_LOG_INFO("Invalid parameters"); + return FWK_E_PARAM; + } + + /* Check for alive value. */ + if (*(scp2pcc_ctx.config->shared_alive_address) != MSG_ALIVE_VALUE) { + /* Attempt to set alive value and try again. */ + *(scp2pcc_ctx.config->shared_alive_address) = MSG_ALIVE_VALUE; + if (*(scp2pcc_ctx.config->shared_alive_address) != MSG_ALIVE_VALUE) { + return FWK_E_STATE; + } + + /* If successful, reset shared memory. */ + reset_shared_memory(); + } + + /* Find unused TX packet. */ + for (index = 0; index < scp2pcc_ctx.config->shared_num_tx; index++) { + offset = index * sizeof(struct mem_msg_packet); + /* Get pointer to packet. */ + packet = (struct mem_msg_packet + *)(scp2pcc_ctx.config->shared_tx_buffer + offset); + + if (packet->type == MSG_UNUSED_MESSAGE_TYPE) { + /* Unused packet found, copy data payload. */ + if (data != NULL) { + wrdmemcpy((void *)&packet->payload, data, (size / 4)); + } + + /* Set size. */ + wrdmemset((void *)&packet->size, size); + + /* Set sequence. */ + wrdmemset((void *)&packet->sequence, scp2pcc_ctx.sequence); + + scp2pcc_ctx.sequence++; + + /* Set type last since it is a sort of valid indicator. */ + wrdmemset((void *)&packet->type, type); + + return FWK_SUCCESS; + } + } + + return FWK_E_NOMEM; +} + +static const struct mod_morello_scp2pcc_api morello_scp2pcc_api = { + .send = mem_msg_send_message, +}; + +static int morello_scp2pcc_init( + fwk_id_t module_id, + unsigned int unused, + const void *data) +{ + if (data == NULL) { + return FWK_E_PARAM; + } + + scp2pcc_ctx.config = (struct mem_msg_config *)data; + + *(scp2pcc_ctx.config->shared_alive_address) = MSG_ALIVE_VALUE; + + return FWK_SUCCESS; +} + +static int morello_scp2pcc_process_bind_request( + fwk_id_t requester_id, + fwk_id_t target_id, + fwk_id_t api_id, + const void **api) +{ + *api = &morello_scp2pcc_api; + + return FWK_SUCCESS; +} + +static int morello_scp2pcc_start(fwk_id_t id) +{ + /* Clear out shared buffers. */ + reset_shared_memory(); + + return FWK_SUCCESS; +} + +const struct fwk_module module_morello_scp2pcc = { + .api_count = 1, + .type = FWK_MODULE_TYPE_PROTOCOL, + .init = morello_scp2pcc_init, + .process_bind_request = morello_scp2pcc_process_bind_request, + .start = morello_scp2pcc_start, +}; -- GitLab From 073dacd67804c792a00b937ad5494629dc48cad0 Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Tue, 5 Oct 2021 10:54:36 +0530 Subject: [PATCH 37/41] morello: include morello_scp2pcc module in scp_ramfw_soc Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul Change-Id: Ibd0d22c587472e4ef53218774424a973dc58d7d9 --- product/morello/scp_ramfw_soc/CMakeLists.txt | 1 + product/morello/scp_ramfw_soc/Firmware.cmake | 3 ++ .../scp_ramfw_soc/config_morello_scp2pcc.c | 28 +++++++++++++++++++ product/morello/scp_ramfw_soc/firmware.mk | 2 ++ 4 files changed, 34 insertions(+) create mode 100644 product/morello/scp_ramfw_soc/config_morello_scp2pcc.c diff --git a/product/morello/scp_ramfw_soc/CMakeLists.txt b/product/morello/scp_ramfw_soc/CMakeLists.txt index a69faea76..17463140c 100644 --- a/product/morello/scp_ramfw_soc/CMakeLists.txt +++ b/product/morello/scp_ramfw_soc/CMakeLists.txt @@ -43,6 +43,7 @@ target_sources( "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_css_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_morello_scp2pcc.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_psu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_psu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_dvfs.c" diff --git a/product/morello/scp_ramfw_soc/Firmware.cmake b/product/morello/scp_ramfw_soc/Firmware.cmake index aa38441b4..94568caf5 100644 --- a/product/morello/scp_ramfw_soc/Firmware.cmake +++ b/product/morello/scp_ramfw_soc/Firmware.cmake @@ -33,6 +33,8 @@ list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../../../module/fip") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_pll") list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/cdns_i2c") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/dmc_bing") +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/morello_scp2pcc") list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/morello_system") list(PREPEND SCP_MODULE_PATHS @@ -63,6 +65,7 @@ list(APPEND SCP_MODULES "css-clock") list(APPEND SCP_MODULES "clock") list(APPEND SCP_MODULES "gtimer") list(APPEND SCP_MODULES "timer") +list(APPEND SCP_MODULES "morello-scp2pcc") list(APPEND SCP_MODULES "scmi-power-domain") list(APPEND SCP_MODULES "scmi-system-power") list(APPEND SCP_MODULES "scmi-management") diff --git a/product/morello/scp_ramfw_soc/config_morello_scp2pcc.c b/product/morello/scp_ramfw_soc/config_morello_scp2pcc.c new file mode 100644 index 000000000..771256e14 --- /dev/null +++ b/product/morello/scp_ramfw_soc/config_morello_scp2pcc.c @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#define MSG_ALIVE_ADDRESS 0xB5FFF000 +#define MSG_RX_BUF_ADDRESS 0xB5FFF104 +#define MSG_TX_BUF_ADDRESS 0xB5FFF004 +#define MSG_NUM_TX_MESSAGES 8 +#define MSG_NUM_RX_MESSAGES 8 + +const struct fwk_module_config config_morello_scp2pcc = { + .data = &((struct mem_msg_config){ + .shared_alive_address = (unsigned volatile int *)MSG_ALIVE_ADDRESS, + .shared_tx_buffer = (uintptr_t)MSG_TX_BUF_ADDRESS, + .shared_num_tx = MSG_NUM_TX_MESSAGES, + .shared_rx_buffer = (uintptr_t)MSG_RX_BUF_ADDRESS, + .shared_num_rx = MSG_NUM_RX_MESSAGES, + }), +}; diff --git a/product/morello/scp_ramfw_soc/firmware.mk b/product/morello/scp_ramfw_soc/firmware.mk index eaed8e054..55cfedfab 100644 --- a/product/morello/scp_ramfw_soc/firmware.mk +++ b/product/morello/scp_ramfw_soc/firmware.mk @@ -33,6 +33,7 @@ BS_FIRMWARE_MODULES := \ clock \ gtimer \ timer \ + morello_scp2pcc \ dvfs \ psu \ mock_psu \ @@ -73,6 +74,7 @@ BS_FIRMWARE_SOURCES := \ config_pik_clock.c \ config_css_clock.c \ config_clock.c \ + config_morello_scp2pcc.c \ config_apcontext.c \ config_dvfs.c \ config_psu.c \ -- GitLab From 97c0c5e70c1f4e4e262825dc9fabdc4629d6eb02 Mon Sep 17 00:00:00 2001 From: Chandni Cherukuri Date: Tue, 5 Oct 2021 11:03:18 +0530 Subject: [PATCH 38/41] morello: add shutdown/reboot communication with PCC On Morello SoC platform, SCP has to communicate with PCC over shared memory interface for system shutdown and reboot. This patch adds support for the same. Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul Change-Id: I46ad477552f40c530605ea99fe4d30472ecb28d4 --- .../module/morello_system/CMakeLists.txt | 8 ++++ .../morello_system/src/mod_morello_system.c | 45 +++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/product/morello/module/morello_system/CMakeLists.txt b/product/morello/module/morello_system/CMakeLists.txt index ec45feb77..1f558ceb2 100644 --- a/product/morello/module/morello_system/CMakeLists.txt +++ b/product/morello/module/morello_system/CMakeLists.txt @@ -6,6 +6,10 @@ # add_library(${SCP_MODULE_TARGET} SCP_MODULE) +if(SCP_ENABLE_PLAT_FVP) +target_compile_definitions(${SCP_MODULE_TARGET} PUBLIC -DPLAT_FVP=1) +endif() + target_include_directories(${SCP_MODULE_TARGET} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") @@ -22,3 +26,7 @@ target_link_libraries( module-scmi module-system-power module-dmc-bing) + +if(NOT SCP_ENABLE_PLAT_FVP) +target_link_libraries(${SCP_MODULE_TARGET} PRIVATE module-morello-scp2pcc) +endif() diff --git a/product/morello/module/morello_system/src/mod_morello_system.c b/product/morello/module/morello_system/src/mod_morello_system.c index 25b72cd3c..b9eec3f65 100644 --- a/product/morello/module/morello_system/src/mod_morello_system.c +++ b/product/morello/module/morello_system/src/mod_morello_system.c @@ -21,6 +21,9 @@ #include #include +#if !defined(PLAT_FVP) +# include +#endif #include #include #include @@ -115,6 +118,11 @@ struct morello_system_ctx { /* Pointer to SDS */ const struct mod_sds_api *sds_api; + +#if !defined(PLAT_FVP) + /* Pointer to SCP to PCC communication API */ + const struct mod_morello_scp2pcc_api *scp2pcc_api; +#endif }; struct morello_system_isr { @@ -177,6 +185,33 @@ static struct morello_system_isr isrs[] = { static int morello_system_shutdown(enum mod_pd_system_shutdown system_shutdown) { +#if !defined(PLAT_FVP) + int status; + switch (system_shutdown) { + case MOD_PD_SYSTEM_SHUTDOWN: + FWK_LOG_INFO("[MORELLO SYSTEM] Request PCC for system shutdown"); + status = morello_system_ctx.scp2pcc_api->send( + NULL, 0, SCP2PCC_TYPE_SHUTDOWN); + break; + + case MOD_PD_SYSTEM_COLD_RESET: + FWK_LOG_INFO("[MORELLO SYSTEM] Request PCC for system reboot"); + status = + morello_system_ctx.scp2pcc_api->send(NULL, 0, SCP2PCC_TYPE_REBOOT); + break; + + default: + FWK_LOG_INFO("[MORELLO SYSTEM] Unknown shutdown command!"); + status = FWK_E_PARAM; + break; + } + + if (status != FWK_SUCCESS) { + FWK_LOG_ERR("[MORELLO SYSTEM] Shutdown/Reboot request to PCC failed"); + return status; + } +#endif + NVIC_SystemReset(); return FWK_E_DEVICE; } @@ -424,6 +459,16 @@ static int morello_system_bind(fwk_id_t id, unsigned int round) if (status != FWK_SUCCESS) return status; +#if !defined(PLAT_FVP) + status = fwk_module_bind( + FWK_ID_MODULE(FWK_MODULE_IDX_MORELLO_SCP2PCC), + FWK_ID_API(FWK_MODULE_IDX_MORELLO_SCP2PCC, 0), + &morello_system_ctx.scp2pcc_api); + if (status != FWK_SUCCESS) { + return status; + } +#endif + return fwk_module_bind( fwk_module_id_sds, FWK_ID_API(FWK_MODULE_IDX_SDS, 0), -- GitLab From 69139604adcc14c58e4427c1244ed6b65732d6b7 Mon Sep 17 00:00:00 2001 From: Anurag Koul Date: Fri, 12 Nov 2021 20:37:46 +0000 Subject: [PATCH 39/41] morello: move MHU mailbox to AP non-trusted RAM Because of an issue with unaligned accesses with MHU SRAM, move AP-SCP MHU mailbox memory region from SRAM to AP Non-trusted RAM. Signed-off-by: Anurag Koul Change-Id: Ibd0f9cc8949b10dd1e9e67ba6e05df801832abd7 --- product/morello/include/morello_scp_mmap.h | 2 + .../morello/scp_ramfw_soc/config_armv7m_mpu.c | 4 +- product/morello/scp_ramfw_soc/config_smt.c | 139 +++++++++--------- 3 files changed, 73 insertions(+), 72 deletions(-) diff --git a/product/morello/include/morello_scp_mmap.h b/product/morello/include/morello_scp_mmap.h index e7958aa39..8b5a37a6d 100644 --- a/product/morello/include/morello_scp_mmap.h +++ b/product/morello/include/morello_scp_mmap.h @@ -167,6 +167,8 @@ #define SCP_SSC_BASE (SCP_SYS1_BASE + 0x2A420000) #define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYS1_BASE + 0x2A430000) +/* Base address of AP-SCP mailbox for non-secure access */ +#define SCP_AP_BASE_NS_MAILBOX_SRAM (SCP_NONTRUSTED_RAM_BASE) /* * Base addresses of MHU devices */ diff --git a/product/morello/scp_ramfw_soc/config_armv7m_mpu.c b/product/morello/scp_ramfw_soc/config_armv7m_mpu.c index 3f373b809..298e99a63 100644 --- a/product/morello/scp_ramfw_soc/config_armv7m_mpu.c +++ b/product/morello/scp_ramfw_soc/config_armv7m_mpu.c @@ -80,8 +80,8 @@ static const ARM_MPU_Region_t regions[] = { ARM_MPU_REGION_SIZE_256B), }, { - /* 0x6520_0000 - 0x6520_FFFF */ - .RBAR = ARM_MPU_RBAR(5, SCP_AP_SHARED_NONSECURE_RAM), + /* 0xA600_0000 - 0xA600_FFFF */ + .RBAR = ARM_MPU_RBAR(5, SCP_AP_BASE_NS_MAILBOX_SRAM), .RASR = ARM_MPU_RASR( 1, ARM_MPU_AP_PRIV, diff --git a/product/morello/scp_ramfw_soc/config_smt.c b/product/morello/scp_ramfw_soc/config_smt.c index da4c92e70..21931cb25 100644 --- a/product/morello/scp_ramfw_soc/config_smt.c +++ b/product/morello/scp_ramfw_soc/config_smt.c @@ -21,76 +21,75 @@ #include -static const struct fwk_element smt_element_table[] = { - [SCP_MORELLO_SCMI_SERVICE_IDX_PSCI] = { - .name = "PSCI", - .data = &((struct mod_smt_channel_config) { - .type = - MOD_SMT_CHANNEL_TYPE_SLAVE, - .policies = - MOD_SMT_POLICY_INIT_MAILBOX | - MOD_SMT_POLICY_SECURE, - .mailbox_address = - SCP_AP_SHARED_SECURE_RAM, - .mailbox_size = - SCP_SCMI_PAYLOAD_SIZE, - .driver_id = - FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_MHU, - MORELLO_MHU_DEVICE_IDX_S_CLUS0, - 0), - .driver_api_id = - FWK_ID_API_INIT( - FWK_MODULE_IDX_MHU, - 0), - }), - }, - [SCP_MORELLO_SCMI_SERVICE_IDX_OSPM] = { - .name = "OSPM", - .data = &((struct mod_smt_channel_config) { - .type = - MOD_SMT_CHANNEL_TYPE_SLAVE, - .policies = - MOD_SMT_POLICY_INIT_MAILBOX, - .mailbox_address = - SCP_AP_SHARED_NONSECURE_RAM, - .mailbox_size = - SCP_SCMI_PAYLOAD_SIZE, - .driver_id = - FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_MHU, - MORELLO_MHU_DEVICE_IDX_NS_CLUS0, - 0), - .driver_api_id = - FWK_ID_API_INIT( - FWK_MODULE_IDX_MHU, - 0), - }), - }, - [SCP_MORELLO_SCMI_SERVICE_IDX_MCP] = { - .name = "MCP", - .data = &((struct mod_smt_channel_config) { - .type = - MOD_SMT_CHANNEL_TYPE_SLAVE, - .policies = - MOD_SMT_POLICY_INIT_MAILBOX | - MOD_SMT_POLICY_SECURE, - .mailbox_address = - SCP_MCP_SHARED_SECURE_RAM, - .mailbox_size = - SCP_SCMI_PAYLOAD_SIZE, - .driver_id = - FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_MHU, - MORELLO_MHU_DEVICE_IDX_S_MCP, - 0), - .driver_api_id = - FWK_ID_API_INIT( - FWK_MODULE_IDX_MHU, - 0), - }), - }, - [SCP_MORELLO_SCMI_SERVICE_IDX_COUNT] = { 0 }, +static const struct fwk_element + smt_element_table[SCP_MORELLO_SCMI_SERVICE_IDX_COUNT + 1] = { + [SCP_MORELLO_SCMI_SERVICE_IDX_PSCI] = { + .name = "PSCI", + .data = &((struct mod_smt_channel_config){ + .type = + MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX | + MOD_SMT_POLICY_SECURE, + .mailbox_address = + SCP_AP_SHARED_SECURE_RAM, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU, + MORELLO_MHU_DEVICE_IDX_S_CLUS0, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU, + 0), + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_OSPM] = { + .name = "OSPM", + .data = &((struct mod_smt_channel_config){ + .type = + MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX, + .mailbox_address = + SCP_AP_BASE_NS_MAILBOX_SRAM, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU, + MORELLO_MHU_DEVICE_IDX_NS_CLUS0, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU, + 0), + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_MCP] = { + .name = "MCP", + .data = &((struct mod_smt_channel_config){ + .type = + MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX | + MOD_SMT_POLICY_SECURE, + .mailbox_address = + SCP_MCP_SHARED_SECURE_RAM, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU, + MORELLO_MHU_DEVICE_IDX_S_MCP, + 0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU, + 0), + }), + }, + [SCP_MORELLO_SCMI_SERVICE_IDX_COUNT] = { 0 }, }; static const struct fwk_element *smt_get_element_table(fwk_id_t module_id) -- GitLab From f08e0aaf1f4832ccfad34640f43e1e2fcfd23a82 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Wed, 17 Nov 2021 15:25:31 +0530 Subject: [PATCH 40/41] morello: add 1466MHz support for DDR Support has been added for 1466 MHz and the DDR frequency has been changed from 1333MHz to 1466MHz Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri Signed-off-by: Anurag Koul Change-Id: I0d32090585b5ed94906b5da677501f82e59465b5 --- .../morello/module/dmc_bing/CMakeLists.txt | 3 +- product/morello/module/dmc_bing/src/Makefile | 3 +- .../module/dmc_bing/src/ddr_phy_values_1466.c | 1552 +++++++++++++++++ .../morello/module/dmc_bing/src/dimm_spd.c | 5 + .../module/dmc_bing/src/mod_dmc_bing.c | 105 +- .../module/dmc_bing/src/morello_ddr_phy.c | 8 +- .../module/dmc_bing/src/morello_ddr_phy.h | 14 + product/morello/scp_ramfw_soc/config_clock.h | 2 +- 8 files changed, 1676 insertions(+), 16 deletions(-) create mode 100644 product/morello/module/dmc_bing/src/ddr_phy_values_1466.c diff --git a/product/morello/module/dmc_bing/CMakeLists.txt b/product/morello/module/dmc_bing/CMakeLists.txt index dc6cfe34a..f17da7b28 100644 --- a/product/morello/module/dmc_bing/CMakeLists.txt +++ b/product/morello/module/dmc_bing/CMakeLists.txt @@ -29,7 +29,8 @@ target_sources(${SCP_MODULE_TARGET} "${CMAKE_CURRENT_SOURCE_DIR}/src/morello_ddr_phy.c" "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_800.c" "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_1200.c" - "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_1333.c") + "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_1333.c" + "${CMAKE_CURRENT_SOURCE_DIR}/src/ddr_phy_values_1466.c") target_link_libraries(${SCP_MODULE_TARGET} PRIVATE module-cdns-i2c) endif() diff --git a/product/morello/module/dmc_bing/src/Makefile b/product/morello/module/dmc_bing/src/Makefile index 7e974d70f..a762306a5 100644 --- a/product/morello/module/dmc_bing/src/Makefile +++ b/product/morello/module/dmc_bing/src/Makefile @@ -15,7 +15,8 @@ BS_LIB_SOURCES += \ morello_ddr_phy.c \ ddr_phy_values_800.c \ ddr_phy_values_1200.c \ - ddr_phy_values_1333.c + ddr_phy_values_1333.c \ + ddr_phy_values_1466.c endif include $(BS_DIR)/lib.mk diff --git a/product/morello/module/dmc_bing/src/ddr_phy_values_1466.c b/product/morello/module/dmc_bing/src/ddr_phy_values_1466.c new file mode 100644 index 000000000..ced82c127 --- /dev/null +++ b/product/morello/module/dmc_bing/src/ddr_phy_values_1466.c @@ -0,0 +1,1552 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Morello DDR-PHY register value configuration for 1466MHz speed. + */ + +#include + +#include + +#include + +#include + +#include +#include + +static uint8_t PHY_WRITE_PATH_LAT_ADD_2933[9] = { 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +static uint16_t PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[9] = { + 0x1A0, 0x120, 0x100, 0, 0, 0, 0x100, 0x100, 0 +}; +static uint8_t PHY_WRLVL_EARLY_FORCE_ZERO_2933[9] = { + 0, 0, 0, 0, 1, 0, 0, 0, 0 +}; +static uint32_t PHY_PAD_VREF_CTRL_DQ_2933; +static uint32_t VREF_TRAINING_CTRL_2933 = 0x00042520; +static uint16_t phy_dq_tsel_select_value; +static uint16_t phy_dqs_tsel_select_value; +static uint32_t phy_pad_data_drive_value = 0x2000073F; +static uint32_t phy_pad_clk_drive_value = 0x0006BF99; + +void ddr_phy_config_1466( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info, + int dmc_id) +{ + fwk_assert((ddr_phy != NULL) && (info != NULL)); + + if (info->number_of_ranks == 1) { + PHY_PAD_VREF_CTRL_DQ_2933 = 0x1234; + phy_dq_tsel_select_value = 0x9990; + phy_dqs_tsel_select_value = 0x9990; + } else { + PHY_PAD_VREF_CTRL_DQ_2933 = 0x1260; + phy_dq_tsel_select_value = 0x8890; + phy_dqs_tsel_select_value = 0x8890; + } + + ddr_phy->DENALI_PHY_00_DATA = 0x76543210; + ddr_phy->DENALI_PHY_01_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_02_DATA = 0x00000000; + ddr_phy->DENALI_PHY_03_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_04_DATA = 0x00000000; + ddr_phy->DENALI_PHY_05_DATA = 0x00000000; + ddr_phy->DENALI_PHY_06_DATA = 0x00010000; + ddr_phy->DENALI_PHY_07_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_08_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_09_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_10_DATA = 0x00010000; + ddr_phy->DENALI_PHY_11_DATA = 0x00000000; + ddr_phy->DENALI_PHY_12_DATA = 0x00000000; + ddr_phy->DENALI_PHY_13_DATA = 0x01000100; + ddr_phy->DENALI_PHY_14_DATA = 0x00000000; + ddr_phy->DENALI_PHY_15_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_16_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_17_DATA = 0x00000008; + ddr_phy->DENALI_PHY_18_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_19_DATA = 0x00005555; + ddr_phy->DENALI_PHY_20_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_21_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_22_DATA = 0x00005656; + ddr_phy->DENALI_PHY_23_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_24_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_25_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_26_DATA = 0x00000000; + ddr_phy->DENALI_PHY_27_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_28_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_29_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_30_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_31_DATA = 0x00000000; + ddr_phy->DENALI_PHY_32_DATA = 0x04080000; + ddr_phy->DENALI_PHY_33_DATA = 0x08040400; + ddr_phy->DENALI_PHY_34_DATA = 0x00000004; + ddr_phy->DENALI_PHY_35_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_36_DATA = 0x00000000; + ddr_phy->DENALI_PHY_37_DATA = 0x00000000; + ddr_phy->DENALI_PHY_38_DATA = 0x00000000; + ddr_phy->DENALI_PHY_39_DATA = 0x00000000; + ddr_phy->DENALI_PHY_40_DATA = 0x00000000; + ddr_phy->DENALI_PHY_41_DATA = 0x00000000; + ddr_phy->DENALI_PHY_42_DATA = 0x00000000; + ddr_phy->DENALI_PHY_43_DATA = 0x00000000; + ddr_phy->DENALI_PHY_44_DATA = 0x00000000; + ddr_phy->DENALI_PHY_45_DATA = 0x00000000; + ddr_phy->DENALI_PHY_46_DATA = 0x00000000; + ddr_phy->DENALI_PHY_47_DATA = 0x00000000; + ddr_phy->DENALI_PHY_48_DATA = 0x00000000; + ddr_phy->DENALI_PHY_49_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_50_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_50_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_51_DATA = 0x00000000; + ddr_phy->DENALI_PHY_52_DATA = 0x00000000; + ddr_phy->DENALI_PHY_53_DATA = 0x00000000; + ddr_phy->DENALI_PHY_54_DATA = 0x00000000; + ddr_phy->DENALI_PHY_55_DATA = 0x20000004; + ddr_phy->DENALI_PHY_56_DATA = 0x00000000; + ddr_phy->DENALI_PHY_57_DATA = 0x00000000; + ddr_phy->DENALI_PHY_58_DATA = 0x00000000; + ddr_phy->DENALI_PHY_59_DATA = 0x00000000; + ddr_phy->DENALI_PHY_60_DATA = 0x00000000; + ddr_phy->DENALI_PHY_61_DATA = 0x00000000; + ddr_phy->DENALI_PHY_62_DATA = 0x00000000; + ddr_phy->DENALI_PHY_63_DATA = 0x00000000; + ddr_phy->DENALI_PHY_64_DATA = 0x00000000; + ddr_phy->DENALI_PHY_65_DATA = 0x00000000; + ddr_phy->DENALI_PHY_66_DATA = 0x00000000; + ddr_phy->DENALI_PHY_67_DATA = 0x00000000; + ddr_phy->DENALI_PHY_68_DATA = 0x00000000; + ddr_phy->DENALI_PHY_69_DATA = 0x00000000; + ddr_phy->DENALI_PHY_70_DATA = 0x00000000; + ddr_phy->DENALI_PHY_71_DATA = 0x00000000; + ddr_phy->DENALI_PHY_72_DATA = 0x00000000; + ddr_phy->DENALI_PHY_73_DATA = 0x00000000; + ddr_phy->DENALI_PHY_74_DATA = 0x00000000; + ddr_phy->DENALI_PHY_75_DATA = 0x00000000; + ddr_phy->DENALI_PHY_76_DATA = 0x00000000; + ddr_phy->DENALI_PHY_77_DATA = 0x00000000; + ddr_phy->DENALI_PHY_78_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_79_DATA = 0x00000000; + ddr_phy->DENALI_PHY_80_DATA = 0x00000000; + ddr_phy->DENALI_PHY_81_DATA = 0x04000000; + ddr_phy->DENALI_PHY_82_DATA = 0x02800280; + ddr_phy->DENALI_PHY_83_DATA = 0x02800280; + ddr_phy->DENALI_PHY_84_DATA = 0x02800280; + ddr_phy->DENALI_PHY_85_DATA = 0x02800280; + ddr_phy->DENALI_PHY_86_DATA = 0x00000280; + ddr_phy->DENALI_PHY_87_DATA = 0x00000000; + ddr_phy->DENALI_PHY_88_DATA = 0x00000000; + ddr_phy->DENALI_PHY_89_DATA = 0x00000000; + ddr_phy->DENALI_PHY_90_DATA = 0x00000000; + ddr_phy->DENALI_PHY_91_DATA = 0x00000000; + ddr_phy->DENALI_PHY_92_DATA = 0x00800080; + ddr_phy->DENALI_PHY_93_DATA = 0x00800080; + ddr_phy->DENALI_PHY_94_DATA = 0x00800080; + ddr_phy->DENALI_PHY_95_DATA = 0x00800080; + ddr_phy->DENALI_PHY_96_DATA = 0x00800080; + ddr_phy->DENALI_PHY_97_DATA = 0x00800080; + ddr_phy->DENALI_PHY_98_DATA = 0x00800080; + ddr_phy->DENALI_PHY_99_DATA = 0x00800080; + ddr_phy->DENALI_PHY_100_DATA = 0x00800080; + ddr_phy->DENALI_PHY_101_DATA = 0x00800080; + ddr_phy->DENALI_PHY_102_DATA = 0x00800080; + ddr_phy->DENALI_PHY_103_DATA = 0x00800080; + ddr_phy->DENALI_PHY_104_DATA = 0x00800080; + ddr_phy->DENALI_PHY_105_DATA = 0x00800080; + ddr_phy->DENALI_PHY_106_DATA = 0x00800080; + ddr_phy->DENALI_PHY_107_DATA = 0x00800080; + ddr_phy->DENALI_PHY_108_DATA = 0x00800080; + ddr_phy->DENALI_PHY_109_DATA = 0x00800080; + ddr_phy->DENALI_PHY_110_DATA = 0x10040001; + ddr_phy->DENALI_PHY_111_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_112_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_113_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_114_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[0]); + ddr_phy->DENALI_PHY_115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_116_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[0] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_117_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[0] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_118_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[0]); + ddr_phy->DENALI_PHY_119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_120_DATA = 0x00800802; + ddr_phy->DENALI_PHY_121_DATA = 0x00081020; + ddr_phy->DENALI_PHY_122_DATA = 0x04010000; + ddr_phy->DENALI_PHY_123_DATA = 0x61314042; + ddr_phy->DENALI_PHY_124_DATA = 0x00314000; + ddr_phy->DENALI_PHY_125_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_126_DATA = 0x05010080; + ddr_phy->DENALI_PHY_127_DATA = 0x00000400; + ddr_phy->DENALI_PHY_128_DATA = 0x42100010; + ddr_phy->DENALI_PHY_129_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_130_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_131_DATA = 0x40420100; + ddr_phy->DENALI_PHY_132_DATA = 0x40518031; + ddr_phy->DENALI_PHY_133_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_134_DATA = 0x00000233; + ddr_phy->DENALI_PHY_135_DATA = 0x00000203; + ddr_phy->DENALI_PHY_136_DATA = 0x03000100; + ddr_phy->DENALI_PHY_137_DATA = 0x20202000; + ddr_phy->DENALI_PHY_138_DATA = 0x20202020; + ddr_phy->DENALI_PHY_139_DATA = 0x80202020; + ddr_phy->DENALI_PHY_140_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_141_DATA = 0x00000000; + ddr_phy->DENALI_PHY_142_DATA = 0x00000000; + ddr_phy->DENALI_PHY_256_DATA = 0x76543210; + ddr_phy->DENALI_PHY_257_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_258_DATA = 0x00000000; + ddr_phy->DENALI_PHY_259_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_260_DATA = 0x00000000; + ddr_phy->DENALI_PHY_261_DATA = 0x00000000; + ddr_phy->DENALI_PHY_262_DATA = 0x00010000; + ddr_phy->DENALI_PHY_263_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_264_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_265_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_266_DATA = 0x00010000; + ddr_phy->DENALI_PHY_267_DATA = 0x00000000; + ddr_phy->DENALI_PHY_268_DATA = 0x00000000; + ddr_phy->DENALI_PHY_269_DATA = 0x01000100; + ddr_phy->DENALI_PHY_270_DATA = 0x00000000; + ddr_phy->DENALI_PHY_271_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_272_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_273_DATA = 0x00000008; + ddr_phy->DENALI_PHY_274_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_275_DATA = 0x00005555; + ddr_phy->DENALI_PHY_276_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_277_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_278_DATA = 0x00005656; + ddr_phy->DENALI_PHY_279_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_280_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_281_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_283_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_284_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_285_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_286_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_287_DATA = 0x00000000; + ddr_phy->DENALI_PHY_288_DATA = 0x04080000; + ddr_phy->DENALI_PHY_289_DATA = 0x08040400; + ddr_phy->DENALI_PHY_290_DATA = 0x00000004; + ddr_phy->DENALI_PHY_291_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_293_DATA = 0x00000000; + ddr_phy->DENALI_PHY_294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_295_DATA = 0x00000000; + ddr_phy->DENALI_PHY_296_DATA = 0x00000000; + ddr_phy->DENALI_PHY_297_DATA = 0x00000000; + ddr_phy->DENALI_PHY_298_DATA = 0x00000000; + ddr_phy->DENALI_PHY_299_DATA = 0x00000000; + ddr_phy->DENALI_PHY_300_DATA = 0x00000000; + ddr_phy->DENALI_PHY_301_DATA = 0x00000000; + ddr_phy->DENALI_PHY_302_DATA = 0x00000000; + ddr_phy->DENALI_PHY_303_DATA = 0x00000000; + ddr_phy->DENALI_PHY_304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_305_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_306_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_306_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_309_DATA = 0x00000000; + ddr_phy->DENALI_PHY_310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_311_DATA = 0x20000004; + ddr_phy->DENALI_PHY_312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_313_DATA = 0x00000000; + ddr_phy->DENALI_PHY_314_DATA = 0x00000000; + ddr_phy->DENALI_PHY_315_DATA = 0x00000000; + ddr_phy->DENALI_PHY_316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_329_DATA = 0x00000000; + ddr_phy->DENALI_PHY_330_DATA = 0x00000000; + ddr_phy->DENALI_PHY_331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_334_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_335_DATA = 0x00000000; + ddr_phy->DENALI_PHY_336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_337_DATA = 0x04000000; + ddr_phy->DENALI_PHY_338_DATA = 0x02800280; + ddr_phy->DENALI_PHY_339_DATA = 0x02800280; + ddr_phy->DENALI_PHY_340_DATA = 0x02800280; + ddr_phy->DENALI_PHY_341_DATA = 0x02800280; + ddr_phy->DENALI_PHY_342_DATA = 0x00000280; + ddr_phy->DENALI_PHY_343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_348_DATA = 0x00800080; + ddr_phy->DENALI_PHY_349_DATA = 0x00800080; + ddr_phy->DENALI_PHY_350_DATA = 0x00800080; + ddr_phy->DENALI_PHY_351_DATA = 0x00800080; + ddr_phy->DENALI_PHY_352_DATA = 0x00800080; + ddr_phy->DENALI_PHY_353_DATA = 0x00800080; + ddr_phy->DENALI_PHY_354_DATA = 0x00800080; + ddr_phy->DENALI_PHY_355_DATA = 0x00800080; + ddr_phy->DENALI_PHY_356_DATA = 0x00800080; + ddr_phy->DENALI_PHY_357_DATA = 0x00800080; + ddr_phy->DENALI_PHY_358_DATA = 0x00800080; + ddr_phy->DENALI_PHY_359_DATA = 0x00800080; + ddr_phy->DENALI_PHY_360_DATA = 0x00800080; + ddr_phy->DENALI_PHY_361_DATA = 0x00800080; + ddr_phy->DENALI_PHY_362_DATA = 0x00800080; + ddr_phy->DENALI_PHY_363_DATA = 0x00800080; + ddr_phy->DENALI_PHY_364_DATA = 0x00800080; + ddr_phy->DENALI_PHY_365_DATA = 0x00800080; + ddr_phy->DENALI_PHY_366_DATA = 0x10040001; + ddr_phy->DENALI_PHY_367_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_368_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_369_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_370_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[1]); + ddr_phy->DENALI_PHY_371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_372_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[1] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_373_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[1] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_374_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[1]); + ddr_phy->DENALI_PHY_375_DATA = 0x00000000; + ddr_phy->DENALI_PHY_376_DATA = 0x00800802; + ddr_phy->DENALI_PHY_377_DATA = 0x00081020; + ddr_phy->DENALI_PHY_378_DATA = 0x04010000; + ddr_phy->DENALI_PHY_379_DATA = 0x61314042; + ddr_phy->DENALI_PHY_380_DATA = 0x00314000; + ddr_phy->DENALI_PHY_381_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_382_DATA = 0x05010080; + ddr_phy->DENALI_PHY_383_DATA = 0x00000400; + ddr_phy->DENALI_PHY_384_DATA = 0x42100010; + ddr_phy->DENALI_PHY_385_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_386_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_387_DATA = 0x40420100; + ddr_phy->DENALI_PHY_388_DATA = 0x40518031; + ddr_phy->DENALI_PHY_389_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_390_DATA = 0x00000233; + ddr_phy->DENALI_PHY_391_DATA = 0x00000203; + ddr_phy->DENALI_PHY_392_DATA = 0x03000100; + ddr_phy->DENALI_PHY_393_DATA = 0x20202000; + ddr_phy->DENALI_PHY_394_DATA = 0x20202020; + ddr_phy->DENALI_PHY_395_DATA = 0x80202020; + ddr_phy->DENALI_PHY_396_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_397_DATA = 0x00000000; + ddr_phy->DENALI_PHY_398_DATA = 0x00000000; + ddr_phy->DENALI_PHY_512_DATA = 0x76543210; + ddr_phy->DENALI_PHY_513_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_514_DATA = 0x00000000; + ddr_phy->DENALI_PHY_515_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_516_DATA = 0x00000000; + ddr_phy->DENALI_PHY_517_DATA = 0x00000000; + ddr_phy->DENALI_PHY_518_DATA = 0x00010000; + ddr_phy->DENALI_PHY_519_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_520_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_521_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_522_DATA = 0x00010000; + ddr_phy->DENALI_PHY_523_DATA = 0x00000000; + ddr_phy->DENALI_PHY_524_DATA = 0x00000000; + ddr_phy->DENALI_PHY_525_DATA = 0x01000100; + ddr_phy->DENALI_PHY_526_DATA = 0x00000000; + ddr_phy->DENALI_PHY_527_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_528_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_529_DATA = 0x00000008; + ddr_phy->DENALI_PHY_530_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_531_DATA = 0x00005555; + ddr_phy->DENALI_PHY_532_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_533_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_534_DATA = 0x00005656; + ddr_phy->DENALI_PHY_535_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_536_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_537_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_539_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_540_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_541_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_542_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_543_DATA = 0x00000000; + ddr_phy->DENALI_PHY_544_DATA = 0x04080000; + ddr_phy->DENALI_PHY_545_DATA = 0x08040400; + ddr_phy->DENALI_PHY_546_DATA = 0x00000004; + ddr_phy->DENALI_PHY_547_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_549_DATA = 0x00000000; + ddr_phy->DENALI_PHY_550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_551_DATA = 0x00000000; + ddr_phy->DENALI_PHY_552_DATA = 0x00000000; + ddr_phy->DENALI_PHY_553_DATA = 0x00000000; + ddr_phy->DENALI_PHY_554_DATA = 0x00000000; + ddr_phy->DENALI_PHY_555_DATA = 0x00000000; + ddr_phy->DENALI_PHY_556_DATA = 0x00000000; + ddr_phy->DENALI_PHY_557_DATA = 0x00000000; + ddr_phy->DENALI_PHY_558_DATA = 0x00000000; + ddr_phy->DENALI_PHY_559_DATA = 0x00000000; + ddr_phy->DENALI_PHY_560_DATA = 0x00000000; + ddr_phy->DENALI_PHY_561_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_562_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_562_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_563_DATA = 0x00000000; + ddr_phy->DENALI_PHY_564_DATA = 0x00000000; + ddr_phy->DENALI_PHY_565_DATA = 0x00000000; + ddr_phy->DENALI_PHY_566_DATA = 0x00000000; + ddr_phy->DENALI_PHY_567_DATA = 0x20000004; + ddr_phy->DENALI_PHY_568_DATA = 0x00000000; + ddr_phy->DENALI_PHY_569_DATA = 0x00000000; + ddr_phy->DENALI_PHY_570_DATA = 0x00000000; + ddr_phy->DENALI_PHY_571_DATA = 0x00000000; + ddr_phy->DENALI_PHY_572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_585_DATA = 0x00000000; + ddr_phy->DENALI_PHY_586_DATA = 0x00000000; + ddr_phy->DENALI_PHY_587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_590_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_591_DATA = 0x00000000; + ddr_phy->DENALI_PHY_592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_593_DATA = 0x04000000; + ddr_phy->DENALI_PHY_594_DATA = 0x02800280; + ddr_phy->DENALI_PHY_595_DATA = 0x02800280; + ddr_phy->DENALI_PHY_596_DATA = 0x02800280; + ddr_phy->DENALI_PHY_597_DATA = 0x02800280; + ddr_phy->DENALI_PHY_598_DATA = 0x00000280; + ddr_phy->DENALI_PHY_599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_604_DATA = 0x00800080; + ddr_phy->DENALI_PHY_605_DATA = 0x00800080; + ddr_phy->DENALI_PHY_606_DATA = 0x00800080; + ddr_phy->DENALI_PHY_607_DATA = 0x00800080; + ddr_phy->DENALI_PHY_608_DATA = 0x00800080; + ddr_phy->DENALI_PHY_609_DATA = 0x00800080; + ddr_phy->DENALI_PHY_610_DATA = 0x00800080; + ddr_phy->DENALI_PHY_611_DATA = 0x00800080; + ddr_phy->DENALI_PHY_612_DATA = 0x00800080; + ddr_phy->DENALI_PHY_613_DATA = 0x00800080; + ddr_phy->DENALI_PHY_614_DATA = 0x00800080; + ddr_phy->DENALI_PHY_615_DATA = 0x00800080; + ddr_phy->DENALI_PHY_616_DATA = 0x00800080; + ddr_phy->DENALI_PHY_617_DATA = 0x00800080; + ddr_phy->DENALI_PHY_618_DATA = 0x00800080; + ddr_phy->DENALI_PHY_619_DATA = 0x00800080; + ddr_phy->DENALI_PHY_620_DATA = 0x00800080; + ddr_phy->DENALI_PHY_621_DATA = 0x00800080; + ddr_phy->DENALI_PHY_622_DATA = 0x10040001; + ddr_phy->DENALI_PHY_623_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_624_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_625_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_626_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[2]); + ddr_phy->DENALI_PHY_627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_628_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[2] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_629_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[2] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_630_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[2]); + ddr_phy->DENALI_PHY_631_DATA = 0x00000000; + ddr_phy->DENALI_PHY_632_DATA = 0x00800802; + ddr_phy->DENALI_PHY_633_DATA = 0x00081020; + ddr_phy->DENALI_PHY_634_DATA = 0x04010000; + ddr_phy->DENALI_PHY_635_DATA = 0x61314042; + ddr_phy->DENALI_PHY_636_DATA = 0x00314000; + ddr_phy->DENALI_PHY_637_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_638_DATA = 0x05010080; + ddr_phy->DENALI_PHY_639_DATA = 0x00000400; + ddr_phy->DENALI_PHY_640_DATA = 0x42100010; + ddr_phy->DENALI_PHY_641_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_642_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_643_DATA = 0x40420100; + ddr_phy->DENALI_PHY_644_DATA = 0x40518031; + ddr_phy->DENALI_PHY_645_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_646_DATA = 0x00000233; + ddr_phy->DENALI_PHY_647_DATA = 0x00000203; + ddr_phy->DENALI_PHY_648_DATA = 0x03000100; + ddr_phy->DENALI_PHY_649_DATA = 0x20202000; + ddr_phy->DENALI_PHY_650_DATA = 0x20202020; + ddr_phy->DENALI_PHY_651_DATA = 0x80202020; + ddr_phy->DENALI_PHY_652_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_653_DATA = 0x00000000; + ddr_phy->DENALI_PHY_654_DATA = 0x00000000; + ddr_phy->DENALI_PHY_768_DATA = 0x76543210; + ddr_phy->DENALI_PHY_769_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_770_DATA = 0x00000000; + ddr_phy->DENALI_PHY_771_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_772_DATA = 0x00000000; + ddr_phy->DENALI_PHY_773_DATA = 0x00000000; + ddr_phy->DENALI_PHY_774_DATA = 0x00010000; + ddr_phy->DENALI_PHY_775_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_776_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_777_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_778_DATA = 0x00010000; + ddr_phy->DENALI_PHY_779_DATA = 0x00000000; + ddr_phy->DENALI_PHY_780_DATA = 0x00000000; + ddr_phy->DENALI_PHY_781_DATA = 0x01000100; + ddr_phy->DENALI_PHY_782_DATA = 0x00000000; + ddr_phy->DENALI_PHY_783_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_784_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_785_DATA = 0x00000008; + ddr_phy->DENALI_PHY_786_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_787_DATA = 0x00005555; + ddr_phy->DENALI_PHY_788_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_789_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_790_DATA = 0x00005656; + ddr_phy->DENALI_PHY_791_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_792_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_793_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_795_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_796_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_797_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_798_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_799_DATA = 0x00000000; + ddr_phy->DENALI_PHY_800_DATA = 0x04080000; + ddr_phy->DENALI_PHY_801_DATA = 0x08040400; + ddr_phy->DENALI_PHY_802_DATA = 0x00000004; + ddr_phy->DENALI_PHY_803_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_805_DATA = 0x00000000; + ddr_phy->DENALI_PHY_806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_807_DATA = 0x00000000; + ddr_phy->DENALI_PHY_808_DATA = 0x00000000; + ddr_phy->DENALI_PHY_809_DATA = 0x00000000; + ddr_phy->DENALI_PHY_810_DATA = 0x00000000; + ddr_phy->DENALI_PHY_811_DATA = 0x00000000; + ddr_phy->DENALI_PHY_812_DATA = 0x00000000; + ddr_phy->DENALI_PHY_813_DATA = 0x00000000; + ddr_phy->DENALI_PHY_814_DATA = 0x00000000; + ddr_phy->DENALI_PHY_815_DATA = 0x00000000; + ddr_phy->DENALI_PHY_816_DATA = 0x00000000; + ddr_phy->DENALI_PHY_817_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_818_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_818_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_819_DATA = 0x00000000; + ddr_phy->DENALI_PHY_820_DATA = 0x00000000; + ddr_phy->DENALI_PHY_821_DATA = 0x00000000; + ddr_phy->DENALI_PHY_822_DATA = 0x00000000; + ddr_phy->DENALI_PHY_823_DATA = 0x20000004; + ddr_phy->DENALI_PHY_824_DATA = 0x00000000; + ddr_phy->DENALI_PHY_825_DATA = 0x00000000; + ddr_phy->DENALI_PHY_826_DATA = 0x00000000; + ddr_phy->DENALI_PHY_827_DATA = 0x00000000; + ddr_phy->DENALI_PHY_828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_841_DATA = 0x00000000; + ddr_phy->DENALI_PHY_842_DATA = 0x00000000; + ddr_phy->DENALI_PHY_843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_846_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_847_DATA = 0x00000000; + ddr_phy->DENALI_PHY_848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_849_DATA = 0x04000000; + ddr_phy->DENALI_PHY_850_DATA = 0x02800280; + ddr_phy->DENALI_PHY_851_DATA = 0x02800280; + ddr_phy->DENALI_PHY_852_DATA = 0x02800280; + ddr_phy->DENALI_PHY_853_DATA = 0x02800280; + ddr_phy->DENALI_PHY_854_DATA = 0x00000280; + ddr_phy->DENALI_PHY_855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_860_DATA = 0x00800080; + ddr_phy->DENALI_PHY_861_DATA = 0x00800080; + ddr_phy->DENALI_PHY_862_DATA = 0x00800080; + ddr_phy->DENALI_PHY_863_DATA = 0x00800080; + ddr_phy->DENALI_PHY_864_DATA = 0x00800080; + ddr_phy->DENALI_PHY_865_DATA = 0x00800080; + ddr_phy->DENALI_PHY_866_DATA = 0x00800080; + ddr_phy->DENALI_PHY_867_DATA = 0x00800080; + ddr_phy->DENALI_PHY_868_DATA = 0x00800080; + ddr_phy->DENALI_PHY_869_DATA = 0x00800080; + ddr_phy->DENALI_PHY_870_DATA = 0x00800080; + ddr_phy->DENALI_PHY_871_DATA = 0x00800080; + ddr_phy->DENALI_PHY_872_DATA = 0x00800080; + ddr_phy->DENALI_PHY_873_DATA = 0x00800080; + ddr_phy->DENALI_PHY_874_DATA = 0x00800080; + ddr_phy->DENALI_PHY_875_DATA = 0x00800080; + ddr_phy->DENALI_PHY_876_DATA = 0x00800080; + ddr_phy->DENALI_PHY_877_DATA = 0x00800080; + ddr_phy->DENALI_PHY_878_DATA = 0x10040001; + ddr_phy->DENALI_PHY_879_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_880_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_881_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_882_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[3]); + ddr_phy->DENALI_PHY_883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_884_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[3] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_885_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[3] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_886_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[3]); + ddr_phy->DENALI_PHY_887_DATA = 0x00000000; + ddr_phy->DENALI_PHY_888_DATA = 0x00800802; + ddr_phy->DENALI_PHY_889_DATA = 0x00081020; + ddr_phy->DENALI_PHY_890_DATA = 0x04010000; + ddr_phy->DENALI_PHY_891_DATA = 0x61314042; + ddr_phy->DENALI_PHY_892_DATA = 0x00314000; + ddr_phy->DENALI_PHY_893_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_894_DATA = 0x05010080; + ddr_phy->DENALI_PHY_895_DATA = 0x00000400; + ddr_phy->DENALI_PHY_896_DATA = 0x42100010; + ddr_phy->DENALI_PHY_897_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_898_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_899_DATA = 0x40420100; + ddr_phy->DENALI_PHY_900_DATA = 0x40518031; + ddr_phy->DENALI_PHY_901_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_902_DATA = 0x00000233; + ddr_phy->DENALI_PHY_903_DATA = 0x00000203; + ddr_phy->DENALI_PHY_904_DATA = 0x03000100; + ddr_phy->DENALI_PHY_905_DATA = 0x20202000; + ddr_phy->DENALI_PHY_906_DATA = 0x20202020; + ddr_phy->DENALI_PHY_907_DATA = 0x80202020; + ddr_phy->DENALI_PHY_908_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_909_DATA = 0x00000000; + ddr_phy->DENALI_PHY_910_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1024_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1025_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1026_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1027_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1028_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1029_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1030_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1031_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1032_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1033_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1034_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1035_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1036_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1037_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1038_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1039_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_1040_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1041_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1042_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1043_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1044_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1045_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1046_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1047_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1048_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1049_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1051_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1052_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1053_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1054_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_1055_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1056_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1057_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1058_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1059_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1061_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1063_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1064_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1065_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1066_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1067_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1068_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1069_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1070_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1071_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1072_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1073_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1074_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1074_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1075_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1076_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1077_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1078_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1079_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1080_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1081_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1082_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1083_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1097_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1098_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1102_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1103_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1105_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1106_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1107_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1108_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1109_DATA = 0x02600260; + ddr_phy->DENALI_PHY_1110_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1116_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1117_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1118_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1119_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1120_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1121_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1122_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1123_DATA = 0x00C000C0; + ddr_phy->DENALI_PHY_1124_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1125_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1126_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1127_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1128_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1129_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1130_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1131_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1132_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1133_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1134_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1135_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1136_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1137_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[4] << 16) | 0x00000100; + ddr_phy->DENALI_PHY_1138_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[4]); + ddr_phy->DENALI_PHY_1139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1140_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[4] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1141_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[4] << 16) | 0x00000120; + ddr_phy->DENALI_PHY_1142_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[4]); + ddr_phy->DENALI_PHY_1143_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1144_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1145_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1146_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1147_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1148_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1149_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1150_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1151_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1152_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1153_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1154_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1155_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1156_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1157_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1158_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1159_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1160_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1161_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1162_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1163_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1164_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1165_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1166_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1280_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1281_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1282_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1283_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1284_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1285_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1286_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1287_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1288_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1289_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1290_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1291_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1292_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1293_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1294_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1295_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_1296_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1297_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1298_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1299_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1300_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1301_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1302_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1303_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1304_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1305_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1307_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1308_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1309_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1310_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_1311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1312_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1313_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1314_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1315_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1320_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1327_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1328_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1329_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1330_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1330_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1332_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1333_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1334_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1335_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1336_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1337_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1338_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1339_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1340_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1341_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1342_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1347_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1348_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1349_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1350_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1351_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1352_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1353_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1354_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1355_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1356_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1357_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1358_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1359_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1360_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1361_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1362_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1363_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1364_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1365_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1366_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1367_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1368_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1369_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1370_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1371_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1372_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1373_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1374_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1375_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1376_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1377_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1378_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1379_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1380_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1381_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1382_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1383_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1384_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1385_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1386_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1387_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1388_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1389_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1390_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1391_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1392_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1393_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1394_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[5]); + ddr_phy->DENALI_PHY_1395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1396_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[5] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1397_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[5] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1398_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[5]); + ddr_phy->DENALI_PHY_1399_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1400_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1401_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1402_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1403_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1404_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1405_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1406_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1407_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1408_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1409_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1410_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1411_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1412_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1413_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1414_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1415_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1416_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1417_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1418_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1419_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1420_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1536_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1537_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1538_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1539_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1540_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1541_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1542_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1543_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1544_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1545_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1546_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1547_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1548_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1549_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1550_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1551_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_1552_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1553_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1554_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1555_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1556_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1557_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1558_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1559_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1560_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1561_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1562_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1563_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1564_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1565_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1566_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_1567_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1568_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1569_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1570_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1571_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1572_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1573_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1574_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1575_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1576_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1577_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1578_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1579_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1580_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1581_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1582_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1583_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1584_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1585_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1586_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1586_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1587_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1588_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1589_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1590_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1591_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1592_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1593_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1594_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1595_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1596_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1597_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1598_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1599_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1600_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1601_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1602_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1603_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1604_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1605_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1606_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1607_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1608_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1609_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1610_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1611_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1612_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1613_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1614_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1615_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1616_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1617_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1618_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1619_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1620_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1621_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1622_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1623_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1624_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1625_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1626_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1627_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1628_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1629_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1630_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1631_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1632_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1633_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1634_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1635_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1636_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1637_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1638_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1639_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1640_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1641_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1642_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1643_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1644_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1645_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1646_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1647_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1648_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1649_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1650_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[6]); + ddr_phy->DENALI_PHY_1651_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1652_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[6] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1653_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[6] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1654_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[6]); + ddr_phy->DENALI_PHY_1655_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1656_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1657_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1658_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1659_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1660_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1661_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1662_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1663_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1664_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1665_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1666_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1667_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1668_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1669_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1670_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1671_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1672_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1673_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1674_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1675_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1676_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1677_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1678_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1792_DATA = 0x76543210; + ddr_phy->DENALI_PHY_1793_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_1794_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1795_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_1796_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1797_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1798_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1799_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_1800_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_1801_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_1802_DATA = 0x00010000; + ddr_phy->DENALI_PHY_1803_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1804_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1805_DATA = 0x01000100; + ddr_phy->DENALI_PHY_1806_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1807_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_1808_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_1809_DATA = 0x00000008; + ddr_phy->DENALI_PHY_1810_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_1811_DATA = 0x00005555; + ddr_phy->DENALI_PHY_1812_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1813_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_1814_DATA = 0x00005656; + ddr_phy->DENALI_PHY_1815_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1816_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_1817_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_1818_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1819_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_1820_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_1821_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_1822_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_1823_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1824_DATA = 0x04080000; + ddr_phy->DENALI_PHY_1825_DATA = 0x08040400; + ddr_phy->DENALI_PHY_1826_DATA = 0x00000004; + ddr_phy->DENALI_PHY_1827_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_1828_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1829_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1830_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1831_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1832_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1833_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1834_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1835_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1836_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1837_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1838_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1839_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1840_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1841_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_1842_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_1842_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_1843_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1844_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1845_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1846_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1847_DATA = 0x20000004; + ddr_phy->DENALI_PHY_1848_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1849_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1850_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1851_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1852_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1853_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1854_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1855_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1856_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1857_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1858_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1859_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1860_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1861_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1862_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1863_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1864_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1865_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1866_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1867_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1868_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1869_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1870_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_1871_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1872_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1873_DATA = 0x04000000; + ddr_phy->DENALI_PHY_1874_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1875_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1876_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1877_DATA = 0x02800280; + ddr_phy->DENALI_PHY_1878_DATA = 0x00000280; + ddr_phy->DENALI_PHY_1879_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1880_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1881_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1882_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1883_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1884_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1885_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1886_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1887_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1888_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1889_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1890_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1891_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1892_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1893_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1894_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1895_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1896_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1897_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1898_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1899_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1900_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1901_DATA = 0x00960096; + ddr_phy->DENALI_PHY_1902_DATA = 0x10040001; + ddr_phy->DENALI_PHY_1903_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_1904_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1905_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1906_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[7]); + ddr_phy->DENALI_PHY_1907_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1908_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[7] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_1909_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[7] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_1910_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[7]); + ddr_phy->DENALI_PHY_1911_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1912_DATA = 0x00800802; + ddr_phy->DENALI_PHY_1913_DATA = 0x00081020; + ddr_phy->DENALI_PHY_1914_DATA = 0x04010000; + ddr_phy->DENALI_PHY_1915_DATA = 0x61314042; + ddr_phy->DENALI_PHY_1916_DATA = 0x00314000; + ddr_phy->DENALI_PHY_1917_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_1918_DATA = 0x05010080; + ddr_phy->DENALI_PHY_1919_DATA = 0x00000400; + ddr_phy->DENALI_PHY_1920_DATA = 0x42100010; + ddr_phy->DENALI_PHY_1921_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_1922_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_1923_DATA = 0x40420100; + ddr_phy->DENALI_PHY_1924_DATA = 0x40518031; + ddr_phy->DENALI_PHY_1925_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_1926_DATA = 0x00000233; + ddr_phy->DENALI_PHY_1927_DATA = 0x00000203; + ddr_phy->DENALI_PHY_1928_DATA = 0x03000100; + ddr_phy->DENALI_PHY_1929_DATA = 0x20202000; + ddr_phy->DENALI_PHY_1930_DATA = 0x20202020; + ddr_phy->DENALI_PHY_1931_DATA = 0x80202020; + ddr_phy->DENALI_PHY_1932_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_1933_DATA = 0x00000000; + ddr_phy->DENALI_PHY_1934_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2048_DATA = 0x76543210; + ddr_phy->DENALI_PHY_2049_DATA = 0x0004C008; + ddr_phy->DENALI_PHY_2050_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2051_DATA = 0x0000003B; + ddr_phy->DENALI_PHY_2052_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2053_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2054_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2055_DATA = 0x00010000 | phy_dq_tsel_select_value; + ddr_phy->DENALI_PHY_2056_DATA = 0x00010000 | phy_dqs_tsel_select_value; + ddr_phy->DENALI_PHY_2057_DATA = 0x0000010F; + ddr_phy->DENALI_PHY_2058_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2059_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2060_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2061_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2062_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2063_DATA = VREF_TRAINING_CTRL_2933; + ddr_phy->DENALI_PHY_2064_DATA = 0x00C00000; + ddr_phy->DENALI_PHY_2065_DATA = 0x00000008; + ddr_phy->DENALI_PHY_2066_DATA = 0x0000AAAA; + ddr_phy->DENALI_PHY_2067_DATA = 0x00005555; + ddr_phy->DENALI_PHY_2068_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2069_DATA = 0x00004A4A; + ddr_phy->DENALI_PHY_2070_DATA = 0x00005656; + ddr_phy->DENALI_PHY_2071_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2072_DATA = 0x0000A9A9; + ddr_phy->DENALI_PHY_2073_DATA = 0x0000B5B5; + ddr_phy->DENALI_PHY_2074_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2075_DATA = 0xBFBF0000; + ddr_phy->DENALI_PHY_2076_DATA = 0x0000F7F7; + ddr_phy->DENALI_PHY_2077_DATA = (PHY_PAD_VREF_CTRL_DQ_2933 << 16) | 0x0000; + ddr_phy->DENALI_PHY_2078_DATA = PHY_PAD_VREF_CTRL_DQ_2933; + ddr_phy->DENALI_PHY_2079_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2080_DATA = 0x04080000; + ddr_phy->DENALI_PHY_2081_DATA = 0x08040400; + ddr_phy->DENALI_PHY_2082_DATA = 0x00000004; + ddr_phy->DENALI_PHY_2083_DATA = 0x0000E4E4; + ddr_phy->DENALI_PHY_2084_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2085_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2086_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2087_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2088_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2089_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2090_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2091_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2092_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2093_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2094_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2095_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2096_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2097_DATA = 0x00000000; + if (info->dimm_mem_width == 4) { + ddr_phy->DENALI_PHY_2098_DATA = 0x00000000; + } else { + ddr_phy->DENALI_PHY_2098_DATA = 0x00010000; + } + ddr_phy->DENALI_PHY_2099_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2100_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2101_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2102_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2103_DATA = 0x20000004; + ddr_phy->DENALI_PHY_2104_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2105_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2106_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2107_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2108_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2109_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2110_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2111_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2112_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2113_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2114_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2115_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2116_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2117_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2118_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2119_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2120_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2121_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2122_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2123_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2124_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2125_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2126_DATA = 0x000FFF00; + ddr_phy->DENALI_PHY_2127_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2128_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2129_DATA = 0x04000000; + ddr_phy->DENALI_PHY_2130_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2131_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2132_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2133_DATA = 0x02800280; + ddr_phy->DENALI_PHY_2134_DATA = 0x00000280; + ddr_phy->DENALI_PHY_2135_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2136_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2137_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2138_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2139_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2140_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2141_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2142_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2143_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2144_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2145_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2146_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2147_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2148_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2149_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2150_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2151_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2152_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2153_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2154_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2155_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2156_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2157_DATA = 0x00960096; + ddr_phy->DENALI_PHY_2158_DATA = 0x10040001; + ddr_phy->DENALI_PHY_2159_DATA = 0x000F1003; + ddr_phy->DENALI_PHY_2160_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2161_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2162_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[8]); + ddr_phy->DENALI_PHY_2163_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2164_DATA = + (PHY_WRITE_PATH_LAT_ADD_2933[8] << 24) | 0x00010166; + ddr_phy->DENALI_PHY_2165_DATA = + (PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2933[8] << 16) | 0x00000200; + ddr_phy->DENALI_PHY_2166_DATA = + (0x01000000 | PHY_WRLVL_EARLY_FORCE_ZERO_2933[8]); + ddr_phy->DENALI_PHY_2167_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2168_DATA = 0x00800802; + ddr_phy->DENALI_PHY_2169_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2170_DATA = 0x04010000; + ddr_phy->DENALI_PHY_2171_DATA = 0x61314042; + ddr_phy->DENALI_PHY_2172_DATA = 0x00314000; + ddr_phy->DENALI_PHY_2173_DATA = 0x800100F1; + ddr_phy->DENALI_PHY_2174_DATA = 0x05010080; + ddr_phy->DENALI_PHY_2175_DATA = 0x00000400; + ddr_phy->DENALI_PHY_2176_DATA = 0x42100010; + ddr_phy->DENALI_PHY_2177_DATA = 0x120C053E; + ddr_phy->DENALI_PHY_2178_DATA = 0x01400F0C; + ddr_phy->DENALI_PHY_2179_DATA = 0x40420100; + ddr_phy->DENALI_PHY_2180_DATA = 0x40518031; + ddr_phy->DENALI_PHY_2181_DATA = 0x0C058031; + ddr_phy->DENALI_PHY_2182_DATA = 0x00000233; + ddr_phy->DENALI_PHY_2183_DATA = 0x00000203; + ddr_phy->DENALI_PHY_2184_DATA = 0x03000100; + ddr_phy->DENALI_PHY_2185_DATA = 0x20202000; + ddr_phy->DENALI_PHY_2186_DATA = 0x20202020; + ddr_phy->DENALI_PHY_2187_DATA = 0x80202020; + ddr_phy->DENALI_PHY_2188_DATA = 0x3f000080; + ddr_phy->DENALI_PHY_2189_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2190_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2304_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2305_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2306_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2307_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2308_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2309_DATA = 0x00050000; + ddr_phy->DENALI_PHY_2310_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2311_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2312_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2313_DATA = 0x02010000; + ddr_phy->DENALI_PHY_2314_DATA = 0x00008008; + ddr_phy->DENALI_PHY_2315_DATA = 0x00081020; + ddr_phy->DENALI_PHY_2316_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2317_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2318_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2319_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2320_DATA = 0x00010100; + ddr_phy->DENALI_PHY_2321_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2322_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2323_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2324_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2325_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2326_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2327_DATA = 0x64000000; + ddr_phy->DENALI_PHY_2328_DATA = 0x00000050; + ddr_phy->DENALI_PHY_2329_DATA = 0x014A114A; + ddr_phy->DENALI_PHY_2330_DATA = 0x0000014A; + ddr_phy->DENALI_PHY_2331_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2332_DATA = 0x00163F00; + ddr_phy->DENALI_PHY_2333_DATA = 0x42080010; + ddr_phy->DENALI_PHY_2334_DATA = 0x0100003E; + ddr_phy->DENALI_PHY_2335_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2336_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2337_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2338_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2339_DATA = 0x01000100; + ddr_phy->DENALI_PHY_2340_DATA = 0x00000100; + ddr_phy->DENALI_PHY_2341_DATA = 0x80002020; + ddr_phy->DENALI_PHY_2342_DATA = 0x00124924; + ddr_phy->DENALI_PHY_2343_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2344_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2345_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2346_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2347_DATA = 0x070A0707; + ddr_phy->DENALI_PHY_2348_DATA = 0x00005400; + ddr_phy->DENALI_PHY_2349_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2350_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2351_DATA = 0x07C13F99; + ddr_phy->DENALI_PHY_2352_DATA = 0x00000099; + ddr_phy->DENALI_PHY_2353_DATA = phy_pad_data_drive_value; + ddr_phy->DENALI_PHY_2354_DATA = 0x0000073F; + ddr_phy->DENALI_PHY_2355_DATA = 0x0006BF00; + ddr_phy->DENALI_PHY_2356_DATA = 0x013200E0; + ddr_phy->DENALI_PHY_2357_DATA = phy_pad_clk_drive_value; + ddr_phy->DENALI_PHY_2358_DATA = 0x00007000; + ddr_phy->DENALI_PHY_2359_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2360_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2361_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2362_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2363_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2364_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2365_DATA = 0x00073F10; + ddr_phy->DENALI_PHY_2366_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2367_DATA = 0x00024410; + ddr_phy->DENALI_PHY_2368_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2369_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2370_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2371_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2372_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2373_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2374_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2375_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2376_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2377_DATA = 0x0006BF99; + ddr_phy->DENALI_PHY_2378_DATA = 0x00700000; + ddr_phy->DENALI_PHY_2379_DATA = 0x00004410; + ddr_phy->DENALI_PHY_2380_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2381_DATA = 0x04102089; + ddr_phy->DENALI_PHY_2382_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2383_DATA = 0x00020011; + ddr_phy->DENALI_PHY_2384_DATA = 0x00021000; + ddr_phy->DENALI_PHY_2385_DATA = 0x00000448; + ddr_phy->DENALI_PHY_2386_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2387_DATA = 0x04000408; + ddr_phy->DENALI_PHY_2388_DATA = 0x00000020; + ddr_phy->DENALI_PHY_2389_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2390_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2391_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2392_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2393_DATA = 0x03000000; + ddr_phy->DENALI_PHY_2394_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2395_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2396_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2397_DATA = 0x04102035; + ddr_phy->DENALI_PHY_2398_DATA = 0x00041020; + ddr_phy->DENALI_PHY_2399_DATA = 0x01C98C98; + ddr_phy->DENALI_PHY_2400_DATA = 0x3F400000; + ddr_phy->DENALI_PHY_2401_DATA = 0x3F3F1F3F; + ddr_phy->DENALI_PHY_2402_DATA = 0x1F3F3F1F; + ddr_phy->DENALI_PHY_2403_DATA = 0x001F3F3F; + ddr_phy->DENALI_PHY_2404_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2405_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2406_DATA = 0x00010000; + ddr_phy->DENALI_PHY_2407_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2408_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2409_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2410_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2411_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2412_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2413_DATA = 0x00040700; + ddr_phy->DENALI_PHY_2414_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2415_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2416_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2417_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2418_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2419_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2420_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2421_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2422_DATA = 0x00000000; + ddr_phy->DENALI_PHY_2423_DATA = 0x00000002; + ddr_phy->DENALI_PHY_2424_DATA = 0x01000000; + ddr_phy->DENALI_PHY_2425_DATA = 0x0000000F; +} diff --git a/product/morello/module/dmc_bing/src/dimm_spd.c b/product/morello/module/dmc_bing/src/dimm_spd.c index fbacb9054..2a1aca03a 100644 --- a/product/morello/module/dmc_bing/src/dimm_spd.c +++ b/product/morello/module/dmc_bing/src/dimm_spd.c @@ -122,6 +122,11 @@ static int chk_ddr4_dimms( status = FWK_E_DATA; } break; + case 1466: + if ((dimm0_dram_param[18] > 0x06) || (dimm1_dram_param[18] > 0x06)) { + return FWK_E_DATA; + } + break; default: fwk_unexpected(); break; diff --git a/product/morello/module/dmc_bing/src/mod_dmc_bing.c b/product/morello/module/dmc_bing/src/mod_dmc_bing.c index 26ec472a8..309736778 100644 --- a/product/morello/module/dmc_bing/src/mod_dmc_bing.c +++ b/product/morello/module/dmc_bing/src/mod_dmc_bing.c @@ -722,6 +722,9 @@ static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) case 1333: addr = 0x000000A4; break; + case 1466: + addr = 0x000000A5; + break; default: fwk_unexpected(); break; @@ -739,6 +742,9 @@ static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) case 1333: addr = 0x00000347; break; + case 1466: + addr = 0x00000354; + break; default: fwk_unexpected(); break; @@ -822,6 +828,13 @@ static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) addr = 0x00000CA3; } break; + case 1466: + if (ddr_info.number_of_ranks == 1) { + addr = 0x00001095; + } else { + addr = 0x000010A3; + } + break; default: fwk_unexpected(); break; @@ -857,6 +870,10 @@ static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) addr = 0x00000820; ddr_info.cwl_value = 14; break; + case 1466: + addr = 0x00000828; + ddr_info.cwl_value = 16; + break; default: fwk_unexpected(); break; @@ -876,6 +893,9 @@ static int direct_ddr_cmd(struct mod_dmc_bing_reg *dmc) case 1333: addr = 0x00000B44; break; + case 1466: + addr = 0x00000B50; + break; default: fwk_unexpected(); break; @@ -1151,7 +1171,12 @@ int dmc_bing_pre_phy_init(struct mod_dmc_bing_reg *dmc) value = 0; dimm_spd_t_rp(&value); dmc->T_RP_NEXT = value; - dmc->T_RPALL_NEXT = 0x00000013; + + if (ddr_info.speed > 1333) { + dmc->T_RPALL_NEXT = 0x00000016; + } else { + dmc->T_RPALL_NEXT = 0x00000013; + } value = 0; dimm_spd_t_rrd(&value); @@ -1161,30 +1186,80 @@ int dmc_bing_pre_phy_init(struct mod_dmc_bing_reg *dmc) dimm_spd_t_act_window(&value); dmc->T_ACT_WINDOW_NEXT = value; - if ((ddr_info.speed == 1333) || (ddr_info.speed == 1200)) { + if (ddr_info.speed == 1466) { + dmc->T_RTR_NEXT = 0x24090905; + } else if ((ddr_info.speed == 1333) || (ddr_info.speed == 1200)) { dmc->T_RTR_NEXT = 0x24090704; } else { dmc->T_RTR_NEXT = 0x14060604; } dmc->T_RTW_NEXT = 0x001B1B1B; - dmc->T_RTP_NEXT = 0x00000008; - dmc->T_WR_NEXT = 0x00000029; + + if (ddr_info.speed == 1466) { + dmc->T_RTP_NEXT = 0x0000000C; + } else { + dmc->T_RTP_NEXT = 0x00000008; + } + + if (ddr_info.speed == 1466) { + dmc->T_WR_NEXT = 0x0000002C; + } else { + dmc->T_WR_NEXT = 0x00000029; + } + dmc->T_WTR_NEXT = 0x001B1B1B; - if ((ddr_info.speed == 1333) || (ddr_info.speed == 1200)) { + if (ddr_info.speed == 1466) { + dmc->T_WTW_NEXT = 0x24090905; + } else if ((ddr_info.speed == 1333) || (ddr_info.speed == 1200)) { dmc->T_WTW_NEXT = 0x24090704; } else { dmc->T_WTW_NEXT = 0x14060604; } - dmc->T_XMPD_NEXT = 0x00000480; - dmc->T_EP_NEXT = 0x00000006; - dmc->T_XP_NEXT = 0x000e0007; - dmc->T_ESR_NEXT = 0x00000007; - dmc->T_XSR_NEXT = 0x03000384; - dmc->T_ESRCK_NEXT = 0x0000000a; - dmc->T_CKXSR_NEXT = 0x0000000a; + if (ddr_info.speed == 1466) { + dmc->T_XMPD_NEXT = 0x00000640; + } else { + dmc->T_XMPD_NEXT = 0x00000480; + } + + if (ddr_info.speed == 1466) { + dmc->T_EP_NEXT = 0x00000008; + } else { + dmc->T_EP_NEXT = 0x00000006; + } + + if (ddr_info.speed == 1466) { + dmc->T_XP_NEXT = 0x0016000A; + } else { + dmc->T_XP_NEXT = 0x000e0007; + } + + if (ddr_info.speed == 1466) { + dmc->T_ESR_NEXT = 0x00000009; + } else { + dmc->T_ESR_NEXT = 0x00000007; + } + + if (ddr_info.speed == 1466) { + dmc->T_XSR_NEXT = 0x04000240; + } else { + dmc->T_XSR_NEXT = 0x03000384; + } + + if (ddr_info.speed == 1466) { + dmc->T_ESRCK_NEXT = 0x00000012; + } else { + dmc->T_ESRCK_NEXT = 0x0000000a; + } + + if (ddr_info.speed == 1466) { + dmc->T_CKXSR_NEXT = 0x00000014; + } else { + dmc->T_CKXSR_NEXT = 0x0000000a; + } + dmc->T_PARITY_NEXT = 0x00001100; dmc->T_ZQCS_NEXT = 0x00000090; @@ -1198,6 +1273,9 @@ int dmc_bing_pre_phy_init(struct mod_dmc_bing_reg *dmc) case 1333: dmc->T_RDDATA_EN_NEXT = 0x000E000E; break; + case 1466: + dmc->T_RDDATA_EN_NEXT = 0x00100010; + break; default: fwk_unexpected(); break; @@ -1215,6 +1293,9 @@ int dmc_bing_pre_phy_init(struct mod_dmc_bing_reg *dmc) case 1333: dmc->T_PHYWRLAT_NEXT = 0x010A000E; break; + case 1466: + dmc->T_PHYWRLAT_NEXT = 0x010A0010; + break; default: fwk_unexpected(); break; diff --git a/product/morello/module/dmc_bing/src/morello_ddr_phy.c b/product/morello/module/dmc_bing/src/morello_ddr_phy.c index 5d39daf27..99a76e96d 100644 --- a/product/morello/module/dmc_bing/src/morello_ddr_phy.c +++ b/product/morello/module/dmc_bing/src/morello_ddr_phy.c @@ -124,6 +124,9 @@ int morello_ddr_phy_config(fwk_id_t element_id, struct dimm_info *info) info->speed); switch (info->speed) { + case 1466: + ddr_phy_config_1466(ddr_phy, info, element_idx); + break; case 1333: ddr_phy_config_1333(ddr_phy, info, element_idx); break; @@ -364,7 +367,7 @@ int write_eye_detect_single_rank( speed = info->speed; range = 1; - tccd_l = (speed == 800) ? 1 : (speed == 1200) ? 2 : 3; + tccd_l = (speed == 800) ? 1 : (speed == 1200) ? 2 : (speed == 1333) ? 3 : 4; direct_addr = (tccd_l << 10) | (1 << 7) | (range - 1) << 6; direct_cmd = ((1 << rank) << 16) | (0x6 << 8) | 1; @@ -708,6 +711,9 @@ int morello_ddr_phy_post_training_configure( if (info->speed >= 1333) { FWK_LOG_INFO("[DDR-PHY] Performing write eye training..."); + if (info->speed == 1466) { + DEFAULT_DELAY_V2 = 0x238; + } status = write_eye_detect(element_id, info, 0xF, 0x4, 0x2, 0); if (status != FWK_SUCCESS) { FWK_LOG_INFO("[DDR-PHY] FAIL!"); diff --git a/product/morello/module/dmc_bing/src/morello_ddr_phy.h b/product/morello/module/dmc_bing/src/morello_ddr_phy.h index 52ab6b4ee..805f4d8cb 100644 --- a/product/morello/module/dmc_bing/src/morello_ddr_phy.h +++ b/product/morello/module/dmc_bing/src/morello_ddr_phy.h @@ -56,6 +56,20 @@ void ddr_phy_config_1333( struct dimm_info *info, int dmc_id); +/* + * \brief Function to configure and run DDR PHY at 1466MHz frequency. + * + * \param ddr_phy Pointer to DDR PHY register space. + * \param info Pointer to DIMM information. + * \param dmc_id Identifier of the DMC instance. + * + * \retval NONE + */ +void ddr_phy_config_1466( + struct mod_morello_ddr_phy_reg *ddr_phy, + struct dimm_info *info, + int dmc_id); + /*! * \brief Configure a DDR physical device * diff --git a/product/morello/scp_ramfw_soc/config_clock.h b/product/morello/scp_ramfw_soc/config_clock.h index 8480cd3af..ca4b7e6ea 100644 --- a/product/morello/scp_ramfw_soc/config_clock.h +++ b/product/morello/scp_ramfw_soc/config_clock.h @@ -13,7 +13,7 @@ /* * DDR Subsystem clock in MHz */ -#define DDR_CLOCK_MHZ 1333UL +#define DDR_CLOCK_MHZ (4400.0 / 3.0) #define CPU_CLOCK_SUD 2100UL #define CPU_CLOCK_UD 2200UL -- GitLab From cce0b3d1620ef90d9fdadb663b104455f3410d0d Mon Sep 17 00:00:00 2001 From: sah01 Date: Thu, 2 Dec 2021 06:38:18 +0000 Subject: [PATCH 41/41] morello: Split platform_info sds struct for fvp and soc Different platform_info sds struct definition will be used for fvp and soc. Signed-off-by: sahil Signed-off-by: Anurag Koul Change-Id: I99de0ad839a480287a1329f4ab3a0845c9fd757b --- product/morello/include/morello_sds.h | 6 ++++- .../morello_system/src/mod_morello_system.c | 22 +++++++++++-------- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/product/morello/include/morello_sds.h b/product/morello/include/morello_sds.h index 8ff1f4dd5..1992bb505 100644 --- a/product/morello/include/morello_sds.h +++ b/product/morello/include/morello_sds.h @@ -44,7 +44,11 @@ enum morello_sds_region_idx { #define MORELLO_SDS_FEATURE_AVAILABILITY_SIZE 4 #define MORELLO_SDS_CPU_BOOTCTR_SIZE 256 #define MORELLO_SDS_CPU_FLAGS_SIZE 256 -#define MORELLO_SDS_PLATFORM_INFO_SIZE 22 +#if defined(PLAT_FVP) +# define MORELLO_SDS_PLATFORM_INFO_SIZE 8 +#else +# define MORELLO_SDS_PLATFORM_INFO_SIZE 22 +#endif /* * Field masks and offsets for the MORELLO_SDS_AP_CPU_INFO structure. diff --git a/product/morello/module/morello_system/src/mod_morello_system.c b/product/morello/module/morello_system/src/mod_morello_system.c index b9eec3f65..5aff1116e 100644 --- a/product/morello/module/morello_system/src/mod_morello_system.c +++ b/product/morello/module/morello_system/src/mod_morello_system.c @@ -56,22 +56,24 @@ struct FWK_PACKED morello_platform_info { /* Local DDR memory size in bytes */ uint64_t local_ddr_size; +#if !defined(PLAT_FVP) /* Remote DDR memory size in bytes */ uint64_t remote_ddr_size; - /* Total number of slave chips */ - uint8_t slave_count; + /* Total number of remote chips */ + uint8_t remote_chip_count; /* If multichip mode */ bool multichip_mode; /* Platform SCC configuration */ uint32_t scc_config; +#endif }; /* MultiChip information */ struct morello_multichip_info { /* If multichip mode */ bool mode; - /* Total number of slave chips */ - uint8_t slave_count; + /* Total number of remote chips */ + uint8_t remote_chip_count; /* Remote ddr size in GB */ uint8_t remote_ddr_size; }; @@ -286,11 +288,6 @@ static int morello_system_fill_platform_info(void) uint64_t size = 0; int status; - /* Force single chip mode */ - sds_platform_info.slave_count = 0; - sds_platform_info.multichip_mode = 0; - sds_platform_info.remote_ddr_size = 0; - status = morello_system_ctx.dmc_bing_api->get_mem_size(&size); if (status != FWK_SUCCESS) { FWK_LOG_INFO("Error calculating local DDR memory size!"); @@ -298,6 +295,12 @@ static int morello_system_fill_platform_info(void) } sds_platform_info.local_ddr_size = size; +#if !defined(PLAT_FVP) + /* Force single chip mode */ + sds_platform_info.remote_chip_count = 0; + sds_platform_info.multichip_mode = 0; + sds_platform_info.remote_ddr_size = 0; + size = sds_platform_info.local_ddr_size + sds_platform_info.remote_ddr_size; /* Account for size reserved for tag bits storage in dmc-bing client mode */ @@ -311,6 +314,7 @@ static int morello_system_fill_platform_info(void) (size / (1024 * 1024))); sds_platform_info.scc_config = SCC->BOOT_GPR1; +#endif return morello_system_ctx.sds_api->struct_write( sds_structure_desc->id, -- GitLab