diff --git a/module/mhu2/include/mod_mhu2.h b/module/mhu2/include/mod_mhu2.h
new file mode 100644
index 0000000000000000000000000000000000000000..3f87e78046af5dd03ed74a192d467f00bae62226
--- /dev/null
+++ b/module/mhu2/include/mod_mhu2.h
@@ -0,0 +1,66 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *      Message Handling Unit (MHU) v2 Device Driver.
+ */
+
+#ifndef MOD_MHU2_H
+#define MOD_MHU2_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \addtogroup GroupModules Modules
+ * @{
+ */
+
+/*!
+ * \defgroup GroupMHUv2 Message Handling Unit (MHU) v2 Driver
+ * @{
+ */
+
+/*!
+ * \brief MHU v2 api indicies
+ */
+enum mod_mhu2_api_idx {
+    /*! SMT driver API */
+    MOD_MHU2_API_IDX_SMT_DRIVER,
+    /*! Number of APIs */
+    MOD_MHU2_API_IDX_COUNT,
+};
+
+/*!
+ * \brief MHU v2 device
+ *
+ * \details Abstract representation of a bidirectional MHU channel that consists
+ *      of a single receive interrupt line and a pair of register sets, one for
+ *      each direction of communication.
+ */
+struct mod_mhu2_channel_config {
+    /*! IRQ number of the receive interrupt line */
+    unsigned int irq;
+
+    /*! Base address of the registers of the incoming MHU */
+    uintptr_t recv;
+
+    /*! Base address of the registers of the outgoing MHU */
+    uintptr_t send;
+
+    /*! Channel number */
+    unsigned int channel;
+};
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#endif /* MOD_MHU2_H */
diff --git a/module/mhu2/src/Makefile b/module/mhu2/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..0e44a3cc4319d017c0182d83b2bd913deba95707
--- /dev/null
+++ b/module/mhu2/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := MHU2
+BS_LIB_SOURCES := mod_mhu2.c
+
+include $(BS_DIR)/lib.mk
diff --git a/module/mhu2/src/mhu2.h b/module/mhu2/src/mhu2.h
new file mode 100644
index 0000000000000000000000000000000000000000..38bbec0338f80c2d52a180798aec69a64b328988
--- /dev/null
+++ b/module/mhu2/src/mhu2.h
@@ -0,0 +1,67 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MHU2_H
+#define MHU2_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+#define CHANNEL_MAX 124
+
+struct mhu2_id_reg {
+    FWK_R  uint32_t  PID4;
+           uint8_t   RESERVED1[0x10 - 0x4];
+    FWK_R  uint32_t  PID0;
+    FWK_R  uint32_t  PID1;
+    FWK_R  uint32_t  PID2;
+    FWK_R  uint32_t  PID3;
+    FWK_R  uint32_t  COMPID0;
+    FWK_R  uint32_t  COMPID1;
+    FWK_R  uint32_t  COMPID2;
+    FWK_R  uint32_t  COMPID3;
+};
+
+struct mhu2_send_channel_reg {
+    FWK_R  uint32_t  STAT;
+           uint8_t   RESERVED0[0xC - 0x4];
+    FWK_W  uint32_t  STAT_SET;
+           uint8_t   RESERVED1[0x20 - 0x10];
+};
+
+struct mhu2_send_reg {
+    struct mhu2_send_channel_reg channel[CHANNEL_MAX];
+    FWK_R  uint32_t  MSG_NO_CAP;
+    FWK_RW uint32_t  RESP_CFG;
+    FWK_RW uint32_t  ACCESS_REQUEST;
+    FWK_R  uint32_t  ACCESS_READY;
+    FWK_R  uint32_t  INT_ACCESS_STAT;
+    FWK_W  uint32_t  INT_ACCESS_CLR;
+    FWK_W  uint32_t  INT_ACCESS_EN;
+           uint8_t   RESERVED0[0xFD0 - 0xF9C];
+    struct mhu2_id_reg id;
+};
+
+struct mhu2_recv_channel_reg {
+    FWK_R  uint32_t  STAT;
+    FWK_R  uint32_t  STAT_PEND;
+    FWK_W  uint32_t  STAT_CLEAR;
+           uint8_t   RESERVED0[0x10 - 0x0C];
+    FWK_R  uint32_t  MASK;
+    FWK_W  uint32_t  MASK_SET;
+    FWK_W  uint32_t  MASK_CLEAR;
+           uint8_t   RESERVED1[0x20 - 0x1C];
+};
+
+struct mhu2_recv_reg {
+    struct mhu2_recv_channel_reg channel[CHANNEL_MAX];
+    FWK_R  uint32_t  MSG_NO_CAP;
+           uint8_t   RESERVED0[0xFD0 - 0xF84];
+    struct mhu2_id_reg id;
+};
+
+#endif /* MHU2_H */
diff --git a/module/mhu2/src/mod_mhu2.c b/module/mhu2/src/mod_mhu2.c
new file mode 100644
index 0000000000000000000000000000000000000000..8e776c2fce7ec9e4340cb0f5c818c073c7e34642
--- /dev/null
+++ b/module/mhu2/src/mod_mhu2.c
@@ -0,0 +1,292 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *      Message Handling Unit (MHU) v2 Device Driver.
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fwk_assert.h>
+#include <fwk_errno.h>
+#include <fwk_id.h>
+#include <fwk_interrupt.h>
+#include <fwk_mm.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_mhu2.h>
+#include <mhu2.h>
+#include <mod_smt.h>
+
+#define MHU_SLOT_COUNT_MAX 32
+
+struct mhu2_smt_channel {
+    fwk_id_t id;
+    const struct mod_smt_driver_input_api *api;
+};
+
+/* MHU channel context */
+struct mhu2_channel_ctx {
+    /* Pointer to the channel configuration */
+    const struct mod_mhu2_channel_config *config;
+
+    /* Pointer to send register set */
+    struct mhu2_send_reg *send;
+
+    /* Pointers to channel-specific register sets */
+    struct mhu2_send_channel_reg *send_channel;
+    struct mhu2_recv_channel_reg *recv_channel;
+
+    /* Number of slots (represented by sub-elements) */
+    unsigned int slot_count;
+
+    /* Mask of slots that are bound to an SMT channel */
+    uint32_t bound_slots;
+
+    /* Table of SMT channels bound to the channel */
+    struct mhu2_smt_channel *smt_channel_table;
+};
+
+/* MHU v2 context */
+static struct mhu2_ctx {
+    /* Table of channel contexts */
+    struct mhu2_channel_ctx *channel_ctx_table;
+
+    /* Number of channels in the channel context table*/
+    unsigned int channel_count;
+} ctx;
+
+static void mhu2_isr(uintptr_t ctx_param)
+{
+    struct mhu2_channel_ctx *channel_ctx = (struct mhu2_channel_ctx *)ctx_param;
+    unsigned int slot;
+    struct mhu2_smt_channel *smt_channel;
+
+    assert(channel_ctx != NULL);
+
+    while (channel_ctx->recv_channel->STAT != 0) {
+        slot = __builtin_ctz(channel_ctx->recv_channel->STAT);
+
+        /*
+         * If the slot is bound to an SMT channel, signal the message to the
+         * SMT channel.
+         */
+        if (channel_ctx->bound_slots & (1 << slot)) {
+            smt_channel = &channel_ctx->smt_channel_table[slot];
+            smt_channel->api->signal_message(smt_channel->id);
+        }
+
+        /* Acknowledge the interrupt */
+        channel_ctx->recv_channel->STAT_CLEAR = 1 << slot;
+    }
+}
+
+/*
+ * SMT module driver API
+ */
+
+static int raise_interrupt(fwk_id_t slot_id)
+{
+    int status;
+    unsigned int slot;
+    struct mhu2_channel_ctx *channel_ctx;
+    struct mhu2_send_reg *send;
+
+    status = fwk_module_check_call(slot_id);
+    if (status != FWK_SUCCESS)
+        return status;
+
+    channel_ctx = &ctx.channel_ctx_table[fwk_id_get_element_idx(slot_id)];
+    slot = fwk_id_get_sub_element_idx(slot_id);
+    send = channel_ctx->send;
+
+    /* Turn on receiver */
+    send->ACCESS_REQUEST = 1;
+    while (send->ACCESS_READY != 1)
+        continue;
+
+    channel_ctx->send_channel->STAT_SET |= (1 << slot);
+
+    /* Signal that the receiver is no longer needed */
+    send->ACCESS_REQUEST = 0;
+
+    return FWK_SUCCESS;
+}
+
+static const struct mod_smt_driver_api mhu2_mod_smt_driver_api = {
+    .raise_interrupt = raise_interrupt,
+};
+
+/*
+ * Framework handlers
+ */
+
+static int mhu2_init(fwk_id_t module_id,
+                     unsigned int channel_count,
+                     const void *unused)
+{
+    if (channel_count == 0) {
+        /* There must be at least 1 mhu channel */
+        assert(false);
+        return FWK_E_PARAM;
+    }
+
+    ctx.channel_ctx_table = fwk_mm_calloc(channel_count,
+        sizeof(ctx.channel_ctx_table[0]));
+    if (ctx.channel_ctx_table == NULL) {
+        /* Unable to allocate memory for channel context table */
+        assert(false);
+        return FWK_E_NOMEM;
+    }
+
+    ctx.channel_count = channel_count;
+
+    return FWK_SUCCESS;
+}
+
+static int mhu2_channel_init(fwk_id_t channel_id,
+                             unsigned int slot_count,
+                             const void *data)
+{
+    const struct mod_mhu2_channel_config *config = data;
+    struct mhu2_channel_ctx *channel_ctx;
+    struct mhu2_recv_reg *recv_reg;
+
+    if ((config == NULL) || (config->recv == 0) || (config->send == 0)) {
+        assert(false);
+        return FWK_E_DATA;
+    }
+
+    channel_ctx = &ctx.channel_ctx_table[fwk_id_get_element_idx(channel_id)];
+    channel_ctx->send = (struct mhu2_send_reg *)config->send;
+
+    if (config->channel >= channel_ctx->send->MSG_NO_CAP) {
+        assert(false);
+        return FWK_E_DATA;
+    }
+
+    channel_ctx->config = config;
+    channel_ctx->slot_count = slot_count;
+    channel_ctx->send_channel = &channel_ctx->send->channel[config->channel];
+    recv_reg = (struct mhu2_recv_reg *)config->recv;
+    channel_ctx->recv_channel = &recv_reg->channel[config->channel];
+
+    channel_ctx->smt_channel_table =
+        fwk_mm_calloc(slot_count, sizeof(channel_ctx->smt_channel_table[0]));
+    if (channel_ctx->smt_channel_table == NULL) {
+        assert(false);
+        return FWK_E_NOMEM;
+    }
+
+    return FWK_SUCCESS;
+}
+
+static int mhu2_bind(fwk_id_t id, unsigned int round)
+{
+    int status;
+    struct mhu2_channel_ctx *channel_ctx;
+    unsigned int slot;
+    struct mhu2_smt_channel *smt_channel;
+
+    if ((round == 1) && fwk_id_is_type(id, FWK_ID_TYPE_ELEMENT)) {
+        channel_ctx = &ctx.channel_ctx_table[fwk_id_get_element_idx(id)];
+
+        for (slot = 0; slot < MHU_SLOT_COUNT_MAX; slot++) {
+            if (!(channel_ctx->bound_slots & (1 << slot)))
+                continue;
+
+            smt_channel = &channel_ctx->smt_channel_table[slot];
+
+            status = fwk_module_bind(smt_channel->id,
+                                     FWK_ID_API(FWK_MODULE_IDX_SMT,
+                                                MOD_SMT_API_IDX_DRIVER_INPUT),
+                                     &smt_channel->api);
+            if (status != FWK_SUCCESS) {
+                /* Unable to bind back to SMT channel */
+                assert(false);
+                return status;
+            }
+        }
+    }
+
+    return FWK_SUCCESS;
+}
+
+static int mhu2_process_bind_request(fwk_id_t source_id,
+                                    fwk_id_t target_id,
+                                    fwk_id_t api_id,
+                                    const void **api)
+{
+    struct mhu2_channel_ctx *channel_ctx;
+    unsigned int slot;
+
+    if (!fwk_id_is_type(target_id, FWK_ID_TYPE_SUB_ELEMENT)) {
+        /*
+         * Something tried to bind to the module or an element. Only binding to
+         * a slot (sub-element) is allowed.
+         */
+        assert(false);
+        return FWK_E_ACCESS;
+    }
+
+    channel_ctx = &ctx.channel_ctx_table[fwk_id_get_element_idx(target_id)];
+    slot = fwk_id_get_sub_element_idx(target_id);
+
+    if (channel_ctx->bound_slots & (1 << slot)) {
+        /* Something tried to bind to a slot that has already been bound to */
+        assert(false);
+        return FWK_E_ACCESS;
+    }
+
+    channel_ctx->smt_channel_table[slot].id = source_id;
+    channel_ctx->bound_slots |= 1 << slot;
+
+    *api = &mhu2_mod_smt_driver_api;
+
+    return FWK_SUCCESS;
+}
+
+static int mhu2_start(fwk_id_t id)
+{
+    int status;
+    struct mhu2_channel_ctx *channel_ctx;
+
+    if (fwk_id_get_type(id) == FWK_ID_TYPE_MODULE)
+        return FWK_SUCCESS;
+
+    channel_ctx = &ctx.channel_ctx_table[fwk_id_get_element_idx(id)];
+
+    if (channel_ctx->bound_slots != 0) {
+        status = fwk_interrupt_set_isr_param(channel_ctx->config->irq,
+                                             &mhu2_isr,
+                                             (uintptr_t)channel_ctx);
+        if (status != FWK_SUCCESS) {
+            /* Failed to set isr */
+            assert(false);
+            return status;
+        }
+        status = fwk_interrupt_enable(channel_ctx->config->irq);
+        if (status != FWK_SUCCESS) {
+            /* Failed to enable isr */
+            assert(false);
+            return status;
+        }
+    }
+
+    return FWK_SUCCESS;
+}
+
+/* MHU v2 module definition */
+const struct fwk_module module_mhu2 = {
+    .name = "MHU2",
+    .type = FWK_MODULE_TYPE_DRIVER,
+    .api_count = MOD_MHU2_API_IDX_COUNT,
+    .init = mhu2_init,
+    .element_init = mhu2_channel_init,
+    .bind = mhu2_bind,
+    .start = mhu2_start,
+    .process_bind_request = mhu2_process_bind_request,
+};
diff --git a/module/pcid/include/mod_pcid.h b/module/pcid/include/mod_pcid.h
new file mode 100644
index 0000000000000000000000000000000000000000..3e1492a8577740d60c79ec29d2af3193fb7c6bb7
--- /dev/null
+++ b/module/pcid/include/mod_pcid.h
@@ -0,0 +1,70 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MOD_PCID_H
+#define MOD_PCID_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \addtogroup GroupModules Modules
+ * @{
+ */
+
+/*!
+ * \defgroup GroupModulePCID PCID
+ *
+ * \brief Module used to check the peripheral and component IDs.
+ *
+ * @{
+ */
+
+/*!
+ * \brief PID and CID registers.
+ */
+struct mod_pcid_registers {
+    FWK_R uint32_t PID4; /*!< Peripheral ID 4 */
+    FWK_R uint32_t PID5; /*!< Peripheral ID 5 */
+    FWK_R uint32_t PID6; /*!< Peripheral ID 6 */
+    FWK_R uint32_t PID7; /*!< Peripheral ID 7 */
+    FWK_R uint32_t PID0; /*!< Peripheral ID 0 */
+    FWK_R uint32_t PID1; /*!< Peripheral ID 1 */
+    FWK_R uint32_t PID2; /*!< Peripheral ID 2 */
+    FWK_R uint32_t PID3; /*!< Peripheral ID 3 */
+    FWK_R uint32_t CID0; /*!< Component ID 0 */
+    FWK_R uint32_t CID1; /*!< Component ID 1 */
+    FWK_R uint32_t CID2; /*!< Component ID 2 */
+    FWK_R uint32_t CID3; /*!< Component ID 3 */
+};
+
+/*!
+ * \brief Check peripheral and component id registers against expected values.
+ *
+ * \param registers Pointer to set of PCID registers to check.
+ * \param expected Pointer to set of PCID Registers that denote the expected
+ *     values.
+ *
+ * \pre \p registers must not be NULL
+ * \pre \p expected must not be NULL
+ *
+ * \retval true All the registers have the expected values.
+ * \retval false One or more registers do not have the expected values.
+ */
+bool mod_pcid_check_registers(const struct mod_pcid_registers *registers,
+                              const struct mod_pcid_registers *expected);
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#endif /* MOD_PCID_H */
diff --git a/module/pcid/src/Makefile b/module/pcid/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..178e971724eee062403243c51f97d76b70fa8230
--- /dev/null
+++ b/module/pcid/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := PCID
+BS_LIB_SOURCES := mod_pcid.c
+
+include $(BS_DIR)/lib.mk
diff --git a/module/pcid/src/mod_pcid.c b/module/pcid/src/mod_pcid.c
new file mode 100644
index 0000000000000000000000000000000000000000..c6b8e4cf85930872d7b43788ae4fe244dc7fd3b1
--- /dev/null
+++ b/module/pcid/src/mod_pcid.c
@@ -0,0 +1,35 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <string.h>
+#include <fwk_assert.h>
+#include <fwk_module.h>
+#include <mod_pcid.h>
+
+bool mod_pcid_check_registers(const struct mod_pcid_registers *registers,
+                              const struct mod_pcid_registers *expected)
+{
+    assert(registers != NULL);
+    assert(expected != NULL);
+
+    return !memcmp(registers, expected, sizeof(*registers));
+}
+
+static int pcid_init(fwk_id_t module_id,
+                     unsigned int element_count,
+                     const void *data)
+{
+    return FWK_SUCCESS;
+}
+
+const struct fwk_module_config config_pcid = { 0 };
+const struct fwk_module module_pcid = {
+    .name = "PCID",
+    .type = FWK_MODULE_TYPE_SERVICE,
+    .init = pcid_init,
+};
diff --git a/module/sid/include/mod_sid.h b/module/sid/include/mod_sid.h
new file mode 100644
index 0000000000000000000000000000000000000000..54e0446d5c7ffb80092257714895f48d42184b39
--- /dev/null
+++ b/module/sid/include/mod_sid.h
@@ -0,0 +1,123 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MOD_SID_H
+#define MOD_SID_H
+
+#include <stdint.h>
+#include <fwk_id.h>
+#include <fwk_module_idx.h>
+#include <mod_pcid.h>
+
+/*!
+ * \addtogroup GroupModules Modules
+ * @{
+ */
+
+/*!
+ * \defgroup GroupModuleSID System Identification (SID)
+ *
+ * \brief Module used to interface with the SID register set.
+ *
+ * \details This module uses the SID register set to get information about the
+ *     subsystem that the firmware is running on. @{
+ */
+
+/*!
+ * \brief Module API indicies.
+ */
+enum mod_sid_api_idx {
+    MOD_SID_API_IDX_INFO, /*!< Index of the info api. */
+    MOD_SID_API_COUNT,    /*!< Number of apis. */
+};
+
+/*!
+ * \brief Info API id.
+ */
+static const fwk_id_t mod_sid_api_id_info =
+    FWK_ID_API_INIT(FWK_MODULE_IDX_SID, MOD_SID_API_IDX_INFO);
+
+/*!
+ * \brief System information
+ */
+struct mod_sid_info {
+    /*! Major revision number of the subsystem */
+    unsigned int system_major_revision;
+
+    /*! Minor revision number of the subsystem */
+    unsigned int system_minor_revision;
+
+    /*! Designer ID of the subsystem */
+    unsigned int system_designer_id;
+
+    /*! Part number of the subsystem */
+    unsigned int system_part_number;
+
+    /*! Major revision number of the SoC */
+    unsigned int soc_major_revision;
+
+    /*! Minor revision number of the SoC */
+    unsigned int soc_minor_revision;
+
+    /*! Designer ID of the SoC */
+    unsigned int soc_designer_id;
+
+    /*! Part number of the SoC */
+    unsigned int soc_part_number;
+
+    /*! ID for the node when there are multiple sockets */
+    unsigned int node_id;
+
+    /*! Configuration number of the subsystem */
+    unsigned int config_number;
+
+    /*! Name of the subsystem */
+    const char *name;
+
+    /*! Element index of the subsystem */
+    unsigned int system_idx;
+};
+
+/*!
+ * \brief Module configuration.
+ */
+struct mod_sid_config {
+    /*! Base address of the SID registers. */
+    uintptr_t sid_base;
+
+    /*! Expected values of the PID and CID registers */
+    struct mod_pcid_registers pcid_expected;
+};
+
+/*!
+ * \brief Subsystem configuration.
+ */
+struct mod_sid_subsystem_config {
+    unsigned int part_number; /*!< Part number of the subsystem */
+};
+
+/*!
+ * \brief Module interface.
+ */
+struct mod_sid_api_info {
+    /*!
+     * \brief Get a pointer to the structure holding the system information.
+     *
+     * \return Pointer to system information structure.
+     */
+    const struct mod_sid_info * (*get_system_info)(void);
+};
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#endif /* MOD_SID_H */
diff --git a/module/sid/src/Makefile b/module/sid/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..4549c344a86202158cd60425db95907cbb63deb2
--- /dev/null
+++ b/module/sid/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := SID
+BS_LIB_SOURCES := mod_sid.c
+
+include $(BS_DIR)/lib.mk
diff --git a/module/sid/src/mod_sid.c b/module/sid/src/mod_sid.c
new file mode 100644
index 0000000000000000000000000000000000000000..9dfae234111a6f4d093f945026bb1236746e2579
--- /dev/null
+++ b/module/sid/src/mod_sid.c
@@ -0,0 +1,116 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_assert.h>
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <fwk_mm.h>
+#include <mod_pcid.h>
+#include <mod_sid.h>
+#include <sid_reg.h>
+
+static struct mod_sid_info info;
+
+static const struct mod_sid_info* get_system_info(void)
+{
+    return &info;
+}
+
+static const struct mod_sid_api_info info_api = {
+    .get_system_info = get_system_info,
+};
+
+static int sid_init(
+    fwk_id_t module_id,
+    unsigned int element_count,
+    const void *data)
+{
+    const struct mod_sid_config *config = data;
+    struct sid_reg *sid_reg;
+
+    if ((config == NULL) || (config->sid_base == 0) || (element_count == 0)) {
+        assert(false);
+        return FWK_E_DATA;
+    }
+
+    sid_reg = (struct sid_reg *)config->sid_base;
+
+    assert(mod_pcid_check_registers(&sid_reg->pcid, &config->pcid_expected));
+
+    info.system_major_revision =
+        (sid_reg->SYSTEM_ID & SID_SYS_SOC_ID_MAJOR_REVISION_MASK)
+        >> SID_SYS_SOC_ID_MAJOR_REVISION_POS;
+
+    info.system_minor_revision =
+        (sid_reg->SYSTEM_ID & SID_SYS_SOC_ID_MINOR_REVISION_MASK)
+        >> SID_SYS_SOC_ID_MINOR_REVISION_POS;
+
+    info.system_designer_id =
+        (sid_reg->SYSTEM_ID & SID_SYS_SOC_ID_DESIGNER_ID_MASK)
+        >> SID_SYS_SOC_ID_DESIGNER_ID_POS;
+
+    info.system_part_number =
+        sid_reg->SYSTEM_ID & SID_SYS_SOC_ID_PART_NUMBER_MASK;
+
+    info.soc_major_revision =
+        (sid_reg->SOC_ID & SID_SYS_SOC_ID_MAJOR_REVISION_MASK)
+        >> SID_SYS_SOC_ID_MAJOR_REVISION_POS;
+
+    info.soc_minor_revision =
+        (sid_reg->SOC_ID & SID_SYS_SOC_ID_MINOR_REVISION_MASK)
+        >> SID_SYS_SOC_ID_MINOR_REVISION_POS;
+
+    info.soc_designer_id =
+        (sid_reg->SOC_ID & SID_SYS_SOC_ID_DESIGNER_ID_MASK)
+        >> SID_SYS_SOC_ID_DESIGNER_ID_POS;
+
+    info.soc_part_number = sid_reg->SOC_ID & SID_SYS_SOC_ID_PART_NUMBER_MASK;
+
+    info.config_number = sid_reg->SYSTEM_CFG;
+    info.node_id = sid_reg->NODE_ID & SID_SYS_NODE_ID_IDENTIFIER_MASK;
+
+    return FWK_SUCCESS;
+}
+
+static int sid_subsystem_init(
+    fwk_id_t subsystem_id,
+    unsigned int unused,
+    const void *data)
+{
+    const struct mod_sid_subsystem_config *subsystem_config;
+
+    assert(data != NULL);
+
+    subsystem_config = data;
+    if (subsystem_config->part_number == info.system_part_number) {
+        info.system_idx = fwk_id_get_element_idx(subsystem_id);
+        info.name = fwk_module_get_name(
+            FWK_ID_ELEMENT(FWK_MODULE_IDX_SID, info.system_idx));
+    }
+
+    return FWK_SUCCESS;
+}
+
+static int sid_proc_bind_req(
+    fwk_id_t requester_id,
+    fwk_id_t id,
+    fwk_id_t api_id,
+    const void **api)
+{
+    *api = &info_api;
+    return FWK_SUCCESS;
+}
+
+const struct fwk_module module_sid = {
+    .name = "SID",
+    .type = FWK_MODULE_TYPE_DRIVER,
+    .api_count = MOD_SID_API_COUNT,
+    .init = sid_init,
+    .element_init = sid_subsystem_init,
+    .process_bind_request = sid_proc_bind_req,
+};
diff --git a/module/sid/src/sid_reg.h b/module/sid/src/sid_reg.h
new file mode 100644
index 0000000000000000000000000000000000000000..f9cf0d6507344a33bb5e0a36d4d1b9ffe67704ff
--- /dev/null
+++ b/module/sid/src/sid_reg.h
@@ -0,0 +1,41 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SID_REG_H
+#define SID_REG_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+#include <mod_pcid.h>
+
+struct sid_reg {
+            uint8_t   RESERVED0[0x40 - 0];
+    FWK_R   uint32_t  SYSTEM_ID;
+            uint8_t   RESERVED1[0x50 - 0x44];
+    FWK_R   uint32_t  SOC_ID;
+            uint8_t   RESERVED2[0x60 - 0x54];
+    FWK_R   uint32_t  NODE_ID;
+            uint8_t   RESERVED3[0x70 - 0x64];
+    FWK_R   uint32_t  SYSTEM_CFG;
+            uint8_t   RESERVED4[0xFD0 - 0x74];
+    const struct mod_pcid_registers pcid;
+};
+
+#define SID_SYS_SOC_ID_PART_NUMBER_MASK UINT32_C(0xFFF)
+
+#define SID_SYS_SOC_ID_DESIGNER_ID_MASK UINT32_C(0xFF000)
+#define SID_SYS_SOC_ID_DESIGNER_ID_POS  UINT32_C(12)
+
+#define SID_SYS_SOC_ID_MINOR_REVISION_MASK UINT32_C(0xF00000)
+#define SID_SYS_SOC_ID_MINOR_REVISION_POS  UINT32_C(20)
+
+#define SID_SYS_SOC_ID_MAJOR_REVISION_MASK UINT32_C(0xF000000)
+#define SID_SYS_SOC_ID_MAJOR_REVISION_POS  UINT32_C(24)
+
+#define SID_SYS_NODE_ID_IDENTIFIER_MASK UINT32_C(0xFF)
+
+#endif /* SID_REG_H */
diff --git a/product/clark/include/clark_core.h b/product/clark/include/clark_core.h
new file mode 100644
index 0000000000000000000000000000000000000000..3cd141028a3bfbec8f81cd40aa99da868f868f25
--- /dev/null
+++ b/product/clark/include/clark_core.h
@@ -0,0 +1,17 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLARK_CORE_H
+#define CLARK_CORE_H
+
+#define CLARK_CORE_PER_CLUSTER_MAX 8
+
+unsigned int clark_core_get_core_per_cluster_count(unsigned int cluster);
+unsigned int clark_core_get_core_count(void);
+unsigned int clark_core_get_cluster_count(void);
+
+#endif /* CLARK_CORE_H */
diff --git a/product/clark/include/clark_pik_cpu.h b/product/clark/include/clark_pik_cpu.h
new file mode 100644
index 0000000000000000000000000000000000000000..8719e7ea8a2bc31f8d065fa9b9af51e0280fefc6
--- /dev/null
+++ b/product/clark/include/clark_pik_cpu.h
@@ -0,0 +1,92 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLARK_PIK_CPU_H
+#define CLARK_PIK_CPU_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \brief PE Static Configuration register definitions
+ */
+struct static_config_reg {
+    FWK_RW  uint32_t STATIC_CONFIG;
+    FWK_RW  uint32_t RVBARADDR_LW;
+    FWK_RW  uint32_t RVBARADDR_UP;
+            uint32_t RESERVED;
+};
+
+/*!
+ * \brief AP cores clock control register definitions
+ */
+struct coreclk_reg {
+    FWK_RW  uint32_t CTRL;
+    FWK_RW  uint32_t DIV;
+            uint32_t RESERVED;
+    FWK_RW  uint32_t MOD;
+};
+
+/*!
+ * \brief CPU (V8.2) PIK register definitions
+ */
+struct pik_cpu_reg {
+    FWK_RW  uint32_t     CLUSTER_CONFIG;
+            uint8_t      RESERVED0[0x10 - 0x4];
+    struct static_config_reg STATIC_CONFIG[16];
+            uint8_t      RESERVED1[0x800 - 0x110];
+    FWK_RW  uint32_t     PPUCLK_CTRL;
+    FWK_RW  uint32_t     PPUCLK_DIV1;
+            uint8_t      RESERVED2[0x810 - 0x808];
+    FWK_RW  uint32_t     PCLK_CTRL;
+            uint8_t      RESERVED3[0x820 - 0x814];
+    FWK_RW  uint32_t     DBGCLK_CTRL;
+    FWK_RW  uint32_t     DBGCLK_DIV1;
+            uint8_t      RESERVED4[0x830 - 0x828];
+    FWK_RW  uint32_t     GICCLK_CTRL;
+            uint8_t      RESERVED5[0x840 - 0x834];
+    FWK_RW  uint32_t     AMBACLK_CTRL;
+            uint8_t      RESERVED6[0x850 - 0x844];
+    FWK_RW  uint32_t     CLUSCLK_CTRL;
+    FWK_RW  uint32_t     CLUSCLK_DIV1;
+            uint8_t      RESERVED7[0x860 - 0x858];
+    struct coreclk_reg   CORECLK[8];
+            uint8_t      RESERVED8[0xA00 - 0x8E0];
+    FWK_R   uint32_t     CLKFORCE_STATUS;
+    FWK_W   uint32_t     CLKFORCE_SET;
+    FWK_W   uint32_t     CLKFORCE_CLR;
+            uint8_t      RESERVED9[0xB00 - 0xA0C];
+    FWK_R   uint32_t     NERRIQ_INT_STATUS;
+    FWK_R   uint32_t     NFAULTIQ_INT_STATUS;
+            uint8_t      RESERVED10[0xFB4 - 0xB08];
+    FWK_R   uint32_t     CAP3;
+    FWK_R   uint32_t     CAP2;
+    FWK_R   uint32_t     CAP;
+    FWK_R   uint32_t     PCL_CONFIG;
+            uint8_t      RESERVED11[0xFD0 - 0xFC4];
+    FWK_R   uint32_t     PID4;
+    FWK_R   uint32_t     PID5;
+    FWK_R   uint32_t     PID6;
+    FWK_R   uint32_t     PID7;
+    FWK_R   uint32_t     PID0;
+    FWK_R   uint32_t     PID1;
+    FWK_R   uint32_t     PID2;
+    FWK_R   uint32_t     PID3;
+    FWK_R   uint32_t     ID0;
+    FWK_R   uint32_t     ID1;
+    FWK_R   uint32_t     ID2;
+    FWK_R   uint32_t     ID3;
+};
+
+#define PIK_CPU_CAP_CLUSSYNC       UINT32_C(0x00000001)
+#define PIK_CPU_CAP_CORESYNC(CORE) ((uint32_t)(1 << ((CORE) + 1)))
+#define PIK_CPU_CAP_PE_MASK        UINT32_C(0xF0000000)
+#define PIK_CPU_CAP_PE_POS         28
+
+#define PIK_CPU_PCL_CONFIG_NO_OF_PPU UINT32_C(0x0000000F)
+
+#endif  /* CLARK_PIK_CPU_H */
diff --git a/product/clark/include/clark_pik_debug.h b/product/clark/include/clark_pik_debug.h
new file mode 100644
index 0000000000000000000000000000000000000000..9de5ddbd6f6bc0c4269136855ab37e830f0c5bfc
--- /dev/null
+++ b/product/clark/include/clark_pik_debug.h
@@ -0,0 +1,50 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLARK_PIK_DEBUG_H
+#define CLARK_PIK_DEBUG_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \brief Debug register definitions
+ */
+struct pik_debug_reg {
+    FWK_RW  uint32_t DEBUG_CTRL;
+    FWK_R   uint32_t DEBUG_STATUS;
+    FWK_RW  uint32_t DEBUG_CONFIG;
+            uint8_t  RESERVED0[0x10 - 0xC];
+    FWK_R   uint32_t APP_DAP_TARGET_ID;
+    FWK_R   uint32_t SCP_DAP_TARGET_ID;
+    FWK_R   uint32_t DAP_INSTANCE_ID;
+            uint8_t  RESERVED1[0x810 - 0x1C];
+    FWK_RW  uint32_t TRACECLK_CTRL;
+    FWK_RW  uint32_t TRACECLK_DIV1;
+            uint8_t  RESERVED2[0x820 - 0x818];
+    FWK_RW  uint32_t PCLKDBG_CTRL;
+            uint8_t  RESERVED3[0x830 - 0x824];
+    FWK_RW  uint32_t ATCLKDBG_CTRL;
+    FWK_RW  uint32_t ATCLKDBG_DIV1;
+    FWK_R   uint8_t  RESERVED4[0xFC0 - 0x838];
+    FWK_R   uint32_t PCL_CONFIG;
+            uint8_t  RESERVED5[0xFD0 - 0xFC4];
+    FWK_R   uint32_t PID4;
+    FWK_R   uint32_t PID5;
+    FWK_R   uint32_t PID6;
+    FWK_R   uint32_t PID7;
+    FWK_R   uint32_t PID0;
+    FWK_R   uint32_t PID1;
+    FWK_R   uint32_t PID2;
+    FWK_R   uint32_t PID3;
+    FWK_R   uint32_t ID0;
+    FWK_R   uint32_t ID1;
+    FWK_R   uint32_t ID2;
+    FWK_R   uint32_t ID3;
+};
+
+#endif  /* CLARK_PIK_DEBUG_H */
diff --git a/product/clark/include/clark_pik_scp.h b/product/clark/include/clark_pik_scp.h
new file mode 100644
index 0000000000000000000000000000000000000000..e02c23f7de03b7a86f0ad9c59d0fc1efcff6875c
--- /dev/null
+++ b/product/clark/include/clark_pik_scp.h
@@ -0,0 +1,100 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     SCP PIK registers
+ */
+
+#ifndef CLARK_PIK_SCP_H
+#define CLARK_PIK_SCP_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \brief SCP PIK register definitions
+ */
+struct pik_scp_reg {
+            uint8_t   RESERVED0[0x10 - 0x0];
+    FWK_RW  uint32_t  RESET_SYNDROME;
+            uint8_t   RESERVED1[0x20 - 0x14];
+    FWK_RW  uint32_t  SURVIVAL_RESET_STATUS;
+            uint8_t   RESERVED2[0x34 - 0x24];
+    FWK_RW  uint32_t  ADDR_TRANS;
+    FWK_RW  uint32_t  DBG_ADDR_TRANS;
+            uint8_t   RESERVED3[0x40 - 0x3C];
+    FWK_RW  uint32_t  WS1_TIMER_MATCH;
+    FWK_RW  uint32_t  WS1_TIMER_EN;
+            uint8_t   RESERVED4[0x200 - 0x48];
+    FWK_R   uint32_t  SS_RESET_STATUS;
+    FWK_W   uint32_t  SS_RESET_SET;
+    FWK_W   uint32_t  SS_RESET_CLR;
+            uint8_t   RESERVED5[0x810 - 0x20C];
+    FWK_RW  uint32_t  CORECLK_CTRL;
+    FWK_RW  uint32_t  CORECLK_DIV1;
+            uint8_t   RESERVED6[0x820 - 0x818];
+    FWK_RW  uint32_t  ACLK_CTRL;
+    FWK_RW  uint32_t  ACLK_DIV1;
+            uint8_t   RESERVED7[0x830 - 0x828];
+    FWK_RW  uint32_t  GTSYNCCLK_CTRL;
+    FWK_RW  uint32_t  GTSYNCCLK_DIV1;
+            uint8_t   RESERVED8[0xA10 - 0x838];
+    FWK_R   uint32_t  PLL_STATUS[17];
+            uint8_t   RESERVED9[0xA60 - 0xA54];
+    FWK_R   uint32_t  CONS_MMUTCU_INT_STATUS;
+    FWK_R   uint32_t  CONS_MMUTBU_INT_STATUS0;
+    FWK_R   uint32_t  CONS_MMUTBU_INT_STATUS1;
+    FWK_W   uint32_t  CONS_MMUTCU_INT_CLR;
+    FWK_W   uint32_t  CONS_MMUTBU_INT_CLR0;
+    FWK_W   uint32_t  CONS_MMUTBU_INT_CLR1;
+            uint8_t   RESERVED10[0xB00 - 0xA78];
+    FWK_R   uint32_t  MHU_NS_INT_STATUS;
+    FWK_R   uint32_t  MHU_S_INT_STATUS;
+            uint8_t   RESERVED11[0xB20 - 0xB08];
+    FWK_R   uint32_t  CPU_PPU_INT_STATUS[8];
+    FWK_R   uint32_t  CLUS_PPU_INT_STATUS;
+            uint8_t   RESERVED12[0xB60 - 0xB44];
+    FWK_R   uint32_t  TIMER_INT_STATUS[8];
+    FWK_R   uint32_t  CPU_PLL_LOCK_STATUS[8];
+            uint8_t   RESERVED13[0xBC0 - 0xBA0];
+    FWK_R   uint32_t  CPU_PLL_UNLOCK_STATUS[8];
+            uint8_t   RESERVED14[0xBF0 - 0xBE0];
+    FWK_R   uint32_t  CLUSTER_PLL_LOCK_STATUS;
+    FWK_R   uint32_t  CLUSTER_PLL_UNLOCK_STATUS;
+            uint8_t   RESERVED15[0xC00 - 0xBF8];
+    FWK_R   uint32_t  CLUS_FAULT_INT_STATUS;
+            uint8_t   RESERVED16[0xC30 - 0xC04];
+    FWK_R   uint32_t  CLUSTER_ECCERR_INT_STATUS;
+            uint8_t   RESERVED17[0xD00 - 0xC34];
+    FWK_R   uint32_t  DMC0_4_INT_STATUS;
+    FWK_R   uint32_t  DMC1_5_INT_STATUS;
+    FWK_R   uint32_t  DMC2_6_INT_STATUS;
+    FWK_R   uint32_t  DMC3_7_INT_STATUS;
+            uint8_t   RESERVED18[0xFC0 - 0xD10];
+    FWK_R   uint32_t  PCL_CFG;
+            uint8_t   RESERVED19[0xFD0 - 0xFC4];
+    FWK_R   uint32_t  PID4;
+    FWK_R   uint32_t  PID5;
+    FWK_R   uint32_t  PID6;
+    FWK_R   uint32_t  PID7;
+    FWK_R   uint32_t  PID0;
+    FWK_R   uint32_t  PID1;
+    FWK_R   uint32_t  PID2;
+    FWK_R   uint32_t  PID3;
+    FWK_R   uint32_t  ID0;
+    FWK_R   uint32_t  ID1;
+    FWK_R   uint32_t  ID2;
+    FWK_R   uint32_t  ID3;
+};
+
+#define PLL_STATUS_0_REFCLK      UINT32_C(0x00000001)
+#define PLL_STATUS_0_SYSPLLLOCK  UINT32_C(0x00000002)
+#define PLL_STATUS_0_DDRPLLLOCK  UINT32_C(0x00000004)
+#define PLL_STATUS_0_INTPLLLOCK  UINT32_C(0x00000008)
+
+#define PLL_STATUS_CPUPLLLOCK(CPU)  ((uint32_t)(1 << (CPU % 32)))
+
+#endif  /* CLARK_PIK_SCP_H */
diff --git a/product/clark/include/clark_pik_system.h b/product/clark/include/clark_pik_system.h
new file mode 100644
index 0000000000000000000000000000000000000000..47f6a8237eafb303b616ef13c73bbc3722e25e80
--- /dev/null
+++ b/product/clark/include/clark_pik_system.h
@@ -0,0 +1,74 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLARK_PIK_SYSTEM_H
+#define CLARK_PIK_SYSTEM_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \brief TCU clock register definitions
+ */
+struct tcuclk_ctrl_reg {
+    FWK_RW uint32_t   TCUCLK_CTRL;
+    FWK_RW uint32_t   TCUCLK_DIV1;
+};
+
+/*!
+ * \brief System PIK register definitions
+ */
+struct pik_system_reg {
+            uint8_t         RESERVED0[0x800 - 0x0];
+    FWK_RW  uint32_t        PPUCLK_CTRL;
+    FWK_RW  uint32_t        PPUCLK_DIV1;
+            uint8_t         RESERVED1[0x820 - 0x808];
+    FWK_RW  uint32_t        INTCLK_CTRL;
+    FWK_RW  uint32_t        INTCLK_DIV1;
+            uint8_t         RESERVED2[0x830 - 0x828];
+    struct tcuclk_ctrl_reg  TCUCLK[4];
+    FWK_RW  uint32_t        GICCLK_CTRL;
+    FWK_RW  uint32_t        GICCLK_DIV1;
+            uint8_t         RESERVED3[0x860 - 0x858];
+    FWK_RW  uint32_t        PCLKSCP_CTRL;
+    FWK_RW  uint32_t        PCLKSCP_DIV1;
+            uint8_t         RESERVED4[0x870 - 0x868];
+    FWK_RW  uint32_t        SYSPERCLK_CTRL;
+    FWK_RW  uint32_t        SYSPERCLK_DIV1;
+            uint8_t         RESERVED5[0x880 - 0x878];
+    FWK_RW  uint32_t        DMCCLK_CTRL;
+    FWK_RW  uint32_t        DMCCLK_DIV1;
+            uint8_t         RESERVED6[0x890 - 0x888];
+    FWK_RW  uint32_t        SYSPCLKDBG_CTRL;
+    FWK_RW  uint32_t        SYSPCLKDBG_DIV1;
+            uint8_t         RESERVED7[0x8A0 - 0x898];
+    FWK_RW  uint32_t        UARTCLK_CTRL;
+    FWK_RW  uint32_t        UARTCLK_DIV1;
+            uint8_t         RESERVED8[0xA00 - 0x8A8];
+    FWK_R   uint32_t        CLKFORCE_STATUS;
+    FWK_W   uint32_t        CLKFORCE_SET;
+    FWK_W   uint32_t        CLKFORCE_CLR;
+            uint8_t         RESERVED9[0xB0C - 0xA0C];
+    FWK_RW  uint32_t        SYSTOP_RST_DLY;
+            uint8_t         RESERVED10[0xFC0 - 0xB10];
+    FWK_R   uint32_t        PCL_CONFIG;
+            uint8_t         RESERVED11[0xFD0 - 0xFC4];
+    FWK_R   uint32_t        PID4;
+    FWK_R   uint32_t        PID5;
+    FWK_R   uint32_t        PID6;
+    FWK_R   uint32_t        PID7;
+    FWK_R   uint32_t        PID0;
+    FWK_R   uint32_t        PID1;
+    FWK_R   uint32_t        PID2;
+    FWK_R   uint32_t        PID3;
+    FWK_R   uint32_t        ID0;
+    FWK_R   uint32_t        ID1;
+    FWK_R   uint32_t        ID2;
+    FWK_R   uint32_t        ID3;
+};
+
+#endif  /* CLARK_PIK_SYSTEM_H */
diff --git a/product/clark/include/clark_power_domain.h b/product/clark/include/clark_power_domain.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad5b09c9df33d0b0eeea7896e766ad7df5fbb410
--- /dev/null
+++ b/product/clark/include/clark_power_domain.h
@@ -0,0 +1,51 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     CLARK System Support
+ */
+
+#ifndef CLARK_POWER_DOMAIN_H
+#define CLARK_POWER_DOMAIN_H
+
+#include <mod_power_domain.h>
+
+/*! Additional CLARK power domain states */
+enum clark_power_domain_states {
+    CLARK_POWER_DOMAIN_STATE_FUNC_RET = MOD_PD_STATE_COUNT,
+    CLARK_POWER_DOMAIN_STATE_FULL_RET,
+    CLARK_POWER_DOMAIN_STATE_MEM_RET,
+    CLARK_POWER_DOMAIN_STATE_COUNT
+};
+
+/*! Power domain state masks */
+enum clark_power_domain_state_masks {
+    CLARK_POWER_DOMAIN_STATE_FUNC_RET_MASK =
+        (1 << CLARK_POWER_DOMAIN_STATE_FUNC_RET),
+    CLARK_POWER_DOMAIN_STATE_FULL_RET_MASK =
+        (1 << CLARK_POWER_DOMAIN_STATE_FULL_RET),
+    CLARK_POWER_DOMAIN_STATE_MEM_RET_MASK =
+        (1 << CLARK_POWER_DOMAIN_STATE_MEM_RET),
+};
+
+/*! Mask for the cluster valid power states */
+#define CLARK_CLUSTER_VALID_STATE_MASK ( \
+                                MOD_PD_STATE_OFF_MASK | \
+                                MOD_PD_STATE_ON_MASK | \
+                                MOD_PD_STATE_SLEEP_MASK | \
+                                CLARK_POWER_DOMAIN_STATE_MEM_RET_MASK | \
+                                CLARK_POWER_DOMAIN_STATE_FUNC_RET_MASK \
+                                )
+
+/*! Mask for the core valid power states */
+#define CLARK_CORE_VALID_STATE_MASK ( \
+                                MOD_PD_STATE_OFF_MASK | \
+                                MOD_PD_STATE_ON_MASK | \
+                                MOD_PD_STATE_SLEEP_MASK | \
+                                CLARK_POWER_DOMAIN_STATE_FULL_RET_MASK \
+                                )
+
+#endif /* CLARK_POWER_DOMAIN_H */
diff --git a/product/clark/include/clark_sds.h b/product/clark/include/clark_sds.h
new file mode 100644
index 0000000000000000000000000000000000000000..e95cf79f048c11ca689d20d2dadb2a34b0fb0c7e
--- /dev/null
+++ b/product/clark/include/clark_sds.h
@@ -0,0 +1,65 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLARK_SDS_H
+#define CLARK_SDS_H
+
+#include <mod_sds.h>
+
+/*
+ * Structure identifiers.
+ */
+enum clark_sds_struct_id {
+    CLARK_SDS_CPU_INFO = 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
+    CLARK_SDS_FIRMWARE_VERSION = 2 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
+    CLARK_SDS_PLATFORM_ID = 3 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
+    CLARK_SDS_RESET_SYNDROME = 4 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
+    CLARK_SDS_FEATURE_AVAILABILITY =
+        5 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
+    CLARK_SDS_CPU_BOOTCTR = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
+    CLARK_SDS_CPU_FLAGS = 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
+};
+
+/*
+ * Structure sizes.
+ */
+#define CLARK_SDS_CPU_INFO_SIZE 4
+#define CLARK_SDS_FIRMWARE_VERSION_SIZE 4
+#define CLARK_SDS_PLATFORM_ID_SIZE 8
+#define CLARK_SDS_RESET_SYNDROME_SIZE 4
+#define CLARK_SDS_FEATURE_AVAILABILITY_SIZE 4
+#define CLARK_SDS_CPU_BOOTCTR_SIZE 256
+#define CLARK_SDS_CPU_FLAGS_SIZE 256
+
+/*
+ * Field masks and offsets for the CLARK_SDS_AP_CPU_INFO structure.
+ */
+#define CLARK_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF
+#define CLARK_SDS_CPU_INFO_PRIMARY_POS 0
+
+/*
+ * Platform information
+ */
+struct clark_sds_platid {
+    /* Subsystem part number */
+    uint32_t platform_identifier;
+    /* Platform type information */
+    uint32_t platform_type_identifier;
+};
+
+/*
+ * Field masks and offsets for the CLARK_SDS_FEATURE_AVAILABILITY structure.
+ */
+#define CLARK_SDS_FEATURE_FIRMWARE_MASK 0x1
+#define CLARK_SDS_FEATURE_DMC_MASK 0x2
+#define CLARK_SDS_FEATURE_MESSAGING_MASK 0x4
+
+#define CLARK_SDS_FEATURE_FIRMWARE_POS 0
+#define CLARK_SDS_FEATURE_DMC_POS 1
+#define CLARK_SDS_FEATURE_MESSAGING_POS 2
+
+#endif /* CLARK_SDS_H */
diff --git a/product/clark/include/fmw_cmsis.h b/product/clark/include/fmw_cmsis.h
new file mode 100644
index 0000000000000000000000000000000000000000..f904b95368233acb35191a08d4abb42e3b33fcf4
--- /dev/null
+++ b/product/clark/include/fmw_cmsis.h
@@ -0,0 +1,34 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FMW_CMSIS_H
+#define FMW_CMSIS_H
+
+#define __CHECK_DEVICE_DEFINES
+#define __CM7_REV 0x0000U
+#define __FPU_PRESENT 0U
+#define __MPU_PRESENT 1U
+#define __ICACHE_PRESENT 0U
+#define __DCACHE_PRESENT 0U
+#define __DTCM_PRESENT 0U
+#define __NVIC_PRIO_BITS 3U
+#define __Vendor_SysTickConfig 0U
+
+typedef enum IRQn {
+    NonMaskableInt_IRQn   = -14,
+    MemoryManagement_IRQn = -12,
+    BusFault_IRQn         = -11,
+    UsageFault_IRQn       = -10,
+    SVCall_IRQn           = -5,
+    DebugMonitor_IRQn     = -4,
+    PendSV_IRQn           = -2,
+    SysTick_IRQn          = -1,
+} IRQn_Type;
+
+#include <core_cm7.h>
+
+#endif /* FMW_CMSIS_H */
diff --git a/product/clark/include/mcp_clark_irq.h b/product/clark/include/mcp_clark_irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..1510ea86f983cbfa21141af6e584e6af041d1f49
--- /dev/null
+++ b/product/clark/include/mcp_clark_irq.h
@@ -0,0 +1,266 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCP_CLARK_IRQ_H
+#define MCP_CLARK_IRQ_H
+
+#include <fwk_interrupt.h>
+
+#define MCP_WDOG_IRQ FWK_INTERRUPT_NMI /* MCP Watchdog (SP805) */
+
+enum mcp_clark_interrupt {
+    RESERVED0_IRQ              = 0, /* Reserved */
+    CDBG_PWR_UP_REQ_IRQ        = 1, /* Coresight Debug Power Request */
+    CSYS_PWR_UP_REQ_IRQ        = 2, /* Coresight System Power Request */
+    CDBG_RST_REQ_IRQ           = 3, /* Coresight Debug Reset Request */
+    GIC_EXT_WAKEUP_IRQ         = 4, /* External GIC Wakeup Request */
+    RESERVED5_IRQ              = 5, /* Reserved */
+    RESERVED6_IRQ              = 6, /* Reserved */
+    RESERVED7_IRQ              = 7, /* Reserved */
+    RESERVED8_IRQ              = 8, /* Reserved */
+    RESERVED9_IRQ              = 9, /* Reserved */
+    RESERVED10_IRQ             = 10, /* Reserved */
+    RESERVED11_IRQ             = 11, /* Reserved */
+    RESERVED12_IRQ             = 12, /* Reserved */
+    RESERVED13_IRQ             = 13, /* Reserved */
+    RESERVED14_IRQ             = 14, /* Reserved */
+    RESERVED15_IRQ             = 15, /* Reserved */
+    SOC_WAKEUP0_IRQ            = 16, /* SoC Expansion Wakeup */
+    SOC_WAKEUP1_IRQ            = 17, /* SoC Expansion Wakeup */
+    SOC_WAKEUP2_IRQ            = 18, /* SoC Expansion Wakeup */
+    SOC_WAKEUP3_IRQ            = 19, /* SoC Expansion Wakeup */
+    SOC_WAKEUP4_IRQ            = 20, /* SoC Expansion Wakeup */
+    SOC_WAKEUP5_IRQ            = 21, /* SoC Expansion Wakeup */
+    SOC_WAKEUP6_IRQ            = 22, /* SoC Expansion Wakeup */
+    SOC_WAKEUP7_IRQ            = 23, /* SoC Expansion Wakeup */
+    SOC_WAKEUP8_IRQ            = 24, /* SoC Expansion Wakeup */
+    SOC_WAKEUP9_IRQ            = 25, /* SoC Expansion Wakeup */
+    SOC_WAKEUP10_IRQ           = 26, /* SoC Expansion Wakeup */
+    SOC_WAKEUP11_IRQ           = 27, /* SoC Expansion Wakeup */
+    SOC_WAKEUP12_IRQ           = 28, /* SoC Expansion Wakeup */
+    SOC_WAKEUP13_IRQ           = 29, /* SoC Expansion Wakeup */
+    SOC_WAKEUP14_IRQ           = 30, /* SoC Expansion Wakeup */
+    SOC_WAKEUP15_IRQ           = 31, /* SoC Expansion Wakeup */
+    MCP_PIK_IRQ                = 32, /* Power Intergration Kit Interrupt */
+    TIMREFCLK_IRQ              = 33, /* REFCLK Physical Timer */
+    MHU_AP_NONSEC_IRQ          = 34, /* MHU Non-Secure IRQ between MCP and AP */
+    RESERVED35_IRQ             = 35, /* Reserved */
+    MHU_AP_SEC_IRQ             = 36, /* MHU Secure IRQ between MCP and AP */
+    CTI_TRIGGER0_IRQ           = 37, /* MCP CTI Trigger */
+    CTI_TRIGGER1_IRQ           = 38, /* MCP CTI Trigger */
+    RESERVED39_IRQ             = 39, /* Reserved */
+    RESERVED40_IRQ             = 40, /* Reserved */
+    RESERVED41_IRQ             = 41, /* Reserved */
+    MCP_UART0_INT_IRQ          = 42, /* Always-on UART interrupt */
+    MCP_UART1_INT_IRQ          = 43, /* Always-on UART interrupt */
+    RESERVED44_IRQ             = 44, /* Reserved */
+    RESERVED45_IRQ             = 45, /* Reserved */
+    RESERVED46_IRQ             = 46, /* Reserved */
+    RESERVED47_IRQ             = 47, /* Reserved */
+    RESERVED48_IRQ             = 48, /* Reserved */
+    RESERVED49_IRQ             = 49, /* Reserved */
+    RESERVED50_IRQ             = 50, /* Reserved */
+    RESERVED51_IRQ             = 51, /* Reserved */
+    RESERVED52_IRQ             = 52, /* Reserved */
+    RESERVED53_IRQ             = 53, /* Reserved */
+    RESERVED54_IRQ             = 54, /* Reserved */
+    RESERVED55_IRQ             = 55, /* Reserved */
+    RESERVED56_IRQ             = 56, /* Reserved */
+    RESERVED57_IRQ             = 57, /* Reserved */
+    RESERVED58_IRQ             = 58, /* Reserved */
+    RESERVED59_IRQ             = 59, /* Reserved */
+    RESERVED60_IRQ             = 60, /* Reserved */
+    RESERVED61_IRQ             = 61, /* Reserved */
+    RESERVED62_IRQ             = 62, /* Reserved */
+    RESERVED63_IRQ             = 63, /* Reserved */
+    RESERVED64_IRQ             = 64, /* Reserved */
+    RESERVED65_IRQ             = 65, /* Reserved */
+    RESERVED66_IRQ             = 66, /* Reserved */
+    RESERVED67_IRQ             = 67, /* Reserved */
+    RESERVED68_IRQ             = 68, /* Reserved */
+    RESERVED69_IRQ             = 69, /* Reserved */
+    RESERVED70_IRQ             = 70, /* Reserved */
+    RESERVED71_IRQ             = 71, /* Reserved */
+    RESERVED72_IRQ             = 72, /* Reserved */
+    RESERVED73_IRQ             = 73, /* Reserved */
+    RESERVED74_IRQ             = 74, /* Reserved */
+    RESERVED75_IRQ             = 75, /* Reserved */
+    RESERVED76_IRQ             = 76, /* Reserved */
+    RESERVED77_IRQ             = 77, /* Reserved */
+    RESERVED78_IRQ             = 78, /* Reserved */
+    RESERVED79_IRQ             = 79, /* Reserved */
+    RESERVED80_IRQ             = 80, /* Reserved */
+    RESERVED81_IRQ             = 81, /* Reserved */
+    RESERVED82_IRQ             = 82, /* Reserved */
+    RESERVED83_IRQ             = 83, /* Reserved */
+    MHU_SCP_NONSEC_IRQ         = 84, /* MHU Non-Sec IRQ between SCP and MCP */
+    MHU_SCP_SEC_IRQ            = 85, /* MHU Secure IRQ between SCP and MCP */
+    RESERVED86_IRQ             = 86, /* Reserved */
+    RESERVED87_IRQ             = 87, /* Reserved */
+    RESERVED88_IRQ             = 88, /* Reserved */
+    RESERVED89_IRQ             = 89, /* Reserved */
+    RESERVED90_IRQ             = 90, /* Reserved */
+    RESERVED91_IRQ             = 91, /* Reserved */
+    RESERVED92_IRQ             = 92, /* Reserved */
+    RESERVED93_IRQ             = 93, /* Reserved */
+    MMU_TCU_RASIRPT_IRQ        = 94, /* Consolidated MMU RAS */
+    MMU_TBU_RASIRPT_IRQ        = 95, /* Consolidated TBU RAS */
+    INT_PPU_IRQ                = 96, /* PPU interrupt from Interconnect PPU */
+    INT_ERRNS_IRQ              = 97, /* Non-Sec error interrupt from
+                                        Interconnect PPU */
+    INT_ERRS_IRQ               = 98, /* Secure error interrupt from
+                                        Interconnect PPU */
+    INT_FAULTS_IRQ             = 99, /* Secure fault interrupt from
+                                        Interconnect PPU */
+    INT_FAULTNS_IRQ            = 100, /* Non-Sec fault interrupt from
+                                         Interconnect PPU */
+    INT_PMU_IRQ                = 101, /* PMU count overflow interrupt */
+    RESERVED102_IRQ            = 102, /* Reserved */
+    RESERVED103_IRQ            = 103, /* Reserved */
+    RESERVED104_IRQ            = 104, /* Reserved */
+    RESERVED105_IRQ            = 105, /* Reserved */
+    RESERVED106_IRQ            = 106, /* Reserved */
+    RESERVED107_IRQ            = 107, /* Reserved */
+    RESERVED108_IRQ            = 108, /* Reserved */
+    RESERVED109_IRQ            = 109, /* Reserved */
+    RESERVED110_IRQ            = 110, /* Reserved */
+    RESERVED111_IRQ            = 111, /* Reserved */
+    RESERVED112_IRQ            = 112, /* Reserved */
+    RESERVED113_IRQ            = 113, /* Reserved */
+    RESERVED114_IRQ            = 114, /* Reserved */
+    RESERVED115_IRQ            = 115, /* Reserved */
+    RESERVED116_IRQ            = 116, /* Reserved */
+    RESERVED117_IRQ            = 117, /* Reserved */
+    RESERVED118_IRQ            = 118, /* Reserved */
+    RESERVED119_IRQ            = 119, /* Reserved */
+    RESERVED120_IRQ            = 120, /* Reserved */
+    RESERVED121_IRQ            = 121, /* Reserved */
+    RESERVED122_IRQ            = 122, /* Reserved */
+    RESERVED123_IRQ            = 123, /* Reserved */
+    RESERVED124_IRQ            = 124, /* Reserved */
+    RESERVED125_IRQ            = 125, /* Reserved */
+    RESERVED126_IRQ            = 126, /* Reserved */
+    RESERVED127_IRQ            = 127, /* Reserved */
+    RESERVED128_IRQ            = 128, /* Reserved */
+    RESERVED129_IRQ            = 129, /* Reserved */
+    RESERVED130_IRQ            = 130, /* Reserved */
+    RESERVED131_IRQ            = 131, /* Reserved */
+    RESERVED132_IRQ            = 132, /* Reserved */
+    RESERVED133_IRQ            = 133, /* Reserved */
+    RESERVED134_IRQ            = 134, /* Reserved */
+    RESERVED135_IRQ            = 135, /* Reserved */
+    RESERVED136_IRQ            = 136, /* Reserved */
+    RESERVED137_IRQ            = 137, /* Reserved */
+    RESERVED138_IRQ            = 138, /* Reserved */
+    MCP_WD_WS1_IRQ             = 139, /* MCP watchdog reset */
+    RESERVED140_IRQ            = 140, /* Reserved */
+    RESERVED141_IRQ            = 141, /* Reserved */
+    RESERVED142_IRQ            = 142, /* Reserved */
+    RESERVED143_IRQ            = 143, /* Reserved */
+    RESERVED144_IRQ            = 144, /* Reserved */
+    RESERVED145_IRQ            = 145, /* Reserved */
+    RESERVED146_IRQ            = 146, /* Reserved */
+    RESERVED147_IRQ            = 147, /* Reserved */
+    RESERVED148_IRQ            = 148, /* Reserved */
+    RESERVED149_IRQ            = 149, /* Reserved */
+    RESERVED150_IRQ            = 150, /* Reserved */
+    RESERVED151_IRQ            = 151, /* Reserved */
+    RESERVED152_IRQ            = 152, /* Reserved */
+    RESERVED153_IRQ            = 153, /* Reserved */
+    RESERVED154_IRQ            = 154, /* Reserved */
+    RESERVED155_IRQ            = 155, /* Reserved */
+    RESERVED156_IRQ            = 156, /* Reserved */
+    RESERVED157_IRQ            = 157, /* Reserved */
+    RESERVED158_IRQ            = 158, /* Reserved */
+    RESERVED159_IRQ            = 159, /* Reserved */
+    RESERVED160_IRQ            = 160, /* Reserved */
+    RESERVED161_IRQ            = 161, /* Reserved */
+    RESERVED162_IRQ            = 162, /* Reserved */
+    RESERVED163_IRQ            = 163, /* Reserved */
+    RESERVED164_IRQ            = 164, /* Reserved */
+    RESERVED165_IRQ            = 165, /* Reserved */
+    RESERVED166_IRQ            = 166, /* Reserved */
+    RESERVED167_IRQ            = 167, /* Reserved */
+    RESERVED168_IRQ            = 168, /* Reserved */
+    RESERVED169_IRQ            = 169, /* Reserved */
+    RESERVED170_IRQ            = 170, /* Reserved */
+    RESERVED171_IRQ            = 171, /* Reserved */
+    RESERVED172_IRQ            = 172, /* Reserved */
+    RESERVED173_IRQ            = 173, /* Reserved */
+    RESERVED174_IRQ            = 174, /* Reserved */
+    RESERVED175_IRQ            = 175, /* Reserved */
+    RESERVED176_IRQ            = 176, /* Reserved */
+    RESERVED177_IRQ            = 177, /* Reserved */
+    RESERVED178_IRQ            = 178, /* Reserved */
+    RESERVED179_IRQ            = 179, /* Reserved */
+    DMCS0_MISC_OFLOW_IRQ       = 180, /* DMC 0/4 Combined Error Overflow */
+    DMCS0_ERR_OFLOW_IRQ        = 181, /* DMC 0/4 Error Overflow */
+    DMCS0_ECC_ERR_INT_IRQ      = 182, /* DMC 0/4 ECC Error Int */
+    DMCS0_MISC_ACCESS_INT_IRQ  = 183, /* DMC 0/4 Combined Miscellaneous
+                                         access int */
+    DMCS0_TEMPERATURE_EVENT_INT_IRQ = 184, /* DMC 0/4 Temperature event int */
+    DMCS0_FAILED_ACCESS_INT_IRQ = 185, /* DMC 0/4 Failed access int */
+    DMCS0_MGR_INT_IRQ          = 186, /* DMC 0/4 combined manager int */
+    DMCS1_MISC_OFLOW_IRQ       = 187, /* DMC 1/5 Combined Error Overflow */
+    DMCS1_ERR_OFLOW_IRQ        = 188, /* DMC 1/5 Error Overflow */
+    DMCS1_ECC_ERR_INT_IRQ      = 189, /* DMC 1/5 ECC Error Int */
+    DMCS1_MISC_ACCESS_INT_IRQ  = 190, /* DMC 1/5 Combined Miscellaneous
+                                         access int */
+    DMCS1_TEMPERATURE_EVENT_INT_IRQ = 191, /* DMC 1/5 Temperature event int */
+    DMCS1_FAILED_ACCESS_INT_IRQ = 192, /* DMC 1/5 Failed access int */
+    DMCS1_MGR_INT_IRQ          = 193, /* DMC 1/5 combined manager int */
+    DMCS2_MISC_OFLOW_IRQ       = 194, /* DMC 2/6 Combined Error Overflow */
+    DMCS2_ERR_OFLOW_IRQ        = 195, /* DMC 2/6 Error Overflow */
+    DMCS2_ECC_ERR_INT_IRQ      = 196, /* DMC 2/6 ECC Error Int */
+    DMCS2_MISC_ACCESS_INT_IRQ  = 197, /* DMC 2/6 Combined Miscellaneous
+                                         access int */
+    DMCS2_TEMPERATURE_EVENT_INT_IRQ = 198, /* DMC 2/6 Temperature event int */
+    DMCS2_FAILED_ACCESS_INT_IRQ = 199, /* DMC 2/6 Failed access int */
+    DMCS2_MGR_INT_IRQ          = 200, /* DMC 2/6 combined manager int */
+    DMCS3_MISC_OFLOW_IRQ       = 201, /* DMC 3/7 Combined Error Overflow */
+    DMCS3_ERR_OFLOW_IRQ        = 202, /* DMC 3/7 Error Overflow */
+    DMCS3_ECC_ERR_INT_IRQ      = 203, /* DMC 3/7 ECC Error Int */
+    DMCS3_MISC_ACCESS_INT_IRQ  = 204, /* DMC 3/7 Combined Miscellaneous
+                                         access int */
+    DMCS3_TEMPERATURE_EVENT_INT_IRQ = 205, /* DMC 3/7 Temperature event int */
+    DMCS3_FAILED_ACCESS_INT_IRQ = 206, /* DMC 3/7 Failed access int */
+    DMCS3_MGR_INT_IRQ          = 207, /* DMC 3/7 combined manager int */
+    MCP_EXT_INTR0_IRQ          = 208, /* MCP Customer Extension */
+    MCP_EXT_INTR1_IRQ          = 209, /* MCP Customer Extension */
+    MCP_EXT_INTR2_IRQ          = 210, /* MCP Customer Extension */
+    MCP_EXT_INTR3_IRQ          = 211, /* MCP Customer Extension */
+    MCP_EXT_INTR4_IRQ          = 212, /* MCP Customer Extension */
+    MCP_EXT_INTR5_IRQ          = 213, /* MCP Customer Extension */
+    MCP_EXT_INTR6_IRQ          = 214, /* MCP Customer Extension */
+    MCP_EXT_INTR7_IRQ          = 215, /* MCP Customer Extension */
+    MCP_EXT_INTR8_IRQ          = 216, /* MCP Customer Extension */
+    MCP_EXT_INTR9_IRQ          = 217, /* MCP Customer Extension */
+    MCP_EXT_INTR10_IRQ         = 218, /* MCP Customer Extension */
+    MCP_EXT_INTR11_IRQ         = 219, /* MCP Customer Extension */
+    MCP_EXT_INTR12_IRQ         = 220, /* MCP Customer Extension */
+    MCP_EXT_INTR13_IRQ         = 221, /* MCP Customer Extension */
+    MCP_EXT_INTR14_IRQ         = 222, /* MCP Customer Extension */
+    MCP_EXT_INTR15_IRQ         = 223, /* MCP Customer Extension */
+    MCP_EXT_INTR16_IRQ         = 224, /* MCP Customer Extension */
+    MCP_EXT_INTR17_IRQ         = 225, /* MCP Customer Extension */
+    MCP_EXT_INTR18_IRQ         = 226, /* MCP Customer Extension */
+    MCP_EXT_INTR19_IRQ         = 227, /* MCP Customer Extension */
+    MCP_EXT_INTR20_IRQ         = 228, /* MCP Customer Extension */
+    MCP_EXT_INTR21_IRQ         = 229, /* MCP Customer Extension */
+    MCP_EXT_INTR22_IRQ         = 230, /* MCP Customer Extension */
+    MCP_EXT_INTR23_IRQ         = 231, /* MCP Customer Extension */
+    MCP_EXT_INTR24_IRQ         = 232, /* MCP Customer Extension */
+    MCP_EXT_INTR25_IRQ         = 233, /* MCP Customer Extension */
+    MCP_EXT_INTR26_IRQ         = 234, /* MCP Customer Extension */
+    MCP_EXT_INTR27_IRQ         = 235, /* MCP Customer Extension */
+    MCP_EXT_INTR28_IRQ         = 236, /* MCP Customer Extension */
+    MCP_EXT_INTR29_IRQ         = 237, /* MCP Customer Extension */
+    MCP_EXT_INTR30_IRQ         = 238, /* MCP Customer Extension */
+    MCP_EXT_INTR31_IRQ         = 239  /* MCP Customer Extension */
+};
+
+#endif /* MCP_CLARK_IRQ_H */
diff --git a/product/clark/include/mcp_clark_mmap.h b/product/clark/include/mcp_clark_mmap.h
new file mode 100644
index 0000000000000000000000000000000000000000..6ca1baab41f8ddadbef61773f1947bb9157c92ca
--- /dev/null
+++ b/product/clark/include/mcp_clark_mmap.h
@@ -0,0 +1,50 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCP_CLARK_MMAP_H
+#define MCP_CLARK_MMAP_H
+
+#include <stdint.h>
+
+/*
+ * Top-level base addresses
+ */
+#define MCP_SOC_EXPANSION1_BASE       UINT32_C(0x01000000)
+#define MCP_SOC_EXPANSION2_BASE       UINT32_C(0x21000000)
+#define MCP_SOC_EXPANSION3_BASE       UINT32_C(0x40000000)
+#define MCP_MHU_SCP_BASE              UINT32_C(0x45600000)
+#define MCP_SOC_EXPANSION4_BASE       UINT32_C(0x48000000)
+#define MCP_PERIPH_BASE               UINT32_C(0x4C000000)
+#define MCP_MEMORY_CONTROLLER         UINT32_C(0x4E000000)
+#define MCP_POWER_PERIPH_BASE         UINT32_C(0x50000000)
+#define MCP_SYS0_BASE                 UINT32_C(0x60000000)
+#define MCP_SYS1_BASE                 UINT32_C(0xA0000000)
+#define MCP_PPB_BASE_INTERNAL         UINT32_C(0xE0000000)
+#define MCP_PPB_BASE_EXTERNAL         UINT32_C(0xE0040000)
+
+/*
+ * Peripherals
+ */
+#define MCP_REFCLK_CNTCTL_BASE        (MCP_PERIPH_BASE)
+#define MCP_REFCLK_CNTBASE0_BASE      (MCP_PERIPH_BASE + 0x1000)
+#define MCP_UART0_BASE                (MCP_PERIPH_BASE + 0x2000)
+#define MCP_UART1_BASE                (MCP_PERIPH_BASE + 0x3000)
+#define MCP_WDOG_BASE                 (MCP_PERIPH_BASE + 0x6000)
+#define MCP_MHU_AP_BASE               (MCP_PERIPH_BASE + 0x400000)
+
+/*
+ * Power control peripherals
+ */
+#define MCP_PIK_BASE                  (MCP_POWER_PERIPH_BASE)
+
+/*
+ * Base addresses of MHU devices v2
+ */
+#define MCP_MHU_MCP_SCP_SND           (MCP_MHU_SCP_BASE + 0x00000)
+#define MCP_MHU_MCP_SCP_RCV           (MCP_MHU_SCP_BASE + 0x10000)
+
+#endif /* MCP_CLARK_MMAP_H */
diff --git a/product/clark/include/mcp_clark_mmap_mcp.h b/product/clark/include/mcp_clark_mmap_mcp.h
new file mode 100644
index 0000000000000000000000000000000000000000..7445448a4a21eba397f56ea70d6a1803c179221f
--- /dev/null
+++ b/product/clark/include/mcp_clark_mmap_mcp.h
@@ -0,0 +1,15 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCP_CLARK_MMAP_MCP_H
+#define MCP_CLARK_MMAP_MCP_H
+
+#define MCP_ROM_BASE            0x00000000
+#define MCP_RAM0_BASE           0x00800000
+#define MCP_RAM1_BASE           0x20000000
+
+#endif /* MCP_CLARK_MMAP_MCP_H */
diff --git a/product/clark/include/mcp_system_mmap_mcp.h b/product/clark/include/mcp_system_mmap_mcp.h
new file mode 100644
index 0000000000000000000000000000000000000000..0f2604e5ce16c6f5c05dbddd575059a7cb4c2ac5
--- /dev/null
+++ b/product/clark/include/mcp_system_mmap_mcp.h
@@ -0,0 +1,17 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCP_SYSTEM_MMAP_MCP_H
+#define MCP_SYSTEM_MMAP_MCP_H
+
+#include <mcp_clark_mmap_mcp.h>
+
+#define MCP_ROM_SIZE                 (64 * 1024)
+#define MCP_RAM0_SIZE                (64 * 1024)
+#define MCP_RAM1_SIZE                (64 * 1024)
+
+#endif /* MCP_SYSTEM_MMAP_MCP_H */
diff --git a/product/clark/include/scp_clark_irq.h b/product/clark/include/scp_clark_irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..49cddcd5a8f6c67ca74b4ec56bd407a2d987de89
--- /dev/null
+++ b/product/clark/include/scp_clark_irq.h
@@ -0,0 +1,283 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCP_CLARK_IRQ_H
+#define SCP_CLARK_IRQ_H
+
+#include <fwk_interrupt.h>
+
+#define SCP_WDOG_IRQ FWK_INTERRUPT_NMI /* SCP Watchdog (SP805) */
+
+enum scp_clark_interrupt {
+    RESERVED0_IRQ              = 0, /* Reserved */
+    CDBG_PWR_UP_REQ_IRQ        = 1, /* Coresight Debug Power Request */
+    CSYS_PWR_UP_REQ_IRQ        = 2, /* Coresight System Power Request */
+    CDBG_RST_REQ_IRQ           = 3, /* Coresight Debug Reset Request */
+    GIC_EXT_WAKEUP_IRQ         = 4, /* External GIC Wakeup Request */
+    RESERVED5_IRQ              = 5, /* Reserved */
+    RESERVED6_IRQ              = 6, /* Reserved */
+    RESERVED7_IRQ              = 7, /* Reserved */
+    RESERVED8_IRQ              = 8, /* Reserved */
+    RESERVED9_IRQ              = 9, /* Reserved */
+    RESERVED10_IRQ             = 10, /* Reserved */
+    RESERVED11_IRQ             = 11, /* Reserved */
+    RESERVED12_IRQ             = 12, /* Reserved */
+    RESERVED13_IRQ             = 13, /* Reserved */
+    RESERVED14_IRQ             = 14, /* Reserved */
+    RESERVED15_IRQ             = 15, /* Reserved */
+    SOC_WAKEUP0_IRQ            = 16, /* SoC Expansion Wakeup */
+    SOC_WAKEUP1_IRQ            = 17, /* SoC Expansion Wakeup */
+    SOC_WAKEUP2_IRQ            = 18, /* SoC Expansion Wakeup */
+    SOC_WAKEUP3_IRQ            = 19, /* SoC Expansion Wakeup */
+    SOC_WAKEUP4_IRQ            = 20, /* SoC Expansion Wakeup */
+    SOC_WAKEUP5_IRQ            = 21, /* SoC Expansion Wakeup */
+    SOC_WAKEUP6_IRQ            = 22, /* SoC Expansion Wakeup */
+    SOC_WAKEUP7_IRQ            = 23, /* SoC Expansion Wakeup */
+    SOC_WAKEUP8_IRQ            = 24, /* SoC Expansion Wakeup */
+    SOC_WAKEUP9_IRQ            = 25, /* SoC Expansion Wakeup */
+    SOC_WAKEUP10_IRQ           = 26, /* SoC Expansion Wakeup */
+    SOC_WAKEUP11_IRQ           = 27, /* SoC Expansion Wakeup */
+    SOC_WAKEUP12_IRQ           = 28, /* SoC Expansion Wakeup */
+    SOC_WAKEUP13_IRQ           = 29, /* SoC Expansion Wakeup */
+    SOC_WAKEUP14_IRQ           = 30, /* SoC Expansion Wakeup */
+    SOC_WAKEUP15_IRQ           = 31, /* SoC Expansion Wakeup */
+    RESERVED32_IRQ             = 32, /* Reserved */
+    TIMREFCLK_IRQ              = 33, /* REFCLK Physical Timer */
+    SYS_GEN_TIMER_SYNC_IRQ     = 34, /* System Generic Timer synchronization */
+    CSTS_SYNC_IRQ              = 35, /* Coresight Time stamp synchronization */
+    RESERVED36_IRQ             = 36, /* Reserved */
+    CTI_TRIGGER0_IRQ           = 37, /* SCP CTI Trigger */
+    CTI_TRIGGER1_IRQ           = 38, /* SCP CTI Trigger */
+    GIC_ERROR_ECC_IRQ          = 39, /* GIC Error (ECC Fatal) */
+    GIC_ERROR_AXIM_IRQ         = 40, /* GIC Error (AXIM) */
+    RESERVED41_IRQ             = 41, /* Reserved */
+    AON_UART_IRQ               = 42, /* Always on UART */
+    RESERVED43_IRQ             = 43, /* Reserved */
+    GEN_WD_WS0_IRQ             = 44, /* Generic Watchdog timer WS0 */
+    GEN_WD_WS1_IRQ             = 45, /* Generic Watchdog timer WS1 */
+    TRUSTED_WD_WS0_IRQ         = 46, /* Trusted Watchdog timer WS0 */
+    TRUSTED_WD_WS1_IRQ         = 47, /* Trusted Watchdog timer WS1 */
+    APPS_UART_IRQ              = 48, /* Application UART */
+    RESERVED49_IRQ             = 49, /* Reserved */
+    PPU_CORES0_IRQ             = 50, /* Consolidated PPU Interrupt for cores
+                                        1-32, 129-160 */
+    PPU_CORES1_IRQ             = 51, /* Consolidated PPU Interrupt for cores
+                                        33-64, 161-192 */
+    PPU_CORES2_IRQ             = 52, /* Consolidated PPU Interrupt for cores
+                                        65-96, 193-224 */
+    PPU_CORES3_IRQ             = 53, /* Consolidated PPU Interrupt for cores
+                                        97-128, 225-256 */
+    PPU_CLUSTERS_IRQ           = 54, /* Consolidated clusters PPU */
+    PLL_CORES0_LOCK_IRQ        = 55, /* Consolidated PLL lock for PLLs
+                                        1-32, 65-96, 129-160, 193-224 */
+    PLL_CORES1_LOCK_IRQ        = 56, /* Consolidated PLL lock for PLLs
+                                        33-64, 97-128, 161-192, 225-256 */
+    PLL_CORES0_UNLOCK_IRQ      = 57, /* Consolidated PLL unlock for PLLs
+                                        1-32, 65-96, 129-160, 193-224 */
+    PLL_CORES1_UNLOCK_IRQ      = 58, /* Consolidated PLL unlock for PLLs
+                                        33-64, 97-128, 161-192, 225-256 */
+    FAULT_CORES0_IRQ           = 59, /* Consolidated fault IRQ for cores 1-32,
+                                        129-160 */
+    FAULT_CORES1_IRQ           = 60, /* Consolidated fault IRQ for cores 33-64,
+                                        161-192 */
+    FAULT_CORES2_IRQ           = 61, /* Consolidated fault IRQ for cores 65-96,
+                                        193-224 */
+    FAULT_CORES3_IRQ           = 62, /* Consolidated fault IRQ for cores 97-128,
+                                        225-256 */
+    FAULT_CLUSTERS_IRQ         = 63, /* Consolidated clusters fault */
+    ECC_CORES0_ERROR_IRQ       = 64, /* Consolidated ECC ERROR for cores
+                                        1-32, 129-160 */
+    ECC_CORES1_ERROR_IRQ       = 65, /* Consolidated ECC ERROR for cores
+                                        33-64, 161-192 */
+    ECC_CORES2_ERROR_IRQ       = 66, /* Consolidated ECC ERROR for cores
+                                        65-96, 193-224 */
+    ECC_CORES3_ERROR_IRQ       = 67, /* Consolidated ECC ERROR for cores
+                                        96-128, 225-256 */
+    ECC_CLUSTERS_ERROR_IRQ     = 68, /* Consolidated clusters ECC ERROR */
+    PLL_CLUSTERS_LOCK_IRQ      = 69, /* Consolidated clusters PLL Lock */
+    PLL_CLUSTERS_UNLOCK_IRQ    = 70, /* Consolidated clusters PLL Unlock*/
+    RESERVED71_IRQ             = 71, /* Reserved */
+    RESERVED72_IRQ             = 72, /* Reserved */
+    RESERVED73_IRQ             = 73, /* Reserved */
+    RESERVED74_IRQ             = 74, /* Reserved */
+    RESERVED75_IRQ             = 75, /* Reserved */
+    RESERVED76_IRQ             = 76, /* Reserved */
+    RESERVED77_IRQ             = 77, /* Reserved */
+    RESERVED78_IRQ             = 78, /* Reserved */
+    RESERVED79_IRQ             = 79, /* Reserved */
+    RESERVED80_IRQ             = 80, /* Reserved */
+    RESERVED81_IRQ             = 81, /* Reserved */
+    MHU_AP_NONSEC_IRQ          = 82, /* MHU non-secure irq bewteen SCP and AP */
+    MHU_AP_SEC_IRQ             = 83, /* MHU secure irq bewteen SCP and AP */
+    MHU_MCP_NONSEC_IRQ         = 84, /* MHU non-secure irq between SCP and
+                                        MCP */
+    MHU_MCP_SEC_IRQ            = 85, /* MHU secure irq bewteen SCP and MCP */
+    RESERVED86_IRQ             = 86, /* Reserved */
+    RESERVED87_IRQ             = 87, /* Reserved */
+    RESERVED88_IRQ             = 88, /* Reserved */
+    RESERVED89_IRQ             = 89, /* Reserved */
+    TIMER_CLUSTERS_IRQ         = 90, /* Consolidated clusters timer interrupt */
+    RESERVED91_IRQ             = 91, /* Reserved */
+    RESERVED92_IRQ             = 92, /* Reserved */
+    RESERVED93_IRQ             = 93, /* Reserved */
+    MMU_TCU_RASIRPT_IRQ        = 94, /* Consolidated MMU RAS */
+    MMU_TBU_RASIRPT_IRQ        = 95, /* Consolidated TBU RAS */
+    INT_PPU_IRQ                = 96, /* PPU interrupt from Interconnect PPU */
+    INT_ERRNS_IRQ              = 97, /* Non-Sec error interrupt from
+                                        Interconnect PPU */
+    INT_ERRS_IRQ               = 98, /* Secure error interrupt from
+                                        Interconnect PPU */
+    INT_FAULTS_IRQ             = 99, /* Secure fault interrupt from
+                                        Interconnect PPU */
+    INT_FAULTNS_IRQ            = 100, /* Non-Sec fault interrupt from
+                                         Interconnect PPU */
+    INT_PMU_IRQ                = 101, /* PMU count overflow interrupt */
+    RESERVED102_IRQ            = 102, /* Reserved */
+    RESERVED103_IRQ            = 103, /* Reserved */
+    RESERVED104_IRQ            = 104, /* Reserved */
+    RESERVED105_IRQ            = 105, /* Reserved */
+    RESERVED106_IRQ            = 106, /* Reserved */
+    RESERVED107_IRQ            = 107, /* Reserved */
+    RESERVED108_IRQ            = 108, /* Reserved */
+    RESERVED109_IRQ            = 109, /* Reserved */
+    RESERVED110_IRQ            = 110, /* Reserved */
+    RESERVED111_IRQ            = 111, /* Reserved */
+    RESERVED112_IRQ            = 112, /* Reserved */
+    RESERVED113_IRQ            = 113, /* Reserved */
+    RESERVED114_IRQ            = 114, /* Reserved */
+    RESERVED115_IRQ            = 115, /* Reserved */
+    RESERVED116_IRQ            = 116, /* Reserved */
+    RESERVED117_IRQ            = 117, /* Reserved */
+    RESERVED118_IRQ            = 118, /* Reserved */
+    RESERVED119_IRQ            = 119, /* Reserved */
+    PPU_DBGCH0_IRQ             = 120, /* Debug Chain 0 PPU */
+    PPU_DBGCH1_IRQ             = 121, /* Debug Chain 1 PPU */
+    PPU_DBGCH2_IRQ             = 122, /* Debug Chain 2 PPU */
+    PPU_DBGCH3_IRQ             = 123, /* Debug Chain 3 PPU */
+    PPU_DBGCH4_IRQ             = 124, /* Debug Chain 4 PPU */
+    PPU_DBGCH5_IRQ             = 125, /* Debug Chain 5 PPU */
+    PPU_DBGCH6_IRQ             = 126, /* Debug Chain 6 PPU */
+    PPU_DBGCH7_IRQ             = 127, /* Debug Chain 7 PPU */
+    RESERVED128_IRQ            = 128, /* Reserved */
+    RESERVED129_IRQ            = 129, /* Reserved */
+    DEBUG_PIK_IRQ              = 130, /* DEBUG PIK */
+    PPU_LOGIC_IRQ              = 131, /* PPU LOGIC */
+    RESERVED132_IRQ            = 132, /* Reserved */
+    RESERVED133_IRQ            = 133, /* Reserved */
+    RESERVED134_IRQ            = 134, /* Reserved */
+    PPU_SRAM_IRQ               = 135, /* PPU SRAM */
+    RESERVED136_IRQ            = 136, /* Reserved */
+    RESERVED137_IRQ            = 137, /* Reserved */
+    RESERVED138_IRQ            = 138, /* Reserved */
+    MCP_WD_WS1_IRQ             = 139, /* MCP watchdog reset */
+    PLL_SYS_LOCK_IRQ           = 140, /* System PLL Lock */
+    PLL_SYS_UNLOCK_IRQ         = 141, /* System PLL Unlock */
+    PLL_INT_LOCK_IRQ           = 142, /* Interconnect PLL Lock */
+    PLL_INT_UNLOCK_IRQ         = 143, /* Interconnect PLL Unlock */
+    RESERVED144_IRQ            = 144, /* Reserved */
+    RESERVED145_IRQ            = 145, /* Reserved */
+    RESERVED146_IRQ            = 146, /* Reserved */
+    RESERVED147_IRQ            = 147, /* Reserved */
+    RESERVED148_IRQ            = 148, /* Reserved */
+    RESERVED149_IRQ            = 149, /* Reserved */
+    RESERVED150_IRQ            = 150, /* Reserved */
+    RESERVED151_IRQ            = 151, /* Reserved */
+    RESERVED152_IRQ            = 152, /* Reserved */
+    RESERVED153_IRQ            = 153, /* Reserved */
+    RESERVED154_IRQ            = 154, /* Reserved */
+    RESERVED155_IRQ            = 155, /* Reserved */
+    RESERVED156_IRQ            = 156, /* Reserved */
+    RESERVED157_IRQ            = 157, /* Reserved */
+    RESERVED158_IRQ            = 158, /* Reserved */
+    RESERVED159_IRQ            = 159, /* Reserved */
+    RESERVED160_IRQ            = 160, /* Reserved */
+    RESERVED161_IRQ            = 161, /* Reserved */
+    RESERVED162_IRQ            = 162, /* Reserved */
+    RESERVED163_IRQ            = 163, /* Reserved */
+    RESERVED164_IRQ            = 164, /* Reserved */
+    RESERVED165_IRQ            = 165, /* Reserved */
+    RESERVED166_IRQ            = 166, /* Reserved */
+    RESERVED167_IRQ            = 167, /* Reserved */
+    RESERVED168_IRQ            = 168, /* Reserved */
+    RESERVED169_IRQ            = 169, /* Reserved */
+    RESERVED170_IRQ            = 170, /* Reserved */
+    RESERVED171_IRQ            = 171, /* Reserved */
+    RESERVED172_IRQ            = 172, /* Reserved */
+    RESERVED173_IRQ            = 173, /* Reserved */
+    PLL_DMC_LOCK_IRQ           = 174, /* DMC PLL LOCK */
+    PLL_DMC_UNLOCK_IRQ         = 175, /* DMC PLL LOCK */
+    RESERVED176_IRQ            = 176, /* Reserved */
+    RESERVED177_IRQ            = 177, /* Reserved */
+    RESERVED178_IRQ            = 178, /* Reserved */
+    RESERVED179_IRQ            = 179, /* Reserved */
+    DMCS0_MISC_OFLOW_IRQ       = 180, /* DMC 0/4 Combined Error Overflow */
+    DMCS0_ERR_OFLOW_IRQ        = 181, /* DMC 0/4 Error Overflow */
+    DMCS0_ECC_ERR_INT_IRQ      = 182, /* DMC 0/4 ECC Error Int */
+    DMCS0_MISC_ACCESS_INT_IRQ  = 183, /* DMC 0/4 Combined Miscellaneous
+                                         access int */
+    DMCS0_TEMPERATURE_EVENT_INT_IRQ = 184, /* DMC 0/4 Temperature event int */
+    DMCS0_FAILED_ACCESS_INT_IRQ = 185, /* DMC 0/4 Failed access int */
+    DMCS0_MGR_INT_IRQ          = 186, /* DMC 0/4 combined manager int */
+    DMCS1_MISC_OFLOW_IRQ       = 187, /* DMC 1/5 Combined Error Overflow */
+    DMCS1_ERR_OFLOW_IRQ        = 188, /* DMC 1/5 Error Overflow */
+    DMCS1_ECC_ERR_INT_IRQ      = 189, /* DMC 1/5 ECC Error Int */
+    DMCS1_MISC_ACCESS_INT_IRQ  = 190, /* DMC 1/5 Combined Miscellaneous
+                                         access int */
+    DMCS1_TEMPERATURE_EVENT_INT_IRQ = 191, /* DMC 1/5 Temperature event int */
+    DMCS1_FAILED_ACCESS_INT_IRQ = 192, /* DMC 1/5 Failed access int */
+    DMCS1_MGR_INT_IRQ          = 193, /* DMC 1/5 combined manager int */
+    DMCS2_MISC_OFLOW_IRQ       = 194, /* DMC 2/6 Combined Error Overflow */
+    DMCS2_ERR_OFLOW_IRQ        = 195, /* DMC 2/6 Error Overflow */
+    DMCS2_ECC_ERR_INT_IRQ      = 196, /* DMC 2/6 ECC Error Int */
+    DMCS2_MISC_ACCESS_INT_IRQ  = 197, /* DMC 2/6 Combined Miscellaneous
+                                         access int */
+    DMCS2_TEMPERATURE_EVENT_INT_IRQ = 198, /* DMC 2/6 Temperature event int */
+    DMCS2_FAILED_ACCESS_INT_IRQ = 199, /* DMC 2/6 Failed access int */
+    DMCS2_MGR_INT_IRQ          = 200, /* DMC 2/6 combined manager int */
+    DMCS3_MISC_OFLOW_IRQ       = 201, /* DMC 3/7 Combined Error Overflow */
+    DMCS3_ERR_OFLOW_IRQ        = 202, /* DMC 3/7 Error Overflow */
+    DMCS3_ECC_ERR_INT_IRQ      = 203, /* DMC 3/7 ECC Error Int */
+    DMCS3_MISC_ACCESS_INT_IRQ  = 204, /* DMC 3/7 Combined Miscellaneous
+                                         access int */
+    DMCS3_TEMPERATURE_EVENT_INT_IRQ = 205, /* DMC 3/7 Temperature event int */
+    DMCS3_FAILED_ACCESS_INT_IRQ = 206, /* DMC 3/7 Failed access int */
+    DMCS3_MGR_INT_IRQ          = 207, /* DMC 3/7 combined manager int */
+    SCP_EXT_INTR0_IRQ          = 208, /* SCP Customer Extension */
+    SCP_EXT_INTR1_IRQ          = 209, /* SCP Customer Extension */
+    SCP_EXT_INTR2_IRQ          = 210, /* SCP Customer Extension */
+    SCP_EXT_INTR3_IRQ          = 211, /* SCP Customer Extension */
+    SCP_EXT_INTR4_IRQ          = 212, /* SCP Customer Extension */
+    SCP_EXT_INTR5_IRQ          = 213, /* SCP Customer Extension */
+    SCP_EXT_INTR6_IRQ          = 214, /* SCP Customer Extension */
+    SCP_EXT_INTR7_IRQ          = 215, /* SCP Customer Extension */
+    SCP_EXT_INTR8_IRQ          = 216, /* SCP Customer Extension */
+    SCP_EXT_INTR9_IRQ          = 217, /* SCP Customer Extension */
+    SCP_EXT_INTR10_IRQ         = 218, /* SCP Customer Extension */
+    SCP_EXT_INTR11_IRQ         = 219, /* SCP Customer Extension */
+    SCP_EXT_INTR12_IRQ         = 220, /* SCP Customer Extension */
+    SCP_EXT_INTR13_IRQ         = 221, /* SCP Customer Extension */
+    SCP_EXT_INTR14_IRQ         = 222, /* SCP Customer Extension */
+    SCP_EXT_INTR15_IRQ         = 223, /* SCP Customer Extension */
+    SCP_EXT_INTR16_IRQ         = 224, /* SCP Customer Extension */
+    SCP_EXT_INTR17_IRQ         = 225, /* SCP Customer Extension */
+    SCP_EXT_INTR18_IRQ         = 226, /* SCP Customer Extension */
+    SCP_EXT_INTR19_IRQ         = 227, /* SCP Customer Extension */
+    SCP_EXT_INTR20_IRQ         = 228, /* SCP Customer Extension */
+    SCP_EXT_INTR21_IRQ         = 229, /* SCP Customer Extension */
+    SCP_EXT_INTR22_IRQ         = 230, /* SCP Customer Extension */
+    SCP_EXT_INTR23_IRQ         = 231, /* SCP Customer Extension */
+    SCP_EXT_INTR24_IRQ         = 232, /* SCP Customer Extension */
+    SCP_EXT_INTR25_IRQ         = 233, /* SCP Customer Extension */
+    SCP_EXT_INTR26_IRQ         = 234, /* SCP Customer Extension */
+    SCP_EXT_INTR27_IRQ         = 235, /* SCP Customer Extension */
+    SCP_EXT_INTR28_IRQ         = 236, /* SCP Customer Extension */
+    SCP_EXT_INTR29_IRQ         = 237, /* SCP Customer Extension */
+    SCP_EXT_INTR30_IRQ         = 238, /* SCP Customer Extension */
+    SCP_EXT_INTR31_IRQ         = 239  /* SCP Customer Extension */
+};
+
+#endif /* SCP_CLARK_IRQ_H */
diff --git a/product/clark/include/scp_clark_mhu.h b/product/clark/include/scp_clark_mhu.h
new file mode 100644
index 0000000000000000000000000000000000000000..86b19d074f07e45bb31a4fce77a7d8ebd4bd0f03
--- /dev/null
+++ b/product/clark/include/scp_clark_mhu.h
@@ -0,0 +1,20 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     MHU module device indexes.
+ */
+
+#ifndef SCP_CLARK_MHU_H
+#define SCP_CLARK_MHU_H
+
+enum scp_clark_mhu_device_idx {
+    SCP_CLARK_MHU_DEVICE_IDX_SCP_AP_S_CLUS0,
+    SCP_CLARK_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0,
+    SCP_CLARK_MHU_DEVICE_IDX_COUNT
+};
+
+#endif /* SCP_CLARK_MHU_H */
diff --git a/product/clark/include/scp_clark_mmap.h b/product/clark/include/scp_clark_mmap.h
new file mode 100644
index 0000000000000000000000000000000000000000..1bd48bfab5c09e98fb8d7e03f181c8dfe09356ca
--- /dev/null
+++ b/product/clark/include/scp_clark_mmap.h
@@ -0,0 +1,87 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCP_CLARK_MMAP_H
+#define SCP_CLARK_MMAP_H
+
+#include <stdint.h>
+
+/*
+ * Top-level base addresses
+ */
+#define SCP_EXPANSION1_BASE           UINT32_C(0x01000000)
+#define SCP_EXPANSION2_BASE           UINT32_C(0x21000000)
+#define SCP_EXPANSION3_BASE           UINT32_C(0x40000000)
+#define SCP_PERIPHERAL_BASE           UINT32_C(0x44000000)
+#define SCP_MEMORY_CONTROLLER         UINT32_C(0x4E000000)
+#define SCP_POWER_PERIPHERAL_BASE     UINT32_C(0x50000000)
+#define SCP_NOC_GPV_BASE              UINT32_C(0x51000000)
+#define SCP_SYS0_BASE                 UINT32_C(0x60000000)
+#define SCP_SYS1_BASE                 UINT32_C(0xA0000000)
+#define SCP_PPB_BASE_INTERNAL         UINT32_C(0xE0000000)
+#define SCP_PPB_BASE_EXTERNAL         UINT32_C(0xE0040000)
+
+/*
+ * Peripherals
+ */
+#define SCP_REFCLK_CNTCTL_BASE        (SCP_PERIPHERAL_BASE + 0x0000)
+#define SCP_REFCLK_CNTBASE0_BASE      (SCP_PERIPHERAL_BASE + 0x1000)
+#define SCP_UART_BASE                 (SCP_PERIPHERAL_BASE + 0x2000)
+#define SCP_WDOG_BASE                 (SCP_PERIPHERAL_BASE + 0x6000)
+#define SCP_CS_CNTCONTROL_BASE        (SCP_PERIPHERAL_BASE + 0xA000)
+#define SCP_MHU_AP_BASE               (SCP_PERIPHERAL_BASE + 0x1000000)
+#define SCP_MHU_MCP_BASE              (SCP_PERIPHERAL_BASE + 0x1800000)
+
+/*
+ * Power control peripherals
+ */
+#define SCP_PIK_SCP_BASE              (SCP_POWER_PERIPHERAL_BASE + 0x00000)
+#define SCP_PIK_DEBUG_BASE            (SCP_POWER_PERIPHERAL_BASE + 0x20000)
+#define SCP_SCP_SENSOR_DEBUG_BASE     (SCP_POWER_PERIPHERAL_BASE + 0x30000)
+#define SCP_PIK_SYSTEM_BASE           (SCP_POWER_PERIPHERAL_BASE + 0x40000)
+#define SCP_SENSOR_SYSTEM_BASE        (SCP_POWER_PERIPHERAL_BASE + 0x50000)
+#define SCP_SENSOR_CLUS0_BASE         (SCP_POWER_PERIPHERAL_BASE + 0x70000)
+#define SCP_SENSOR_CLUS1_BASE         (SCP_POWER_PERIPHERAL_BASE + 0x90000)
+#define SCP_PIK_DEBUG_CHAIN_BASE      (SCP_POWER_PERIPHERAL_BASE + 0x500000)
+#define SCP_PIK_CLUSTER_BASE(n)       ((SCP_POWER_PERIPHERAL_BASE + 0x60000) + \
+                                      ((n) * 0x20000))
+
+/*
+ * PPU base address
+ */
+#define SCP_PPU_SCP_BASE              (SCP_PIK_SCP_BASE + 0x1000)
+#define SCP_PPU_SYS0_BASE             (SCP_PIK_SYSTEM_BASE + 0x1000)
+#define SCP_PPU_SYS1_BASE             (SCP_PIK_SYSTEM_BASE + 0x5000)
+#define SCP_PPU_DEBUG_BASE            (SCP_PIK_DEBUG_BASE + 0x1000)
+#define SCP_PPU_CLUSTER_BASE(n)       (SCP_PIK_CLUSTER_BASE((n)) + 0x1000)
+#define SCP_PPU_CORE_BASE(n, m)       (SCP_PPU_CLUSTER_BASE((n)) + \
+                                       ((m) + 1) * 0x1000)
+
+/*
+ * System access port 0
+ */
+#define SCP_CMN600_BASE               (SCP_SYS0_BASE + 0x10000000)
+
+/*
+ * System access port 1
+ */
+#define SCP_TRUSTED_RAM_BASE          (SCP_SYS1_BASE + 0x04000000)
+#define SCP_NONTRUSTED_RAM_BASE       (SCP_SYS1_BASE + 0x06000000)
+#define SCP_REFCLK_CNTCONTROL_BASE    (SCP_SYS1_BASE + 0x2A430000)
+#define SCP_SID_BASE                  (SCP_SYS1_BASE + 0x2A4A0000)
+
+/*
+ * Base addresses of MHU devices v2
+ */
+#define SCP_MHU_SCP_AP_SND_NS_CLUS0  (SCP_MHU_AP_BASE + 0x00000)
+#define SCP_MHU_SCP_AP_RCV_NS_CLUS0  (SCP_MHU_AP_BASE + 0x10000)
+#define SCP_MHU_SCP_AP_SND_S_CLUS0   (SCP_MHU_AP_BASE + 0x400000)
+#define SCP_MHU_SCP_AP_RCV_S_CLUS0   (SCP_MHU_AP_BASE + 0x410000)
+#define SCP_MHU_SCP_MCP_SND          (SCP_MHU_MCP_BASE + 0x00000)
+#define SCP_MHU_SCP_MCP_RCV          (SCP_MHU_MCP_BASE + 0x10000)
+
+#endif /* SCP_CLARK_MMAP_H */
diff --git a/product/clark/include/scp_clark_mmap_scp.h b/product/clark/include/scp_clark_mmap_scp.h
new file mode 100644
index 0000000000000000000000000000000000000000..429c3e460b930bfe2e5a21b4bdf92a46760381a0
--- /dev/null
+++ b/product/clark/include/scp_clark_mmap_scp.h
@@ -0,0 +1,15 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCP_CLARK_MMAP_SCP_H
+#define SCP_CLARK_MMAP_SCP_H
+
+#define SCP_ROM_BASE                0x00000000
+#define SCP_RAM0_BASE               0x00800000
+#define SCP_RAM1_BASE               0x20000000
+
+#endif /* SCP_CLARK_MMAP_SCP_H */
diff --git a/product/clark/include/scp_clark_pik.h b/product/clark/include/scp_clark_pik.h
new file mode 100644
index 0000000000000000000000000000000000000000..9f3e6e320dd031835f344dc8a5bff9cfbcafe695
--- /dev/null
+++ b/product/clark/include/scp_clark_pik.h
@@ -0,0 +1,20 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCP_CLARK_PIK_H
+#define SCP_CLARK_PIK_H
+
+#include <scp_clark_mmap.h>
+#include <clark_pik_cpu.h>
+#include <clark_pik_scp.h>
+#include <clark_pik_system.h>
+
+#define PIK_CLUSTER(IDX) ((struct pik_cpu_reg *) SCP_PIK_CLUSTER_BASE(IDX))
+#define PIK_SCP          ((struct pik_scp_reg *) SCP_PIK_SCP_BASE)
+#define PIK_SYSTEM       ((struct pik_system_reg *) SCP_PIK_SYSTEM_BASE)
+
+#endif /* SCP_CLARK_PIK_H */
diff --git a/product/clark/include/scp_clark_scmi.h b/product/clark/include/scp_clark_scmi.h
new file mode 100644
index 0000000000000000000000000000000000000000..165945998003c9123cffcd8ff324177ba953aa40
--- /dev/null
+++ b/product/clark/include/scp_clark_scmi.h
@@ -0,0 +1,28 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     Definitions for SCMI and SMT module configurations.
+ */
+
+#ifndef SCP_CLARK_SCMI_H
+#define SCP_CLARK_SCMI_H
+
+/* SCMI agent identifiers */
+enum scp_clark_scmi_agent_id {
+    /* 0 is reserved for the platform */
+    SCP_SCMI_AGENT_ID_OSPM = 1,
+    SCP_SCMI_AGENT_ID_PSCI,
+};
+
+/* SCMI service indexes */
+enum scp_clark_scmi_service_idx {
+    SCP_CLARK_SCMI_SERVICE_IDX_PSCI,
+    SCP_CLARK_SCMI_SERVICE_IDX_OSPM,
+    SCP_CLARK_SCMI_SERVICE_IDX_COUNT,
+};
+
+#endif /* SCP_CLARK_SCMI_H */
diff --git a/product/clark/include/scp_software_mmap.h b/product/clark/include/scp_software_mmap.h
new file mode 100644
index 0000000000000000000000000000000000000000..8d9f2a2f315833dcc7c25c65bb5a8d89a6e05a0d
--- /dev/null
+++ b/product/clark/include/scp_software_mmap.h
@@ -0,0 +1,50 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     Software defined memory map shared between SCP and AP cores.
+ */
+
+#ifndef SCP_SOFTWARE_MMAP_H
+#define SCP_SOFTWARE_MMAP_H
+
+#include <scp_clark_mmap.h>
+#include <fwk_macros.h>
+
+#define SCP_NOR_FLASH_BASE                  0x08000000
+#define SCP_NOR_BASE                        (SCP_NOR_FLASH_BASE + 0x03D80000)
+#define SCP_IMAGE_SIZE                      (256 * FWK_KIB)
+
+#define SCP_AP_SHARED_SECURE_BASE           (SCP_TRUSTED_RAM_BASE)
+#define SCP_AP_SHARED_SECURE_SIZE           (4 * FWK_KIB)
+
+/* Non-secure shared memory at the base of Non-trusted SRAM */
+#define SCP_AP_SHARED_NONSECURE_BASE        (SCP_NONTRUSTED_RAM_BASE)
+#define SCP_AP_SHARED_NONSECURE_SIZE        (4 * FWK_KIB)
+
+/* SDS Memory Region */
+#define SCP_SDS_MEM_BASE                    (SCP_AP_SHARED_SECURE_BASE)
+#define SCP_SDS_MEM_SIZE                    (3520)
+
+/* AP Context Area */
+#define SCP_AP_CONTEXT_BASE                 (SCP_AP_SHARED_SECURE_BASE + \
+                                            SCP_AP_SHARED_SECURE_SIZE - \
+                                            SCP_AP_CONTEXT_SIZE)
+#define SCP_AP_CONTEXT_SIZE                 (64)
+
+/* SCMI Secure Payload Areas */
+#define SCP_SCMI_PAYLOAD_SIZE               (128)
+#define SCP_SCMI_PAYLOAD_S_A2P_BASE         (SCP_SDS_MEM_BASE + \
+                                            SCP_SDS_MEM_SIZE)
+#define SCP_SCMI_PAYLOAD_S_P2A_BASE         (SCP_SCMI_PAYLOAD_S_A2P_BASE + \
+                                            SCP_SCMI_PAYLOAD_SIZE)
+
+/* SCMI Non-Secure Payload Areas */
+#define SCP_SCMI_PAYLOAD_NS_A2P_BASE        (SCP_AP_SHARED_NONSECURE_BASE)
+#define SCP_SCMI_PAYLOAD_NS_P2A_BASE        (SCP_SCMI_PAYLOAD_NS_A2P_BASE + \
+                                            SCP_SCMI_PAYLOAD_SIZE)
+
+#endif /* SCP_SOFTWARE_MMAP_H */
diff --git a/product/clark/include/scp_system_mmap.h b/product/clark/include/scp_system_mmap.h
new file mode 100644
index 0000000000000000000000000000000000000000..e941d5c731b4feb0a09b72763f0fe8bfdfa39d73
--- /dev/null
+++ b/product/clark/include/scp_system_mmap.h
@@ -0,0 +1,41 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCP_SYSTEM_MMAP_H
+#define SCP_SYSTEM_MMAP_H
+
+#include <scp_clark_mmap.h>
+
+#define SCP_PLAT_BASE           (SCP_SYS0_BASE + 0x3FFE0000)
+
+#define SCP_PLL_BASE            (SCP_EXPANSION2_BASE + 0x01000000)
+
+#define SCP_PLL_SYSPLL          (SCP_PLL_BASE)
+#define SCP_PLL_CLUS0           (SCP_PLL_BASE + 0x00000004)
+#define SCP_PLL_CLUS1           (SCP_PLL_BASE + 0x00000008)
+#define SCP_PLL_DMC             (SCP_PLL_BASE + 0x00000010)
+#define SCP_PLL_INTERCONNECT    (SCP_PLL_BASE + 0x00000020)
+
+#define SCP_PLL_CPU0            (SCP_PLL_BASE + 0x00000100)
+#define SCP_PLL_CPU1            (SCP_PLL_BASE + 0x00000104)
+#define SCP_PLL_CPU2            (SCP_PLL_BASE + 0x00000108)
+#define SCP_PLL_CPU3            (SCP_PLL_BASE + 0x0000010C)
+#define SCP_PLL_CPU4            (SCP_PLL_BASE + 0x00000110)
+#define SCP_PLL_CPU5            (SCP_PLL_BASE + 0x00000114)
+#define SCP_PLL_CPU6            (SCP_PLL_BASE + 0x00000118)
+#define SCP_PLL_CPU7            (SCP_PLL_BASE + 0x0000011C)
+
+#define SCP_DDR_PHY0            (SCP_SYS0_BASE + 0x3FB60000)
+#define SCP_DDR_PHY1            (SCP_SYS0_BASE + 0x3FB70000)
+
+#define SCP_DMC0                (SCP_MEMORY_CONTROLLER + 0x00000000)
+#define SCP_DMC1                (SCP_MEMORY_CONTROLLER + 0x00100000)
+
+#define SCP_SENSOR_SOC_TEMP     (SCP_PLAT_BASE + 0x00000080)
+#define SCP_PLATFORM_ID         (SCP_PLAT_BASE + 0x000000E0)
+
+#endif /* SCP_SYSTEM_MMAP_H*/
diff --git a/product/clark/include/scp_system_mmap_scp.h b/product/clark/include/scp_system_mmap_scp.h
new file mode 100644
index 0000000000000000000000000000000000000000..b08da46b83960fdde890ba207f4a989156ea60b2
--- /dev/null
+++ b/product/clark/include/scp_system_mmap_scp.h
@@ -0,0 +1,17 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCP_SYSTEM_MMAP_SCP_H
+#define SCP_SYSTEM_MMAP_SCP_H
+
+#include <scp_clark_mmap_scp.h>
+
+#define SCP_ROM_SIZE                 (64 * 1024)
+#define SCP_RAM0_SIZE                (256 * 1024)
+#define SCP_RAM1_SIZE                (256 * 1024)
+
+#endif /* SCP_SYSTEM_MMAP_SCP_H */
diff --git a/product/clark/include/system_clock.h b/product/clark/include/system_clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..4345935328d0f734077de49d142b40c9f960d58e
--- /dev/null
+++ b/product/clark/include/system_clock.h
@@ -0,0 +1,16 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SYSTEM_CLOCK_H
+#define SYSTEM_CLOCK_H
+
+#include <fwk_macros.h>
+
+#define CLOCK_RATE_REFCLK       (100UL * FWK_MHZ)
+#define CLOCK_RATE_SYSPLLCLK    (2000UL * FWK_MHZ)
+
+#endif /* SYSTEM_CLOCK_H */
diff --git a/product/clark/mcp_romfw/config_clark_rom.c b/product/clark/mcp_romfw/config_clark_rom.c
new file mode 100644
index 0000000000000000000000000000000000000000..f63c81839c7e6579194a2e30f1c85af03b1c7a5d
--- /dev/null
+++ b/product/clark/mcp_romfw/config_clark_rom.c
@@ -0,0 +1,17 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_module.h>
+#include <mod_clark_rom.h>
+#include <mcp_clark_mmap_mcp.h>
+
+const struct fwk_module_config config_clark_rom = {
+    .data = &((struct clark_rom_config) {
+        .ramfw_base = MCP_RAM0_BASE,
+        .load_ram_size = 0,
+    })
+};
diff --git a/product/clark/mcp_romfw/config_clock.c b/product/clark/mcp_romfw/config_clock.c
new file mode 100644
index 0000000000000000000000000000000000000000..8e7817626893e4a4e9263d8eed1c202e238af27f
--- /dev/null
+++ b/product/clark/mcp_romfw/config_clock.c
@@ -0,0 +1,10 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_module.h>
+
+const struct fwk_module_config config_clock = { 0 };
diff --git a/product/clark/mcp_romfw/config_log.c b/product/clark/mcp_romfw/config_log.c
new file mode 100644
index 0000000000000000000000000000000000000000..e510f47a86e311e04fd3c820edfeafaeb82c6663
--- /dev/null
+++ b/product/clark/mcp_romfw/config_log.c
@@ -0,0 +1,58 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_banner.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_log.h>
+#include <mod_pl011.h>
+#include <mcp_clark_mmap.h>
+
+/*
+ * PL011 module
+ */
+static const struct fwk_element pl011_element_desc_table[] = {
+    [0] = {
+        .name = "uart0",
+        .data = &((struct mod_pl011_device_config) {
+            .reg_base = MCP_UART0_BASE,
+            .baud_rate_bps = 115200,
+            .clock_rate_hz = 24 * FWK_MHZ,
+            .clock_id = FWK_ID_NONE_INIT,
+            }),
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *get_pl011_table(fwk_id_t module_id)
+{
+    return pl011_element_desc_table;
+}
+
+struct fwk_module_config config_pl011 = {
+    .get_element_table = get_pl011_table,
+};
+
+/*
+ * Log module
+ */
+static const struct mod_log_config log_data = {
+    .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0),
+    .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0),
+    .log_groups = MOD_LOG_GROUP_ERROR |
+                  MOD_LOG_GROUP_INFO |
+                  MOD_LOG_GROUP_WARNING |
+                  MOD_LOG_GROUP_DEBUG,
+    .banner = FWK_BANNER_MCP
+              FWK_BANNER_ROM_FIRMWARE
+              BUILD_VERSION_DESCRIBE_STRING "\n",
+};
+
+struct fwk_module_config config_log = {
+    .data = &log_data,
+};
diff --git a/product/clark/mcp_romfw/firmware.mk b/product/clark/mcp_romfw/firmware.mk
new file mode 100644
index 0000000000000000000000000000000000000000..2f8e63d28287b3c69c299694bd2a2aae7ed996b4
--- /dev/null
+++ b/product/clark/mcp_romfw/firmware.mk
@@ -0,0 +1,25 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_FIRMWARE_CPU := cortex-m7
+BS_FIRMWARE_HAS_MULTITHREADING := no
+BS_FIRMWARE_HAS_NOTIFICATION := yes
+BS_FIRMWARE_MODULE_HEADERS_ONLY := \
+    power_domain
+
+BS_FIRMWARE_MODULES := \
+    pl011 \
+    log \
+    clock \
+    clark_rom
+
+BS_FIRMWARE_SOURCES := \
+    config_log.c \
+    config_clock.c \
+    config_clark_rom.c
+
+include $(BS_DIR)/firmware.mk
diff --git a/product/clark/mcp_romfw/fmw_memory.ld.S b/product/clark/mcp_romfw/fmw_memory.ld.S
new file mode 100644
index 0000000000000000000000000000000000000000..29cd40484e45719456e2f942b7f74ef2dd0d761e
--- /dev/null
+++ b/product/clark/mcp_romfw/fmw_memory.ld.S
@@ -0,0 +1,32 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     ROM firmware memory layout for the linker script.
+ */
+
+#ifndef FMW_MEMORY_LD_S
+#define FMW_MEMORY_LD_S
+
+#include <mcp_system_mmap_mcp.h>
+
+#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION
+
+/*
+ * ROM memory
+ */
+#define FIRMWARE_MEM0_SIZE  MCP_ROM_SIZE
+#define FIRMWARE_MEM0_BASE  MCP_ROM_BASE
+
+/*
+ * RAM memory
+ */
+#define FIRMWARE_MEM1_SIZE  MCP_RAM1_SIZE
+#define FIRMWARE_MEM1_BASE  MCP_RAM1_BASE
+
+#define FIRMWARE_STACK_SIZE (1 * 1024)
+
+#endif /* FMW_MEMORY_LD_S */
diff --git a/product/clark/module/clark_rom/include/mod_clark_rom.h b/product/clark/module/clark_rom/include/mod_clark_rom.h
new file mode 100644
index 0000000000000000000000000000000000000000..b20e296e495189ce088e0c907fc02cf84b03ac6b
--- /dev/null
+++ b/product/clark/module/clark_rom/include/mod_clark_rom.h
@@ -0,0 +1,45 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MOD_CLARK_ROM_H
+#define MOD_CLARK_ROM_H
+
+#include <stdint.h>
+
+/*!
+ * \addtogroup GroupCLARKModule CLARK Product Modules
+ * @{
+ */
+
+/*!
+ * \defgroup GroupCLARK ROM Support
+ * @{
+ */
+
+/*!
+ * \brief Module configuration data.
+ */
+struct clark_rom_config {
+    /*! Base address of the RAM firmware image */
+    const uintptr_t ramfw_base;
+
+    /*! Base address of the NOR flash memory */
+    const uintptr_t nor_base;
+
+    /*! The RAM size to load */
+    const unsigned int load_ram_size;
+};
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#endif /* MOD_CLARK_ROM_H */
diff --git a/product/clark/module/clark_rom/src/Makefile b/product/clark/module/clark_rom/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..bebbdb87180cc9bb45b78c9676acd946c40b6181
--- /dev/null
+++ b/product/clark/module/clark_rom/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := clark ROM
+BS_LIB_SOURCES := mod_clark_rom.c
+
+include $(BS_DIR)/lib.mk
\ No newline at end of file
diff --git a/product/clark/module/clark_rom/src/mod_clark_rom.c b/product/clark/module/clark_rom/src/mod_clark_rom.c
new file mode 100644
index 0000000000000000000000000000000000000000..3a64a9efbe583a093180f0aaca043cd7ebfc4a8e
--- /dev/null
+++ b/product/clark/module/clark_rom/src/mod_clark_rom.c
@@ -0,0 +1,118 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <fwk_errno.h>
+#include <fwk_interrupt.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <fwk_thread.h>
+#include <mod_log.h>
+#include <mod_clark_rom.h>
+
+static const struct clark_rom_config *rom_config;
+static struct mod_log_api *log_api;
+
+enum rom_event {
+    ROM_EVENT_RUN,
+    ROM_EVENT_COUNT
+};
+
+/*
+ * This function assumes that the RAM firmware image is located at the beginning
+ * of the SCP SRAM. The reset handler will be at offset 0x4 (the second entry of
+ * the vector table).
+ */
+static void jump_to_ramfw(void)
+{
+    uintptr_t const *reset_base = (uintptr_t *)(rom_config->ramfw_base + 0x4);
+    void (*ramfw_reset_handler)(void);
+
+    /*
+     * Disable interrupts for the duration of the ROM firmware to RAM firmware
+     * transition.
+     */
+    fwk_interrupt_global_disable();
+
+    ramfw_reset_handler = (void (*)(void))*reset_base;
+
+    /*
+     * Execute the RAM firmware's reset handler to pass control from ROM
+     * firmware to the RAM firmware.
+     */
+    ramfw_reset_handler();
+}
+
+/*
+ * Framework API
+ */
+static int clark_rom_init(fwk_id_t module_id, unsigned int element_count,
+    const void *data)
+{
+    rom_config = data;
+
+    return FWK_SUCCESS;
+}
+
+static int clark_rom_bind(fwk_id_t id, unsigned int round)
+{
+    int status;
+
+    /* Use second round only (round numbering is zero-indexed) */
+    if (round == 1) {
+        /* Bind to the log component */
+        status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG),
+                                 FWK_ID_API(FWK_MODULE_IDX_LOG, 0),
+                                 &log_api);
+
+        if (status != FWK_SUCCESS)
+            return FWK_E_PANIC;
+    }
+
+    return FWK_SUCCESS;
+}
+
+static int clark_rom_start(fwk_id_t id)
+{
+    int status;
+    struct fwk_event event = {
+        .source_id = FWK_ID_MODULE(FWK_MODULE_IDX_CLARK_ROM),
+        .target_id = FWK_ID_MODULE(FWK_MODULE_IDX_CLARK_ROM),
+        .id = FWK_ID_EVENT(FWK_MODULE_IDX_CLARK_ROM, ROM_EVENT_RUN),
+    };
+
+    status = fwk_thread_put_event(&event);
+
+    return status;
+}
+
+static int clark_rom_process_event(const struct fwk_event *event,
+    struct fwk_event *resp)
+{
+    log_api->log(MOD_LOG_GROUP_INFO, "[ROM] Launch RAM\n");
+
+    if (rom_config->load_ram_size != 0) {
+        memcpy((void *)rom_config->ramfw_base,
+            (uint8_t *)rom_config->nor_base, rom_config->load_ram_size);
+    }
+
+    jump_to_ramfw();
+
+    return FWK_SUCCESS;
+}
+
+/* Module descriptor */
+const struct fwk_module module_clark_rom = {
+    .name = "CLARK_ROM",
+    .type = FWK_MODULE_TYPE_SERVICE,
+    .event_count = ROM_EVENT_COUNT,
+    .init = clark_rom_init,
+    .bind = clark_rom_bind,
+    .start = clark_rom_start,
+    .process_event = clark_rom_process_event,
+};
diff --git a/product/clark/module/clark_system/include/mod_clark_system.h b/product/clark/module/clark_system/include/mod_clark_system.h
new file mode 100644
index 0000000000000000000000000000000000000000..63ace7f0b9fb9c8da673260526c3d20f1ca2a15f
--- /dev/null
+++ b/product/clark/module/clark_system/include/mod_clark_system.h
@@ -0,0 +1,64 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     CLARK System Support
+ */
+
+#ifndef MOD_CLARK_SYSTEM_H
+#define MOD_CLARK_SYSTEM_H
+
+#include <mod_power_domain.h>
+
+/*!
+ * \addtogroup GroupCLARKModule CLARK Product Modules
+ * @{
+ */
+
+/*!
+ * \defgroup GroupCLARKSystem CLARK System Support
+ * @{
+ */
+
+/*!
+ * \brief Additional CLARK system power states.
+ */
+enum mod_clark_system_power_states {
+    MOD_CLARK_SYSTEM_POWER_STATE_SLEEP0 = MOD_PD_STATE_COUNT,
+    MOD_CLARK_SYSTEM_POWER_STATE_SLEEP1,
+    MOD_CLARK_SYSTEM_POWER_STATE_COUNT
+};
+
+/*!
+ * \brief System power state masks.
+ */
+enum mod_clark_system_power_state_masks {
+    MOD_CLARK_SYSTEM_POWER_STATE_SLEEP0_MASK =
+        (1 << MOD_CLARK_SYSTEM_POWER_STATE_SLEEP0),
+    MOD_CLARK_SYSTEM_POWER_STATE_SLEEP1_MASK =
+        (1 << MOD_CLARK_SYSTEM_POWER_STATE_SLEEP1),
+};
+
+/*!
+ * \brief Indices of the interfaces exposed by the module.
+ */
+enum mod_clark_system_api_idx {
+    /*! API index for the driver interface of the SYSTEM POWER module */
+    MOD_CLARK_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER,
+
+    /*! Number of exposed interfaces */
+    MOD_CLARK_SYSTEM_API_COUNT
+};
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#endif /* MOD_CLARK_SYSTEM_H */
diff --git a/product/clark/module/clark_system/src/Makefile b/product/clark/module/clark_system/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..9003732cef07f24e81b74bd47ece92b4c90bd8ba
--- /dev/null
+++ b/product/clark/module/clark_system/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := CLARK SYSTEM
+BS_LIB_SOURCES = mod_clark_system.c
+
+include $(BS_DIR)/lib.mk
diff --git a/product/clark/module/clark_system/src/mod_clark_system.c b/product/clark/module/clark_system/src/mod_clark_system.c
new file mode 100644
index 0000000000000000000000000000000000000000..1abe4a666c77f3fe5e4a8a78558de15800e39650
--- /dev/null
+++ b/product/clark/module/clark_system/src/mod_clark_system.c
@@ -0,0 +1,269 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     CLARK System Support.
+ */
+
+#include <stdint.h>
+#include <fmw_cmsis.h>
+#include <fwk_assert.h>
+#include <fwk_id.h>
+#include <fwk_interrupt.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <fwk_notification.h>
+#include <mod_clock.h>
+#include <mod_clark_system.h>
+#include <mod_log.h>
+#include <mod_system_power.h>
+#include <mod_power_domain.h>
+#include <mod_ppu_v1.h>
+#include <clark_core.h>
+#include <clark_pik_scp.h>
+#include <scp_clark_irq.h>
+#include <scp_clark_mmap.h>
+#include <config_clock.h>
+
+/* Module context */
+struct clark_system_ctx {
+    /* Pointer to the SCP PIK registers */
+    struct pik_scp_reg *pik_scp_reg;
+
+    /* Log API pointer */
+    const struct mod_log_api *log_api;
+
+    /* Pointer to the Interrupt Service Routine API of the PPU_V1 module */
+    const struct ppu_v1_isr_api *ppu_v1_isr_api;
+
+    /* Power domain module restricted API pointer */
+    struct mod_pd_restricted_api *mod_pd_restricted_api;
+};
+
+struct clark_system_isr {
+    unsigned int interrupt;
+    void (*handler)(void);
+};
+
+static struct clark_system_ctx clark_system_ctx;
+const struct fwk_module_config config_clark_system = { 0 };
+
+/*
+ *  PPU Interrupt Service Routines for cluster and core power domains
+ */
+
+static void ppu_cores_isr(unsigned int first, uint32_t status)
+{
+    unsigned int core_idx;
+
+    while (status != 0) {
+        core_idx = __builtin_ctz(status);
+        status &= ~(1 << core_idx);
+
+        if ((first + core_idx) >= clark_core_get_core_count())
+            continue;
+
+        clark_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler(
+            FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, first + core_idx));
+    }
+}
+
+static void ppu_cores_isr_0(void)
+{
+    ppu_cores_isr(0, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[0]);
+    ppu_cores_isr(128, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[4]);
+}
+
+static void ppu_cores_isr_1(void)
+{
+    ppu_cores_isr(32, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[1]);
+    ppu_cores_isr(160, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[5]);
+}
+
+static void ppu_cores_isr_2(void)
+{
+    ppu_cores_isr(64, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[2]);
+    ppu_cores_isr(192, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[6]);
+}
+
+static void ppu_cores_isr_3(void)
+{
+    ppu_cores_isr(96, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[3]);
+    ppu_cores_isr(224, clark_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[7]);
+}
+
+static void ppu_clusters_isr(void)
+{
+    uint32_t status = clark_system_ctx.pik_scp_reg->CLUS_PPU_INT_STATUS;
+    unsigned int cluster_idx;
+
+    while (status != 0) {
+        cluster_idx = __builtin_ctz(status);
+
+        clark_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler(
+            FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1,
+            clark_core_get_core_count() + cluster_idx));
+
+        status &= ~(1 << cluster_idx);
+    }
+}
+
+/*
+ *  PPU Interrupt Service Routine table
+ */
+
+static struct clark_system_isr isrs[] = {
+    [0] = { .interrupt = PPU_CORES0_IRQ,
+            .handler = ppu_cores_isr_0 },
+    [1] = { .interrupt = PPU_CORES1_IRQ,
+            .handler = ppu_cores_isr_1 },
+    [2] = { .interrupt = PPU_CORES2_IRQ,
+            .handler = ppu_cores_isr_2 },
+    [3] = { .interrupt = PPU_CORES3_IRQ,
+            .handler = ppu_cores_isr_3 },
+    [4] = { .interrupt = PPU_CLUSTERS_IRQ,
+            .handler = ppu_clusters_isr },
+};
+
+/*
+ * System power's driver API
+ */
+
+static int clark_system_shutdown(
+    enum mod_pd_system_shutdown system_shutdown)
+{
+    NVIC_SystemReset();
+
+    return FWK_E_DEVICE;
+}
+
+static const struct mod_system_power_driver_api
+    clark_system_system_power_driver_api = {
+    .system_shutdown = clark_system_shutdown,
+};
+
+/*
+ * Functions fulfilling the framework's module interface
+ */
+
+static int clark_system_mod_init(fwk_id_t module_id, unsigned int unused,
+    const void *unused2)
+{
+    int status;
+    unsigned int idx;
+    struct clark_system_isr *isr;
+
+    for (idx = 0; idx < FWK_ARRAY_SIZE(isrs); idx++) {
+        isr = &isrs[idx];
+        status = fwk_interrupt_set_isr(isr->interrupt, isr->handler);
+        if (status != FWK_SUCCESS)
+            return status;
+    }
+
+    clark_system_ctx.pik_scp_reg = (struct pik_scp_reg *)SCP_PIK_SCP_BASE;
+
+    return FWK_SUCCESS;
+}
+
+static int clark_system_bind(fwk_id_t id, unsigned int round)
+{
+    int status;
+
+    if (round == 0) {
+        status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG),
+            FWK_ID_API(FWK_MODULE_IDX_LOG, 0), &clark_system_ctx.log_api);
+        if (status != FWK_SUCCESS)
+            return status;
+    }
+
+    status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN),
+        FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED),
+        &clark_system_ctx.mod_pd_restricted_api);
+    if (status != FWK_SUCCESS)
+        return status;
+
+    return fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1),
+        FWK_ID_API(FWK_MODULE_IDX_PPU_V1, MOD_PPU_V1_API_IDX_ISR),
+        &clark_system_ctx.ppu_v1_isr_api);
+}
+
+static int clark_system_process_bind_request(fwk_id_t requester_id,
+    fwk_id_t pd_id, fwk_id_t api_id, const void **api)
+{
+    *api = &clark_system_system_power_driver_api;
+    return FWK_SUCCESS;
+}
+
+static int clark_system_start(fwk_id_t id)
+{
+    int status;
+
+    status = fwk_notification_subscribe(
+        mod_clock_notification_id_state_changed,
+        FWK_ID_ELEMENT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT),
+        id);
+    if (status != FWK_SUCCESS)
+        return status;
+
+    clark_system_ctx.log_api->log(MOD_LOG_GROUP_DEBUG,
+        "[CLARK SYSTEM] Requesting SYSTOP initialization...\n");
+
+    return
+        clark_system_ctx.mod_pd_restricted_api->set_composite_state_async(
+            FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), false,
+            MOD_PD_COMPOSITE_STATE(MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON,
+                                   MOD_PD_STATE_OFF, MOD_PD_STATE_OFF));
+}
+
+int clark_system_process_notification(const struct fwk_event *event,
+    struct fwk_event *resp_event)
+{
+    int status;
+    struct clock_notification_params *params;
+    struct mod_pd_restricted_api *mod_pd_restricted_api;
+
+    assert(fwk_id_is_equal(event->id, mod_clock_notification_id_state_changed));
+    assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE));
+
+    params = (struct clock_notification_params *)event->params;
+
+    /*
+     * Initialize primary core when the system is initialized for the first time
+     * only
+     */
+    if (params->new_state == MOD_CLOCK_STATE_RUNNING) {
+        clark_system_ctx.log_api->log(MOD_LOG_GROUP_DEBUG,
+            "[CLARK SYSTEM] Initializing the primary core...\n");
+
+        mod_pd_restricted_api = clark_system_ctx.mod_pd_restricted_api;
+
+        status =  mod_pd_restricted_api->set_composite_state_async(
+            FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0),
+            false,
+            MOD_PD_COMPOSITE_STATE(MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON,
+                MOD_PD_STATE_ON, MOD_PD_STATE_ON));
+        if (status != FWK_SUCCESS)
+            return status;
+
+        /* Unsubscribe to the notification */
+        return fwk_notification_unsubscribe(event->id, event->source_id,
+                                            event->target_id);
+    }
+
+    return FWK_SUCCESS;
+}
+
+const struct fwk_module module_clark_system = {
+    .name = "CLARK_SYSTEM",
+    .type = FWK_MODULE_TYPE_DRIVER,
+    .api_count = MOD_CLARK_SYSTEM_API_COUNT,
+    .init = clark_system_mod_init,
+    .bind = clark_system_bind,
+    .process_bind_request = clark_system_process_bind_request,
+    .process_notification = clark_system_process_notification,
+    .start = clark_system_start,
+};
diff --git a/product/clark/product.mk b/product/clark/product.mk
new file mode 100644
index 0000000000000000000000000000000000000000..ed9aa518f2e9ab8170036cebea570c581f6e708c
--- /dev/null
+++ b/product/clark/product.mk
@@ -0,0 +1,13 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platforms supported by the clark product: SGI-Clark.
+#
+
+BS_PRODUCT_NAME := clark
+BS_FIRMWARE_LIST := scp_romfw \
+                    scp_ramfw \
+                    mcp_romfw
diff --git a/product/clark/scp_ramfw/RTX_Config.h b/product/clark/scp_ramfw/RTX_Config.h
new file mode 100644
index 0000000000000000000000000000000000000000..688d384f1466607648a22255cf7163b58413d85f
--- /dev/null
+++ b/product/clark/scp_ramfw/RTX_Config.h
@@ -0,0 +1,56 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *      RTX2 v5 configuration file.
+ *      The file must be called RTX_Config.h as it is included by the an RTX
+ *      file in order to create a object file containing the configuration.
+ */
+
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+
+/* System */
+#define OS_DYNAMIC_MEM_SIZE        0
+#define OS_TICK_FREQ               1000 /* Hz */
+#define OS_ROBIN_ENABLE            0
+#define OS_ROBIN_TIMEOUT           0
+#define OS_ISR_FIFO_QUEUE          16
+
+/* Thread */
+#define OS_THREAD_OBJ_MEM          0
+#define OS_THREAD_NUM              1
+#define OS_THREAD_DEF_STACK_NUM    0
+#define OS_THREAD_USER_STACK_SIZE  0
+#define OS_STACK_SIZE              200
+#define OS_IDLE_THREAD_STACK_SIZE  200
+#define OS_STACK_CHECK             1
+#define OS_STACK_WATERMARK         0
+#define OS_PRIVILEGE_MODE          1
+
+/* Timer */
+#define OS_TIMER_OBJ_MEM           0
+#define OS_TIMER_NUM               1
+#define OS_TIMER_THREAD_PRIO       40
+#define OS_TIMER_THREAD_STACK_SIZE 200
+#define OS_TIMER_CB_QUEUE          4
+
+/* Event flags */
+#define OS_EVFLAGS_OBJ_MEM         0
+#define OS_EVFLAGS_NUM             1
+
+#define OS_MUTEX_OBJ_MEM           0
+#define OS_MUTEX_NUM               1
+#define OS_SEMAPHORE_OBJ_MEM       0
+#define OS_SEMAPHORE_NUM           1
+#define OS_MEMPOOL_OBJ_MEM         0
+#define OS_MEMPOOL_NUM             1
+#define OS_MEMPOOL_DATA_SIZE       0
+#define OS_MSGQUEUE_OBJ_MEM        0
+#define OS_MSGQUEUE_NUM            1
+#define OS_MSGQUEUE_DATA_SIZE      0
+
+#endif /* RTX_CONFIG_H_ */
diff --git a/product/clark/scp_ramfw/config_apcontext.c b/product/clark/scp_ramfw/config_apcontext.c
new file mode 100644
index 0000000000000000000000000000000000000000..250d5209b87f7624257d97ad16523a9af8e9de41
--- /dev/null
+++ b/product/clark/scp_ramfw/config_apcontext.c
@@ -0,0 +1,26 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_apcontext.h>
+#include <scp_software_mmap.h>
+#include <config_clock.h>
+
+/*
+ * AP Context module configuration
+ */
+static const struct mod_apcontext_config apcontext_data = {
+    .base = SCP_AP_CONTEXT_BASE,
+    .size = SCP_AP_CONTEXT_SIZE,
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        CLOCK_IDX_INTERCONNECT),
+};
+
+struct fwk_module_config config_apcontext = {
+    .data = &apcontext_data,
+};
diff --git a/product/clark/scp_ramfw/config_armv7m_mpu.c b/product/clark/scp_ramfw/config_armv7m_mpu.c
new file mode 100644
index 0000000000000000000000000000000000000000..9943b764cf307599a854c654f0b97577b85db36a
--- /dev/null
+++ b/product/clark/scp_ramfw/config_armv7m_mpu.c
@@ -0,0 +1,47 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <scp_clark_mmap.h>
+#include <scp_clark_mmap_scp.h>
+#include <mod_armv7m_mpu.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+
+static const ARM_MPU_Region_t regions[] = {
+    { /* 0x0000_0000 - 0xFFFF_FFFF */
+        .RBAR = ARM_MPU_RBAR(0, 0x00000000),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 1, 0, 1, 0, ARM_MPU_REGION_SIZE_4GB),
+    },
+    { /* 0x0080_0000 - 0x00FF_FFFF */
+        .RBAR = ARM_MPU_RBAR(1, SCP_RAM0_BASE),
+        .RASR = ARM_MPU_RASR(
+            0, ARM_MPU_AP_PRO, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB),
+    },
+    { /* 0x2000_0000 - 0x20FF_FFFF */
+        .RBAR = ARM_MPU_RBAR(2, SCP_RAM1_BASE),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB),
+    },
+    { /* 0xA400_0000 - 0xA400_7FFF*/
+        .RBAR = ARM_MPU_RBAR(3, SCP_TRUSTED_RAM_BASE),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_4KB),
+    },
+    { /* 0xA600_0000 - 0xA600_7FFF */
+        .RBAR = ARM_MPU_RBAR(4, SCP_NONTRUSTED_RAM_BASE),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B),
+    },
+};
+
+const struct fwk_module_config config_armv7m_mpu = {
+    .data = &((struct mod_armv7m_mpu_config){
+        .region_count = FWK_ARRAY_SIZE(regions),
+        .regions = regions,
+    }),
+};
diff --git a/product/clark/scp_ramfw/config_clock.c b/product/clark/scp_ramfw/config_clock.c
new file mode 100644
index 0000000000000000000000000000000000000000..32a76ad109e6fda706060c65ecf9d0e768973138
--- /dev/null
+++ b/product/clark/scp_ramfw/config_clock.c
@@ -0,0 +1,78 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_clock.h>
+#include <mod_css_clock.h>
+#include <mod_pik_clock.h>
+#include <mod_power_domain.h>
+#include <clark_core.h>
+#include <system_clock.h>
+#include <config_clock.h>
+#include <config_power_domain.h>
+
+static const struct fwk_element clock_dev_desc_table[] = {
+    [CLOCK_IDX_INTERCONNECT] = {
+        .name = "Interconnect",
+        .data = &((struct mod_clock_dev_config) {
+            .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK,
+                CLOCK_PIK_IDX_INTERCONNECT),
+            .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
+                MOD_PIK_CLOCK_API_TYPE_CLOCK),
+        }),
+    },
+    [CLOCK_IDX_CPU_GROUP0] = {
+        .name = "CPU_GROUP0",
+        .data = &((struct mod_clock_dev_config) {
+            .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK,
+                CLOCK_CSS_IDX_CPU_GROUP0),
+            .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK,
+                MOD_CSS_CLOCK_API_TYPE_CLOCK),
+        }),
+    },
+    [CLOCK_IDX_CPU_GROUP1] = {
+        .name = "CPU_GROUP1",
+        .data = &((struct mod_clock_dev_config) {
+            .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK,
+                CLOCK_CSS_IDX_CPU_GROUP1),
+            .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK,
+                MOD_CSS_CLOCK_API_TYPE_CLOCK),
+        }),
+    },
+    { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id)
+{
+    unsigned int i;
+    struct mod_clock_dev_config *dev_config;
+
+    for (i = 0; i < CLOCK_IDX_COUNT; i++) {
+        dev_config =
+            (struct mod_clock_dev_config *)clock_dev_desc_table[i].data;
+        dev_config->pd_source_id = fwk_id_build_element_id(
+            fwk_module_id_power_domain,
+            clark_core_get_core_count() + PD_STATIC_DEV_IDX_SYSTOP);
+    }
+
+    return clock_dev_desc_table;
+}
+
+const struct fwk_module_config config_clock = {
+    .get_element_table = clock_get_dev_desc_table,
+    .data = &((struct mod_clock_config) {
+        .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT(
+            FWK_MODULE_IDX_POWER_DOMAIN,
+            MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION),
+        .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT(
+            FWK_MODULE_IDX_POWER_DOMAIN,
+            MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION),
+    }),
+
+};
diff --git a/product/clark/scp_ramfw/config_clock.h b/product/clark/scp_ramfw/config_clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..2f66c42b688cb163b1231f4fd75a4b3049b66eee
--- /dev/null
+++ b/product/clark/scp_ramfw/config_clock.h
@@ -0,0 +1,64 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONFIG_CLOCK_H
+#define CONFIG_CLOCK_H
+
+/*
+ * Clock indexes.
+ */
+enum clock_idx {
+    CLOCK_IDX_INTERCONNECT,
+    CLOCK_IDX_CPU_GROUP0,
+    CLOCK_IDX_CPU_GROUP1,
+    CLOCK_IDX_COUNT
+};
+
+/*
+ * PIK clock indexes.
+ */
+enum clock_pik_idx {
+    CLOCK_PIK_IDX_CLUS0_CPU0,
+    CLOCK_PIK_IDX_CLUS0_CPU1,
+    CLOCK_PIK_IDX_CLUS0_CPU2,
+    CLOCK_PIK_IDX_CLUS0_CPU3,
+    CLOCK_PIK_IDX_CLUS1_CPU0,
+    CLOCK_PIK_IDX_CLUS1_CPU1,
+    CLOCK_PIK_IDX_CLUS1_CPU2,
+    CLOCK_PIK_IDX_CLUS1_CPU3,
+    CLOCK_PIK_IDX_DMC,
+    CLOCK_PIK_IDX_INTERCONNECT,
+    CLOCK_PIK_IDX_SCP,
+    CLOCK_PIK_IDX_GIC,
+    CLOCK_PIK_IDX_PCLKSCP,
+    CLOCK_PIK_IDX_SYSPERCLK,
+    CLOCK_PIK_IDX_UARTCLK,
+    CLOCK_PIK_IDX_COUNT
+};
+
+/*
+ * CSS clock indexes.
+ */
+enum clock_css_idx {
+    CLOCK_CSS_IDX_CPU_GROUP0,
+    CLOCK_CSS_IDX_CPU_GROUP1,
+    CLOCK_CSS_IDX_COUNT
+};
+
+/*
+ * PLL clock indexes.
+ */
+enum clock_pll_idx {
+    CLOCK_PLL_IDX_CPU0,
+    CLOCK_PLL_IDX_CPU1,
+    CLOCK_PLL_IDX_SYS,
+    CLOCK_PLL_IDX_DMC,
+    CLOCK_PLL_IDX_INTERCONNECT,
+    CLOCK_PLL_IDX_COUNT
+};
+
+#endif /* CONFIG_CLOCK_H */
diff --git a/product/clark/scp_ramfw/config_cmn600.c b/product/clark/scp_ramfw/config_cmn600.c
new file mode 100644
index 0000000000000000000000000000000000000000..03371c7ed11f3c077d2e9e061ccbdc5649145624
--- /dev/null
+++ b/product/clark/scp_ramfw/config_cmn600.c
@@ -0,0 +1,108 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_cmn600.h>
+#include <scp_clark_mmap.h>
+#include <config_clock.h>
+
+#define ROOT_NODE_OFFSET 0xD00000
+
+/*
+ * CMN600 nodes
+ */
+#define DMC0_ID 0x60
+#define DMC1_ID 0x6c
+#define NODE_ID_HND 0x68
+#define NODE_ID_SBSX 0x64
+
+static const unsigned int snf_table[] = {
+    DMC0_ID, /* Maps to HN-F logical node 0 */
+    DMC0_ID, /* Maps to HN-F logical node 1 */
+    DMC1_ID, /* Maps to HN-F logical node 2 */
+    DMC1_ID, /* Maps to HN-F logical node 3 */
+};
+
+static const struct mod_cmn600_memory_region_map mmap[] = {
+    {
+        /*
+         * System cache backed region
+         * Map: 0x0000_0000_0000 - 0xFFFF_FFFF_FFFF (256 TB)
+         */
+        .base = UINT64_C(0x000000000000),
+        .size = UINT64_C(256) * FWK_TIB,
+        .type = MOD_CMN600_MEMORY_REGION_TYPE_SYSCACHE,
+    },
+    {
+        /*
+         * Boot region
+         * Map: 0x0000_0000_0000 - 0x0000_0001_FFFF (128 MB)
+         */
+        .base = UINT64_C(0x000000000000),
+        .size = UINT64_C(128) * FWK_MIB,
+        .type = MOD_CMN600_REGION_TYPE_SYSCACHE_SUB,
+        .node_id = NODE_ID_SBSX,
+    },
+    {
+        /*
+         * Peripherals
+         * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB)
+         */
+        .base = UINT64_C(0x0008000000),
+        .size = UINT64_C(128) * FWK_MIB,
+        .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+        .node_id = NODE_ID_HND,
+    },
+    {
+        /*
+         * Peripherals
+         * Map: 0x00_1000_0000 - 0x00_1FFF_FFFF (256 MB)
+         */
+        .base = UINT64_C(0x0010000000),
+        .size = UINT64_C(256) * FWK_MIB,
+        .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+        .node_id = NODE_ID_HND,
+    },
+    {
+        /*
+         * Peripherals
+         * Map: 0x00_2000_0000 - 0x00_3FFF_FFFF (512 MB)
+         */
+        .base = UINT64_C(0x0020000000),
+        .size = UINT64_C(512) * FWK_MIB,
+        .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+        .node_id = NODE_ID_HND,
+    },
+    {
+        /*
+         * Peripherals
+         * Map: 0x00_4000_0000 - 0x00_7FFF_FFFF (1 GB)
+         */
+        .base = UINT64_C(0x0040000000),
+        .size = UINT64_C(1) * FWK_GIB,
+        .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+        .node_id = NODE_ID_HND,
+    },
+};
+
+const struct fwk_module_config config_cmn600 = {
+    .get_element_table = NULL,
+    .data = &((struct mod_cmn600_config) {
+        .base = SCP_CMN600_BASE,
+        .mesh_size_x = 4,
+        .mesh_size_y = 2,
+        .hnd_node_id = NODE_ID_HND,
+        .snf_table = snf_table,
+        .snf_count = FWK_ARRAY_SIZE(snf_table),
+        .mmap_table = mmap,
+        .mmap_count = FWK_ARRAY_SIZE(mmap),
+        .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+            CLOCK_IDX_INTERCONNECT),
+    }),
+};
diff --git a/product/clark/scp_ramfw/config_css_clock.c b/product/clark/scp_ramfw/config_css_clock.c
new file mode 100644
index 0000000000000000000000000000000000000000..63f3ecd4a7db7923cb690f77e840d50a40ad5eb2
--- /dev/null
+++ b/product/clark/scp_ramfw/config_css_clock.c
@@ -0,0 +1,189 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_css_clock.h>
+#include <mod_system_pll.h>
+#include <mod_pik_clock.h>
+#include <scp_clark_pik.h>
+#include <config_clock.h>
+
+static const struct mod_css_clock_rate rate_table_cpu_group_0[] = {
+    {
+        /* Super Underdrive */
+        .rate = 1313 * FWK_MHZ,
+        .pll_rate = 1313 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Underdrive */
+        .rate = 1531 * FWK_MHZ,
+        .pll_rate = 1531 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Nominal */
+        .rate = 1750 * FWK_MHZ,
+        .pll_rate = 1750 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Overdrive */
+        .rate = 2100 * FWK_MHZ,
+        .pll_rate = 2100 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Super Overdrive */
+        .rate = 2600 * FWK_MHZ,
+        .pll_rate = 2600 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+};
+
+static const struct mod_css_clock_rate rate_table_cpu_group_1[] = {
+    {
+        /* Super Underdrive */
+        .rate = 1313 * FWK_MHZ,
+        .pll_rate = 1313 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Underdrive */
+        .rate = 1531 * FWK_MHZ,
+        .pll_rate = 1531 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Nominal */
+        .rate = 1750 * FWK_MHZ,
+        .pll_rate = 1750 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Overdrive */
+        .rate = 2100 * FWK_MHZ,
+        .pll_rate = 2100 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Super Overdrive */
+        .rate = 2600 * FWK_MHZ,
+        .pll_rate = 2600 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+};
+
+static const fwk_id_t member_table_cpu_group_0[] = {
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3),
+};
+
+static const fwk_id_t member_table_cpu_group_1[] = {
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU0),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU1),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU2),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU3),
+};
+
+static const struct fwk_element css_clock_element_table[] = {
+    [CLOCK_CSS_IDX_CPU_GROUP0] = {
+        .name = "CPU_GROUP_0",
+        .data = &((struct mod_css_clock_dev_config) {
+            .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
+            .rate_table = rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+            .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
+            .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                CLOCK_PLL_IDX_CPU0),
+            .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
+            .member_table = member_table_cpu_group_0,
+            .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0),
+            .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
+                MOD_PIK_CLOCK_API_TYPE_CSS),
+            .initial_rate = 2600 * FWK_MHZ,
+            .modulation_supported = true,
+        }),
+    },
+    [CLOCK_CSS_IDX_CPU_GROUP1] = {
+        .name = "CPU_GROUP_1",
+        .data = &((struct mod_css_clock_dev_config) {
+            .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
+            .rate_table = rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+            .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
+            .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                CLOCK_PLL_IDX_CPU1),
+            .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
+            .member_table = member_table_cpu_group_1,
+            .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_1),
+            .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
+                MOD_PIK_CLOCK_API_TYPE_CSS),
+            .initial_rate = 2600 * FWK_MHZ,
+            .modulation_supported = true,
+        }),
+    },
+    [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *css_clock_get_element_table
+    (fwk_id_t module_id)
+{
+    return css_clock_element_table;
+}
+
+const struct fwk_module_config config_css_clock = {
+    .get_element_table = css_clock_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_ddr_phy500.c b/product/clark/scp_ramfw/config_ddr_phy500.c
new file mode 100644
index 0000000000000000000000000000000000000000..06fca4c51283b63b47a953a6a006d698a2e8901b
--- /dev/null
+++ b/product/clark/scp_ramfw/config_ddr_phy500.c
@@ -0,0 +1,57 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <mod_ddr_phy500.h>
+#include <scp_system_mmap.h>
+
+/* Default configuration values for DDR PHY500 devices. */
+static struct mod_ddr_phy500_reg ddr_reg_val = {
+    .INIT_COMPLETE  = 0x00000001,
+    .READ_DELAY     = 0x00000001,
+    .CAPTURE_MASK   = 0x00000002,
+    .T_CTRL_DELAY   = 0x0C000000,
+    .T_WRLAT        = 0x00000001,
+    .T_RDDATA_EN    = 0x00001600,
+    .T_RDLAT        = 0x00000011,
+    .DFI_LP_ACK     = 0x00030000,
+    .DFI_WR_PREMBL  = 0x00000001,
+    .DELAY_SEL      = 0x0000000D,
+    .REF_EN         = 0x00000000,
+    .T_CTRL_UPD_MIN = 0x00000000,
+};
+
+/* Table of DDR PHY500 element descriptions. */
+static struct fwk_element ddr_phy500_element_table[] = {
+    [0] = { .name = "DDR_PHY500-0",
+            .data = &((struct mod_ddr_phy500_element_config) {
+                .ddr = SCP_DDR_PHY0,
+        }),
+    },
+    [1] = { .name = "DDR_PHY500-1",
+            .data = &((struct mod_ddr_phy500_element_config) {
+                .ddr = SCP_DDR_PHY1,
+        }),
+    },
+    [2] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *ddr_phy500_get_element_table
+    (fwk_id_t module_id)
+{
+    return ddr_phy500_element_table;
+}
+
+/* Configuration of the DDR PHY500 module. */
+const struct fwk_module_config config_ddr_phy500 = {
+    .get_element_table = ddr_phy500_get_element_table,
+    .data = &((struct mod_ddr_phy500_module_config) {
+            .ddr_reg_val = &ddr_reg_val,
+            .initialize_init_complete = true,
+            .initialize_ref_en = true,
+        }),
+};
diff --git a/product/clark/scp_ramfw/config_dmc620.c b/product/clark/scp_ramfw/config_dmc620.c
new file mode 100644
index 0000000000000000000000000000000000000000..f4cf3546024b93d26dcfc40fca924cde2168735a
--- /dev/null
+++ b/product/clark/scp_ramfw/config_dmc620.c
@@ -0,0 +1,216 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_dmc620.h>
+#include <scp_system_mmap.h>
+#include <config_clock.h>
+
+#define COL_BITS 2
+#define BANK_BITS 4
+#define RANK_BITS 1
+#define ROW_BITS 4
+#define BANK_HASH_ENABLE 1
+#define MEM_TYPE 2
+#define ADDR_DEC 0x68C
+#define STRIPE_DEC 1
+#define MEM_DEVICE_WIDTH 0
+#define BANK_GROUP 3
+#define MEM_CHANNEL 2
+#define ADDRESS_CONTROL_NEXT_VAL ((BANK_HASH_ENABLE << 28) | \
+                                 (RANK_BITS << 24) | (BANK_BITS << 16) | \
+                                 (ROW_BITS << 8) | (COL_BITS))
+#define DECODE_CONTROL_NEXT_VAL ((ADDR_DEC << 10) | (STRIPE_DEC << 4))
+#define MEMORY_TYPE_NEXT_VAL ((BANK_GROUP << 16) | (MEM_DEVICE_WIDTH << 8) | \
+                             (MEM_TYPE))
+
+struct mod_dmc620_reg dmc_val = {
+    .ADDRESS_CONTROL_NEXT = ADDRESS_CONTROL_NEXT_VAL,
+    .DECODE_CONTROL_NEXT = DECODE_CONTROL_NEXT_VAL,
+    .FORMAT_CONTROL = 0x00000003,
+    .ADDRESS_MAP_NEXT = 0x00000002,
+    .LOW_POWER_CONTROL_NEXT = 0x00000010,
+    .TURNAROUND_CONTROL_NEXT = 0x1F0F0F0F,
+    .HIT_TURNAROUND_CONTROL_NEXT = 0x08909FBF,
+    .QOS_CLASS_CONTROL_NEXT = 0x00000FC8,
+    .ESCALATION_CONTROL_NEXT = 0x00080F00,
+    .QV_CONTROL_31_00_NEXT = 0x76543210,
+    .QV_CONTROL_63_32_NEXT = 0xFEDCBA98,
+    .RT_CONTROL_31_00_NEXT = 0x00000000,
+    .RT_CONTROL_63_32_NEXT = 0x00000000,
+    .TIMEOUT_CONTROL_NEXT = 0x00000001,
+    .CREDIT_CONTROL_NEXT = 0x00000F03,
+    .WRITE_PRIORITY_CONTROL_31_00_NEXT = 0x00000000,
+    .WRITE_PRIORITY_CONTROL_63_32_NEXT = 0xECA86421,
+    .QUEUE_THRESHOLD_CONTROL_31_00_NEXT = 0x00000008,
+    .QUEUE_THRESHOLD_CONTROL_63_32_NEXT = 0x00000000,
+    .ADDRESS_SHUTTER_31_00_NEXT = 0x11111110,
+    .ADDRESS_SHUTTER_63_32_NEXT = 0x11111111,
+    .ADDRESS_SHUTTER_95_64_NEXT = 0x11111111,
+    .ADDRESS_SHUTTER_127_96_NEXT = 0x11111111,
+    .ADDRESS_SHUTTER_159_128_NEXT = 0x11111111,
+    .ADDRESS_SHUTTER_191_160_NEXT = 0x11111111,
+    .MEMORY_ADDRESS_MAX_31_00_NEXT = 0xFFFF001F,
+    .MEMORY_ADDRESS_MAX_43_32_NEXT = 0x00000FFF,
+    .ACCESS_ADDRESS_NEXT = {
+        [0] = {.MIN_31_00 = 0x0000000F, .MIN_43_32 = 0x00000000},
+        [1] = {.MIN_31_00 = 0x0000000F, .MIN_43_32 = 0x00000000},
+        [2] = {.MIN_31_00 = 0x0000000F},
+        [3] = {.MIN_31_00 = 0x0000000F},
+        [4] = {.MIN_31_00 = 0x0000000F},
+        [5] = {.MIN_31_00 = 0x0000000F},
+        [6] = {.MIN_31_00 = 0x0000000F},
+        [7] = {.MIN_31_00 = 0x0000000F},
+    },
+    .DCI_REPLAY_TYPE_NEXT = 0x00000000,
+    .DCI_STRB = 0x00000007,
+    .DCI_DATA = 0x00000000,
+    .REFRESH_CONTROL_NEXT = 0x00000000,
+    .MEMORY_TYPE_NEXT = MEMORY_TYPE_NEXT_VAL,
+    .FEATURE_CONFIG = 0x00001800,
+    .FEATURE_CONTROL_NEXT = 0x00000000,
+    .MUX_CONTROL_NEXT = 0x00000000,
+    .T_REFI_NEXT = 0x90000618,
+    .T_RFC_NEXT = 0x06A8C230,
+    .T_MRR_NEXT = 0x00000001,
+    .T_MRW_NEXT = 0x00010018,
+    .T_RCD_NEXT = 0x00000014,
+    .T_RAS_NEXT = 0x00000034,
+    .T_RP_NEXT = 0x00000014,
+    .T_RPALL_NEXT = 0x00000014,
+    .T_RRD_NEXT = 0x04000805,
+    .T_ACT_WINDOW_NEXT = 0x00001010,
+    .T_RTR_NEXT = 0x14060804,
+    .T_RTW_NEXT = 0x000A0A0A,
+    .T_RTP_NEXT = 0x0000000C,
+    .T_WR_NEXT = 0x0000002C,
+    .T_WTR_NEXT = 0x00022019,
+    .T_WTW_NEXT = 0x14060804,
+    .T_XMPD_NEXT = 0x00000510,
+    .T_EP_NEXT = 0x00000008,
+    .T_XP_NEXT = 0x0014000A,
+    .T_ESR_NEXT = 0x00000009,
+    .T_XSR_NEXT = 0x04000110,
+    .T_ESRCK_NEXT = 0x00000010,
+    .T_CKXSR_NEXT = 0x00000010,
+    .T_CMD_NEXT = 0x00000000,
+    .T_PARITY_NEXT = 0x00001600,
+    .T_ZQCS_NEXT = 0x00000090,
+    .T_RW_ODT_CLR_NEXT = 0x0000005E,
+    .T_RDDATA_EN_NEXT = 0x00000000,
+    .T_PHYWRLAT_NEXT = 0x001F000E,
+    .T_PHYRDLAT_NEXT = 0x0000002E,
+    .RDLVL_CONTROL_NEXT = 0x00000000,
+    .RDLVL_MRS_NEXT = 0x00000424,
+    .T_RDLVL_EN_NEXT = 0x00000001,
+    .T_RDLVL_RR_NEXT = 0x0000001A,
+    .WRLVL_CONTROL_NEXT = 0x00100000,
+    .WRLVL_MRS_NEXT = 0x00000181,
+    .T_WRLVL_EN_NEXT = 0x00000018,
+    .T_WRLVL_WW_NEXT = 0x00000001,
+    .PHY_POWER_CONTROL_NEXT = 0x00000000,
+    .T_LPRESP_NEXT = 0x00000000,
+    .PHY_UPDATE_CONTROL_NEXT = 0x00000000,
+    .T_ODTH_NEXT = 0x00000006,
+    .ODT_TIMING_NEXT = 0x07003900,
+    .ODT_WR_CONTROL_31_00_NEXT = 0x08040201,
+    .ODT_WR_CONTROL_63_32_NEXT = 0x80402010,
+    .ODT_RD_CONTROL_31_00_NEXT = 0x00000000,
+    .ODT_RD_CONTROL_63_32_NEXT = 0x00000000,
+    .ERR0CTLR0 = DMC_ERR0CTRL0_ED_ENABLE |
+                 DMC_ERR0CTRL0_DE_ENABLE |
+                 DMC_ERR0CTRL0_UI_ENABLE |
+                 DMC_ERR0CTRL0_FI_ENABLE |
+                 DMC_ERR0CTRL0_CFI_ENABLE,
+};
+
+/* Table of DMC620 elements descriptions. */
+static struct fwk_element dmc620_element_table[] = {
+    [0] = { .name = "DMC620-0",
+            .data = &((struct mod_dmc620_element_config) {
+                .dmc = SCP_DMC0,
+                .ddr_id = FWK_ID_ELEMENT_INIT(
+                    FWK_MODULE_IDX_DDR_PHY500, 0),
+                .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+                    CLOCK_IDX_INTERCONNECT),
+        }),
+    },
+    [1] = { .name = "DMC620-1",
+            .data = &((struct mod_dmc620_element_config) {
+                .dmc = SCP_DMC1,
+                .ddr_id = FWK_ID_ELEMENT_INIT(
+                    FWK_MODULE_IDX_DDR_PHY500, 1),
+                .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+                    CLOCK_IDX_INTERCONNECT),
+        }),
+    },
+    [2] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *dmc620_get_element_table(fwk_id_t module_id)
+{
+    return dmc620_element_table;
+}
+
+static void direct_ddr_cmd(struct mod_dmc620_reg *dmc)
+{
+    dmc->DIRECT_ADDR = 0x00000004;
+    dmc->DIRECT_CMD  = 0x0001000A;
+    dmc->DIRECT_ADDR = 0x00000006;
+    dmc->DIRECT_CMD  = 0x00030004;
+    dmc->DIRECT_ADDR = 0x00000000;
+    dmc->DIRECT_CMD  = 0x0001000B;
+    dmc->DIRECT_ADDR = 0x00000001;
+    dmc->DIRECT_CMD  = 0x0003000B;
+    dmc->DIRECT_ADDR = 0x000003E8;
+    dmc->DIRECT_CMD  = 0x0001000D;
+    dmc->DIRECT_ADDR = 0x00000258;
+    dmc->DIRECT_CMD  = 0x0001000D;
+    dmc->DIRECT_ADDR = 0x00010001;
+    dmc->DIRECT_CMD  = 0x0003000B;
+    dmc->DIRECT_ADDR = 0x0000003C;
+    dmc->DIRECT_CMD  = 0x0001000D;
+    dmc->DIRECT_ADDR = 0x00000000;
+    dmc->DIRECT_CMD  = 0x00030000;
+    dmc->DIRECT_ADDR = 0x0000003C;
+    dmc->DIRECT_ADDR = 0x00000420;
+    dmc->DIRECT_CMD  = 0x00030301;
+    dmc->DIRECT_ADDR = 0x00001000;
+    dmc->DIRECT_CMD  = 0x00030601;
+    dmc->DIRECT_ADDR = 0x00000600;
+    dmc->DIRECT_CMD  = 0x00030501;
+    dmc->DIRECT_ADDR = 0x00000000;
+    dmc->DIRECT_CMD  = 0x30030401;
+    dmc->DIRECT_ADDR = 0x00000028;
+    dmc->DIRECT_CMD  = 0x00030201;
+    dmc->DIRECT_ADDR = 0x00000001;
+    dmc->DIRECT_CMD  = 0x00030101;
+    dmc->DIRECT_ADDR = 0x00000D50;
+    dmc->DIRECT_CMD  = 0x00030001;
+    dmc->DIRECT_ADDR = 0x000003F6;
+    dmc->DIRECT_CMD  = 0x0001000D;
+    dmc->DIRECT_ADDR = 0x0000000A;
+    dmc->DIRECT_CMD  = 0x0001000D;
+    dmc->DIRECT_ADDR = 0x00000400;
+    dmc->DIRECT_CMD  = 0x00030005;
+    dmc->DIRECT_ADDR = 0x000003FF;
+    dmc->DIRECT_CMD  = 0x0001000D;
+
+}
+
+/* Configuration of the DMC500 module. */
+const struct fwk_module_config config_dmc620 = {
+    .get_element_table = dmc620_get_element_table,
+    .data = &((struct mod_dmc620_module_config) {
+            .dmc_val = &dmc_val,
+            .ddr_module_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_DDR_PHY500),
+            .ddr_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_DDR_PHY500, 0),
+            .direct_ddr_cmd = direct_ddr_cmd,
+        }),
+};
diff --git a/product/clark/scp_ramfw/config_dvfs.c b/product/clark/scp_ramfw/config_dvfs.c
new file mode 100644
index 0000000000000000000000000000000000000000..3ef546f62d9962709c8133b4cfa3add222e3f7af
--- /dev/null
+++ b/product/clark/scp_ramfw/config_dvfs.c
@@ -0,0 +1,74 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_dvfs.h>
+#include <config_clock.h>
+
+static struct mod_dvfs_opp opps[] = {
+        {
+            .frequency = 1313 * FWK_MHZ,
+            .voltage = 100,
+        },
+        {
+            .frequency = 1531 * FWK_MHZ,
+            .voltage = 200,
+        },
+        {
+            .frequency = 1750 * FWK_MHZ,
+            .voltage = 300,
+        },
+        {
+            .frequency = 2100 * FWK_MHZ,
+            .voltage = 400,
+        },
+        {
+            .frequency = 2600 * FWK_MHZ,
+            .voltage = 500,
+        },
+        { 0 }
+};
+
+static const struct mod_dvfs_domain_config cpu_group0 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP0),
+    .latency = 1200,
+    .sustained_idx = 2,
+    .opps = opps,
+};
+
+static const struct mod_dvfs_domain_config cpu_group1 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP1),
+    .latency = 1200,
+    .sustained_idx = 2,
+    .opps = opps,
+};
+
+static const struct fwk_element element_table[] = {
+    [0] = {
+        .name = "GROUP0",
+        .data = &cpu_group0,
+    },
+    [1] = {
+        .name = "GROUP1",
+        .data = &cpu_group1,
+    },
+    { 0 }
+};
+
+static const struct fwk_element *dvfs_get_element_table(fwk_id_t module_id)
+{
+    return element_table;
+}
+
+const struct fwk_module_config config_dvfs = {
+    .get_element_table = dvfs_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_log.c b/product/clark/scp_ramfw/config_log.c
new file mode 100644
index 0000000000000000000000000000000000000000..7ef1e530b5afad12beea094e37cbfbde588997c5
--- /dev/null
+++ b/product/clark/scp_ramfw/config_log.c
@@ -0,0 +1,58 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_banner.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_log.h>
+#include <mod_pl011.h>
+#include <scp_clark_mmap.h>
+
+/*
+ * PL011 module
+ */
+static const struct fwk_element pl011_element_desc_table[] = {
+    [0] = {
+        .name = "scp-uart1",
+        .data = &((struct mod_pl011_device_config) {
+            .reg_base = SCP_UART_BASE,
+            .baud_rate_bps = 115200,
+            .clock_rate_hz = 24 * FWK_MHZ,
+            .clock_id = FWK_ID_NONE_INIT,
+            }),
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *get_pl011_table(fwk_id_t module_id)
+{
+    return pl011_element_desc_table;
+}
+
+struct fwk_module_config config_pl011 = {
+    .get_element_table = get_pl011_table,
+};
+
+/*
+ * Log module
+ */
+static const struct mod_log_config log_data = {
+    .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0),
+    .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0),
+    .log_groups = MOD_LOG_GROUP_ERROR |
+                  MOD_LOG_GROUP_INFO |
+                  MOD_LOG_GROUP_WARNING |
+                  MOD_LOG_GROUP_DEBUG,
+    .banner = FWK_BANNER_SCP
+              FWK_BANNER_RAM_FIRMWARE
+              BUILD_VERSION_DESCRIBE_STRING "\n",
+};
+
+struct fwk_module_config config_log = {
+    .data = &log_data,
+};
diff --git a/product/clark/scp_ramfw/config_mhu2.c b/product/clark/scp_ramfw/config_mhu2.c
new file mode 100644
index 0000000000000000000000000000000000000000..e633121615f96ba7f227cd916bbcc0921d86822e
--- /dev/null
+++ b/product/clark/scp_ramfw/config_mhu2.c
@@ -0,0 +1,47 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <mod_mhu2.h>
+#include <scp_clark_irq.h>
+#include <scp_clark_mmap.h>
+#include <scp_clark_mhu.h>
+
+static const struct fwk_element mhu_element_table[] = {
+    [SCP_CLARK_MHU_DEVICE_IDX_SCP_AP_S_CLUS0] = {
+        .name = "MHU_SCP_AP_S",
+        .sub_element_count = 1,
+        .data = &((struct mod_mhu2_channel_config) {
+            .irq = MHU_AP_SEC_IRQ,
+            .recv = SCP_MHU_SCP_AP_RCV_S_CLUS0,
+            .send = SCP_MHU_SCP_AP_SND_S_CLUS0,
+            .channel = 0,
+        })
+    },
+    [SCP_CLARK_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0] = {
+        .name = "MHU_SCP_AP_NS",
+        .sub_element_count = 1,
+        .data = &((struct mod_mhu2_channel_config) {
+            .irq = MHU_AP_NONSEC_IRQ,
+            .recv = SCP_MHU_SCP_AP_RCV_NS_CLUS0,
+            .send = SCP_MHU_SCP_AP_SND_NS_CLUS0,
+            .channel = 0,
+        })
+    },
+    [SCP_CLARK_MHU_DEVICE_IDX_COUNT] = { 0 },
+};
+
+static const struct fwk_element *mhu_get_element_table(fwk_id_t module_id)
+{
+    return mhu_element_table;
+}
+
+const struct fwk_module_config config_mhu2 = {
+    .get_element_table = mhu_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_mock_psu.c b/product/clark/scp_ramfw/config_mock_psu.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c72b9ad704543e3ad377b0e8c12173a2a8d58aa
--- /dev/null
+++ b/product/clark/scp_ramfw/config_mock_psu.c
@@ -0,0 +1,39 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <mod_mock_psu.h>
+
+static const struct fwk_element element_table[] = {
+    {
+        .name = "DVFS_GROUP0",
+        .data =
+            &(const struct mod_mock_psu_device_config){
+                .default_enabled = true,
+                .default_voltage = 100,
+            },
+    },
+    {
+        .name = "DVFS_GROUP1",
+        .data =
+            &(const struct mod_mock_psu_device_config){
+                .default_enabled = true,
+                .default_voltage = 100,
+            },
+    },
+    { 0 }
+};
+
+static const struct fwk_element *get_element_table(fwk_id_t module_id)
+{
+    return element_table;
+}
+
+const struct fwk_module_config config_mock_psu = {
+    .get_element_table = get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_pik_clock.c b/product/clark/scp_ramfw/config_pik_clock.c
new file mode 100644
index 0000000000000000000000000000000000000000..227678262c2987ce491ad3bfa8580bbb885a501f
--- /dev/null
+++ b/product/clark/scp_ramfw/config_pik_clock.c
@@ -0,0 +1,298 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <mod_pik_clock.h>
+#include <clark_pik_system.h>
+#include <scp_clark_pik.h>
+#include <system_clock.h>
+#include <config_clock.h>
+
+/*
+ * Rate lookup tables
+ */
+
+static struct mod_pik_clock_rate rate_table_cpu_group_0[] = {
+    {
+        .rate = 2600 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .divider = 1, /* Rate adjusted via CPU PLL */
+    },
+};
+
+static struct mod_pik_clock_rate rate_table_cpu_group_1[] = {
+    {
+        .rate = 2600 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .divider = 1, /* Rate adjusted via CPU PLL */
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_sys_intclk[] = {
+    {
+        .rate = 2000 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_INTCLK_SOURCE_INTPLL,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .divider = 1,
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_sys_dmcclk[] = {
+    {
+        .rate = 1600 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_DMCCLK_SOURCE_DDRPLL,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .divider = 1,
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_scp[] = {
+    {
+        .rate = 250 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS,
+        .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ),
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_gicclk[] = {
+    {
+        .rate = 1000 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS,
+        .divider = CLOCK_RATE_SYSPLLCLK / (1000 * FWK_MHZ),
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_pclkscp[] = {
+    {
+        .rate = 400 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS,
+        .divider = CLOCK_RATE_SYSPLLCLK / (400 * FWK_MHZ),
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_sysperclk[] = {
+    {
+        .rate = 500 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS,
+        .divider = CLOCK_RATE_SYSPLLCLK / (500 * FWK_MHZ),
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_uartclk[] = {
+    {
+        .rate = 250 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS,
+        .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ),
+    },
+};
+
+static const struct fwk_element pik_clock_element_table[] = {
+    /*
+     * Cluster 0 CPUS
+     */
+    [CLOCK_PIK_IDX_CLUS0_CPU0] = {
+        .name = "CLUS0_CPU0",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[0].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[0].MOD,
+            .rate_table = rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU1] = {
+        .name = "CLUS0_CPU1",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[1].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[1].MOD,
+            .rate_table = rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU2] = {
+        .name = "CLUS0_CPU2",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[2].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[2].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[2].MOD,
+            .rate_table = rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU3] = {
+        .name = "CLUS0_CPU3",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[3].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[3].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[3].MOD,
+            .rate_table = rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU0] = {
+        .name = "CLUS1_CPU0",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[0].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[0].MOD,
+            .rate_table = rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU1] = {
+        .name = "CLUS1_CPU1",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[1].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[1].MOD,
+            .rate_table = rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU2] = {
+        .name = "CLUS1_CPU2",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[2].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[2].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[2].MOD,
+            .rate_table = rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU3] = {
+        .name = "CLUS1_CPU3",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[3].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[3].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[3].MOD,
+            .rate_table = rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_DMC] = {
+        .name = "DMC",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->DMCCLK_CTRL,
+            .divext_reg = &PIK_SYSTEM->DMCCLK_DIV1,
+            .rate_table = rate_table_sys_dmcclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_sys_dmcclk),
+            .initial_rate = 1600 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_INTERCONNECT] = {
+        .name = "INTERCONNECT",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->INTCLK_CTRL,
+            .divext_reg = &PIK_SYSTEM->INTCLK_DIV1,
+            .rate_table = rate_table_sys_intclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_sys_intclk),
+            .initial_rate = 2000 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_SCP] = {
+        .name = "SCP",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SCP->CORECLK_CTRL,
+            .divsys_reg = &PIK_SCP->CORECLK_DIV1,
+            .rate_table = rate_table_scp,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_scp),
+            .initial_rate = 250 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_GIC] = {
+        .name = "GIC",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->GICCLK_CTRL,
+            .divsys_reg = &PIK_SYSTEM->GICCLK_DIV1,
+            .rate_table = rate_table_gicclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk),
+            .initial_rate = 1000 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_PCLKSCP] = {
+        .name = "PCLKSCP",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->PCLKSCP_CTRL,
+            .divsys_reg = &PIK_SYSTEM->PCLKSCP_DIV1,
+            .rate_table = rate_table_pclkscp,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp),
+            .initial_rate = 400 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_SYSPERCLK] = {
+        .name = "SYSPERCLK",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->SYSPERCLK_CTRL,
+            .divsys_reg = &PIK_SYSTEM->SYSPERCLK_DIV1,
+            .rate_table = rate_table_sysperclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk),
+            .initial_rate = 500 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_UARTCLK] = {
+        .name = "UARTCLK",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->UARTCLK_CTRL,
+            .divsys_reg = &PIK_SYSTEM->UARTCLK_DIV1,
+            .rate_table = rate_table_uartclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk),
+            .initial_rate = 250 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *pik_clock_get_element_table
+    (fwk_id_t module_id)
+{
+    return pik_clock_element_table;
+}
+
+const struct fwk_module_config config_pik_clock = {
+    .get_element_table = pik_clock_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_power_domain.c b/product/clark/scp_ramfw/config_power_domain.c
new file mode 100644
index 0000000000000000000000000000000000000000..647bc2c5f7924ac7ce51aa3476e7d90d91e2ae83
--- /dev/null
+++ b/product/clark/scp_ramfw/config_power_domain.c
@@ -0,0 +1,213 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <fwk_element.h>
+#include <fwk_macros.h>
+#include <fwk_mm.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_system_power.h>
+#include <mod_power_domain.h>
+#include <mod_ppu_v1.h>
+#include <clark_power_domain.h>
+#include <clark_core.h>
+#include <config_ppu_v0.h>
+#include <config_power_domain.h>
+
+/* Maximum power domain name size including the null terminator */
+#define PD_NAME_SIZE 12
+
+/* Mask of the allowed states for the systop power domain */
+static const uint32_t systop_allowed_state_mask_table[] = {
+    [0] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK |
+          (1 << MOD_SYSTEM_POWER_POWER_STATE_SLEEP0) |
+          (1 << MOD_SYSTEM_POWER_POWER_STATE_SLEEP1)
+};
+
+/*
+ * Mask of the allowed states for the top level power domains
+ * (but the cluster power domains) depending on the system states.
+ */
+static const uint32_t toplevel_allowed_state_mask_table[] = {
+    [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK,
+    [MOD_PD_STATE_ON] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK,
+    [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK,
+    [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK
+};
+
+/*
+ * Mask of the allowed states for the cluster power domain depending on the
+ * system states.
+ */
+static const uint32_t cluster_pd_allowed_state_mask_table[] = {
+    [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK,
+    [MOD_PD_STATE_ON] = CLARK_CLUSTER_VALID_STATE_MASK,
+    [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK,
+    [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK
+};
+
+/* Mask of the allowed states for a core depending on the cluster states. */
+static const uint32_t core_pd_allowed_state_mask_table[] = {
+    [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK,
+    [MOD_PD_STATE_ON] = CLARK_CORE_VALID_STATE_MASK,
+    [MOD_PD_STATE_SLEEP] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK,
+    [CLARK_POWER_DOMAIN_STATE_FUNC_RET] = CLARK_CORE_VALID_STATE_MASK,
+    [CLARK_POWER_DOMAIN_STATE_MEM_RET] = MOD_PD_STATE_OFF_MASK
+};
+
+/* Power module specific configuration data (none) */
+static const struct mod_power_domain_config
+    clark_power_domain_config = { 0 };
+
+static struct fwk_element clark_power_domain_static_element_table[] = {
+    [PD_STATIC_DEV_IDX_CLUSTER0] = {
+        .name = "CLUS0",
+        .data = &((struct mod_power_domain_element_config) {
+            .attributes.pd_type = MOD_PD_TYPE_CLUSTER,
+            .tree_pos = MOD_PD_TREE_POS(
+                MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER0, 0),
+            .api_id = FWK_ID_API_INIT(
+                FWK_MODULE_IDX_PPU_V1,
+                MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER),
+            .allowed_state_mask_table = cluster_pd_allowed_state_mask_table,
+            .allowed_state_mask_table_size =
+                FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table)
+        }),
+    },
+    [PD_STATIC_DEV_IDX_CLUSTER1] = {
+        .name = "CLUS1",
+        .data = &((struct mod_power_domain_element_config) {
+            .attributes.pd_type = MOD_PD_TYPE_CLUSTER,
+            .tree_pos = MOD_PD_TREE_POS(
+                MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER1, 0),
+            .api_id = FWK_ID_API_INIT(
+                FWK_MODULE_IDX_PPU_V1,
+                MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER),
+            .allowed_state_mask_table = cluster_pd_allowed_state_mask_table,
+            .allowed_state_mask_table_size =
+                FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table)
+        }),
+    },
+    [PD_STATIC_DEV_IDX_DBGTOP] = {
+        .name = "DBGTOP",
+        .data = &((struct mod_power_domain_element_config) {
+            .attributes.pd_type = MOD_PD_TYPE_DEVICE_DEBUG,
+            .tree_pos = MOD_PD_TREE_POS(
+                MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_DBGTOP, 0),
+            .driver_id = FWK_ID_ELEMENT_INIT(
+                FWK_MODULE_IDX_PPU_V0, PPU_V0_ELEMENT_IDX_DBGTOP),
+            .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V0, 0),
+            .allowed_state_mask_table = toplevel_allowed_state_mask_table,
+            .allowed_state_mask_table_size =
+                FWK_ARRAY_SIZE(toplevel_allowed_state_mask_table)
+        }),
+    },
+    [PD_STATIC_DEV_IDX_SYSTOP] = {
+        .name = "SYSTOP",
+        .data = &((struct mod_power_domain_element_config) {
+            .attributes.pd_type = MOD_PD_TYPE_SYSTEM,
+            .tree_pos = MOD_PD_TREE_POS(
+                MOD_PD_LEVEL_2, 0, 0, 0, 0),
+            .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER),
+            .api_id = FWK_ID_API_INIT(
+                FWK_MODULE_IDX_SYSTEM_POWER,
+                MOD_SYSTEM_POWER_API_IDX_PD_DRIVER),
+            .allowed_state_mask_table = systop_allowed_state_mask_table,
+            .allowed_state_mask_table_size =
+                FWK_ARRAY_SIZE(systop_allowed_state_mask_table)
+        }),
+    },
+};
+
+/*
+ * Function definitions with internal linkage
+ */
+static const struct fwk_element *clark_power_domain_get_element_table
+    (fwk_id_t module_id)
+{
+    struct fwk_element *element_table, *element;
+    struct mod_power_domain_element_config *pd_config_table, *pd_config;
+    unsigned int core_idx;
+    unsigned int cluster_idx;
+    unsigned int core_count;
+    unsigned int cluster_count;
+    unsigned int core_element_count = 0;
+
+    core_count = clark_core_get_core_count();
+    cluster_count = clark_core_get_cluster_count();
+
+    element_table = fwk_mm_calloc(
+        core_count
+        + FWK_ARRAY_SIZE(clark_power_domain_static_element_table)
+        + 1, /* Terminator */
+        sizeof(struct fwk_element));
+    if (element_table == NULL)
+        return NULL;
+
+    pd_config_table = fwk_mm_calloc(core_count,
+        sizeof(struct mod_power_domain_element_config));
+    if (pd_config_table == NULL)
+        return NULL;
+
+    for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) {
+        for (core_idx = 0;
+             core_idx < clark_core_get_core_per_cluster_count(cluster_idx);
+             core_idx++) {
+
+            element = &element_table[core_element_count];
+            pd_config = &pd_config_table[core_element_count];
+
+            element->name = fwk_mm_alloc(PD_NAME_SIZE, 1);
+            if (element->name == NULL)
+                return NULL;
+
+            snprintf((char *)element->name, PD_NAME_SIZE, "CLUS%uCORE%u",
+                cluster_idx, core_idx);
+
+            element->data = pd_config;
+
+            pd_config->attributes.pd_type = MOD_PD_TYPE_CORE;
+            pd_config->tree_pos = MOD_PD_TREE_POS(
+                MOD_PD_LEVEL_0, 0, 0, cluster_idx, core_idx);
+            pd_config->driver_id =
+                FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1,
+                               core_element_count);
+            pd_config->api_id = FWK_ID_API(
+                FWK_MODULE_IDX_PPU_V1,
+                MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER);
+            pd_config->allowed_state_mask_table =
+                core_pd_allowed_state_mask_table;
+            pd_config->allowed_state_mask_table_size =
+                FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table);
+            core_element_count++;
+        }
+
+        /* Define the driver id for the cluster */
+        pd_config = (struct mod_power_domain_element_config *)
+            clark_power_domain_static_element_table[cluster_idx].data;
+        pd_config->driver_id =
+            FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1,
+                           (core_count + cluster_idx));
+    }
+
+    memcpy(element_table + core_count,
+           clark_power_domain_static_element_table,
+           sizeof(clark_power_domain_static_element_table));
+
+    return element_table;
+}
+
+/*
+ * Power module configuration data
+ */
+const struct fwk_module_config config_power_domain = {
+    .get_element_table = clark_power_domain_get_element_table,
+    .data = &clark_power_domain_config,
+};
diff --git a/product/clark/scp_ramfw/config_power_domain.h b/product/clark/scp_ramfw/config_power_domain.h
new file mode 100644
index 0000000000000000000000000000000000000000..c71ae55ac7137169828e19e6f90dd5a4e1501bee
--- /dev/null
+++ b/product/clark/scp_ramfw/config_power_domain.h
@@ -0,0 +1,27 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONFIG_POWER_DOMAIN_H
+#define CONFIG_POWER_DOMAIN_H
+
+/*
+ * Power domain indices for the statically defined domains used for:
+ * - Indexing the domains in the clark_power_domain_static_element_table
+ * - Indexing the SYSTOP children in the power domain tree
+ *
+ * When calculating a power domain element index, use the formula:
+ * core_count + pd_static_dev_idx
+ */
+enum pd_static_dev_idx {
+    PD_STATIC_DEV_IDX_CLUSTER0,
+    PD_STATIC_DEV_IDX_CLUSTER1,
+    PD_STATIC_DEV_IDX_DBGTOP,
+    PD_STATIC_DEV_IDX_SYSTOP,
+    PD_STATIC_DEV_IDX_COUNT
+};
+
+#endif /* CONFIG_POWER_DOMAIN_H */
diff --git a/product/clark/scp_ramfw/config_ppu_v0.c b/product/clark/scp_ramfw/config_ppu_v0.c
new file mode 100644
index 0000000000000000000000000000000000000000..c2426fc2094e246fd390929ff36f03958281a865
--- /dev/null
+++ b/product/clark/scp_ramfw/config_ppu_v0.c
@@ -0,0 +1,37 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <mod_ppu_v0.h>
+#include <config_ppu_v0.h>
+#include <scp_clark_irq.h>
+#include <scp_clark_mmap.h>
+
+static struct fwk_element ppu_v0_element_table[] = {
+    [PPU_V0_ELEMENT_IDX_DBGTOP] = {
+        .name = "DBGTOP",
+        .data = &((struct mod_ppu_v0_pd_config) {
+            .pd_type = MOD_PD_TYPE_DEVICE_DEBUG,
+            .ppu.reg_base = SCP_PPU_DEBUG_BASE,
+        }),
+    },
+    [PPU_V0_ELEMENT_IDX_COUNT] = { 0 }, /* Termination entry */
+};
+
+
+static const struct fwk_element *ppu_v0_get_element_table(fwk_id_t module_id)
+{
+    return ppu_v0_element_table;
+}
+
+/*
+ * Power module configuration data
+ */
+const struct fwk_module_config config_ppu_v0 = {
+    .get_element_table = ppu_v0_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_ppu_v0.h b/product/clark/scp_ramfw/config_ppu_v0.h
new file mode 100644
index 0000000000000000000000000000000000000000..7858b2b11a05542a2924104aa56a72e3d4020f65
--- /dev/null
+++ b/product/clark/scp_ramfw/config_ppu_v0.h
@@ -0,0 +1,16 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONFIG_PPU_V0_H
+#define CONFIG_PPU_V0_H
+
+enum ppu_v0_element_idx {
+    PPU_V0_ELEMENT_IDX_DBGTOP,
+    PPU_V0_ELEMENT_IDX_COUNT
+};
+
+#endif /* CONFIG_PPU_V0_H */
diff --git a/product/clark/scp_ramfw/config_ppu_v1.c b/product/clark/scp_ramfw/config_ppu_v1.c
new file mode 100644
index 0000000000000000000000000000000000000000..e12831b834c643330f06f6b04932750899adba63
--- /dev/null
+++ b/product/clark/scp_ramfw/config_ppu_v1.c
@@ -0,0 +1,161 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include <stdio.h>
+#include <fwk_assert.h>
+#include <fwk_element.h>
+#include <fwk_macros.h>
+#include <fwk_mm.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_cmn600.h>
+#include <mod_power_domain.h>
+#include <mod_ppu_v1.h>
+#include <clark_core.h>
+#include <scp_clark_irq.h>
+#include <scp_clark_mmap.h>
+#include <config_power_domain.h>
+
+/* Maximum PPU core name size including the null terminator */
+#define PPU_CORE_NAME_SIZE 12
+
+/* Maximum PPU cluster name size including the null terminator */
+#define PPU_CLUS_NAME_SIZE 6
+
+/* Lookup table for translating cluster indicies into CMN600 node IDs */
+static const unsigned int cluster_idx_to_node_id[] = {76, 32};
+
+/* Module configuration data */
+static struct mod_ppu_v1_config ppu_v1_config_data = {
+    .pd_notification_id = FWK_ID_NOTIFICATION_INIT(
+        FWK_MODULE_IDX_POWER_DOMAIN,
+        MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION),
+};
+
+static struct fwk_element ppu_v1_system_element_table[] = {
+    [0] = {
+        .name = "SYS0",
+        .data = &((struct mod_ppu_v1_pd_config) {
+            .pd_type = MOD_PD_TYPE_SYSTEM,
+            .ppu.reg_base = SCP_PPU_SYS0_BASE,
+            .observer_id = FWK_ID_NONE_INIT,
+        }),
+    },
+    [1] = {
+        .name = "SYS1",
+        .data = &((struct mod_ppu_v1_pd_config) {
+            .pd_type = MOD_PD_TYPE_SYSTEM,
+            .ppu.reg_base = SCP_PPU_SYS1_BASE,
+            .observer_id = FWK_ID_NONE_INIT,
+        }),
+    },
+};
+
+static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id)
+{
+    struct fwk_element *element_table, *element;
+    struct mod_ppu_v1_pd_config *pd_config_table, *pd_config;
+    unsigned int core_idx;
+    unsigned int cluster_idx;
+    unsigned int core_count;
+    unsigned int cluster_count;
+    unsigned int core_element_count = 0;
+
+    core_count = clark_core_get_core_count();
+    cluster_count = clark_core_get_cluster_count();
+
+    assert(cluster_count == FWK_ARRAY_SIZE(cluster_idx_to_node_id));
+
+    /*
+     * Allocate element descriptors based on:
+     *   Number of cores
+     *   + Number of cluster descriptors
+     *   + Number of system power domain descriptors
+     *   + 1 terminator descriptor
+     */
+    element_table = fwk_mm_calloc(core_count + cluster_count +
+        FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1,
+        sizeof(struct fwk_element));
+    if (element_table == NULL)
+        return NULL;
+
+    pd_config_table = fwk_mm_calloc(core_count + cluster_count,
+                                    sizeof(struct mod_ppu_v1_pd_config));
+    if (pd_config_table == NULL)
+        return NULL;
+
+    for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) {
+        for (core_idx = 0;
+             core_idx < clark_core_get_core_per_cluster_count(cluster_idx);
+             core_idx++) {
+            element = &element_table[core_element_count];
+            pd_config = &pd_config_table[core_element_count];
+
+            element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1);
+            if (element->name == NULL)
+                return NULL;
+
+            snprintf((char *)element->name, PPU_CORE_NAME_SIZE, "CLUS%uCORE%u",
+                cluster_idx, core_idx);
+
+            element->data = pd_config;
+
+            pd_config->pd_type = MOD_PD_TYPE_CORE;
+            pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(cluster_idx, core_idx);
+            pd_config->ppu.irq = FWK_INTERRUPT_NONE;
+            pd_config->cluster_id =
+                FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1,
+                               (core_count + cluster_idx));
+            pd_config->observer_id = FWK_ID_NONE;
+            core_element_count++;
+        }
+
+        element = &element_table[core_count + cluster_idx];
+        pd_config = &pd_config_table[core_count + cluster_idx];
+
+        element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1);
+        if (element->name == NULL)
+            return NULL;
+
+        snprintf((char *)element->name, PPU_CLUS_NAME_SIZE, "CLUS%u",
+            cluster_idx);
+
+        element->data = pd_config;
+
+        pd_config->pd_type = MOD_PD_TYPE_CLUSTER;
+        pd_config->ppu.reg_base = SCP_PPU_CLUSTER_BASE(cluster_idx);
+        pd_config->ppu.irq = FWK_INTERRUPT_NONE;
+        pd_config->observer_id = fwk_module_id_cmn600;
+        pd_config->observer_api = FWK_ID_API(FWK_MODULE_IDX_CMN600,
+                                             MOD_CMN600_API_IDX_PPU_OBSERVER);
+        pd_config->post_ppu_on_param =
+            (void *)&cluster_idx_to_node_id[cluster_idx];
+    }
+
+    memcpy(&element_table[core_count + cluster_count],
+           ppu_v1_system_element_table,
+           sizeof(ppu_v1_system_element_table));
+
+    /*
+     * Configure pd_source_id with the SYSTOP identifier from the power domain
+     * module which is dynamically defined based on the number of cores.
+     */
+    ppu_v1_config_data.pd_source_id = fwk_id_build_element_id(
+        fwk_module_id_power_domain,
+        core_count + PD_STATIC_DEV_IDX_SYSTOP);
+
+    return element_table;
+}
+
+/*
+ * Power module configuration data
+ */
+const struct fwk_module_config config_ppu_v1 = {
+    .get_element_table = ppu_v1_get_element_table,
+    .data = &ppu_v1_config_data,
+};
diff --git a/product/clark/scp_ramfw/config_psu.c b/product/clark/scp_ramfw/config_psu.c
new file mode 100644
index 0000000000000000000000000000000000000000..8c5740e5d189d94901de5bed9aeb969156bfcd08
--- /dev/null
+++ b/product/clark/scp_ramfw/config_psu.c
@@ -0,0 +1,41 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_mock_psu.h>
+#include <mod_psu.h>
+
+static const struct fwk_element element_table[] = {
+    {
+        .name = "DVFS_GROUP0",
+        .data = &(const struct mod_psu_device_config) {
+            .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 0),
+            .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MOCK_PSU,
+                                             MOD_MOCK_PSU_API_IDX_PSU_DRIVER)
+        },
+    },
+    {
+        .name = "DVFS_GROUP1",
+        .data = &(const struct mod_psu_device_config){
+            .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 1),
+            .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MOCK_PSU,
+                                             MOD_MOCK_PSU_API_IDX_PSU_DRIVER)
+        },
+    },
+    { 0 }
+};
+
+static const struct fwk_element *psu_get_element_table(fwk_id_t module_id)
+{
+    return element_table;
+}
+
+const struct fwk_module_config config_psu = {
+    .get_element_table = psu_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_scmi.c b/product/clark/scp_ramfw/config_scmi.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e836838706055936b59b0a776eed615322dad7e
--- /dev/null
+++ b/product/clark/scp_ramfw/config_scmi.c
@@ -0,0 +1,71 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <scp_clark_scmi.h>
+#include <mod_scmi.h>
+#include <internal/scmi.h>
+#include <mod_smt.h>
+
+static const struct fwk_element service_table[] = {
+    [SCP_CLARK_SCMI_SERVICE_IDX_PSCI] = {
+        .name = "SERVICE0",
+        .data = &((struct mod_scmi_service_config) {
+            .transport_id = FWK_ID_ELEMENT_INIT(
+                FWK_MODULE_IDX_SMT,
+                SCP_CLARK_SCMI_SERVICE_IDX_PSCI),
+            .transport_api_id = FWK_ID_API_INIT(
+                FWK_MODULE_IDX_SMT,
+                MOD_SMT_API_IDX_SCMI_TRANSPORT),
+            .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI,
+        }),
+    },
+    [SCP_CLARK_SCMI_SERVICE_IDX_OSPM] = {
+        .name = "SERVICE1",
+        .data = &((struct mod_scmi_service_config) {
+            .transport_id = FWK_ID_ELEMENT_INIT(
+                FWK_MODULE_IDX_SMT,
+                SCP_CLARK_SCMI_SERVICE_IDX_OSPM),
+            .transport_api_id = FWK_ID_API_INIT(
+                FWK_MODULE_IDX_SMT,
+                MOD_SMT_API_IDX_SCMI_TRANSPORT),
+            .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM,
+        }),
+    },
+    [SCP_CLARK_SCMI_SERVICE_IDX_COUNT] = { 0 }
+};
+
+static const struct fwk_element *get_service_table(fwk_id_t module_id)
+{
+    return service_table;
+}
+
+static struct mod_scmi_agent agent_table[] = {
+    [SCP_SCMI_AGENT_ID_OSPM] = {
+        .type = SCMI_AGENT_TYPE_OSPM,
+        .name = "OSPM",
+    },
+    [SCP_SCMI_AGENT_ID_PSCI] = {
+        .type = SCMI_AGENT_TYPE_PSCI,
+        .name = "PSCI",
+    },
+};
+
+const struct fwk_module_config config_scmi = {
+    .get_element_table = get_service_table,
+    .data = &((struct mod_scmi_config) {
+        .protocol_count_max = 9,
+        .agent_count = FWK_ARRAY_SIZE(agent_table) - 1,
+        .agent_table = agent_table,
+        .vendor_identifier = "arm",
+        .sub_vendor_identifier = "arm",
+    }),
+};
diff --git a/product/clark/scp_ramfw/config_scmi_apcore.c b/product/clark/scp_ramfw/config_scmi_apcore.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c24de77051f93bbc130bdb35f4bf77da7603dc4
--- /dev/null
+++ b/product/clark/scp_ramfw/config_scmi_apcore.c
@@ -0,0 +1,31 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <clark_core.h>
+#include <scp_clark_pik.h>
+#include <mod_scmi_apcore.h>
+#include <fwk_element.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+
+static const struct mod_scmi_apcore_reset_register_group
+    reset_reg_group_table[] = {
+        {
+            .base_register =
+                (uintptr_t)&PIK_CLUSTER(0)->STATIC_CONFIG[0].RVBARADDR_LW,
+            .register_count = CLARK_CORE_PER_CLUSTER_MAX,
+        },
+    };
+
+const struct fwk_module_config config_scmi_apcore = {
+    .data = &((struct mod_scmi_apcore_config){
+        .reset_register_width = MOD_SCMI_APCORE_REG_WIDTH_64,
+        .reset_register_group_count =
+            FWK_ARRAY_SIZE(reset_reg_group_table),
+        .reset_register_group_table = &reset_reg_group_table[0],
+    }),
+};
diff --git a/product/clark/scp_ramfw/config_scmi_perf.c b/product/clark/scp_ramfw/config_scmi_perf.c
new file mode 100644
index 0000000000000000000000000000000000000000..fa4d82a6f8db4b9b058ad43c7975f287f0cbc52f
--- /dev/null
+++ b/product/clark/scp_ramfw/config_scmi_perf.c
@@ -0,0 +1,36 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <scp_clark_scmi.h>
+#include <mod_scmi_perf.h>
+
+static const struct mod_scmi_perf_domain_config domains[] = {
+    [0] = {
+        .permissions = &(const uint32_t[]) {
+            [SCP_SCMI_AGENT_ID_OSPM] = MOD_SCMI_PERF_PERMS_SET_LEVEL  |
+                                       MOD_SCMI_PERF_PERMS_SET_LIMITS,
+            [SCP_SCMI_AGENT_ID_PSCI] = MOD_SCMI_PERF_PERMS_NONE,
+        }
+    },
+    [1] = {
+        .permissions = &(const uint32_t[]) {
+            [SCP_SCMI_AGENT_ID_OSPM] = MOD_SCMI_PERF_PERMS_SET_LEVEL  |
+                                       MOD_SCMI_PERF_PERMS_SET_LIMITS,
+            [SCP_SCMI_AGENT_ID_PSCI] = MOD_SCMI_PERF_PERMS_NONE,
+        }
+    },
+};
+
+const struct fwk_module_config config_scmi_perf = {
+    .get_element_table = NULL,
+    .data = &((struct mod_scmi_perf_config) {
+        .domains = &domains,
+    }),
+};
diff --git a/product/clark/scp_ramfw/config_scmi_system_power.c b/product/clark/scp_ramfw/config_scmi_system_power.c
new file mode 100644
index 0000000000000000000000000000000000000000..a405c6f0c464bc5ea195ba200f590907aea8fb1c
--- /dev/null
+++ b/product/clark/scp_ramfw/config_scmi_system_power.c
@@ -0,0 +1,17 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_module.h>
+#include <mod_scmi_system_power.h>
+#include <mod_system_power.h>
+
+const struct fwk_module_config config_scmi_system_power = {
+    .data = &((struct mod_scmi_system_power_config) {
+        .system_view = MOD_SCMI_SYSTEM_VIEW_FULL,
+        .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0
+    }),
+};
diff --git a/product/clark/scp_ramfw/config_sds.c b/product/clark/scp_ramfw/config_sds.c
new file mode 100644
index 0000000000000000000000000000000000000000..e2dd29e8b9a40141ce6fe738560dc593f1fe4d5a
--- /dev/null
+++ b/product/clark/scp_ramfw/config_sds.c
@@ -0,0 +1,104 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <fwk_assert.h>
+#include <fwk_element.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_sds.h>
+#include <mod_sid.h>
+#include <clark_sds.h>
+#include <scp_clark_mmap.h>
+#include <scp_clark_pik.h>
+#include <scp_software_mmap.h>
+#include <scp_system_mmap.h>
+#include <config_clock.h>
+
+static const uint32_t version_packed = FWK_BUILD_VERSION;
+static const uint32_t feature_flags = (CLARK_SDS_FEATURE_FIRMWARE_MASK |
+                                       CLARK_SDS_FEATURE_DMC_MASK |
+                                       CLARK_SDS_FEATURE_MESSAGING_MASK);
+
+const struct mod_sds_config sds_module_config = {
+    .region_base_address = SCP_SDS_MEM_BASE,
+    .region_size = SCP_SDS_MEM_SIZE,
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        CLOCK_IDX_INTERCONNECT)
+};
+
+static struct fwk_element sds_element_table[] = {
+    {
+        .name = "CPU Info",
+        .data = &((struct mod_sds_structure_desc) {
+            .id = CLARK_SDS_CPU_INFO,
+            .size = CLARK_SDS_CPU_INFO_SIZE,
+            .finalize = true,
+        }),
+    },
+    {
+        .name = "Firmware version",
+        .data = &((struct mod_sds_structure_desc) {
+            .id = CLARK_SDS_FIRMWARE_VERSION,
+            .size = CLARK_SDS_FIRMWARE_VERSION_SIZE,
+            .payload = &version_packed,
+            .finalize = true,
+        }),
+    },
+    {
+        .name = "Reset Syndrome",
+        .data = &((struct mod_sds_structure_desc) {
+            .id = CLARK_SDS_RESET_SYNDROME,
+            .size = CLARK_SDS_RESET_SYNDROME_SIZE,
+            .payload = (void *)(&PIK_SCP->RESET_SYNDROME),
+            .finalize = true,
+        }),
+    },
+    {
+        .name = "Feature Availability",
+        .data = &((struct mod_sds_structure_desc) {
+            .id = CLARK_SDS_FEATURE_AVAILABILITY,
+            .size = CLARK_SDS_FEATURE_AVAILABILITY_SIZE,
+            .payload = &feature_flags,
+            .finalize = true,
+        }),
+    },
+#ifdef MODE_DEBUG
+    {
+        .name = "Boot Counters",
+        .data = &((struct mod_sds_structure_desc) {
+            .id = CLARK_SDS_CPU_BOOTCTR,
+            .size = CLARK_SDS_CPU_BOOTCTR_SIZE,
+            .finalize = true,
+        }),
+    },
+    {
+        .name = "CPU Flags",
+        .data = &((struct mod_sds_structure_desc) {
+            .id = CLARK_SDS_CPU_FLAGS,
+            .size = CLARK_SDS_CPU_FLAGS_SIZE,
+            .finalize = true,
+        }),
+    },
+#endif
+    { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *sds_get_element_table(fwk_id_t module_id)
+{
+    static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size");
+    static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size");
+    static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size");
+
+    return sds_element_table;
+}
+
+struct fwk_module_config config_sds = {
+    .get_element_table = sds_get_element_table,
+    .data = &sds_module_config,
+};
diff --git a/product/clark/scp_ramfw/config_sensor.c b/product/clark/scp_ramfw/config_sensor.c
new file mode 100644
index 0000000000000000000000000000000000000000..5f47b8c42aa9ea9507bd16a186203ad964477db0
--- /dev/null
+++ b/product/clark/scp_ramfw/config_sensor.c
@@ -0,0 +1,72 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_reg_sensor.h>
+#include <mod_sensor.h>
+#include <scp_system_mmap.h>
+
+enum REG_SENSOR_DEVICES {
+    REG_SENSOR_DEV_SOC_TEMP,
+    REG_SENSOR_DEV_COUNT,
+};
+
+/*
+ * Register Sensor driver config
+ */
+static const struct fwk_element reg_sensor_element_table[] = {
+    [REG_SENSOR_DEV_SOC_TEMP] = {
+        .name = "Soc Temperature",
+        .data = &((struct mod_reg_sensor_dev_config) {
+            .reg = (uintptr_t)(SCP_SENSOR_SOC_TEMP),
+        }),
+    },
+    [REG_SENSOR_DEV_COUNT] = { 0 },
+};
+
+static const struct fwk_element *get_reg_sensor_element_table(fwk_id_t id)
+{
+    return reg_sensor_element_table;
+}
+
+struct fwk_module_config config_reg_sensor = {
+    .get_element_table = get_reg_sensor_element_table,
+};
+
+
+/*
+ * Sensor module config
+ */
+static const struct mod_sensor_dev_config soctemp_config = {
+    .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_REG_SENSOR,
+                                     REG_SENSOR_DEV_SOC_TEMP),
+    .info = &((struct mod_sensor_info) {
+        .type = MOD_SENSOR_TYPE_DEGREES_C,
+        .update_interval = 0,
+        .update_interval_multiplier = 0,
+        .unit_multiplier = 0,
+    }),
+};
+
+static const struct fwk_element sensor_element_table[] = {
+    [0] = {
+        .name = "Soc Temperature",
+        .data = &soctemp_config,
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *get_sensor_element_table(fwk_id_t module_id)
+{
+    return sensor_element_table;
+}
+
+const struct fwk_module_config config_sensor = {
+    .get_element_table = get_sensor_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_smt.c b/product/clark/scp_ramfw/config_smt.c
new file mode 100644
index 0000000000000000000000000000000000000000..9ea86a2572efae9d68e66b4d76b60cc37a79ea67
--- /dev/null
+++ b/product/clark/scp_ramfw/config_smt.c
@@ -0,0 +1,64 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_smt.h>
+#include <clark_core.h>
+#include <scp_clark_mhu.h>
+#include <scp_clark_scmi.h>
+#include <scp_software_mmap.h>
+#include <config_power_domain.h>
+
+static const struct fwk_element smt_element_table[] = {
+    [SCP_CLARK_SCMI_SERVICE_IDX_PSCI] = {
+        .name = "PSCI",
+        .data = &((struct mod_smt_channel_config) {
+            .type = MOD_SMT_CHANNEL_TYPE_SLAVE,
+            .policies = MOD_SMT_POLICY_INIT_MAILBOX | MOD_SMT_POLICY_SECURE,
+            .mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_S_A2P_BASE,
+            .mailbox_size = SCP_SCMI_PAYLOAD_SIZE,
+            .driver_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_MHU2,
+                SCP_CLARK_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, 0),
+            .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0),
+        })
+    },
+    [SCP_CLARK_SCMI_SERVICE_IDX_OSPM] = {
+        .name = "OSPM",
+        .data = &((struct mod_smt_channel_config) {
+            .type = MOD_SMT_CHANNEL_TYPE_SLAVE,
+            .policies = MOD_SMT_POLICY_INIT_MAILBOX,
+            .mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_NS_A2P_BASE,
+            .mailbox_size = SCP_SCMI_PAYLOAD_SIZE,
+            .driver_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_MHU2,
+                 SCP_CLARK_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0, 0),
+            .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0),
+        })
+    },
+    [SCP_CLARK_SCMI_SERVICE_IDX_COUNT] = { 0 },
+};
+
+static const struct fwk_element *smt_get_element_table(fwk_id_t module_id)
+{
+    unsigned int idx;
+    struct mod_smt_channel_config *config;
+
+    for (idx = 0; idx < SCP_CLARK_SCMI_SERVICE_IDX_COUNT; idx++) {
+        config = (struct mod_smt_channel_config *)(smt_element_table[idx].data);
+        config->pd_source_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN,
+            clark_core_get_core_count() + PD_STATIC_DEV_IDX_SYSTOP);
+    }
+
+    return smt_element_table;
+}
+
+const struct fwk_module_config config_smt = {
+    .get_element_table = smt_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_system_pll.c b/product/clark/scp_ramfw/config_system_pll.c
new file mode 100644
index 0000000000000000000000000000000000000000..fb0df7d4160a0a73de380cec218dd80219a10a82
--- /dev/null
+++ b/product/clark/scp_ramfw/config_system_pll.c
@@ -0,0 +1,90 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <mod_system_pll.h>
+#include <clark_pik_scp.h>
+#include <scp_clark_pik.h>
+#include <scp_system_mmap.h>
+#include <config_clock.h>
+
+static const struct fwk_element system_pll_element_table[] = {
+    [CLOCK_PLL_IDX_CPU0] = {
+        .name = "CPU_PLL_0",
+        .data = &((struct mod_system_pll_dev_config) {
+            .control_reg = (void *)SCP_PLL_CPU0,
+            .status_reg = (void *)&PIK_SCP->PLL_STATUS[1],
+            .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0),
+            .initial_rate = 2600 * FWK_MHZ,
+            .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+            .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+            .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+        }),
+    },
+    [CLOCK_PLL_IDX_CPU1] = {
+        .name = "CPU_PLL_1",
+        .data = &((struct mod_system_pll_dev_config) {
+            .control_reg = (void *)SCP_PLL_CPU1,
+            .status_reg = (void *)&PIK_SCP->PLL_STATUS[1],
+            .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(1),
+            .initial_rate = 2600 * FWK_MHZ,
+            .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+            .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+            .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+        }),
+    },
+    [CLOCK_PLL_IDX_SYS] = {
+        .name = "SYS_PLL",
+        .data = &((struct mod_system_pll_dev_config) {
+            .control_reg = (void *)SCP_PLL_SYSPLL,
+            .status_reg = (void *)&PIK_SCP->PLL_STATUS[0],
+            .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK,
+            .initial_rate = 2000 * FWK_MHZ,
+            .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+            .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+            .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+        }),
+    },
+    [CLOCK_PLL_IDX_DMC] = {
+        .name = "DMC_PLL",
+        .data = &((struct mod_system_pll_dev_config) {
+            .control_reg = (void *)SCP_PLL_DMC,
+            .status_reg = (void *)&PIK_SCP->PLL_STATUS[0],
+            .lock_flag_mask = PLL_STATUS_0_DDRPLLLOCK,
+            .initial_rate = 1600 * FWK_MHZ,
+            .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+            .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+            .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+        }),
+    },
+    [CLOCK_PLL_IDX_INTERCONNECT] = {
+        .name = "INT_PLL",
+        .data = &((struct mod_system_pll_dev_config) {
+            .control_reg = (void *)SCP_PLL_INTERCONNECT,
+            .status_reg = (void *)&PIK_SCP->PLL_STATUS[0],
+            .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK,
+            .initial_rate = 2000 * FWK_MHZ,
+            .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+            .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+            .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+        }),
+    },
+    [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *system_pll_get_element_table
+    (fwk_id_t module_id)
+{
+    return system_pll_element_table;
+}
+
+const struct fwk_module_config config_system_pll = {
+    .get_element_table = system_pll_get_element_table,
+};
diff --git a/product/clark/scp_ramfw/config_system_power.c b/product/clark/scp_ramfw/config_system_power.c
new file mode 100644
index 0000000000000000000000000000000000000000..f82598850527b2e0734f091da7518632f3f50370
--- /dev/null
+++ b/product/clark/scp_ramfw/config_system_power.c
@@ -0,0 +1,58 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <scp_clark_irq.h>
+#include <mod_clark_system.h>
+#include <mod_system_power.h>
+#include <mod_ppu_v1.h>
+#include <clark_core.h>
+
+/* Table with only a terminator */
+static const struct fwk_element clark_system_element_table = { 0 };
+
+static struct mod_system_power_config system_power_config = {
+    .soc_wakeup_irq = SOC_WAKEUP0_IRQ,
+
+    /* PPU settings */
+    .ppu_sys_api_id = FWK_ID_API_INIT(
+        FWK_MODULE_IDX_PPU_V1,
+        MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER),
+
+    /* System driver */
+    .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_CLARK_SYSTEM),
+    .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CLARK_SYSTEM,
+         MOD_CLARK_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER),
+};
+
+static const struct fwk_element *clark_system_get_element_table(
+    fwk_id_t unused)
+{
+    /* The system PPUs are placed after the core and cluster PPUs */
+    unsigned int ppu_idx_base = clark_core_get_core_count() +
+                                clark_core_get_cluster_count();
+
+    /* Set the system PPU elements */
+    system_power_config.ppu_sys0_id = fwk_id_build_element_id(
+        fwk_module_id_ppu_v1, ppu_idx_base);
+    system_power_config.ppu_sys1_id = fwk_id_build_element_id(
+        fwk_module_id_ppu_v1, ppu_idx_base + 1);
+
+    /*
+     * Return table with only a terminator as this function is only used to
+     * setup the dynamic module data.
+     */
+    return &clark_system_element_table;
+}
+
+const struct fwk_module_config config_system_power = {
+    .get_element_table = clark_system_get_element_table,
+    .data = &system_power_config,
+};
diff --git a/product/clark/scp_ramfw/config_timer.c b/product/clark/scp_ramfw/config_timer.c
new file mode 100644
index 0000000000000000000000000000000000000000..cd4466426d14c2c219e3d697d39a0edf4ad22cb4
--- /dev/null
+++ b/product/clark/scp_ramfw/config_timer.c
@@ -0,0 +1,67 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_gtimer.h>
+#include <mod_timer.h>
+#include <scp_clark_irq.h>
+#include <scp_clark_mmap.h>
+#include <system_clock.h>
+#include <config_clock.h>
+
+/*
+ * Generic timer driver config
+ */
+static const struct fwk_element gtimer_dev_table[] = {
+    [0] = {
+        .name = "REFCLK",
+        .data = &((struct mod_gtimer_dev_config) {
+            .hw_timer   = SCP_REFCLK_CNTBASE0_BASE,
+            .hw_counter = SCP_REFCLK_CNTCTL_BASE,
+            .control    = SCP_REFCLK_CNTCONTROL_BASE,
+            .frequency  = CLOCK_RATE_REFCLK,
+            .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+                CLOCK_IDX_INTERCONNECT)
+        })
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *gtimer_get_dev_table(fwk_id_t module_id)
+{
+    return gtimer_dev_table;
+}
+
+const struct fwk_module_config config_gtimer = {
+    .get_element_table = gtimer_get_dev_table,
+};
+
+/*
+ * Timer HAL config
+ */
+static const struct fwk_element timer_dev_table[] = {
+    [0] = {
+        .name = "REFCLK",
+        .data = &((struct mod_timer_dev_config) {
+            .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0),
+            .timer_irq = TIMREFCLK_IRQ,
+        }),
+        .sub_element_count = 8, /* Number of alarms */
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id)
+{
+    return timer_dev_table;
+}
+
+const struct fwk_module_config config_timer = {
+    .get_element_table = timer_get_dev_table,
+};
diff --git a/product/clark/scp_ramfw/firmware.mk b/product/clark/scp_ramfw/firmware.mk
new file mode 100644
index 0000000000000000000000000000000000000000..8a678bbe05980025d26484b8943eced7d28ae8a1
--- /dev/null
+++ b/product/clark/scp_ramfw/firmware.mk
@@ -0,0 +1,80 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_FIRMWARE_CPU := cortex-m7
+BS_FIRMWARE_HAS_MULTITHREADING := yes
+BS_FIRMWARE_HAS_NOTIFICATION := yes
+BS_FIRMWARE_MODULE_HEADERS_ONLY :=
+
+BS_FIRMWARE_MODULES := \
+    armv7m_mpu \
+    sid \
+    pcid \
+    pl011 \
+    log \
+    cmn600 \
+    apcontext \
+    power_domain \
+    ppu_v0 \
+    ppu_v1 \
+    system_power \
+    dmc620 \
+    ddr_phy500 \
+    mhu2 \
+    smt \
+    scmi \
+    sds \
+    system_pll \
+    pik_clock \
+    css_clock \
+    clock \
+    gtimer \
+    timer \
+    sensor \
+    reg_sensor \
+    scmi_sensor \
+    scmi_power_domain \
+    scmi_system_power \
+    scmi_apcore \
+    mock_psu \
+    psu \
+    dvfs \
+    scmi_perf \
+    clark_system
+
+BS_FIRMWARE_SOURCES := \
+    config_system_power.c \
+    config_sid.c \
+    rtx_config.c \
+    clark_core.c \
+    config_armv7m_mpu.c \
+    config_log.c \
+    config_power_domain.c \
+    config_ppu_v0.c \
+    config_ppu_v1.c \
+    config_dmc620.c \
+    config_ddr_phy500.c \
+    config_mhu2.c \
+    config_smt.c \
+    config_scmi.c \
+    config_sds.c \
+    config_timer.c \
+    config_sensor.c \
+    config_cmn600.c \
+    config_scmi_system_power.c \
+    config_system_pll.c \
+    config_pik_clock.c \
+    config_css_clock.c \
+    config_clock.c \
+    config_mock_psu.c \
+    config_psu.c \
+    config_dvfs.c \
+    config_scmi_perf.c \
+    config_scmi_apcore.c \
+    config_apcontext.c
+
+include $(BS_DIR)/firmware.mk
diff --git a/product/clark/scp_ramfw/fmw_memory.ld.S b/product/clark/scp_ramfw/fmw_memory.ld.S
new file mode 100644
index 0000000000000000000000000000000000000000..c80bdd29f84a9754baf91c0e3d88c1b4bd67258c
--- /dev/null
+++ b/product/clark/scp_ramfw/fmw_memory.ld.S
@@ -0,0 +1,32 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     RAM firmware memory layout for the linker script.
+ */
+
+#ifndef FMW_MEMORY_LD_S
+#define FMW_MEMORY_LD_S
+
+#include <scp_system_mmap_scp.h>
+
+#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION
+
+/*
+ * RAM instruction memory
+ */
+#define FIRMWARE_MEM0_SIZE  SCP_RAM0_SIZE
+#define FIRMWARE_MEM0_BASE  SCP_RAM0_BASE
+
+/*
+ * RAM data memory
+ */
+#define FIRMWARE_MEM1_SIZE  SCP_RAM1_SIZE
+#define FIRMWARE_MEM1_BASE  SCP_RAM1_BASE
+
+#define FIRMWARE_STACK_SIZE (1 * 1024)
+
+#endif /* FMW_MEMORY_LD_S */
diff --git a/product/clark/scp_ramfw/rtx_config.c b/product/clark/scp_ramfw/rtx_config.c
new file mode 100644
index 0000000000000000000000000000000000000000..75f44c538dab520fb4da57d76714b399b2bd181d
--- /dev/null
+++ b/product/clark/scp_ramfw/rtx_config.c
@@ -0,0 +1,36 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <cmsis_compiler.h>
+#include <rtx_os.h>
+#include <system_clock.h>
+
+#include <rtx_lib.c>
+
+/*
+ * Required by RTX to configure the SysTick timer.
+ */
+uint32_t SystemCoreClock = CLOCK_RATE_REFCLK;
+
+/*
+ * Idle thread
+ */
+__NO_RETURN void osRtxIdleThread(void *argument)
+{
+    while (true)
+        __WFI();
+}
+
+/*
+ * OS error handler
+ */
+uint32_t osRtxErrorNotify(uint32_t code, void *object_id)
+{
+    osRtxIdleThread(object_id);
+}
diff --git a/product/clark/scp_romfw/config_clark_rom.c b/product/clark/scp_romfw/config_clark_rom.c
new file mode 100644
index 0000000000000000000000000000000000000000..d8ad330c84bfb33f19c920d14cfdafad6add7cb4
--- /dev/null
+++ b/product/clark/scp_romfw/config_clark_rom.c
@@ -0,0 +1,19 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_module.h>
+#include <mod_clark_rom.h>
+#include <scp_software_mmap.h>
+#include <scp_clark_mmap_scp.h>
+
+const struct fwk_module_config config_clark_rom = {
+    .data = &((struct clark_rom_config) {
+        .ramfw_base = SCP_RAM0_BASE,
+        .nor_base = SCP_NOR_BASE,
+        .load_ram_size = SCP_IMAGE_SIZE,
+    })
+};
diff --git a/product/clark/scp_romfw/config_clock.c b/product/clark/scp_romfw/config_clock.c
new file mode 100644
index 0000000000000000000000000000000000000000..a01a1d372d31f16b58a1ed93e66d4ba7724732eb
--- /dev/null
+++ b/product/clark/scp_romfw/config_clock.c
@@ -0,0 +1,12 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <mod_clock.h>
+
+const struct fwk_module_config config_clock = { 0 };
diff --git a/product/clark/scp_romfw/config_gtimer.c b/product/clark/scp_romfw/config_gtimer.c
new file mode 100644
index 0000000000000000000000000000000000000000..b14d57e37d4b4e3fe7f2ce40e037aac4cb672028
--- /dev/null
+++ b/product/clark/scp_romfw/config_gtimer.c
@@ -0,0 +1,38 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <mod_gtimer.h>
+#include <scp_clark_mmap.h>
+#include <system_clock.h>
+
+/*
+ * Generic timer driver config
+ */
+static const struct fwk_element gtimer_dev_table[] = {
+    [0] = {
+        .name = "REFCLK",
+        .data = &((struct mod_gtimer_dev_config) {
+            .hw_timer   = SCP_REFCLK_CNTBASE0_BASE,
+            .hw_counter = SCP_REFCLK_CNTCTL_BASE,
+            .control    = SCP_REFCLK_CNTCONTROL_BASE,
+            .frequency  = CLOCK_RATE_REFCLK,
+            .clock_id   = FWK_ID_NONE_INIT,
+        })
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *gtimer_get_dev_table(fwk_id_t module_id)
+{
+    return gtimer_dev_table;
+}
+
+const struct fwk_module_config config_gtimer = {
+    .get_element_table = gtimer_get_dev_table,
+};
diff --git a/product/clark/scp_romfw/config_log.c b/product/clark/scp_romfw/config_log.c
new file mode 100644
index 0000000000000000000000000000000000000000..eb59739ee3a43c438cb1d2c7604b5345ced1e36d
--- /dev/null
+++ b/product/clark/scp_romfw/config_log.c
@@ -0,0 +1,58 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_banner.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_log.h>
+#include <mod_pl011.h>
+#include <scp_system_mmap.h>
+
+/*
+ * PL011 module
+ */
+static const struct fwk_element pl011_element_desc_table[] = {
+    [0] = {
+        .name = "uart",
+        .data = &((struct mod_pl011_device_config) {
+            .reg_base = SCP_UART_BASE,
+            .baud_rate_bps = 115200,
+            .clock_rate_hz = 24 * FWK_MHZ,
+            .clock_id = FWK_ID_NONE_INIT,
+            }),
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *get_pl011_table(fwk_id_t module_id)
+{
+    return pl011_element_desc_table;
+}
+
+struct fwk_module_config config_pl011 = {
+    .get_element_table = get_pl011_table,
+};
+
+/*
+ * Log module
+ */
+static const struct mod_log_config log_data = {
+    .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0),
+    .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0),
+    .log_groups = MOD_LOG_GROUP_ERROR |
+                  MOD_LOG_GROUP_INFO |
+                  MOD_LOG_GROUP_WARNING |
+                  MOD_LOG_GROUP_DEBUG,
+    .banner = FWK_BANNER_SCP
+              FWK_BANNER_ROM_FIRMWARE
+              BUILD_VERSION_DESCRIBE_STRING "\n",
+};
+
+struct fwk_module_config config_log = {
+    .data = &log_data,
+};
diff --git a/product/clark/scp_romfw/firmware.mk b/product/clark/scp_romfw/firmware.mk
new file mode 100644
index 0000000000000000000000000000000000000000..134f51a2f6b0a188337d65307d8be316ae38bdd3
--- /dev/null
+++ b/product/clark/scp_romfw/firmware.mk
@@ -0,0 +1,31 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_FIRMWARE_CPU := cortex-m7
+BS_FIRMWARE_HAS_MULTITHREADING := no
+BS_FIRMWARE_HAS_NOTIFICATION := yes
+BS_FIRMWARE_MODULE_HEADERS_ONLY := \
+    power_domain \
+    timer
+
+BS_FIRMWARE_MODULES := \
+    sid \
+    pcid \
+    pl011 \
+    log \
+    clark_rom \
+    gtimer \
+    clock
+
+BS_FIRMWARE_SOURCES := \
+    config_sid.c \
+    config_log.c \
+    config_clark_rom.c \
+    config_gtimer.c \
+    config_clock.c
+
+include $(BS_DIR)/firmware.mk
diff --git a/product/clark/scp_romfw/fmw_memory.ld.S b/product/clark/scp_romfw/fmw_memory.ld.S
new file mode 100644
index 0000000000000000000000000000000000000000..6d3a33d38e7bb67a72e02daaf7f808689d1c34c2
--- /dev/null
+++ b/product/clark/scp_romfw/fmw_memory.ld.S
@@ -0,0 +1,32 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     ROM firmware memory layout for the linker script.
+ */
+
+#ifndef FMW_MEMORY_LD_S
+#define FMW_MEMORY_LD_S
+
+#include <scp_system_mmap_scp.h>
+
+#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION
+
+/*
+ * ROM memory
+ */
+#define FIRMWARE_MEM0_SIZE  SCP_ROM_SIZE
+#define FIRMWARE_MEM0_BASE  SCP_ROM_BASE
+
+/*
+ * RAM memory
+ */
+#define FIRMWARE_MEM1_SIZE  SCP_RAM1_SIZE
+#define FIRMWARE_MEM1_BASE  SCP_RAM1_BASE
+
+#define FIRMWARE_STACK_SIZE (1 * 1024)
+
+#endif /* FMW_MEMORY_LD_S */
diff --git a/product/clark/src/clark_core.c b/product/clark/src/clark_core.c
new file mode 100644
index 0000000000000000000000000000000000000000..84cf7b10cf09bcafef0addae1188ada563b8a619
--- /dev/null
+++ b/product/clark/src/clark_core.c
@@ -0,0 +1,31 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_assert.h>
+#include <clark_core.h>
+
+/* Clark only has one configuration, hence the constant values */
+
+#define CORES_PER_CLUSTER 4
+#define NUMBER_OF_CLUSTERS 2
+
+unsigned int clark_core_get_core_per_cluster_count(unsigned int cluster)
+{
+    assert(cluster < clark_core_get_cluster_count());
+
+    return CORES_PER_CLUSTER;
+}
+
+unsigned int clark_core_get_core_count(void)
+{
+    return NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER;
+}
+
+unsigned int clark_core_get_cluster_count(void)
+{
+    return NUMBER_OF_CLUSTERS;
+}
diff --git a/product/clark/src/config_sid.c b/product/clark/src/config_sid.c
new file mode 100644
index 0000000000000000000000000000000000000000..f59d9c138893b6ce4e92467f9676c1afd3f89ef5
--- /dev/null
+++ b/product/clark/src/config_sid.c
@@ -0,0 +1,50 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <mod_sid.h>
+#include <scp_clark_mmap.h>
+
+static const struct fwk_element subsystem_table[] = {
+    {
+        .name = "Clark",
+        .data = &(struct mod_sid_subsystem_config) {
+            .part_number = 0x786,
+        }
+    },
+    {
+        .name = "Christensen",
+        .data = &(struct mod_sid_subsystem_config) {
+            .part_number = 0x785,
+        }
+    },
+    { 0 },
+};
+
+static const struct fwk_element *get_subsystem_table(fwk_id_t id)
+{
+    return subsystem_table;
+}
+
+const struct fwk_module_config config_sid = {
+    .get_element_table = get_subsystem_table,
+    .data = &(struct mod_sid_config) {
+        .sid_base = SCP_SID_BASE,
+        .pcid_expected = {
+            .PID0 = 0xD2,
+            .PID1 = 0xB0,
+            .PID2 = 0x0B,
+            .PID3 = 0x00,
+            .PID4 = 0x04,
+            .CID0 = 0x0D,
+            .CID1 = 0xF0,
+            .CID2 = 0x05,
+            .CID3 = 0xB1,
+        },
+    },
+};
diff --git a/tools/ci.py b/tools/ci.py
index 807880bfd701ddafcae538741670f1ac815e68f3..380258f1f6542ed6549089fb1a4e9baf219b7744 100755
--- a/tools/ci.py
+++ b/tools/ci.py
@@ -170,6 +170,40 @@ def main():
     result = subprocess.call(cmd, shell=True)
     results.append(('Product n1sdp build (GCC)', result))
 
+    banner('Test building clark product')
+
+    cmd = \
+        'CC=arm-none-eabi-gcc ' \
+        'PRODUCT=clark ' \
+        'MODE=release ' \
+        'make clean all'
+    result = subprocess.call(cmd, shell=True)
+    results.append(('Product clark release build (GCC)', result))
+
+    cmd = \
+        'CC=armclang ' \
+        'PRODUCT=clark ' \
+        'MODE=release ' \
+        'make clean all'
+    result = subprocess.call(cmd, shell=True)
+    results.append(('Product clark release build (ARM)', result))
+
+    cmd = \
+        'CC=arm-none-eabi-gcc ' \
+        'PRODUCT=clark ' \
+        'MODE=debug ' \
+        'make clean all'
+    result = subprocess.call(cmd, shell=True)
+    results.append(('Product clark debug build (GCC)', result))
+
+    cmd = \
+        'CC=armclang ' \
+        'PRODUCT=clark ' \
+        'MODE=debug ' \
+        'make clean all'
+    result = subprocess.call(cmd, shell=True)
+    results.append(('Product clark debug build (ARM)', result))
+
     banner('Tests summary')
 
     total_success = 0