diff --git a/product/n1sdp/include/n1sdp_scp_mmap.h b/product/n1sdp/include/n1sdp_scp_mmap.h index 7ceb73e251581af584bfda5079d08f711a94c59a..cd458a3a48172081ed4184f646a790830fbe0cd3 100644 --- a/product/n1sdp/include/n1sdp_scp_mmap.h +++ b/product/n1sdp/include/n1sdp_scp_mmap.h @@ -32,6 +32,10 @@ #define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000) #define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000) #define SCP_WDOG_BASE (SCP_PERIPHERAL_BASE + 0x6000) + +/* + * CoreSight control base + */ #define SCP_CS_CNTCONTROL_BASE (SCP_PERIPHERAL_BASE + 0xA000) /* diff --git a/product/n1sdp/include/n1sdp_ssc.h b/product/n1sdp/include/n1sdp_ssc.h new file mode 100644 index 0000000000000000000000000000000000000000..cebbfc32f0cdf1806c09bcba1ca67d556205e0a8 --- /dev/null +++ b/product/n1sdp/include/n1sdp_ssc.h @@ -0,0 +1,44 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef N1SDP_SSC_H +#define N1SDP_SSC_H + +#include +#include +#include + +/*! + * \brief System Security Control (SSC) register definitions + */ +struct ssc_reg { + uint8_t RESERVED1[0x10 - 0x0]; + FWK_R uint32_t SSC_DBGCFG_STAT; + FWK_W uint32_t SSC_DBGCFG_SET; + FWK_W uint32_t SSC_DBGCFG_CLR; + uint8_t RESERVED2[0x28 - 0x1C]; + FWK_RW uint32_t SSC_AUXDBGCFG; + uint8_t RESERVED3[0x30 - 0x2C]; + FWK_RW uint32_t SSC_GPRETN; + uint8_t RESERVED4[0x40 - 0x34]; + FWK_R uint32_t SSC_VERSION; + uint8_t RESERVED5[0xFD0 - 0x44]; + FWK_R uint32_t PID4; + uint8_t RESERVED6[0xFE0 - 0xFD4]; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t COMPID0; + FWK_R uint32_t COMPID1; + FWK_R uint32_t COMPID2; + FWK_R uint32_t COMPID3; +}; + +#define SSC ((struct ssc_reg *)SCP_SSC_BASE) + +#endif /* N1SDP_SSC_H */ diff --git a/product/n1sdp/mcp_ramfw/config_log.c b/product/n1sdp/mcp_ramfw/config_log.c index 072f67a39edabc3913442ded763a46ed056751b0..e8bd4d1ac9c587cc2d66ef78fbdef6e62b2f8edb 100644 --- a/product/n1sdp/mcp_ramfw/config_log.c +++ b/product/n1sdp/mcp_ramfw/config_log.c @@ -22,7 +22,7 @@ static const struct fwk_element pl011_element_desc_table[] = { .name = "MCP-UART", .data = &((struct mod_pl011_device_config) { .reg_base = MCP_UART0_BASE, - .baud_rate_bps = 38400, + .baud_rate_bps = BAUD_RATE_19200, .clock_rate_hz = CLOCK_RATE_REFCLK, .clock_id = FWK_ID_NONE_INIT, }), diff --git a/product/n1sdp/module/n1sdp_system/include/mod_n1sdp_system.h b/product/n1sdp/module/n1sdp_system/include/mod_n1sdp_system.h index bd56147f00fecba9209a5fc349bcb0aaa08ddcd0..1830132d447e763c7889d25d20cfb9632951130d 100644 --- a/product/n1sdp/module/n1sdp_system/include/mod_n1sdp_system.h +++ b/product/n1sdp/module/n1sdp_system/include/mod_n1sdp_system.h @@ -31,10 +31,15 @@ * firmware to internal/external memory and set the RVBAR register of the * AP cores to corresponding memory's base address and then switch ON * the PPU of primary core to release from reset. This macro specifies the - * base address of the memory (DDR) to which AP firmware will be copied to - * and therefore the value to set in the RVBAR of all AP cores. + * base address of the Trusted AP SRAM to which AP firmware will be copied + * to and therefore the value to set in the RVBAR of all AP cores. */ -#define AP_CPU_RESET_ADDR UINT64_C(0xFF000000) + +/*! Offset of the Trusted SRAM between AP and SCP Address Space*/ +#define AP_SCP_SRAM_OFFSET UINT32_C(0xA0000000) + +/*! AP Cores Reset Address in SCP Address Space */ +#define AP_CORE_RESET_ADDR UINT64_C(0xA4040000) /*! DDR Base address where AP BL33 (UEFI) will be copied to. */ #define AP_BL33_BASE_ADDR UINT64_C(0xE0000000) @@ -46,7 +51,7 @@ * Number of bits to shift in AP's memory map address to map to SCP's * 1MB window. */ -#define SCP_AP_1MB_WINDOW_ADDR_SHIFT 20 +#define SCP_AP_1MB_WINDOW_ADDR_SHIFT 20 /*! * \brief API indices. diff --git a/product/n1sdp/module/n1sdp_system/src/mod_n1sdp_system.c b/product/n1sdp/module/n1sdp_system/src/mod_n1sdp_system.c index 6f5375d7537ff32ade481d910a16d5c5d45ca4a8..6f9d82565bd383faca78b81e0371b2be8c9af509 100644 --- a/product/n1sdp/module/n1sdp_system/src/mod_n1sdp_system.c +++ b/product/n1sdp/module/n1sdp_system/src/mod_n1sdp_system.c @@ -30,8 +30,19 @@ #include #include #include +#include #include +/* Coresight counter register definitions */ +struct cs_cnt_ctrl_reg { + FWK_RW uint32_t CS_CNTCR; + FWK_R uint32_t CS_CNTSR; + FWK_RW uint32_t CS_CNTCVLW; + FWK_RW uint32_t CS_CNTCVUP; +}; + +#define CS_CNTCONTROL ((struct cs_cnt_ctrl_reg *)SCP_CS_CNTCONTROL_BASE) + /* Module context */ struct n1sdp_system_ctx { @@ -157,9 +168,35 @@ struct mod_n1sdp_system_ap_memory_access_api .disable_ap_memory_access = n1sdp_system_disable_ap_memory_access, }; -static int n1sdp_system_copy_to_ap_memory(uint64_t dram_address, - uint32_t spi_address, - uint32_t size) +/* + * Function to copy into AP SRAM. + */ +static int n1sdp_system_copy_to_ap_sram(uint64_t sram_address, + uint32_t spi_address, + uint32_t size) +{ + uint32_t target_addr = (uint32_t)sram_address; + + memcpy((void *)target_addr, (void *)spi_address, size); + + if (memcmp((void *)target_addr, (void *)spi_address, size) != 0) { + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_INFO, + "[N1SDP SYSTEM] Copy failed at destination address: 0x%08x\n", + target_addr); + return FWK_E_DATA; + } + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_INFO, + "[N1SDP SYSTEM] Copied binary to SRAM address: 0x%08x\n", + sram_address); + return FWK_SUCCESS; +} + +/* + * Function to copy into DRAM location + */ +static int n1sdp_system_copy_to_ap_ddr(uint64_t dram_address, + uint32_t spi_address, + uint32_t size) { uint32_t scp_address = 0; uint32_t copy_size = 0; @@ -179,9 +216,9 @@ static int n1sdp_system_copy_to_ap_memory(uint64_t dram_address, /* Get the size for this copy operation. */ if (size > (SCP_AP_1MB_WINDOW_SIZE - addr_offset)) { /* - * If the copy operation will wrap around the end of the 1MB window - * we need to cut it off at the wrap around point and change the - * the window address. + * If the copy operation will wrap around the end of the + * 1MB window we need to cut it off at the wrap around + * point and change the window address. */ copy_size = (uint32_t)(SCP_AP_1MB_WINDOW_SIZE - addr_offset); } else { @@ -213,6 +250,29 @@ exit: return status; } +void cdbg_pwrupreq_handler(void) +{ + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_INFO, + "[N1SDP SYSTEM] Received debug power up request interrupt\n"); + + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_INFO, + "[N1SDP SYSTEM] Power on Debug PIK\n"); + + /* Clear interrupt */ + PIK_DEBUG->DEBUG_CTRL |= (0x1 << 1); + fwk_interrupt_disable(CDBG_PWR_UP_REQ_IRQ); +} + +void csys_pwrupreq_handler(void) +{ + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_INFO, + "[N1SDP SYSTEM] Received system power up request interrupt\n"); + + /* Clear interrupt */ + PIK_DEBUG->DEBUG_CTRL |= (0x1 << 2); + fwk_interrupt_disable(CSYS_PWR_UP_REQ_IRQ); +} + /* * Functions fulfilling the framework's module interface */ @@ -290,6 +350,32 @@ static int n1sdp_system_start(fwk_id_t id) if (status != FWK_SUCCESS) return status; + status = fwk_interrupt_set_isr(CDBG_PWR_UP_REQ_IRQ, cdbg_pwrupreq_handler); + if (status == FWK_SUCCESS) { + fwk_interrupt_enable(CDBG_PWR_UP_REQ_IRQ); + + status = fwk_interrupt_set_isr(CSYS_PWR_UP_REQ_IRQ, + csys_pwrupreq_handler); + if (status == FWK_SUCCESS) { + fwk_interrupt_enable(CSYS_PWR_UP_REQ_IRQ); + + PIK_CLUSTER(0)->CLKFORCE_SET = 0x00000004; + PIK_CLUSTER(1)->CLKFORCE_SET = 0x00000004; + + /* Enable debugger access in SSC */ + SSC->SSC_DBGCFG_SET = 0x000000FF; + + /* Setup CoreSight counter */ + CS_CNTCONTROL->CS_CNTCR |= (1 << 0); + CS_CNTCONTROL->CS_CNTCVLW = 0x00000000; + CS_CNTCONTROL->CS_CNTCVUP = 0x0000FFFF; + } else + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_DEBUG, + "[N1SDP SYSTEM] CSYS PWR UP REQ IRQ register failed\n"); + } else + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_DEBUG, + "[N1SDP SYSTEM] CDBG PWR UP REQ IRQ register failed\n"); + n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_DEBUG, "[N1SDP SYSTEM] Requesting SYSTOP initialization...\n"); @@ -366,9 +452,9 @@ static int n1sdp_system_process_notification(const struct fwk_event *event, n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_INFO, "[N1SDP SYSTEM] Copying AP BL31 to address 0x%x...\n", - AP_CPU_RESET_ADDR); + AP_CORE_RESET_ADDR); - status = n1sdp_system_copy_to_ap_memory(AP_CPU_RESET_ADDR, + status = n1sdp_system_copy_to_ap_sram(AP_CORE_RESET_ADDR, fip_desc_table[fip_index_bl31].address, fip_desc_table[fip_index_bl31].size); if (status != FWK_SUCCESS) @@ -378,7 +464,7 @@ static int n1sdp_system_process_notification(const struct fwk_event *event, "[N1SDP SYSTEM] Copying AP BL33 to address 0x%x...\n", AP_BL33_BASE_ADDR); - status = n1sdp_system_copy_to_ap_memory(AP_BL33_BASE_ADDR, + status = n1sdp_system_copy_to_ap_ddr(AP_BL33_BASE_ADDR, fip_desc_table[fip_index_bl33].address, fip_desc_table[fip_index_bl33].size); if (status != FWK_SUCCESS) @@ -388,17 +474,18 @@ static int n1sdp_system_process_notification(const struct fwk_event *event, n1sdp_system_ctx.log_api->log(MOD_LOG_GROUP_INFO, "[N1SDP SYSTEM] Setting AP Reset Address to 0x%x\n", - AP_CPU_RESET_ADDR); + AP_CORE_RESET_ADDR); cluster_count = n1sdp_core_get_cluster_count(); for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { for (core_idx = 0; - core_idx < n1sdp_core_get_core_per_cluster_count(cluster_idx); - core_idx++) { + core_idx < n1sdp_core_get_core_per_cluster_count(cluster_idx); + core_idx++) { PIK_CLUSTER(cluster_idx)->STATIC_CONFIG[core_idx].RVBARADDR_LW - = (uint32_t)(AP_CPU_RESET_ADDR); + = (uint32_t)(AP_CORE_RESET_ADDR - AP_SCP_SRAM_OFFSET); PIK_CLUSTER(cluster_idx)->STATIC_CONFIG[core_idx].RVBARADDR_UP - = (uint32_t)(AP_CPU_RESET_ADDR >> 32); + = (uint32_t) + ((AP_CORE_RESET_ADDR - AP_SCP_SRAM_OFFSET) >> 32); } } diff --git a/product/n1sdp/scp_ramfw/config_armv7m_mpu.c b/product/n1sdp/scp_ramfw/config_armv7m_mpu.c index 84a92d5fed9f5bcfce5edf6afe15a1b1c1f6b0e7..4149b1971a4cc297f5b95da6f40670e0778a279b 100644 --- a/product/n1sdp/scp_ramfw/config_armv7m_mpu.c +++ b/product/n1sdp/scp_ramfw/config_armv7m_mpu.c @@ -27,20 +27,20 @@ static const ARM_MPU_Region_t regions[] = { .RASR = ARM_MPU_RASR( 1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB), }, - { /* 0xA400_0000 - 0xA400_0FFF*/ + { /* 0xA400_0000 - 0xA407_FFFF*/ .RBAR = ARM_MPU_RBAR(3, SCP_TRUSTED_RAM_BASE), .RASR = ARM_MPU_RASR( - 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_4KB), + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB), }, { /* 0x6540_0000 - 0x6540_00FF */ .RBAR = ARM_MPU_RBAR(4, SCP_AP_SHARED_SECURE_RAM), .RASR = ARM_MPU_RASR( 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B), }, - { /* 0x6520_0000 - 0x6520_00FF */ + { /* 0x6520_0000 - 0x6520_FFFF */ .RBAR = ARM_MPU_RBAR(5, SCP_AP_SHARED_NONSECURE_RAM), .RASR = ARM_MPU_RASR( - 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B), + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB), }, }; diff --git a/product/n1sdp/scp_ramfw/config_log.c b/product/n1sdp/scp_ramfw/config_log.c index 9e71cc7a1e96cdd3a4bccbc4fe26b936633d4d9e..e01a91836a415a2b0d59a67862167a925d591ec5 100644 --- a/product/n1sdp/scp_ramfw/config_log.c +++ b/product/n1sdp/scp_ramfw/config_log.c @@ -22,7 +22,7 @@ static const struct fwk_element pl011_element_desc_table[] = { .name = "SCP-UART", .data = &((struct mod_pl011_device_config) { .reg_base = SCP_UART_BASE, - .baud_rate_bps = 38400, + .baud_rate_bps = BAUD_RATE_19200, .clock_rate_hz = CLOCK_RATE_REFCLK, .clock_id = FWK_ID_NONE_INIT, }), diff --git a/product/n1sdp/scp_ramfw/config_ppu_v0.c b/product/n1sdp/scp_ramfw/config_ppu_v0.c index 02612010ab7f5e311eb5ef80fb0615cf9fad8d81..8ae80ef0bd9d13054d60603bfd1ce4e0552e1aaa 100644 --- a/product/n1sdp/scp_ramfw/config_ppu_v0.c +++ b/product/n1sdp/scp_ramfw/config_ppu_v0.c @@ -18,6 +18,7 @@ static struct fwk_element ppu_v0_element_table[] = { .data = &((struct mod_ppu_v0_pd_config) { .pd_type = MOD_PD_TYPE_DEVICE_DEBUG, .ppu.reg_base = SCP_PPU_DEBUG_BASE, + .default_power_on = true, }), }, [PPU_V0_ELEMENT_IDX_COUNT] = { 0 }, /* Termination entry */