diff --git a/module/pik_clock/src/mod_pik_clock.c b/module/pik_clock/src/mod_pik_clock.c index a812d12881480f280de4d8a316c97f3bfd3ea0ad..136f314dd628291739443f892af7507f145d2498 100644 --- a/module/pik_clock/src/mod_pik_clock.c +++ b/module/pik_clock/src/mod_pik_clock.c @@ -554,6 +554,7 @@ static const struct mod_clock_drv_api api_clock = { * Direct driver API functions */ +#if BUILD_HAS_MOD_CSS_CLOCK static int pik_clock_direct_set_div(fwk_id_t clock_id, uint32_t divider_type, uint32_t divider) { @@ -656,6 +657,7 @@ static const struct mod_css_clock_direct_api api_direct = { .set_mod = pik_clock_direct_set_mod, .process_power_transition = pik_clock_direct_power_state_change, }; +#endif /* * Framework handler functions diff --git a/product/n1sdp/include/n1sdp_mcp_irq.h b/product/n1sdp/include/n1sdp_mcp_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..2416cf4032951400eb4a9d5e49efdedd8e5283ee --- /dev/null +++ b/product/n1sdp/include/n1sdp_mcp_irq.h @@ -0,0 +1,271 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef N1SDP_MCP_IRQ_H +#define N1SDP_MCP_IRQ_H + +#include + +#define MCP_WDOG_IRQ FWK_INTERRUPT_NMI /* MCP Watchdog (SP805) */ + +enum mcp_n1sdp_interrupt { + RESERVED0_IRQ = 0, /* Reserved */ + CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */ + CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */ + CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */ + GIC_EXT_WAKEUP_IRQ = 4, /* External GIC Wakeup Request */ + RESERVED5_IRQ = 5, /* Reserved */ + RESERVED6_IRQ = 6, /* Reserved */ + RESERVED7_IRQ = 7, /* Reserved */ + RESERVED8_IRQ = 8, /* Reserved */ + RESERVED9_IRQ = 9, /* Reserved */ + RESERVED10_IRQ = 10, /* Reserved */ + RESERVED11_IRQ = 11, /* Reserved */ + RESERVED12_IRQ = 12, /* Reserved */ + RESERVED13_IRQ = 13, /* Reserved */ + RESERVED14_IRQ = 14, /* Reserved */ + RESERVED15_IRQ = 15, /* Reserved */ + MCP_EXT_IRQ = 16, /* MCP External IRQ */ + GPIO_COMBINED_IRQ = 17, /* GPIO Combined IRQ */ + GPIO_0_IRQ = 18, /* GPIO 0 IRQ */ + GPIO_1_IRQ = 19, /* GPIO 1 IRQ */ + GPIO_2_IRQ = 20, /* GPIO 2 IRQ */ + GPIO_3_IRQ = 21, /* GPIO 3 IRQ */ + GPIO_4_IRQ = 22, /* GPIO 4 IRQ */ + GPIO_5_IRQ = 23, /* GPIO 5 IRQ */ + GPIO_6_IRQ = 24, /* GPIO 6 IRQ */ + GPIO_7_IRQ = 25, /* GPIO 7 IRQ */ + RESERVED26_IRQ = 26, /* Reserved */ + RESERVED27_IRQ = 27, /* Reserved */ + RESERVED28_IRQ = 28, /* Reserved */ + RESERVED29_IRQ = 29, /* Reserved */ + RESERVED30_IRQ = 30, /* Reserved */ + RESERVED31_IRQ = 31, /* Reserved */ + RESERVED32_IRQ = 32, /* Reserved */ + TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + MHU_AP_NONSEC_IRQ = 34, /* MHU non-secure irq from AP to + MCP */ + RESERVED35_IRQ = 35, /* Reserved */ + MHU_AP_SEC_IRQ = 36, /* MHU secure irq from AP to MCP */ + CTI_TRIGGER0_IRQ = 37, /* MCP CTI0 Trigger */ + CTI_TRIGGER1_IRQ = 38, /* MCP CTI1 Trigger */ + RESERVED39_IRQ = 39, /* Reserved */ + RESERVED40_IRQ = 40, /* Reserved */ + RESERVED41_IRQ = 41, /* Reserved */ + MCP_UART0_IRQ = 42, /* MCP UART0 */ + MCP_UART1_IRQ = 43, /* MCP UART1 */ + RESERVED44_IRQ = 44, /* Reserved */ + RESERVED45_IRQ = 45, /* Reserved */ + RESERVED46_IRQ = 46, /* Reserved */ + RESERVED47_IRQ = 47, /* Reserved */ + RESERVED48_IRQ = 48, /* Reserved */ + RESERVED49_IRQ = 49, /* Reserved */ + RESERVED50_IRQ = 50, /* Reserved */ + RESERVED51_IRQ = 51, /* Reserved */ + RESERVED52_IRQ = 52, /* Reserved */ + RESERVED53_IRQ = 53, /* Reserved */ + RESERVED54_IRQ = 54, /* Reserved */ + RESERVED55_IRQ = 55, /* Reserved */ + RESERVED56_IRQ = 56, /* Reserved */ + RESERVED57_IRQ = 57, /* Reserved */ + RESERVED58_IRQ = 58, /* Reserved */ + RESERVED59_IRQ = 59, /* Reserved */ + RESERVED60_IRQ = 60, /* Reserved */ + RESERVED61_IRQ = 61, /* Reserved */ + RESERVED62_IRQ = 62, /* Reserved */ + RESERVED63_IRQ = 63, /* Reserved */ + RESERVED64_IRQ = 64, /* Reserved */ + RESERVED65_IRQ = 65, /* Reserved */ + RESERVED66_IRQ = 66, /* Reserved */ + RESERVED67_IRQ = 67, /* Reserved */ + RESERVED68_IRQ = 68, /* Reserved */ + RESERVED69_IRQ = 69, /* Reserved */ + RESERVED70_IRQ = 70, /* Reserved */ + RESERVED71_IRQ = 71, /* Reserved */ + RESERVED72_IRQ = 72, /* Reserved */ + RESERVED73_IRQ = 73, /* Reserved */ + RESERVED74_IRQ = 74, /* Reserved */ + RESERVED75_IRQ = 75, /* Reserved */ + RESERVED76_IRQ = 76, /* Reserved */ + RESERVED77_IRQ = 77, /* Reserved */ + RESERVED78_IRQ = 78, /* Reserved */ + RESERVED79_IRQ = 79, /* Reserved */ + RESERVED80_IRQ = 80, /* Reserved */ + RESERVED81_IRQ = 81, /* Reserved */ + RESERVED82_IRQ = 82, /* Reserved */ + RESERVED83_IRQ = 83, /* Reserved */ + MHU_SCP_NONSEC_IRQ = 84, /* MHU non-secure irq from SCP to + MCP */ + MHU_SCP_SEC_IRQ = 85, /* MHU secure irq from SCP to MCP */ + RESERVED86_IRQ = 86, /* Reserved */ + RESERVED87_IRQ = 87, /* Reserved */ + RESERVED88_IRQ = 88, /* Reserved */ + RESERVED89_IRQ = 89, /* Reserved */ + RESERVED90_IRQ = 90, /* Reserved */ + RESERVED91_IRQ = 91, /* Reserved */ + RESERVED92_IRQ = 92, /* Reserved */ + RESERVED93_IRQ = 93, /* Reserved */ + MMU_TCU_RASIRPT_IRQ = 94, /* Consolidated MMU RAS */ + MMU_TBU_RASIRPT_IRQ = 95, /* Consolidated TBU RAS */ + INT_PPU_IRQ = 96, /* PPU interrupt from Interconnect + PPU */ + INT_ERRNS_IRQ = 97, /* Non-Sec error interrupt from + Interconnect PPU */ + INT_ERRS_IRQ = 98, /* Secure error interrupt from + Interconnect PPU */ + INT_FAULTS_IRQ = 99, /* Secure fault interrupt from + Interconnect PPU */ + INT_FAULTNS_IRQ = 100, /* Non-Sec fault interrupt from + Interconnect PPU */ + PMU_CNT_OVF_IRQ = 101, /* PMU count overflow irq */ + RESERVED102_IRQ = 102, /* Reserved */ + RESERVED103_IRQ = 103, /* Reserved */ + RESERVED104_IRQ = 104, /* Reserved */ + RESERVED105_IRQ = 105, /* Reserved */ + RESERVED106_IRQ = 106, /* Reserved */ + RESERVED107_IRQ = 107, /* Reserved */ + RESERVED108_IRQ = 108, /* Reserved */ + RESERVED109_IRQ = 109, /* Reserved */ + RESERVED110_IRQ = 110, /* Reserved */ + RESERVED111_IRQ = 111, /* Reserved */ + RESERVED112_IRQ = 112, /* Reserved */ + RESERVED113_IRQ = 113, /* Reserved */ + RESERVED114_IRQ = 114, /* Reserved */ + RESERVED115_IRQ = 115, /* Reserved */ + RESERVED116_IRQ = 116, /* Reserved */ + RESERVED117_IRQ = 117, /* Reserved */ + RESERVED118_IRQ = 118, /* Reserved */ + RESERVED119_IRQ = 119, /* Reserved */ + RESERVED120_IRQ = 120, /* Reserved */ + RESERVED121_IRQ = 121, /* Reserved */ + RESERVED122_IRQ = 122, /* Reserved */ + RESERVED123_IRQ = 123, /* Reserved */ + RESERVED124_IRQ = 124, /* Reserved */ + RESERVED125_IRQ = 125, /* Reserved */ + RESERVED126_IRQ = 126, /* Reserved */ + RESERVED127_IRQ = 127, /* Reserved */ + RESERVED128_IRQ = 128, /* Reserved */ + RESERVED129_IRQ = 129, /* Reserved */ + RESERVED130_IRQ = 130, /* Reserved */ + RESERVED131_IRQ = 131, /* Reserved */ + RESERVED132_IRQ = 132, /* Reserved */ + RESERVED133_IRQ = 133, /* Reserved */ + RESERVED134_IRQ = 134, /* Reserved */ + RESERVED135_IRQ = 135, /* Reserved */ + RESERVED136_IRQ = 136, /* Reserved */ + RESERVED137_IRQ = 137, /* Reserved */ + RESERVED138_IRQ = 138, /* Reserved */ + MCP_WD_WS1_IRQ = 139, /* MCP watchdog reset */ + RESERVED140_IRQ = 140, /* Reserved */ + RESERVED141_IRQ = 141, /* Reserved */ + RESERVED142_IRQ = 142, /* Reserved */ + RESERVED143_IRQ = 143, /* Reserved */ + RESERVED144_IRQ = 144, /* Reserved */ + RESERVED145_IRQ = 145, /* Reserved */ + RESERVED146_IRQ = 146, /* Reserved */ + RESERVED147_IRQ = 147, /* Reserved */ + RESERVED148_IRQ = 148, /* Reserved */ + RESERVED149_IRQ = 149, /* Reserved */ + RESERVED150_IRQ = 150, /* Reserved */ + RESERVED151_IRQ = 151, /* Reserved */ + RESERVED152_IRQ = 152, /* Reserved */ + RESERVED153_IRQ = 153, /* Reserved */ + RESERVED154_IRQ = 154, /* Reserved */ + RESERVED155_IRQ = 155, /* Reserved */ + RESERVED156_IRQ = 156, /* Reserved */ + RESERVED157_IRQ = 157, /* Reserved */ + RESERVED158_IRQ = 158, /* Reserved */ + RESERVED159_IRQ = 159, /* Reserved */ + RESERVED160_IRQ = 160, /* Reserved */ + RESERVED161_IRQ = 161, /* Reserved */ + RESERVED162_IRQ = 162, /* Reserved */ + RESERVED163_IRQ = 163, /* Reserved */ + RESERVED164_IRQ = 164, /* Reserved */ + RESERVED165_IRQ = 165, /* Reserved */ + RESERVED166_IRQ = 166, /* Reserved */ + RESERVED167_IRQ = 167, /* Reserved */ + RESERVED168_IRQ = 168, /* Reserved */ + RESERVED169_IRQ = 169, /* Reserved */ + RESERVED170_IRQ = 170, /* Reserved */ + RESERVED171_IRQ = 171, /* Reserved */ + RESERVED172_IRQ = 172, /* Reserved */ + RESERVED173_IRQ = 173, /* Reserved */ + RESERVED174_IRQ = 174, /* Reserved */ + RESERVED175_IRQ = 175, /* Reserved */ + RESERVED176_IRQ = 176, /* Reserved */ + RESERVED177_IRQ = 177, /* Reserved */ + RESERVED178_IRQ = 178, /* Reserved */ + RESERVED179_IRQ = 179, /* Reserved */ + DMCS0_MISC_OFLOW_IRQ = 180, /* DMC 0/4 Combined Misc Overflow */ + DMCS0_ERR_OFLOW_IRQ = 181, /* DMC 0/4 Error Overflow */ + DMCS0_ECC_ERR_INT_IRQ = 182, /* DMC 0/4 ECC Error Int */ + DMCS0_MISC_ACCESS_INT_IRQ = 183, /* DMC 0/4 Combined Miscellaneous + access int */ + DMCS0_TEMPERATURE_EVENT_INT_IRQ = 184, /* DMC 0/4 Temperature event int */ + DMCS0_FAILED_ACCESS_INT_IRQ = 185, /* DMC 0/4 Failed access int */ + DMCS0_MGR_INT_IRQ = 186, /* DMC 0/4 combined manager int */ + DMCS1_MISC_OFLOW_IRQ = 187, /* DMC 1/5 Combined Misc Overflow */ + DMCS1_ERR_OFLOW_IRQ = 188, /* DMC 1/5 Error Overflow */ + DMCS1_ECC_ERR_INT_IRQ = 189, /* DMC 1/5 ECC Error Int */ + DMCS1_MISC_ACCESS_INT_IRQ = 190, /* DMC 1/5 Combined Miscellaneous + access int */ + DMCS1_TEMPERATURE_EVENT_INT_IRQ = 191, /* DMC 1/5 Temperature event int */ + DMCS1_FAILED_ACCESS_INT_IRQ = 192, /* DMC 1/5 Failed access int */ + DMCS1_MGR_INT_IRQ = 193, /* DMC 1/5 combined manager int */ + DMCS2_MISC_OFLOW_IRQ = 194, /* DMC 2/6 Combined Misc Overflow */ + DMCS2_ERR_OFLOW_IRQ = 195, /* DMC 2/6 Error Overflow */ + DMCS2_ECC_ERR_INT_IRQ = 196, /* DMC 2/6 ECC Error Int */ + DMCS2_MISC_ACCESS_INT_IRQ = 197, /* DMC 2/6 Combined Miscellaneous + access int */ + DMCS2_TEMPERATURE_EVENT_INT_IRQ = 198, /* DMC 2/6 Temperature event int */ + DMCS2_FAILED_ACCESS_INT_IRQ = 199, /* DMC 2/6 Failed access int */ + DMCS2_MGR_INT_IRQ = 200, /* DMC 2/6 combined manager int */ + DMCS3_MISC_OFLOW_IRQ = 201, /* DMC 3/7 Combined Misc Overflow */ + DMCS3_ERR_OFLOW_IRQ = 202, /* DMC 3/7 Error Overflow */ + DMCS3_ECC_ERR_INT_IRQ = 203, /* DMC 3/7 ECC Error Int */ + DMCS3_MISC_ACCESS_INT_IRQ = 204, /* DMC 3/7 Combined Miscellaneous + access int */ + DMCS3_TEMPERATURE_EVENT_INT_IRQ = 205, /* DMC 3/7 Temperature event int */ + DMCS3_FAILED_ACCESS_INT_IRQ = 206, /* DMC 3/7 Failed access int */ + DMCS3_MGR_INT_IRQ = 207, /* DMC 3/7 combined manager int */ + MCP_I2C0_IRQ = 208, /* MCP C2C I2C interrupt */ + MCP_I2C1_IRQ = 209, /* MCP PCC I2C interrupt */ + MCP_QSPI_IRQ = 210, /* MCP QSPI interrupt */ + RESERVED211_IRQ = 211, /* Reserved */ + RESERVED212_IRQ = 212, /* Reserved */ + RESERVED213_IRQ = 213, /* Reserved */ + RESERVED214_IRQ = 214, /* Reserved */ + RESERVED215_IRQ = 215, /* Reserved */ + RESERVED216_IRQ = 216, /* Reserved */ + RESERVED217_IRQ = 217, /* Reserved */ + RESERVED218_IRQ = 218, /* Reserved */ + RESERVED219_IRQ = 219, /* Reserved */ + PCIE_AER_IRQ = 220, /* PCIe address enable interrupt */ + PCIE_LOCAL_INT_REST_IRQ = 221, /* PCIe local error & status + interrupt */ + PCIE_LOCAL_INT_RAS_IRQ = 222, /* PCIe local RAS interrupt */ + CCIX_AER_IRQ = 223, /* PCIe address enable interrupt */ + CCIX_LOCAL_INT_REST_IRQ = 224, /* PCIe local error & status + interrupt */ + CCIX_LOCAL_INT_RAS_IRQ = 225, /* PCIe local RAS interrupt */ + RESERVED226_IRQ = 226, /* Reserved */ + RESERVED227_IRQ = 227, /* Reserved */ + RESERVED228_IRQ = 228, /* Reserved */ + RESERVED229_IRQ = 229, /* Reserved */ + RESERVED230_IRQ = 230, /* Reserved */ + RESERVED231_IRQ = 231, /* Reserved */ + RESERVED232_IRQ = 232, /* Reserved */ + RESERVED233_IRQ = 233, /* Reserved */ + RESERVED234_IRQ = 234, /* Reserved */ + RESERVED235_IRQ = 235, /* Reserved */ + RESERVED236_IRQ = 236, /* Reserved */ + RESERVED237_IRQ = 237, /* Reserved */ + RESERVED238_IRQ = 238, /* Reserved */ + RESERVED239_IRQ = 239, /* Reserved */ +}; + +#endif /* N1SDP_MCP_IRQ_H */ diff --git a/product/n1sdp/include/n1sdp_mcp_mmap.h b/product/n1sdp/include/n1sdp_mcp_mmap.h new file mode 100644 index 0000000000000000000000000000000000000000..60004c2e3cd87988296072f47f8ab09c54182b74 --- /dev/null +++ b/product/n1sdp/include/n1sdp_mcp_mmap.h @@ -0,0 +1,68 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef N1SDP_MCP_MMAP_H +#define N1SDP_MCP_MMAP_H + +#include + +/* + * Top-level base addresses + */ +#define MCP_SOC_EXPANSION1_BASE UINT32_C(0x01000000) +#define MCP_SOC_EXPANSION2_BASE UINT32_C(0x21000000) +#define MCP_SOC_EXPANSION3_BASE UINT32_C(0x40000000) +#define MCP_SOC_EXPANSION4_BASE UINT32_C(0x48000000) +#define MCP_PERIPH_BASE UINT32_C(0x4C000000) +#define MCP_MEMORY_CONTROLLER UINT32_C(0x4E000000) +#define MCP_POWER_PERIPH_BASE UINT32_C(0x50000000) +#define MCP_SYS0_BASE UINT32_C(0x60000000) +#define MCP_SYS1_BASE UINT32_C(0xA0000000) +#define MCP_PPB_BASE_INTERNAL UINT32_C(0xE0000000) +#define MCP_PPB_BASE_EXTERNAL UINT32_C(0xE0040000) + +/* + * Peripherals + */ +#define MCP_REFCLK_CNTCTL_BASE (MCP_PERIPH_BASE) +#define MCP_REFCLK_CNTBASE0_BASE (MCP_PERIPH_BASE + 0x1000) +#define MCP_UART0_BASE (MCP_PERIPH_BASE + 0x2000) +#define MCP_WDOG_BASE (MCP_PERIPH_BASE + 0x6000) + +#define MCP_I2C0_BASE (0x3FFFE000) +#define MCP_I2C1_BASE (0x3FFFF000) + +/* + * Power control peripherals + */ +#define MCP_PIK_BASE (MCP_POWER_PERIPH_BASE) + +/* + * Base addresses of MHUv1 devices + */ +#define MCP_MHU_AP_BASE (MCP_PERIPH_BASE + 0x400000) +#define MCP_MHU_SCP_BASE UINT32_C(0x45600000) + +#define MHU_MCP_TO_AP_NS (MCP_MHU_AP_BASE + 0x0020) +#define MHU_AP_TO_MCP_NS (MCP_MHU_AP_BASE + 0x0120) +#define MHU_MCP_TO_AP_S (MCP_MHU_AP_BASE + 0x0200) +#define MHU_AP_TO_MCP_S (MCP_MHU_AP_BASE + 0x0300) + +#define MHU_SCP_TO_MCP_NS (MCP_MHU_SCP_BASE + 0x0020) +#define MHU_MCP_TO_SCP_NS (MCP_MHU_SCP_BASE + 0x0120) +#define MHU_SCP_TO_MCP_S (MCP_MHU_SCP_BASE + 0x0200) +#define MHU_MCP_TO_SCP_S (MCP_MHU_SCP_BASE + 0x0300) + +/* + * Shared memory regions + */ +#define MCP_AP_SHARED_SECURE_RAM (MCP_PERIPH_BASE + 0x420000) +#define MCP_AP_SHARED_NONSECURE_RAM (MCP_PERIPH_BASE + 0x410000) +#define MCP_SCP_SHARED_SECURE_RAM (0x45620000) +#define MCP_SCP_SHARED_NONSECURE_RAM (0x45610000) + +#endif /* N1SDP_MCP_MMAP_H */ diff --git a/product/n1sdp/include/n1sdp_mcp_pik.h b/product/n1sdp/include/n1sdp_mcp_pik.h new file mode 100644 index 0000000000000000000000000000000000000000..f76f3b15e7648b7de01f6932fa5cd8619a650476 --- /dev/null +++ b/product/n1sdp/include/n1sdp_mcp_pik.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef N1SDP_MCP_PIK_H +#define N1SDP_MCP_PIK_H + +#include +#include + +#define PIK_MCP ((struct pik_mcp_reg *) MCP_PIK_BASE) + +#endif /* N1SDP_MCP_PIK_H */ diff --git a/product/n1sdp/include/n1sdp_mcp_software_mmap.h b/product/n1sdp/include/n1sdp_mcp_software_mmap.h new file mode 100644 index 0000000000000000000000000000000000000000..a64aecd1536d9bdb051793d09954755b0d6c0764 --- /dev/null +++ b/product/n1sdp/include/n1sdp_mcp_software_mmap.h @@ -0,0 +1,29 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Software defined memory map shared between SCP and MCP cores. + */ + +#ifndef N1SDP_MCP_SOFTWARE_MMAP_H +#define N1SDP_MCP_SOFTWARE_MMAP_H + +#include + +/* SCMI payload size */ +#define MCP_SCMI_PAYLOAD_SIZE (128) + +/* SCMI non-secure payload areas */ +#define SCMI_PAYLOAD_SCP_TO_MCP_NS (MCP_SCP_SHARED_NONSECURE_RAM) +#define SCMI_PAYLOAD_MCP_TO_SCP_NS (MCP_SCP_SHARED_NONSECURE_RAM + \ + MCP_SCMI_PAYLOAD_SIZE) + +/* SCMI secure payload areas */ +#define SCMI_PAYLOAD_SCP_TO_MCP_S (MCP_SCP_SHARED_SECURE_RAM) +#define SCMI_PAYLOAD_MCP_TO_SCP_S (MCP_SCP_SHARED_SECURE_RAM + \ + MCP_SCMI_PAYLOAD_SIZE) + +#endif /* N1SDP_MCP_SOFTWARE_MMAP_H */ diff --git a/product/n1sdp/include/n1sdp_mcp_system_mmap.h b/product/n1sdp/include/n1sdp_mcp_system_mmap.h new file mode 100644 index 0000000000000000000000000000000000000000..98c8d0871cb437df6cbaaafd538f62dc0d4f1bbb --- /dev/null +++ b/product/n1sdp/include/n1sdp_mcp_system_mmap.h @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef N1SDP_MCP_SYSTEM_MMAP_H +#define N1SDP_MCP_SYSTEM_MMAP_H + +/* + * External QSPI flash memory - mapped address + */ +#define MCP_QSPI_FLASH_BASE_ADDR 0x30000000 +#define MCP_QSPI_FLASH_BASE_ADDR_ALT 0x00800000 +#define MCP_QSPI_FLASH_SIZE 0x02000000 + +/* + * Internal MCP's ROM/RAM base address + */ +#define MCP_ROM_BASE 0x00000000 +#define MCP_RAM0_BASE 0x00800000 +#define MCP_RAM1_BASE 0x20000000 + +/* + * Internal MCP's ROM/RAM sizes + */ +#define MCP_ROM_SIZE (128 * 1024) +#define MCP_RAM0_SIZE (512 * 1024) +#define MCP_RAM1_SIZE (256 * 1024) + +#endif /* N1SDP_MCP_SYSTEM_MMAP_H */ diff --git a/product/n1sdp/include/n1sdp_pik_mcp.h b/product/n1sdp/include/n1sdp_pik_mcp.h new file mode 100644 index 0000000000000000000000000000000000000000..7be5086ae179eb1c5dd360e295155d1680f13bce --- /dev/null +++ b/product/n1sdp/include/n1sdp_pik_mcp.h @@ -0,0 +1,60 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MCP PIK registers + */ + +#ifndef N1SDP_PIK_MCP_H +#define N1SDP_PIK_MCP_H + +#include +#include + +/*! + * \brief MCP PIK register definitions + */ +struct pik_mcp_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x20 - 0x14]; + FWK_RW uint32_t SURVIVAL_RESET_STATUS; + uint8_t RESERVED2[0x34 - 0x24]; + FWK_RW uint32_t ADDR_TRANS; + FWK_RW uint32_t DBG_ADDR_TRANS; + uint8_t RESERVED3[0x40 - 0x3C]; + FWK_RW uint32_t WS1_TIMER_MATCH; + FWK_RW uint32_t WS1_TIMER_EN; + uint8_t RESERVED4[0x200 - 0x48]; + FWK_R uint32_t SS_RESET_STATUS; + FWK_W uint32_t SS_RESET_SET; + FWK_W uint32_t SS_RESET_CLR; + uint8_t RESERVED5[0x810 - 0x20C]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED6[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED7[0xA10 - 0x828]; + FWK_R uint32_t PLL_STATUS0; + uint8_t RESERVED8[0xFC0 - 0xA14]; + FWK_R uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED18[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* N1SDP_PIK_MCP_H */ diff --git a/product/n1sdp/mcp_ramfw/RTX_Config.h b/product/n1sdp/mcp_ramfw/RTX_Config.h new file mode 100644 index 0000000000000000000000000000000000000000..7fa9f64e828836a3bd775365fdd34212475c32dd --- /dev/null +++ b/product/n1sdp/mcp_ramfw/RTX_Config.h @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RTX2 v5 configuration file. + * The file must be called RTX_Config.h as it is included by an RTX + * file in order to create an object file containing the configuration. + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +/* System */ +#define OS_DYNAMIC_MEM_SIZE 0 +#define OS_TICK_FREQ 1000 /* Hz */ +#define OS_ROBIN_ENABLE 0 +#define OS_ROBIN_TIMEOUT 0 +#define OS_ISR_FIFO_QUEUE 16 + +/* Thread */ +#define OS_THREAD_OBJ_MEM 0 +#define OS_THREAD_NUM 1 +#define OS_THREAD_DEF_STACK_NUM 0 +#define OS_THREAD_USER_STACK_SIZE 0 +#define OS_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_STACK_CHECK 1 +#define OS_STACK_WATERMARK 0 +#define OS_PRIVILEGE_MODE 1 + +/* Timer */ +#define OS_TIMER_OBJ_MEM 0 +#define OS_TIMER_NUM 1 +#define OS_TIMER_THREAD_PRIO 40 +#define OS_TIMER_THREAD_STACK_SIZE 200 +#define OS_TIMER_CB_QUEUE 4 + +/* Event flags */ +#define OS_EVFLAGS_OBJ_MEM 0 +#define OS_EVFLAGS_NUM 1 + +#define OS_MUTEX_OBJ_MEM 0 +#define OS_MUTEX_NUM 1 +#define OS_SEMAPHORE_OBJ_MEM 0 +#define OS_SEMAPHORE_NUM 1 +#define OS_MEMPOOL_OBJ_MEM 0 +#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_DATA_SIZE 0 +#define OS_MSGQUEUE_OBJ_MEM 0 +#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_DATA_SIZE 0 + +#endif /* RTX_CONFIG_H_ */ diff --git a/product/n1sdp/mcp_ramfw/config_armv7m_mpu.c b/product/n1sdp/mcp_ramfw/config_armv7m_mpu.c new file mode 100644 index 0000000000000000000000000000000000000000..c6bff184abbc8ee8ef10c86b4dd716c95bc4470a --- /dev/null +++ b/product/n1sdp/mcp_ramfw/config_armv7m_mpu.c @@ -0,0 +1,47 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +static const ARM_MPU_Region_t regions[] = { + { /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 0, 1, 0, ARM_MPU_REGION_SIZE_4GB), + }, + { /* 0x0080_0000 - 0x0087_FFFF */ + .RBAR = ARM_MPU_RBAR(1, MCP_RAM0_BASE), + .RASR = ARM_MPU_RASR( + 0, ARM_MPU_AP_PRO, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB), + }, + { /* 0x2000_0000 - 0x2003_FFFF */ + .RBAR = ARM_MPU_RBAR(2, MCP_RAM1_BASE), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB), + }, + { /* 0x4562_0000 - 0x4562_00FF */ + .RBAR = ARM_MPU_RBAR(3, MCP_SCP_SHARED_SECURE_RAM), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B), + }, + { /* 0x4561_0000 - 0x4561_00FF */ + .RBAR = ARM_MPU_RBAR(4, MCP_SCP_SHARED_NONSECURE_RAM), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; diff --git a/product/n1sdp/mcp_ramfw/config_clock.c b/product/n1sdp/mcp_ramfw/config_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..f1b03e643c1161c417b44b714b7ec24e8c8916a0 --- /dev/null +++ b/product/n1sdp/mcp_ramfw/config_clock.c @@ -0,0 +1,14 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* + * Empty placeholder for compatibility as all clocks are + * managed by SCP. + */ +const struct fwk_module_config config_clock = { 0 }; diff --git a/product/n1sdp/mcp_ramfw/config_clock.h b/product/n1sdp/mcp_ramfw/config_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..bb02958a25b490617374f3e4f30f4f2e174a4b2c --- /dev/null +++ b/product/n1sdp/mcp_ramfw/config_clock.h @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_CLOCK_H +#define CONFIG_CLOCK_H + +#include + +/* + * PIK clock rates. + */ +#define PIK_CLK_RATE_MCP_CORECLK (300 * FWK_MHZ) +#define PIK_CLK_RATE_MCP_AXICLK (300 * FWK_MHZ) + +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CLOCK_PIK_IDX_MCP_CORECLK, + CLOCK_PIK_IDX_MCP_AXICLK, + CLOCK_PIK_IDX_COUNT +}; + +#endif /* CONFIG_CLOCK_H */ diff --git a/product/n1sdp/mcp_ramfw/config_log.c b/product/n1sdp/mcp_ramfw/config_log.c new file mode 100644 index 0000000000000000000000000000000000000000..072f67a39edabc3913442ded763a46ed056751b0 --- /dev/null +++ b/product/n1sdp/mcp_ramfw/config_log.c @@ -0,0 +1,59 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * PL011 module + */ +static const struct fwk_element pl011_element_desc_table[] = { + [0] = { + .name = "MCP-UART", + .data = &((struct mod_pl011_device_config) { + .reg_base = MCP_UART0_BASE, + .baud_rate_bps = 38400, + .clock_rate_hz = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_pl011_table(fwk_id_t module_id) +{ + return pl011_element_desc_table; +} + +struct fwk_module_config config_pl011 = { + .get_element_table = get_pl011_table, +}; + +/* + * Log module + */ +static const struct mod_log_config log_data = { + .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0), + .log_groups = MOD_LOG_GROUP_ERROR | + MOD_LOG_GROUP_INFO | + MOD_LOG_GROUP_WARNING | + MOD_LOG_GROUP_DEBUG, + .banner = FWK_BANNER_MCP + FWK_BANNER_RAM_FIRMWARE + BUILD_VERSION_DESCRIBE_STRING "\n", +}; + +struct fwk_module_config config_log = { + .data = &log_data, +}; diff --git a/product/n1sdp/mcp_ramfw/config_pik_clock.c b/product/n1sdp/mcp_ramfw/config_pik_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..35018aae19f9f58266c10ddf42eb94534c02bcd0 --- /dev/null +++ b/product/n1sdp/mcp_ramfw/config_pik_clock.c @@ -0,0 +1,78 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Rate lookup tables + */ + +static const struct mod_pik_clock_rate rate_table_mcp_coreclk[] = { + { + .rate = PIK_CLK_RATE_MCP_CORECLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_CORECLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_mcp_axiclk[] = { + { + .rate = PIK_CLK_RATE_MCP_AXICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_AXICLK, + }, +}; + +static const struct fwk_element pik_clock_element_table[] = { + [CLOCK_PIK_IDX_MCP_CORECLK] = { + .name = "MCP CORECLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_MCP->CORECLK_CTRL, + .divsys_reg = &PIK_MCP->CORECLK_DIV1, + .rate_table = rate_table_mcp_coreclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_coreclk), + .initial_rate = PIK_CLK_RATE_MCP_CORECLK, + .defer_initialization = true, + }), + }, + [CLOCK_PIK_IDX_MCP_AXICLK] = { + .name = "MCP AXICLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_MCP->CORECLK_CTRL, + .divsys_reg = &PIK_MCP->CORECLK_DIV1, + .rate_table = rate_table_mcp_axiclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_axiclk), + .initial_rate = PIK_CLK_RATE_MCP_AXICLK, + .defer_initialization = true, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *pik_clock_get_element_table + (fwk_id_t module_id) +{ + return pik_clock_element_table; +} + +const struct fwk_module_config config_pik_clock = { + .get_element_table = pik_clock_get_element_table, +}; diff --git a/product/n1sdp/mcp_ramfw/firmware.mk b/product/n1sdp/mcp_ramfw/firmware.mk new file mode 100644 index 0000000000000000000000000000000000000000..74d827de7b7d22efaf86b08046eb203f80745a63 --- /dev/null +++ b/product/n1sdp/mcp_ramfw/firmware.mk @@ -0,0 +1,29 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := yes +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := \ + power_domain \ + css_clock + +BS_FIRMWARE_MODULES := \ + armv7m_mpu \ + pl011 \ + log \ + pik_clock \ + clock + +BS_FIRMWARE_SOURCES := \ + rtx_config.c \ + config_armv7m_mpu.c \ + config_log.c \ + config_pik_clock.c \ + config_clock.c + +include $(BS_DIR)/firmware.mk diff --git a/product/n1sdp/mcp_ramfw/fmw_memory.ld.S b/product/n1sdp/mcp_ramfw/fmw_memory.ld.S new file mode 100644 index 0000000000000000000000000000000000000000..7099e37045b112c41e26ed3edf5bfb1adde7304f --- /dev/null +++ b/product/n1sdp/mcp_ramfw/fmw_memory.ld.S @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_LD_S +#define FMW_MEMORY_LD_S + +#include + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FIRMWARE_MEM0_SIZE MCP_RAM0_SIZE +#define FIRMWARE_MEM0_BASE MCP_RAM0_BASE + +/* + * RAM data memory + */ +#define FIRMWARE_MEM1_SIZE MCP_RAM1_SIZE +#define FIRMWARE_MEM1_BASE MCP_RAM1_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_LD_S */ diff --git a/product/n1sdp/mcp_ramfw/rtx_config.c b/product/n1sdp/mcp_ramfw/rtx_config.c new file mode 100644 index 0000000000000000000000000000000000000000..3d54e676a6127f33e5acd5e66035d333d451fbfc --- /dev/null +++ b/product/n1sdp/mcp_ramfw/rtx_config.c @@ -0,0 +1,35 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* + * Required by RTX to configure the SysTick timer. + */ +uint32_t SystemCoreClock = CLOCK_RATE_REFCLK; + +/* + * Idle thread + */ +__NO_RETURN void osRtxIdleThread(void *argument) +{ + while (true) + __WFI(); +} + +/* + * OS error handler + */ +uint32_t osRtxErrorNotify(uint32_t code, void *object_id) +{ + osRtxIdleThread(object_id); +} diff --git a/product/n1sdp/product.mk b/product/n1sdp/product.mk index 7cd081333b0c634054263a994b79570e674e86da..2d4c6512e355c9702a37ed24b2ca967942f9d041 100644 --- a/product/n1sdp/product.mk +++ b/product/n1sdp/product.mk @@ -6,4 +6,4 @@ # BS_PRODUCT_NAME := n1sdp -BS_FIRMWARE_LIST := scp_ramfw +BS_FIRMWARE_LIST := scp_ramfw mcp_ramfw