From b58415e3f4f10960423c17f86b2b5692bbd11963 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 4 Dec 2019 11:43:15 +0530 Subject: [PATCH 01/34] product/rddanielxlr: add config data for SID driver module SID peripheral on this platform provides information about the platform ID and config ID. So add the configuration data for SID module. The base address of the SID register block is provided for the SID module to read out the IDs from the SID registers. Change-Id: I7bedc53e1ac885f362dfeac939196c71f764b405 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_css_mmap.h | 15 +++++++ product/rddanielxlr/include/scp_mmap.h | 13 ++++++ product/rddanielxlr/src/config_sid.c | 47 ++++++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 product/rddanielxlr/include/scp_css_mmap.h create mode 100644 product/rddanielxlr/include/scp_mmap.h create mode 100644 product/rddanielxlr/src/config_sid.c diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h new file mode 100644 index 000000000..4c35d5051 --- /dev/null +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_CSS_MMAP_H +#define SCP_CSS_MMAP_H + +#include "scp_mmap.h" + +#define SCP_SID_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A4A0000) + +#endif /* SCP_CSS_MMAP_H */ diff --git a/product/rddanielxlr/include/scp_mmap.h b/product/rddanielxlr/include/scp_mmap.h new file mode 100644 index 000000000..9752f0204 --- /dev/null +++ b/product/rddanielxlr/include/scp_mmap.h @@ -0,0 +1,13 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_MMAP_H +#define SCP_MMAP_H + +#define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 + +#endif /* SCP_MMAP_H */ diff --git a/product/rddanielxlr/src/config_sid.c b/product/rddanielxlr/src/config_sid.c new file mode 100644 index 000000000..5ba0abcd5 --- /dev/null +++ b/product/rddanielxlr/src/config_sid.c @@ -0,0 +1,47 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_css_mmap.h" + +#include + +#include +#include +#include + +static const struct fwk_element subsystem_table[] = { + { + .name = "RD-Daniel Cfg-XLR", + .data = &(struct mod_sid_subsystem_config) { + .part_number = 0x78a, + } + }, + { 0 }, +}; + +static const struct fwk_element *get_subsystem_table(fwk_id_t id) +{ + return subsystem_table; +} + +const struct fwk_module_config config_sid = { + .get_element_table = get_subsystem_table, + .data = &(struct mod_sid_config) { + .sid_base = SCP_SID_BASE, + .pcid_expected = { + .PID0 = 0xD2, + .PID1 = 0xB0, + .PID2 = 0x0B, + .PID3 = 0x00, + .PID4 = 0x04, + .CID0 = 0x0D, + .CID1 = 0xF0, + .CID2 = 0x05, + .CID3 = 0xB1, + }, + }, +}; -- GitLab From 7a10052b8ef85fcc1a1fec56624d51e84033243e Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Thu, 9 Apr 2020 14:46:12 +0530 Subject: [PATCH 02/34] product/rddanielxlr: add config data for system info module System info module provides a abstraction to retrieve the chip id in a platform agnostic way. Change-Id: If0cbb5d10dd5591753e8ccb24632da04da69bc99 Signed-off-by: Aditya Angadi --- product/rddanielxlr/src/config_system_info.c | 24 ++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 product/rddanielxlr/src/config_system_info.c diff --git a/product/rddanielxlr/src/config_system_info.c b/product/rddanielxlr/src/config_system_info.c new file mode 100644 index 000000000..841b39bed --- /dev/null +++ b/product/rddanielxlr/src/config_system_info.c @@ -0,0 +1,24 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include + +const struct fwk_module_config config_system_info = { + .get_element_table = NULL, + .data = &((struct mod_system_info_config) { + .system_info_driver_module_id = + FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SID), + .system_info_driver_data_api_id = + FWK_ID_API_INIT(FWK_MODULE_IDX_SID, + MOD_SID_SYSTEM_INFO_DRIVER_DATA_API_IDX), + }), +}; -- GitLab From 694d3fd11490660af1dd4e015a517088d668ed43 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 4 Dec 2019 12:08:45 +0530 Subject: [PATCH 03/34] product/rddanielxlr: add config data for pl011 UART module PL011 controller is used as a console port for debug and log messages. Add configuration data of this controller including base address and input clock frequency for the PL011 module to use. Change-Id: I713e675736561db4f4cdaab1da994d9fe69a3fa8 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_css_mmap.h | 2 ++ product/rddanielxlr/include/scp_mmap.h | 1 + product/rddanielxlr/src/config_pl011.c | 38 ++++++++++++++++++++++ 3 files changed, 41 insertions(+) create mode 100644 product/rddanielxlr/src/config_pl011.c diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index 4c35d5051..fe9e2fe00 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -12,4 +12,6 @@ #define SCP_SID_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A4A0000) +#define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) + #endif /* SCP_CSS_MMAP_H */ diff --git a/product/rddanielxlr/include/scp_mmap.h b/product/rddanielxlr/include/scp_mmap.h index 9752f0204..02ee6ef63 100644 --- a/product/rddanielxlr/include/scp_mmap.h +++ b/product/rddanielxlr/include/scp_mmap.h @@ -8,6 +8,7 @@ #ifndef SCP_MMAP_H #define SCP_MMAP_H +#define SCP_PERIPHERAL_BASE 0x44000000 #define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 #endif /* SCP_MMAP_H */ diff --git a/product/rddanielxlr/src/config_pl011.c b/product/rddanielxlr/src/config_pl011.c new file mode 100644 index 000000000..07192a92c --- /dev/null +++ b/product/rddanielxlr/src/config_pl011.c @@ -0,0 +1,38 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_css_mmap.h" + +#include + +#include +#include +#include +#include + +static const struct fwk_element pl011_element_desc_table[] = { + [0] = { + .name = "uart", + .data = &((struct mod_pl011_device_config) { + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + .pd_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_pl011_table(fwk_id_t id) +{ + return pl011_element_desc_table; +} + +const struct fwk_module_config config_pl011 = { + .get_element_table = get_pl011_table, +}; -- GitLab From db6a469d0c49b0d13be78f1f050fd8ecdbb33101 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 4 Dec 2019 14:04:09 +0530 Subject: [PATCH 04/34] product/rddanielxlr: add config data for log module in ROM firmware Provide the configuration data for the log module that includes the details of the console to use to display the log messages and the type of log messages that are allowed to be displayed. Change-Id: I2021fffcda058e56a73c216c728323cc0b3b7879 Signed-off-by: Aditya Angadi --- product/rddanielxlr/scp_romfw/config_log.c | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 product/rddanielxlr/scp_romfw/config_log.c diff --git a/product/rddanielxlr/scp_romfw/config_log.c b/product/rddanielxlr/scp_romfw/config_log.c new file mode 100644 index 000000000..ebb6acb0e --- /dev/null +++ b/product/rddanielxlr/scp_romfw/config_log.c @@ -0,0 +1,25 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include + +static const struct mod_log_config log_data = { + .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0), + .banner = FWK_BANNER_SCP + FWK_BANNER_ROM_FIRMWARE + BUILD_VERSION_DESCRIBE_STRING "\n", +}; + +struct fwk_module_config config_log = { + .data = &log_data, +}; -- GitLab From 4e5b202b6bb737c8ba23d01c944ea4e6559a0b81 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 4 Dec 2019 14:44:57 +0530 Subject: [PATCH 05/34] product/rddanielxlr: add config data for clock module in ROM firmware The clock module config data is empty for scp rom firmware image as this structure is required only to resolve build time dependencies across modules. Change-Id: If7fff2a905fca08ffbb1b9ac9998ffe44dcec252 Signed-off-by: Aditya Angadi --- product/rddanielxlr/scp_romfw/config_clock.c | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 product/rddanielxlr/scp_romfw/config_clock.c diff --git a/product/rddanielxlr/scp_romfw/config_clock.c b/product/rddanielxlr/scp_romfw/config_clock.c new file mode 100644 index 000000000..4afc18468 --- /dev/null +++ b/product/rddanielxlr/scp_romfw/config_clock.c @@ -0,0 +1,10 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +const struct fwk_module_config config_clock = { 0 }; -- GitLab From 088ab54d19d372549ce267838adecdd715526c5a Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Thu, 5 Dec 2019 11:16:56 +0530 Subject: [PATCH 06/34] product/rddanielxlr: add SCP RAM firmware load module Add a service module that will be built into romfw. This module issues an event to itself and this event, when processed, loads and passes execution control to the RAM firmware's reset handler. Change-Id: I7b31f33318ecd81ebb3a30ac988b96ce0e18848d Signed-off-by: Aditya Angadi --- .../module/mscp_rom/include/mod_mscp_rom.h | 45 ++++++++ .../rddanielxlr/module/mscp_rom/src/Makefile | 11 ++ .../module/mscp_rom/src/mod_mscp_rom.c | 100 ++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 product/rddanielxlr/module/mscp_rom/include/mod_mscp_rom.h create mode 100644 product/rddanielxlr/module/mscp_rom/src/Makefile create mode 100644 product/rddanielxlr/module/mscp_rom/src/mod_mscp_rom.c diff --git a/product/rddanielxlr/module/mscp_rom/include/mod_mscp_rom.h b/product/rddanielxlr/module/mscp_rom/include/mod_mscp_rom.h new file mode 100644 index 000000000..9e654473b --- /dev/null +++ b/product/rddanielxlr/module/mscp_rom/include/mod_mscp_rom.h @@ -0,0 +1,45 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MOD_MSCP_ROM_H +#define MOD_MSCP_ROM_H + +#include + +/*! + * \addtogroup GroupSCPModule MSCP Product Modules + * @{ + */ + +/*! + * \defgroup GroupSCP ROM Support + * @{ + */ + +/*! + * \brief Module configuration data. + */ +struct mscp_rom_config { + /*! Base address in RAM at which RAM firmware image has to be loaded */ + const uintptr_t ramfw_ram_base; + + /*! Base address of RAM firmware image on the NOR flash memory */ + const uintptr_t ramfw_flash_base; + + /*! The size of the RAM firmware image on the NOR flash memory */ + const unsigned int ramfw_flash_size; +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_MSCP_ROM_H */ diff --git a/product/rddanielxlr/module/mscp_rom/src/Makefile b/product/rddanielxlr/module/mscp_rom/src/Makefile new file mode 100644 index 000000000..ad0d7e5ef --- /dev/null +++ b/product/rddanielxlr/module/mscp_rom/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := MSCP ROM +BS_LIB_SOURCES := mod_mscp_rom.c + +include $(BS_DIR)/lib.mk diff --git a/product/rddanielxlr/module/mscp_rom/src/mod_mscp_rom.c b/product/rddanielxlr/module/mscp_rom/src/mod_mscp_rom.c new file mode 100644 index 000000000..e0f2823b5 --- /dev/null +++ b/product/rddanielxlr/module/mscp_rom/src/mod_mscp_rom.c @@ -0,0 +1,100 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +static const struct mscp_rom_config *rom_config; + +enum rom_event { + ROM_EVENT_RUN, + ROM_EVENT_COUNT +}; + +/* + * This function assumes that the RAM firmware image is located at the beginning + * of the SCP/MCP RAM. The reset handler will be at offset 0x4 (the second entry + * of the vector table). + */ +static void jump_to_ramfw(void) +{ + uintptr_t const *reset_base = + (uintptr_t *)(rom_config->ramfw_ram_base + 0x4); + void (*ramfw_reset_handler)(void); + + /* + * Disable interrupts for the duration of the ROM firmware to RAM firmware + * transition. + */ + fwk_interrupt_global_disable(); + + ramfw_reset_handler = (void (*)(void))*reset_base; + + /* + * Execute the RAM firmware's reset handler to pass control from ROM + * firmware to the RAM firmware. + */ + ramfw_reset_handler(); +} + +static int mscp_rom_init(fwk_id_t module_id, unsigned int element_count, + const void *data) +{ + rom_config = data; + + return FWK_SUCCESS; +} + +static int mscp_rom_start(fwk_id_t id) +{ + int status; + struct fwk_event event = { + .source_id = FWK_ID_MODULE(FWK_MODULE_IDX_MSCP_ROM), + .target_id = FWK_ID_MODULE(FWK_MODULE_IDX_MSCP_ROM), + .id = FWK_ID_EVENT(FWK_MODULE_IDX_MSCP_ROM, ROM_EVENT_RUN), + }; + + status = fwk_thread_put_event(&event); + + return status; +} + +static int mscp_rom_process_event(const struct fwk_event *event, + struct fwk_event *resp) +{ + FWK_LOG_INFO("[ROM] Loading RAM firmware\n"); + + if (rom_config->ramfw_flash_size != 0) { + memcpy((void *)rom_config->ramfw_ram_base, + (uint8_t *)rom_config->ramfw_flash_base, + rom_config->ramfw_flash_size); + } + + FWK_LOG_INFO("[ROM] Starting RAM firmware execution\n"); + jump_to_ramfw(); + + return FWK_SUCCESS; +} + +/* Module descriptor */ +const struct fwk_module module_mscp_rom = { + .name = "MSCP_ROM", + .type = FWK_MODULE_TYPE_SERVICE, + .event_count = ROM_EVENT_COUNT, + .init = mscp_rom_init, + .start = mscp_rom_start, + .process_event = mscp_rom_process_event, +}; -- GitLab From 0b311ad259512e68068a6b44ce31ceb6fb93fcbc Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Thu, 5 Dec 2019 14:50:48 +0530 Subject: [PATCH 07/34] product/rddanielxlr: add config data for SCP RAM firmware load module The MSCP RAM firmware load module is used to load the SCP RAM firmware from the NOR flash to SCP RAM. Provide the base address and size of the firmware image to be loaded from and the base address of the location to which the firmware is loaded to. Change-Id: Ia8f4b6d4955ca3415c00d576f40dbb4b35d2444a Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_mmap.h | 2 ++ product/rddanielxlr/include/scp_soc_mmap.h | 15 +++++++++++++ .../rddanielxlr/include/scp_software_mmap.h | 19 +++++++++++++++++ .../rddanielxlr/scp_romfw/config_scp_rom.c | 21 +++++++++++++++++++ 4 files changed, 57 insertions(+) create mode 100644 product/rddanielxlr/include/scp_soc_mmap.h create mode 100644 product/rddanielxlr/include/scp_software_mmap.h create mode 100644 product/rddanielxlr/scp_romfw/config_scp_rom.c diff --git a/product/rddanielxlr/include/scp_mmap.h b/product/rddanielxlr/include/scp_mmap.h index 02ee6ef63..c5a05bb3a 100644 --- a/product/rddanielxlr/include/scp_mmap.h +++ b/product/rddanielxlr/include/scp_mmap.h @@ -8,6 +8,8 @@ #ifndef SCP_MMAP_H #define SCP_MMAP_H +#define SCP_ITC_RAM_BASE 0x00800000 +#define SCP_SOC_EXPANSION1_BASE 0x01000000 #define SCP_PERIPHERAL_BASE 0x44000000 #define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 diff --git a/product/rddanielxlr/include/scp_soc_mmap.h b/product/rddanielxlr/include/scp_soc_mmap.h new file mode 100644 index 000000000..68265847d --- /dev/null +++ b/product/rddanielxlr/include/scp_soc_mmap.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_SOC_MMAP_H +#define SCP_SOC_MMAP_H + +#include "scp_mmap.h" + +#define SCP_NOR0_FLASH_BASE (SCP_SOC_EXPANSION1_BASE + 0x07000000) + +#endif /* SCP_SOC_MMAP_H */ diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h new file mode 100644 index 000000000..f66c317ff --- /dev/null +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_SOFTWARE_MMAP_H +#define SCP_SOFTWARE_MMAP_H + +#include "scp_soc_mmap.h" + +#include + +/* SCP RAM firmware base and size on the flash */ +#define SCP_RAMFW_IMAGE_FLASH_BASE (SCP_NOR0_FLASH_BASE + 0x03D80000) +#define SCP_RAMFW_IMAGE_FLASH_SIZE (256 * FWK_KIB) + +#endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/rddanielxlr/scp_romfw/config_scp_rom.c b/product/rddanielxlr/scp_romfw/config_scp_rom.c new file mode 100644 index 000000000..93b418118 --- /dev/null +++ b/product/rddanielxlr/scp_romfw/config_scp_rom.c @@ -0,0 +1,21 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "scp_software_mmap.h" + +#include + +#include + +const struct fwk_module_config config_mscp_rom = { + .data = &((struct mscp_rom_config) { + .ramfw_ram_base = SCP_ITC_RAM_BASE, + .ramfw_flash_base = SCP_RAMFW_IMAGE_FLASH_BASE, + .ramfw_flash_size = SCP_RAMFW_IMAGE_FLASH_SIZE, + }) +}; -- GitLab From 503c5d5f0adcfeefff4aafbde0d7a5134c0c6ca0 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Fri, 13 Dec 2019 13:55:23 +0530 Subject: [PATCH 08/34] product/rddanielxlr: add build support for scp rom firmware Add the linker script and makefile to support the build of the SCP ROM firmware. Change-Id: I1ef8166a79b525beb5feda4fb628d13d29f781e1 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_mmap.h | 2 ++ .../rddanielxlr/include/scp_software_mmap.h | 4 +++ product/rddanielxlr/scp_romfw/firmware.mk | 32 ++++++++++++++++++ product/rddanielxlr/scp_romfw/fmw_memory.h | 33 +++++++++++++++++++ 4 files changed, 71 insertions(+) create mode 100644 product/rddanielxlr/scp_romfw/firmware.mk create mode 100644 product/rddanielxlr/scp_romfw/fmw_memory.h diff --git a/product/rddanielxlr/include/scp_mmap.h b/product/rddanielxlr/include/scp_mmap.h index c5a05bb3a..e9aeb39f1 100644 --- a/product/rddanielxlr/include/scp_mmap.h +++ b/product/rddanielxlr/include/scp_mmap.h @@ -8,8 +8,10 @@ #ifndef SCP_MMAP_H #define SCP_MMAP_H +#define SCP_BOOT_ROM_BASE 0x00000000 #define SCP_ITC_RAM_BASE 0x00800000 #define SCP_SOC_EXPANSION1_BASE 0x01000000 +#define SCP_DTC_RAM_BASE 0x20000000 #define SCP_PERIPHERAL_BASE 0x44000000 #define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h index f66c317ff..afab09cd2 100644 --- a/product/rddanielxlr/include/scp_software_mmap.h +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -12,6 +12,10 @@ #include +/* SCP ROM and RAM firmware size loaded on main memory */ +#define SCP_BOOT_ROM_SIZE (64 * 1024) +#define SCP_DTC_RAM_SIZE (256 * 1024) + /* SCP RAM firmware base and size on the flash */ #define SCP_RAMFW_IMAGE_FLASH_BASE (SCP_NOR0_FLASH_BASE + 0x03D80000) #define SCP_RAMFW_IMAGE_FLASH_SIZE (256 * FWK_KIB) diff --git a/product/rddanielxlr/scp_romfw/firmware.mk b/product/rddanielxlr/scp_romfw/firmware.mk new file mode 100644 index 000000000..584bd2b32 --- /dev/null +++ b/product/rddanielxlr/scp_romfw/firmware.mk @@ -0,0 +1,32 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := no +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := \ + power_domain \ + timer + +BS_FIRMWARE_MODULES := \ + sid \ + system_info \ + pcid \ + pl011 \ + log \ + clock \ + mscp_rom \ + +BS_FIRMWARE_SOURCES := \ + config_sid.c \ + config_system_info.c \ + config_log.c \ + config_pl011.c \ + config_clock.c \ + config_scp_rom.c \ + +include $(BS_DIR)/firmware.mk diff --git a/product/rddanielxlr/scp_romfw/fmw_memory.h b/product/rddanielxlr/scp_romfw/fmw_memory.h new file mode 100644 index 000000000..65fee6471 --- /dev/null +++ b/product/rddanielxlr/scp_romfw/fmw_memory.h @@ -0,0 +1,33 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * ROM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "scp_mmap.h" +#include "scp_software_mmap.h" + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * ROM memory + */ +#define FIRMWARE_MEM0_SIZE SCP_BOOT_ROM_SIZE +#define FIRMWARE_MEM0_BASE SCP_BOOT_ROM_BASE + +/* + * RAM memory + */ +#define FIRMWARE_MEM1_SIZE SCP_DTC_RAM_SIZE +#define FIRMWARE_MEM1_BASE SCP_DTC_RAM_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_H */ -- GitLab From 67daee1219b33e75473a02857398c4e5743ebf51 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 11:14:15 +0530 Subject: [PATCH 09/34] product/rddanielxlr: add configuration data for log module in ram firmware Log module provides the details of the console to display messages and the type of messages that can be displayed. Provide the data for same. Change-Id: Ic27adf6a46eb2bf3081c63210f2be9daf1fc2afc Signed-off-by: Aditya Angadi --- product/rddanielxlr/scp_ramfw/config_log.c | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_log.c diff --git a/product/rddanielxlr/scp_ramfw/config_log.c b/product/rddanielxlr/scp_ramfw/config_log.c new file mode 100644 index 000000000..0c76b1454 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_log.c @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include + +/* + * Log module + */ +static const struct mod_log_config log_data = { + .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0), + .banner = FWK_BANNER_SCP + FWK_BANNER_RAM_FIRMWARE + BUILD_VERSION_DESCRIBE_STRING "\n", +}; + +struct fwk_module_config config_log = { + .data = &log_data, +}; -- GitLab From 137388e846cc97f0f96d10d5606c9284a18b314d Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 16 Dec 2019 09:45:23 +0530 Subject: [PATCH 10/34] product/rddanielxlr: add configuration data for MPU module Add configuration data for MPU module. The SCP RAMs, trusted RAM and non-trusted memory regions are specified. Change-Id: I1cfe38d9065a784eca0518687cebeeafb99bac2e Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/fmw_cmsis.h | 34 +++++++++++++ .../rddanielxlr/include/scp_software_mmap.h | 6 +++ .../rddanielxlr/scp_ramfw/config_armv7m_mpu.c | 51 +++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 product/rddanielxlr/include/fmw_cmsis.h create mode 100644 product/rddanielxlr/scp_ramfw/config_armv7m_mpu.c diff --git a/product/rddanielxlr/include/fmw_cmsis.h b/product/rddanielxlr/include/fmw_cmsis.h new file mode 100644 index 000000000..89e48f5d8 --- /dev/null +++ b/product/rddanielxlr/include/fmw_cmsis.h @@ -0,0 +1,34 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#define __CHECK_DEVICE_DEFINES +#define __CM7_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __ICACHE_PRESENT 0U +#define __DCACHE_PRESENT 0U +#define __DTCM_PRESENT 0U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + NonMaskableInt_IRQn = -14, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, +} IRQn_Type; + +#include + +#endif /* FMW_CMSIS_H */ diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h index afab09cd2..d7ef18830 100644 --- a/product/rddanielxlr/include/scp_software_mmap.h +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -20,4 +20,10 @@ #define SCP_RAMFW_IMAGE_FLASH_BASE (SCP_NOR0_FLASH_BASE + 0x03D80000) #define SCP_RAMFW_IMAGE_FLASH_SIZE (256 * FWK_KIB) +/* SCP trusted and non-trusted RAM base address */ +#define SCP_TRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + \ + 0x04000000) +#define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + \ + 0x06000000) + #endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_armv7m_mpu.c b/product/rddanielxlr/scp_ramfw/config_armv7m_mpu.c new file mode 100644 index 000000000..cdeeac7a1 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_armv7m_mpu.c @@ -0,0 +1,51 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "scp_software_mmap.h" + +#include + +#include +#include + +#include + +static const ARM_MPU_Region_t regions[] = { + { /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 0, 1, 0, ARM_MPU_REGION_SIZE_4GB), + }, + { /* 0x0080_0000 - 0x00FF_FFFF */ + .RBAR = ARM_MPU_RBAR(1, SCP_ITC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 0, ARM_MPU_AP_PRO, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB), + }, + { /* 0x2000_0000 - 0x20FF_FFFF */ + .RBAR = ARM_MPU_RBAR(2, SCP_DTC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB), + }, + { /* 0xA400_0000 - 0xA400_7FFF*/ + .RBAR = ARM_MPU_RBAR(3, SCP_TRUSTED_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_4KB), + }, + { /* 0xA600_0000 - 0xA600_7FFF */ + .RBAR = ARM_MPU_RBAR(4, SCP_NONTRUSTED_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config) { + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; -- GitLab From 9b9860fdbb2bfcc77c59b230f49b907b617a2def Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 16 Dec 2019 10:08:44 +0530 Subject: [PATCH 11/34] product/rddanielxlr: add platform specific definitions for rtx Add platform specific definitions for callback functions for cmsis rtx. Change-Id: I946f1578e15a7946cf1bdf9607a457702ac0518d Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/clock_soc.h | 15 ++++++ product/rddanielxlr/scp_ramfw/RTX_Config.h | 56 ++++++++++++++++++++++ product/rddanielxlr/scp_ramfw/rtx_config.c | 38 +++++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 product/rddanielxlr/include/clock_soc.h create mode 100644 product/rddanielxlr/scp_ramfw/RTX_Config.h create mode 100644 product/rddanielxlr/scp_ramfw/rtx_config.c diff --git a/product/rddanielxlr/include/clock_soc.h b/product/rddanielxlr/include/clock_soc.h new file mode 100644 index 000000000..6f7848c27 --- /dev/null +++ b/product/rddanielxlr/include/clock_soc.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CLOCK_SOC_H +#define CLOCK_SOC_H + +#include + +#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) + +#endif /* CLOCK_SOC_H */ diff --git a/product/rddanielxlr/scp_ramfw/RTX_Config.h b/product/rddanielxlr/scp_ramfw/RTX_Config.h new file mode 100644 index 000000000..35ce37d14 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/RTX_Config.h @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RTX2 v5 configuration file. + * The file must be called RTX_Config.h as it is included by the an RTX + * file in order to create a object file containing the configuration. + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +/* System */ +#define OS_DYNAMIC_MEM_SIZE 0 +#define OS_TICK_FREQ 1000 /* Hz */ +#define OS_ROBIN_ENABLE 0 +#define OS_ROBIN_TIMEOUT 0 +#define OS_ISR_FIFO_QUEUE 16 + +/* Thread */ +#define OS_THREAD_OBJ_MEM 0 +#define OS_THREAD_NUM 1 +#define OS_THREAD_DEF_STACK_NUM 0 +#define OS_THREAD_USER_STACK_SIZE 0 +#define OS_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_STACK_CHECK 1 +#define OS_STACK_WATERMARK 0 +#define OS_PRIVILEGE_MODE 1 + +/* Timer */ +#define OS_TIMER_OBJ_MEM 0 +#define OS_TIMER_NUM 1 +#define OS_TIMER_THREAD_PRIO 40 +#define OS_TIMER_THREAD_STACK_SIZE 200 +#define OS_TIMER_CB_QUEUE 4 + +/* Event flags */ +#define OS_EVFLAGS_OBJ_MEM 0 +#define OS_EVFLAGS_NUM 1 + +#define OS_MUTEX_OBJ_MEM 0 +#define OS_MUTEX_NUM 1 +#define OS_SEMAPHORE_OBJ_MEM 0 +#define OS_SEMAPHORE_NUM 1 +#define OS_MEMPOOL_OBJ_MEM 0 +#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_DATA_SIZE 0 +#define OS_MSGQUEUE_OBJ_MEM 0 +#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_DATA_SIZE 0 + +#endif /* RTX_CONFIG_H_ */ diff --git a/product/rddanielxlr/scp_ramfw/rtx_config.c b/product/rddanielxlr/scp_ramfw/rtx_config.c new file mode 100644 index 000000000..3f0acbaaa --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/rtx_config.c @@ -0,0 +1,38 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" + +#include +#include + +#include + +#include +#include + +/* + * Required by RTX to configure the SysTick timer. + */ +uint32_t SystemCoreClock = CLOCK_RATE_REFCLK; + +/* + * Idle thread + */ +__NO_RETURN void osRtxIdleThread(void *argument) +{ + while (true) + __WFI(); +} + +/* + * OS error handler + */ +uint32_t osRtxErrorNotify(uint32_t code, void *object_id) +{ + osRtxIdleThread(object_id); +} -- GitLab From 02fea5005a761fc7d80d29a40862f3b8de92f501 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 16 Dec 2019 10:10:32 +0530 Subject: [PATCH 12/34] product/rddanielxlr: add SCP PIK register space declaration SCP PIK includes registers for various system configuration and status. SCP PIK is first one to come out of reset and it generates all the reset conrols for SCP. Add the register space declaration for SCP PIK and the subsequent base address from element management peripheral space. Change-Id: I168c8d91102724901827dbf4ca1d6e29fd05d54d Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_css_mmap.h | 2 + product/rddanielxlr/include/scp_mmap.h | 1 + product/rddanielxlr/include/scp_pik.h | 106 +++++++++++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 product/rddanielxlr/include/scp_pik.h diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index fe9e2fe00..bd35ddec0 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -14,4 +14,6 @@ #define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) +#define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) + #endif /* SCP_CSS_MMAP_H */ diff --git a/product/rddanielxlr/include/scp_mmap.h b/product/rddanielxlr/include/scp_mmap.h index e9aeb39f1..d1e1e6292 100644 --- a/product/rddanielxlr/include/scp_mmap.h +++ b/product/rddanielxlr/include/scp_mmap.h @@ -13,6 +13,7 @@ #define SCP_SOC_EXPANSION1_BASE 0x01000000 #define SCP_DTC_RAM_BASE 0x20000000 #define SCP_PERIPHERAL_BASE 0x44000000 +#define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE 0x50000000 #define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 #endif /* SCP_MMAP_H */ diff --git a/product/rddanielxlr/include/scp_pik.h b/product/rddanielxlr/include/scp_pik.h new file mode 100644 index 000000000..9ce9d6f8a --- /dev/null +++ b/product/rddanielxlr/include/scp_pik.h @@ -0,0 +1,106 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP PIK registers + */ + +#ifndef SCP_PIK_H +#define SCP_PIK_H + +#include "scp_css_mmap.h" + +#include + +#include + +/*! + * \brief SCP PIK register definitions + */ +struct pik_scp_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x20 - 0x14]; + FWK_RW uint32_t SURVIVAL_RESET_STATUS; + uint8_t RESERVED2[0x34 - 0x24]; + FWK_RW uint32_t ADDR_TRANS; + FWK_RW uint32_t DBG_ADDR_TRANS; + uint8_t RESERVED3[0x40 - 0x3C]; + FWK_RW uint32_t WS1_TIMER_MATCH; + FWK_RW uint32_t WS1_TIMER_EN; + uint8_t RESERVED4[0x200 - 0x48]; + FWK_R uint32_t SS_RESET_STATUS; + FWK_W uint32_t SS_RESET_SET; + FWK_W uint32_t SS_RESET_CLR; + uint8_t RESERVED5[0x810 - 0x20C]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED6[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED7[0x830 - 0x828]; + FWK_RW uint32_t GTSYNCCLK_CTRL; + FWK_RW uint32_t GTSYNCCLK_DIV1; + uint8_t RESERVED8[0xA10 - 0x838]; + FWK_R uint32_t PLL_STATUS[17]; + uint8_t RESERVED9[0xA60 - 0xA54]; + FWK_R uint32_t CONS_MMUTCU_INT_STATUS; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; + FWK_W uint32_t CONS_MMUTCU_INT_CLR; + FWK_W uint32_t CONS_MMUTBU_INT_CLR0; + FWK_W uint32_t CONS_MMUTBU_INT_CLR1; + uint8_t RESERVED10[0xB00 - 0xA78]; + FWK_R uint32_t MHU_NS_INT_STATUS; + FWK_R uint32_t MHU_S_INT_STATUS; + uint8_t RESERVED11[0xB20 - 0xB08]; + FWK_R uint32_t CPU_PPU_INT_STATUS[8]; + FWK_R uint32_t CLUS_PPU_INT_STATUS; + uint8_t RESERVED12[0xB60 - 0xB44]; + FWK_R uint32_t TIMER_INT_STATUS[8]; + FWK_R uint32_t CPU_PLL_LOCK_STATUS[8]; + uint8_t RESERVED13[0xBC0 - 0xBA0]; + FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8]; + uint8_t RESERVED14[0xBF0 - 0xBE0]; + FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS; + FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS; + uint8_t RESERVED15[0xC00 - 0xBF8]; + FWK_R uint32_t CLUS_FAULT_INT_STATUS; + uint8_t RESERVED16[0xC30 - 0xC04]; + FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS; + uint8_t RESERVED17[0xD00 - 0xC34]; + FWK_R uint32_t DMC0_4_INT_STATUS; + FWK_R uint32_t DMC1_5_INT_STATUS; + FWK_R uint32_t DMC2_6_INT_STATUS; + FWK_R uint32_t DMC3_7_INT_STATUS; + uint8_t RESERVED18[0xFC0 - 0xD10]; + FWK_R uint32_t PCL_CFG; + uint8_t RESERVED19[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define PLL_STATUS_0_REFCLK UINT32_C(0x00000001) +#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002) +#define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004) +#define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008) + +#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) + +/* Pointer to SCP PIK */ +#define SCP_PIK_PTR ((struct pik_scp_reg *) SCP_PIK_SCP_BASE) + +#endif /* SCP_PIK_H */ -- GitLab From 8aee17711426268edc2c41904c2391ebb6148aaf Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 6 Jan 2020 15:47:07 +0530 Subject: [PATCH 13/34] product/rddanielxlr: add CPU PIK register space declaration CPU PIK includes registers for configuration and clock control for AP cores. Add the register space declaration and the base address macro for the CPU PIK. Change-Id: I49e6b9a6c64d2d50a94b8ae2f048300bb75dd8d4 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/cpu_pik.h | 90 ++++++++++++++++++++++ product/rddanielxlr/include/scp_css_mmap.h | 2 + 2 files changed, 92 insertions(+) create mode 100644 product/rddanielxlr/include/cpu_pik.h diff --git a/product/rddanielxlr/include/cpu_pik.h b/product/rddanielxlr/include/cpu_pik.h new file mode 100644 index 000000000..b789638a4 --- /dev/null +++ b/product/rddanielxlr/include/cpu_pik.h @@ -0,0 +1,90 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CPU_PIK_H +#define CPU_PIK_H + +#include "scp_css_mmap.h" + +#include + +#include + +/*! + * \brief PE Static Configuration register definitions + */ +struct static_config_reg { + FWK_RW uint32_t STATIC_CONFIG; + FWK_RW uint32_t RVBARADDR_LW; + FWK_RW uint32_t RVBARADDR_UP; + uint32_t RESERVED; +}; + +/*! + * \brief AP cores clock control register definitions + */ +struct coreclk_reg { + FWK_RW uint32_t CTRL; + FWK_RW uint32_t DIV; + uint32_t RESERVED; + FWK_RW uint32_t MOD; +}; + +/*! + * \brief CPU (V8.2) PIK register definitions + */ +struct pik_cpu_reg { + FWK_RW uint32_t CLUSTER_CONFIG; + uint8_t RESERVED0[0x10 - 0x4]; + struct static_config_reg STATIC_CONFIG[16]; + uint8_t RESERVED1[0x800 - 0x110]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint8_t RESERVED2[0x810 - 0x808]; + FWK_RW uint32_t PCLK_CTRL; + uint8_t RESERVED3[0x820 - 0x814]; + FWK_RW uint32_t DBGCLK_CTRL; + FWK_RW uint32_t DBGCLK_DIV1; + uint8_t RESERVED4[0x830 - 0x828]; + FWK_RW uint32_t GICCLK_CTRL; + uint8_t RESERVED5[0x840 - 0x834]; + FWK_RW uint32_t AMBACLK_CTRL; + uint8_t RESERVED6[0x850 - 0x844]; + FWK_RW uint32_t CLUSCLK_CTRL; + FWK_RW uint32_t CLUSCLK_DIV1; + uint8_t RESERVED7[0x860 - 0x858]; + struct coreclk_reg CORECLK[8]; + uint8_t RESERVED8[0xA00 - 0x8E0]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB00 - 0xA0C]; + FWK_R uint32_t NERRIQ_INT_STATUS; + FWK_R uint32_t NFAULTIQ_INT_STATUS; + uint8_t RESERVED10[0xFB4 - 0xB08]; + FWK_R uint32_t CAP3; + FWK_R uint32_t CAP2; + FWK_R uint32_t CAP; + FWK_R uint32_t PCL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define CLUSTER_PIK_PTR(IDX) ((struct pik_cpu_reg *) SCP_PIK_CLUSTER_BASE(IDX)) + +#endif /* CPU_PIK_H */ diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index bd35ddec0..50bbea4ff 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -15,5 +15,7 @@ #define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) #define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) +#define SCP_PIK_CLUSTER_BASE(n) ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ + + 0x60000) + ((n) * 0x20000)) #endif /* SCP_CSS_MMAP_H */ -- GitLab From addbffe9e97248dcf7d08787aeec83fe3fa66358 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Tue, 7 Jan 2020 08:53:51 +0530 Subject: [PATCH 14/34] product/rddanielxlr: add System PIK register space declaration System PIK includes registers for clock control of System PPU, CMN Rhodes Interconnect and DMC. Add the register space declaration and base address from element management peripheral space. Change-Id: Ic5ab7befed62579dd2a40918ed72a6429d6ea0e4 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_css_mmap.h | 2 + product/rddanielxlr/include/system_pik.h | 79 ++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 product/rddanielxlr/include/system_pik.h diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index 50bbea4ff..db8622a65 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -17,5 +17,7 @@ #define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) #define SCP_PIK_CLUSTER_BASE(n) ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ + 0x60000) + ((n) * 0x20000)) +#define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ + + 0x40000) #endif /* SCP_CSS_MMAP_H */ diff --git a/product/rddanielxlr/include/system_pik.h b/product/rddanielxlr/include/system_pik.h new file mode 100644 index 000000000..d83bd1de7 --- /dev/null +++ b/product/rddanielxlr/include/system_pik.h @@ -0,0 +1,79 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SYSTEM_PIK_H +#define SYSTEM_PIK_H + +#include "scp_css_mmap.h" + +#include + +#include + +/*! + * \brief TCU clock register definitions + */ +struct tcuclk_ctrl_reg { + FWK_RW uint32_t TCUCLK_CTRL; + FWK_RW uint32_t TCUCLK_DIV1; +}; + +/*! + * \brief System PIK register definitions + */ +struct pik_system_reg { + uint8_t RESERVED0[0x800 - 0x0]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint8_t RESERVED1[0x820 - 0x808]; + FWK_RW uint32_t INTCLK_CTRL; + FWK_RW uint32_t INTCLK_DIV1; + uint8_t RESERVED2[0x830 - 0x828]; + struct tcuclk_ctrl_reg TCUCLK[4]; + FWK_RW uint32_t GICCLK_CTRL; + FWK_RW uint32_t GICCLK_DIV1; + uint8_t RESERVED3[0x860 - 0x858]; + FWK_RW uint32_t PCLKSCP_CTRL; + FWK_RW uint32_t PCLKSCP_DIV1; + uint8_t RESERVED4[0x870 - 0x868]; + FWK_RW uint32_t SYSPERCLK_CTRL; + FWK_RW uint32_t SYSPERCLK_DIV1; + uint8_t RESERVED5[0x880 - 0x878]; + FWK_RW uint32_t DMCCLK_CTRL; + FWK_RW uint32_t DMCCLK_DIV1; + uint8_t RESERVED6[0x890 - 0x888]; + FWK_RW uint32_t SYSPCLKDBG_CTRL; + FWK_RW uint32_t SYSPCLKDBG_DIV1; + uint8_t RESERVED7[0x8A0 - 0x898]; + FWK_RW uint32_t UARTCLK_CTRL; + FWK_RW uint32_t UARTCLK_DIV1; + uint8_t RESERVED8[0xA00 - 0x8A8]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB0C - 0xA0C]; + FWK_RW uint32_t SYSTOP_RST_DLY; + uint8_t RESERVED10[0xFC0 - 0xB10]; + FWK_R uint32_t PCL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define SYSTEM_PIK_PTR ((struct pik_system_reg *) SCP_PIK_SYSTEM_BASE) + +#endif /* SYSTEM_PIK_H */ -- GitLab From 609dea6a7570ab76a7eaeaf7775161e609b85a5c Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Tue, 7 Jan 2020 10:21:04 +0530 Subject: [PATCH 15/34] product/rddanielxlr: add config data for system pll driver Add the base address of the control registers and the initial rates for the PLL hardware in RD-Daniel. Change-Id: Ife51031e362705ebf59f87591f756b32d4682e82 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/clock_soc.h | 14 +++ product/rddanielxlr/include/scp_mmap.h | 1 + product/rddanielxlr/include/scp_soc_mmap.h | 10 ++ .../rddanielxlr/scp_ramfw/config_system_pll.c | 115 ++++++++++++++++++ 4 files changed, 140 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_system_pll.c diff --git a/product/rddanielxlr/include/clock_soc.h b/product/rddanielxlr/include/clock_soc.h index 6f7848c27..632760a76 100644 --- a/product/rddanielxlr/include/clock_soc.h +++ b/product/rddanielxlr/include/clock_soc.h @@ -12,4 +12,18 @@ #define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) +/* + * PLL clock indexes. + */ +enum clock_pll_idx { + CLOCK_PLL_IDX_CPU0, + CLOCK_PLL_IDX_CPU1, + CLOCK_PLL_IDX_CPU2, + CLOCK_PLL_IDX_CPU3, + CLOCK_PLL_IDX_SYS, + CLOCK_PLL_IDX_DMC, + CLOCK_PLL_IDX_INTERCONNECT, + CLOCK_PLL_IDX_COUNT +}; + #endif /* CLOCK_SOC_H */ diff --git a/product/rddanielxlr/include/scp_mmap.h b/product/rddanielxlr/include/scp_mmap.h index d1e1e6292..cac5edafa 100644 --- a/product/rddanielxlr/include/scp_mmap.h +++ b/product/rddanielxlr/include/scp_mmap.h @@ -12,6 +12,7 @@ #define SCP_ITC_RAM_BASE 0x00800000 #define SCP_SOC_EXPANSION1_BASE 0x01000000 #define SCP_DTC_RAM_BASE 0x20000000 +#define SCP_SOC_EXPANSION3_BASE 0x40000000 #define SCP_PERIPHERAL_BASE 0x44000000 #define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE 0x50000000 #define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 diff --git a/product/rddanielxlr/include/scp_soc_mmap.h b/product/rddanielxlr/include/scp_soc_mmap.h index 68265847d..aa6088741 100644 --- a/product/rddanielxlr/include/scp_soc_mmap.h +++ b/product/rddanielxlr/include/scp_soc_mmap.h @@ -11,5 +11,15 @@ #include "scp_mmap.h" #define SCP_NOR0_FLASH_BASE (SCP_SOC_EXPANSION1_BASE + 0x07000000) +#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000) + +#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) +#define SCP_PLL_DMC (SCP_PLL_BASE + 0x00000010) +#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) + +#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) +#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) +#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) +#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) #endif /* SCP_SOC_MMAP_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_system_pll.c b/product/rddanielxlr/scp_ramfw/config_system_pll.c new file mode 100644 index 000000000..d84fdcefe --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_system_pll.c @@ -0,0 +1,115 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_pik.h" +#include "scp_soc_mmap.h" + +#include + +#include +#include +#include +#include + +static const struct fwk_element system_pll_element_table[] = { + [CLOCK_PLL_IDX_CPU0] = { + .name = "CPU_PLL_0", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU0, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU1] = { + .name = "CPU_PLL_1", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU1, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(1), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU2] = { + .name = "CPU_PLL_2", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU2, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(2), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU3] = { + .name = "CPU_PLL_3", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU3, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(3), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_SYS] = { + .name = "SYS_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_SYSPLL, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_DMC] = { + .name = "DMC_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_DMC, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_DDRPLLLOCK, + .initial_rate = 1600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_INTERCONNECT] = { + .name = "INT_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_INTERCONNECT, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *system_pll_get_element_table + (fwk_id_t module_id) +{ + return system_pll_element_table; +} + +const struct fwk_module_config config_system_pll = { + .get_element_table = system_pll_get_element_table, +}; -- GitLab From bef67b351a7582fa666b554970561f8397bf391e Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Tue, 7 Jan 2020 15:21:18 +0530 Subject: [PATCH 16/34] product/rddanielxlr: add configuration data for PIK clock driver The configuration data for PIK clock devices includes the base address of control registers and the rate table with initial rate. Change-Id: I0fb5eef8f2fe61b5f0736e3b97d7fa060e88766d Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/clock_soc.h | 19 ++ .../rddanielxlr/scp_ramfw/config_pik_clock.c | 242 ++++++++++++++++++ 2 files changed, 261 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_pik_clock.c diff --git a/product/rddanielxlr/include/clock_soc.h b/product/rddanielxlr/include/clock_soc.h index 632760a76..cd25f4d6f 100644 --- a/product/rddanielxlr/include/clock_soc.h +++ b/product/rddanielxlr/include/clock_soc.h @@ -11,6 +11,7 @@ #include #define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) /* * PLL clock indexes. @@ -26,4 +27,22 @@ enum clock_pll_idx { CLOCK_PLL_IDX_COUNT }; +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CLOCK_PIK_IDX_CLUS0_CPU0, + CLOCK_PIK_IDX_CLUS1_CPU0, + CLOCK_PIK_IDX_CLUS2_CPU0, + CLOCK_PIK_IDX_CLUS3_CPU0, + CLOCK_PIK_IDX_DMC, + CLOCK_PIK_IDX_INTERCONNECT, + CLOCK_PIK_IDX_SCP, + CLOCK_PIK_IDX_GIC, + CLOCK_PIK_IDX_PCLKSCP, + CLOCK_PIK_IDX_SYSPERCLK, + CLOCK_PIK_IDX_UARTCLK, + CLOCK_PIK_IDX_COUNT +}; + #endif /* CLOCK_SOC_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_pik_clock.c b/product/rddanielxlr/scp_ramfw/config_pik_clock.c new file mode 100644 index 000000000..fbabe4a14 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_pik_clock.c @@ -0,0 +1,242 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "cpu_pik.h" +#include "scp_pik.h" +#include "system_pik.h" + +#include + +#include +#include +#include +#include + +#include + +/* + * Rate lookup tables + */ +static struct mod_pik_clock_rate rate_table_cpu_group[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static const struct mod_pik_clock_rate rate_table_sys_intclk[] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_INTCLK_SOURCE_INTPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sys_dmcclk[] = { + { + .rate = 1600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_DMCCLK_SOURCE_DDRPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scp[] = { + { + .rate = 250 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_gicclk[] = { + { + .rate = 1000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (1000 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_pclkscp[] = { + { + .rate = 400 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (400 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_sysperclk[] = { + { + .rate = 500 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (500 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_uartclk[] = { + { + .rate = 250 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ), + }, +}; + +static const struct fwk_element pik_clock_element_table[] = { + + [CLOCK_PIK_IDX_CLUS0_CPU0] = { + .name = "CLUS0_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].CTRL, + .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV, + .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + }), + }, + [CLOCK_PIK_IDX_CLUS1_CPU0] = { + .name = "CLUS1_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR(1)->CORECLK[0].CTRL, + .divext_reg = &CLUSTER_PIK_PTR(1)->CORECLK[0].DIV, + .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + }), + }, + [CLOCK_PIK_IDX_CLUS2_CPU0] = { + .name = "CLUS2_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR(2)->CORECLK[0].CTRL, + .divext_reg = &CLUSTER_PIK_PTR(2)->CORECLK[0].DIV, + .modulator_reg = &CLUSTER_PIK_PTR(2)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + }), + }, + [CLOCK_PIK_IDX_CLUS3_CPU0] = { + .name = "CLUS3_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR(3)->CORECLK[0].CTRL, + .divext_reg = &CLUSTER_PIK_PTR(3)->CORECLK[0].DIV, + .modulator_reg = &CLUSTER_PIK_PTR(3)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + }), + }, + [CLOCK_PIK_IDX_DMC] = { + .name = "DMC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->DMCCLK_CTRL, + .divext_reg = &SYSTEM_PIK_PTR->DMCCLK_DIV1, + .rate_table = rate_table_sys_dmcclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_dmcclk), + .initial_rate = 1600 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_INTERCONNECT] = { + .name = "INTERCONNECT", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->INTCLK_CTRL, + .divext_reg = &SYSTEM_PIK_PTR->INTCLK_DIV1, + .rate_table = rate_table_sys_intclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_intclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_SCP] = { + .name = "SCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCP_PIK_PTR->CORECLK_CTRL, + .divsys_reg = &SCP_PIK_PTR->CORECLK_DIV1, + .rate_table = rate_table_scp, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp), + .initial_rate = 250 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_GIC] = { + .name = "GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, + .rate_table = rate_table_gicclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), + .initial_rate = 1000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_PCLKSCP] = { + .name = "PCLKSCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->PCLKSCP_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->PCLKSCP_DIV1, + .rate_table = rate_table_pclkscp, + .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), + .initial_rate = 400 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_SYSPERCLK] = { + .name = "SYSPERCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, + .rate_table = rate_table_sysperclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk), + .initial_rate = 500 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_UARTCLK] = { + .name = "UARTCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->UARTCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->UARTCLK_DIV1, + .rate_table = rate_table_uartclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), + .initial_rate = 250 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *pik_clock_get_element_table + (fwk_id_t module_id) +{ + return pik_clock_element_table; +} + +const struct fwk_module_config config_pik_clock = { + .get_element_table = pik_clock_get_element_table, +}; -- GitLab From 7c9db935c3619a206fc5a3b9075fcb244469e337 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 08:42:31 +0530 Subject: [PATCH 17/34] product/rddanielxlr: add configuration data for subsytem clock driver Provide setup data i.e source pll, member table and rate table for css clocks. Change-Id: I143f07ad02c582aeab734620229b186df217e529 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/clock_soc.h | 11 ++ .../rddanielxlr/scp_ramfw/config_css_clock.c | 179 ++++++++++++++++++ 2 files changed, 190 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_css_clock.c diff --git a/product/rddanielxlr/include/clock_soc.h b/product/rddanielxlr/include/clock_soc.h index cd25f4d6f..2b8b27573 100644 --- a/product/rddanielxlr/include/clock_soc.h +++ b/product/rddanielxlr/include/clock_soc.h @@ -45,4 +45,15 @@ enum clock_pik_idx { CLOCK_PIK_IDX_COUNT }; +/* + * CSS clock indexes. + */ +enum clock_css_idx { + CLOCK_CSS_IDX_CPU_GROUP0, + CLOCK_CSS_IDX_CPU_GROUP1, + CLOCK_CSS_IDX_CPU_GROUP2, + CLOCK_CSS_IDX_CPU_GROUP3, + CLOCK_CSS_IDX_COUNT +}; + #endif /* CLOCK_SOC_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_css_clock.c b/product/rddanielxlr/scp_ramfw/config_css_clock.c new file mode 100644 index 000000000..f018cfe75 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_css_clock.c @@ -0,0 +1,179 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +static const struct mod_css_clock_rate rate_table_cpu_group[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const fwk_id_t member_table_cpu_group_0[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), +}; + +static const fwk_id_t member_table_cpu_group_1[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU0), +}; + +static const fwk_id_t member_table_cpu_group_2[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS2_CPU0), +}; + +static const fwk_id_t member_table_cpu_group_3[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS3_CPU0), +}; + +static const struct fwk_element css_clock_element_table[] = { + [CLOCK_CSS_IDX_CPU_GROUP0] = { + .name = "CPU_GROUP_0", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU0), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_0, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP1] = { + .name = "CPU_GROUP_1", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU1), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_1, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_1), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP2] = { + .name = "CPU_GROUP_2", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU2), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_2, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_2), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP3] = { + .name = "CPU_GROUP_3", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU3), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_3, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_3), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *css_clock_get_element_table + (fwk_id_t module_id) +{ + return css_clock_element_table; +} + +const struct fwk_module_config config_css_clock = { + .get_element_table = css_clock_get_element_table, +}; -- GitLab From dabc1f3d33000ad41261dae480a3f5808b33fae0 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 09:03:38 +0530 Subject: [PATCH 18/34] product/rddanielxlr: add helper functions to obtain platform topology Functions to obtain the platform topology information such as core count, cluster count help in adding configuration data dynamically and can be used by modules to add the configuration data dynamically. Change-Id: I5ab8c5dbc50d9695e38ea3a5cc6b047b28b724c0 Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/rddanielxlr_core.h | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 product/rddanielxlr/include/rddanielxlr_core.h diff --git a/product/rddanielxlr/include/rddanielxlr_core.h b/product/rddanielxlr/include/rddanielxlr_core.h new file mode 100644 index 000000000..539df82ca --- /dev/null +++ b/product/rddanielxlr/include/rddanielxlr_core.h @@ -0,0 +1,37 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIELXLR_CORE_H +#define RDDANIELXLR_CORE_H + +#include + +#define RDDANIELXLR_CORE_PER_CLUSTER_MAX 1 + +#define CORES_PER_CLUSTER 1 +#define NUMBER_OF_CLUSTERS 4 + +static inline unsigned int rddanielxlr_core_get_cluster_count(void) +{ + return NUMBER_OF_CLUSTERS; +} + +static inline unsigned int rddanielxlr_core_get_core_per_cluster_count( + unsigned int cluster) +{ + fwk_assert(cluster < rddanielxlr_core_get_cluster_count()); + + return CORES_PER_CLUSTER; +} + +static inline unsigned int rddanielxlr_core_get_core_count(void) +{ + return rddanielxlr_core_get_core_per_cluster_count(0) * + rddanielxlr_core_get_cluster_count(); +} + +#endif /* RDDANIELXLR_CORE_H */ -- GitLab From 2c4ab95910ac423900f1b5257dfa335403581158 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 10:26:11 +0530 Subject: [PATCH 19/34] product/rddanielxlr: add configuration data for power domain and ppu modules Provide the config data such as ppu base addresses and irq map for the ppu driver and config data for power domain hal to construct the power domain tree. Change-Id: Ide8690fe24631f6898f1089706642d05e58938d5 Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/config_power_domain.h | 28 +++ .../include/rddanielxlr_power_domain.h | 25 +++ product/rddanielxlr/include/scp_css_mmap.h | 7 + .../scp_ramfw/config_power_domain.c | 212 ++++++++++++++++++ product/rddanielxlr/scp_ramfw/config_ppu_v1.c | 155 +++++++++++++ 5 files changed, 427 insertions(+) create mode 100644 product/rddanielxlr/include/config_power_domain.h create mode 100644 product/rddanielxlr/include/rddanielxlr_power_domain.h create mode 100644 product/rddanielxlr/scp_ramfw/config_power_domain.c create mode 100644 product/rddanielxlr/scp_ramfw/config_ppu_v1.c diff --git a/product/rddanielxlr/include/config_power_domain.h b/product/rddanielxlr/include/config_power_domain.h new file mode 100644 index 000000000..720abdb1a --- /dev/null +++ b/product/rddanielxlr/include/config_power_domain.h @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_POWER_DOMAIN_H +#define CONFIG_POWER_DOMAIN_H + +/* + * Power domain indices for the statically defined domains used for: + * - Indexing the domains in the rddanielxlr_power_domain_static_element_table + * - Indexing the SYSTOP children in the power domain tree + * + * When calculating a power domain element index, use the formula: + * core_count + pd_static_dev_idx + */ +enum pd_static_dev_idx { + PD_STATIC_DEV_IDX_CLUSTER0, + PD_STATIC_DEV_IDX_CLUSTER1, + PD_STATIC_DEV_IDX_CLUSTER2, + PD_STATIC_DEV_IDX_CLUSTER3, + PD_STATIC_DEV_IDX_SYSTOP, + PD_STATIC_DEV_IDX_COUNT +}; + +#endif /* CONFIG_POWER_DOMAIN_H */ diff --git a/product/rddanielxlr/include/rddanielxlr_power_domain.h b/product/rddanielxlr/include/rddanielxlr_power_domain.h new file mode 100644 index 000000000..19044efac --- /dev/null +++ b/product/rddanielxlr/include/rddanielxlr_power_domain.h @@ -0,0 +1,25 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIELXLR_POWER_DOMAIN_H +#define RDDANIELXLR_POWER_DOMAIN_H + +#include + +/*! Mask for the cluster valid power states */ +#define RDDANIELXLR_CLUSTER_VALID_STATE_MASK ( \ + MOD_PD_STATE_OFF_MASK | \ + MOD_PD_STATE_ON_MASK \ + ) + +/*! Mask for the core valid power states */ +#define RDDANIELXLR_CORE_VALID_STATE_MASK ( \ + MOD_PD_STATE_OFF_MASK | \ + MOD_PD_STATE_ON_MASK \ + ) + +#endif /* RDDANIELXLR_POWER_DOMAIN_H */ diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index db8622a65..f59a172c9 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -20,4 +20,11 @@ #define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ + 0x40000) +#define SCP_PPU_SCP_BASE (SCP_PIK_SCP_BASE + 0x1000) + +#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000) +#define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000) + +#define SCP_PPU_BASE(n) (SCP_PIK_CLUSTER_BASE(n) + 0x2000) + #endif /* SCP_CSS_MMAP_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_power_domain.c b/product/rddanielxlr/scp_ramfw/config_power_domain.c new file mode 100644 index 000000000..ad7ceae5d --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_power_domain.c @@ -0,0 +1,212 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "config_power_domain.h" +#include "rddanielxlr_core.h" +#include "rddanielxlr_power_domain.h" + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +/* Maximum power domain name size including the null terminator */ +#define PD_NAME_SIZE 12 + +/* Mask of the allowed states for the systop power domain */ +static const uint32_t systop_allowed_state_mask_table[] = { + [0] = MOD_PD_STATE_ON_MASK +}; + +/* + * Mask of the allowed states for the cluster power domain depending on the + * system states. + */ +static const uint32_t cluster_pd_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = RDDANIELXLR_CLUSTER_VALID_STATE_MASK, +}; + +/* Mask of the allowed states for a core depending on the cluster states. */ +static const uint32_t core_pd_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MOD_PD_STATE_ON] = RDDANIELXLR_CORE_VALID_STATE_MASK, +}; + +/* Power module specific configuration data (none) */ +static const struct mod_power_domain_config + rddanielxlr_power_domain_config = { 0 }; + +static struct fwk_element rddanielxlr_power_domain_static_element_table[] = { + [PD_STATIC_DEV_IDX_CLUSTER0] = { + .name = "CLUS0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER0, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER1] = { + .name = "CLUS1", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER1, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER2] = { + .name = "CLUS2", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER2, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER3] = { + .name = "CLUS3", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER3, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_SYSTOP] = { + .name = "SYSTOP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_2, 0, 0, 0, 0), + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) + }), + }, +}; + +/* + * Function definitions with internal linkage + */ +static const struct fwk_element *rddanielxlr_power_domain_get_element_table + (fwk_id_t module_id) +{ + struct fwk_element *element_table, *element; + struct mod_power_domain_element_config *pd_config_table, *pd_config; + unsigned int core_idx; + unsigned int cluster_idx; + unsigned int core_count; + unsigned int cluster_count; + unsigned int core_element_count = 0; + + core_count = rddanielxlr_core_get_core_count(); + cluster_count = rddanielxlr_core_get_cluster_count(); + + element_table = fwk_mm_calloc( + core_count + + FWK_ARRAY_SIZE(rddanielxlr_power_domain_static_element_table) + + 1, /* Terminator */ + sizeof(struct fwk_element)); + if (element_table == NULL) + return NULL; + + pd_config_table = fwk_mm_calloc(core_count, + sizeof(struct mod_power_domain_element_config)); + if (pd_config_table == NULL) + return NULL; + + for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { + for (core_idx = 0; + core_idx < rddanielxlr_core_get_core_per_cluster_count(cluster_idx); + core_idx++) { + + element = &element_table[core_element_count]; + pd_config = &pd_config_table[core_element_count]; + + element->name = fwk_mm_alloc(PD_NAME_SIZE, 1); + if (element->name == NULL) + return NULL; + + snprintf((char *)element->name, PD_NAME_SIZE, "CLUS%uCORE%u", + cluster_idx, core_idx); + + element->data = pd_config; + + pd_config->attributes.pd_type = MOD_PD_TYPE_CORE; + pd_config->tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_0, 0, 0, cluster_idx, core_idx); + pd_config->driver_id = + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + core_element_count); + pd_config->api_id = FWK_ID_API( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER); + pd_config->allowed_state_mask_table = + core_pd_allowed_state_mask_table; + pd_config->allowed_state_mask_table_size = + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table); + core_element_count++; + } + + /* Define the driver id for the cluster */ + pd_config = (struct mod_power_domain_element_config *) + rddanielxlr_power_domain_static_element_table[cluster_idx].data; + pd_config->driver_id = + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + (core_count + cluster_idx)); + } + + memcpy(element_table + core_count, + rddanielxlr_power_domain_static_element_table, + sizeof(rddanielxlr_power_domain_static_element_table)); + + return element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_power_domain = { + .get_element_table = rddanielxlr_power_domain_get_element_table, + .data = &rddanielxlr_power_domain_config, +}; diff --git a/product/rddanielxlr/scp_ramfw/config_ppu_v1.c b/product/rddanielxlr/scp_ramfw/config_ppu_v1.c new file mode 100644 index 000000000..6b1dd8516 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_ppu_v1.c @@ -0,0 +1,155 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_power_domain.h" +#include "rddanielxlr_core.h" +#include "scp_css_mmap.h" + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Maximum PPU core name size including the null terminator */ +#define PPU_CORE_NAME_SIZE 12 + +/* Maximum PPU cluster name size including the null terminator */ +#define PPU_CLUS_NAME_SIZE 6 + +/* Module configuration data */ +static struct mod_ppu_v1_config ppu_v1_config_data = { + .pd_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), +}; + +static struct fwk_element ppu_v1_system_element_table[] = { + [0] = { + .name = "SYS0", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS0_BASE, + .observer_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { + .name = "SYS1", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS1_BASE, + .observer_id = FWK_ID_NONE_INIT, + }), + }, +}; + +static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) +{ + struct fwk_element *element_table, *element; + struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; + unsigned int core_idx; + unsigned int cluster_idx; + unsigned int core_count; + unsigned int cluster_count; + unsigned int core_element_count = 0; + + core_count = rddanielxlr_core_get_core_count(); + cluster_count = rddanielxlr_core_get_cluster_count(); + + /* + * Allocate element descriptors based on: + * Number of cores + * + Number of cluster descriptors + * + Number of system power domain descriptors + * + 1 terminator descriptor + */ + element_table = fwk_mm_calloc(core_count + cluster_count + + FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, + sizeof(struct fwk_element)); + if (element_table == NULL) + return NULL; + + pd_config_table = fwk_mm_calloc(core_count + cluster_count, + sizeof(struct mod_ppu_v1_pd_config)); + if (pd_config_table == NULL) + return NULL; + + for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { + for (core_idx = 0; + core_idx < rddanielxlr_core_get_core_per_cluster_count(cluster_idx); + core_idx++) { + element = &element_table[core_element_count]; + pd_config = &pd_config_table[core_element_count]; + + element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); + if (element->name == NULL) + return NULL; + + snprintf((char *)element->name, PPU_CORE_NAME_SIZE, "CLUS%uCORE%u", + cluster_idx, core_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CORE; + pd_config->ppu.reg_base = SCP_PPU_BASE(cluster_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->cluster_id = + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + (core_count + cluster_idx)); + pd_config->observer_id = FWK_ID_NONE; + core_element_count++; + } + + element = &element_table[core_count + cluster_idx]; + pd_config = &pd_config_table[core_count + cluster_idx]; + + element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); + if (element->name == NULL) + return NULL; + + snprintf((char *)element->name, PPU_CLUS_NAME_SIZE, "CLUS%u", + cluster_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CLUSTER; + pd_config->ppu.reg_base = SCP_PPU_BASE(cluster_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->observer_id = FWK_ID_NONE; + pd_config->observer_api = FWK_ID_NONE; + } + + memcpy(&element_table[core_count + cluster_count], + ppu_v1_system_element_table, + sizeof(ppu_v1_system_element_table)); + + /* + * Configure pd_source_id with the SYSTOP identifier from the power domain + * module which is dynamically defined based on the number of cores. + */ + ppu_v1_config_data.pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + core_count + PD_STATIC_DEV_IDX_SYSTOP); + + return element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_ppu_v1 = { + .get_element_table = ppu_v1_get_element_table, + .data = &ppu_v1_config_data, +}; -- GitLab From d32a39abed329785593e40626809f975a018960f Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 10:33:43 +0530 Subject: [PATCH 20/34] product/rddanielxlr: add configuration data for Clock HAL Provide the configuration data for clock hal which includes the clock driver id, api id and the power domain source. Change-Id: I6c3e50a087aa40b46087a0893f1f7b108eb20979 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/clock_soc.h | 12 +++ product/rddanielxlr/scp_ramfw/config_clock.c | 97 ++++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_clock.c diff --git a/product/rddanielxlr/include/clock_soc.h b/product/rddanielxlr/include/clock_soc.h index 2b8b27573..e57f26f39 100644 --- a/product/rddanielxlr/include/clock_soc.h +++ b/product/rddanielxlr/include/clock_soc.h @@ -56,4 +56,16 @@ enum clock_css_idx { CLOCK_CSS_IDX_COUNT }; +/* + * Clock indexes. + */ +enum clock_idx { + CLOCK_IDX_INTERCONNECT, + CLOCK_IDX_CPU_GROUP0, + CLOCK_IDX_CPU_GROUP1, + CLOCK_IDX_CPU_GROUP2, + CLOCK_IDX_CPU_GROUP3, + CLOCK_IDX_COUNT +}; + #endif /* CLOCK_SOC_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_clock.c b/product/rddanielxlr/scp_ramfw/config_clock.c new file mode 100644 index 000000000..df35fa458 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_clock.c @@ -0,0 +1,97 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "config_power_domain.h" +#include "rddanielxlr_core.h" + +#include +#include +#include +#include + +#include +#include +#include +#include + +static const struct fwk_element clock_dev_desc_table[] = { + [CLOCK_IDX_INTERCONNECT] = { + .name = "Interconnect", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, + CLOCK_PIK_IDX_INTERCONNECT), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP0] = { + .name = "CPU_GROUP0", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP1] = { + .name = "CPU_GROUP1", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP1), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP2] = { + .name = "CPU_GROUP2", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP2), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP3] = { + .name = "CPU_GROUP3", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP3), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id) +{ + unsigned int i; + struct mod_clock_dev_config *dev_config; + + for (i = 0; i < CLOCK_IDX_COUNT; i++) { + dev_config = + (struct mod_clock_dev_config *)clock_dev_desc_table[i].data; + dev_config->pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + rddanielxlr_core_get_core_count() + PD_STATIC_DEV_IDX_SYSTOP); + } + + return clock_dev_desc_table; +} + +const struct fwk_module_config config_clock = { + .get_element_table = clock_get_dev_desc_table, + .data = &((struct mod_clock_config) { + .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), + .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION), + }), +}; -- GitLab From 91b3d875d1a2db617b9dbca1897bf922f049d2f3 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 10:46:25 +0530 Subject: [PATCH 21/34] product/rddanielxlr: add configuration data for cmn rhodes driver CMN-Rhodes is the interconnect used in RD-Daniel XLR platform. Add configuration data such as base address, memory region map, SNF table and mesh sizes. Change-Id: Ic654b6c57b8eddc36a75675f0cc5b92c75d6d565 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_css_mmap.h | 2 + product/rddanielxlr/include/scp_mmap.h | 1 + .../rddanielxlr/scp_ramfw/config_cmn_rhodes.c | 587 ++++++++++++++++++ 3 files changed, 590 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_cmn_rhodes.c diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index f59a172c9..6eaaa0daa 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -10,6 +10,8 @@ #include "scp_mmap.h" +#define SCP_CMN_RHODES_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000) + #define SCP_SID_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A4A0000) #define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) diff --git a/product/rddanielxlr/include/scp_mmap.h b/product/rddanielxlr/include/scp_mmap.h index cac5edafa..d19529d16 100644 --- a/product/rddanielxlr/include/scp_mmap.h +++ b/product/rddanielxlr/include/scp_mmap.h @@ -15,6 +15,7 @@ #define SCP_SOC_EXPANSION3_BASE 0x40000000 #define SCP_PERIPHERAL_BASE 0x44000000 #define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE 0x50000000 +#define SCP_SYSTEM_ACCESS_PORT0_BASE 0x60000000 #define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 #endif /* SCP_MMAP_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_cmn_rhodes.c b/product/rddanielxlr/scp_ramfw/config_cmn_rhodes.c new file mode 100644 index 000000000..d04002820 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_cmn_rhodes.c @@ -0,0 +1,587 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_css_mmap.h" + +#include + +#include +#include +#include + +/* + * CMN_RHODES nodes + */ +#define MEM_CNTRL0_ID 332 +#define MEM_CNTRL1_ID 333 +#define MEM_CNTRL2_ID 16 +#define MEM_CNTRL3_ID 17 +#define MEM_CNTRL4_ID 32 +#define MEM_CNTRL5_ID 33 +#define MEM_CNTRL6_ID 348 +#define MEM_CNTRL7_ID 349 +#define NODE_ID_HND 4 +#define NODE_ID_SBSX 340 + +/* + * CCIX Related macros + */ +#define CHIP_0 0 +#define CHIP_1 1 +#define CHIP_2 2 +#define CHIP_3 3 +#define CCIX_PORT_0 0 +#define CCIX_PORT_1 1 +#define CCIX_PORT_2 2 +#define CCIX_PORT_3 3 +#define CCIX_PORT_4 4 +#define CCIX_PORT_5 5 + +#define RNF_PER_CHIP 16 +#define CHIP_COUNT 4 + +static const unsigned int snf_table_0_2[] = { + MEM_CNTRL2_ID, /* Maps to HN-F logical node 0 */ + MEM_CNTRL2_ID, /* Maps to HN-F logical node 1 */ + MEM_CNTRL2_ID, /* Maps to HN-F logical node 2 */ + MEM_CNTRL2_ID, /* Maps to HN-F logical node 3 */ + MEM_CNTRL2_ID, /* Maps to HN-F logical node 4 */ + MEM_CNTRL2_ID, /* Maps to HN-F logical node 5 */ + MEM_CNTRL2_ID, /* Maps to HN-F logical node 6 */ + MEM_CNTRL2_ID, /* Maps to HN-F logical node 7 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 8 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 9 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 10 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 11 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 12 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 13 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 14 */ + MEM_CNTRL3_ID, /* Maps to HN-F logical node 15 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 16 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 17 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 18 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 19 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 20 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 21 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 22 */ + MEM_CNTRL4_ID, /* Maps to HN-F logical node 23 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 24 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 25 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 26 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 27 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 28 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 29 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 30 */ + MEM_CNTRL5_ID, /* Maps to HN-F logical node 31 */ +}; + +static const unsigned int snf_table_1_3[] = { + MEM_CNTRL0_ID, /* Maps to HN-F logical node 0 */ + MEM_CNTRL0_ID, /* Maps to HN-F logical node 1 */ + MEM_CNTRL0_ID, /* Maps to HN-F logical node 2 */ + MEM_CNTRL0_ID, /* Maps to HN-F logical node 3 */ + MEM_CNTRL0_ID, /* Maps to HN-F logical node 4 */ + MEM_CNTRL0_ID, /* Maps to HN-F logical node 5 */ + MEM_CNTRL0_ID, /* Maps to HN-F logical node 6 */ + MEM_CNTRL0_ID, /* Maps to HN-F logical node 7 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 8 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 9 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 10 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 11 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 12 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 13 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 14 */ + MEM_CNTRL1_ID, /* Maps to HN-F logical node 15 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 16 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 17 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 18 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 19 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 20 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 21 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 22 */ + MEM_CNTRL6_ID, /* Maps to HN-F logical node 23 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 24 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 25 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 26 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 27 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 28 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 29 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 30 */ + MEM_CNTRL7_ID, /* Maps to HN-F logical node 31 */ + }; + + +static const struct mod_cmn_rhodes_mem_region_map mmap[] = { + { + /* + * System cache backed region + * Map: 0x0000_0000_0000 - 0x00FF_FFFFF_FFFF (16 TB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(16) * FWK_TIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_SYSCACHE, + }, + { + /* + * Boot region + * Map: 0x0000_0000_0000 - 0x0000_0001_FFFF (128 MB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_RHODES_REGION_TYPE_SYSCACHE_SUB, + .node_id = NODE_ID_SBSX, + }, + { + /* + * Peripherals + * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB) + */ + .base = UINT64_C(0x0008000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_1000_0000 - 0x00_1FFF_FFFF (256 MB) + */ + .base = UINT64_C(0x0010000000), + .size = UINT64_C(256) * FWK_MIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_2000_0000 - 0x00_3FFF_FFFF (512 MB) + */ + .base = UINT64_C(0x0020000000), + .size = UINT64_C(512) * FWK_MIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_4000_0000 - 0x00_7FFF_FFFF (1 GB) + */ + .base = UINT64_C(0x0040000000), + .size = UINT64_C(1) * FWK_GIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, +}; + +/* CCIX Related configuration data */ + +/* Chip-0 Config data */ +static const struct mod_cmn_rhodes_ccix_config ccix_config_table_chip_0[] = { + { + .ldid = CCIX_PORT_0, + .haid = (RNF_PER_CHIP * CHIP_0) + CCIX_PORT_0, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x40000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x40000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_2) + CCIX_PORT_5, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_2), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_2) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_2, + .haid = (RNF_PER_CHIP * CHIP_0) + CCIX_PORT_2, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x80000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x80000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_3) + CCIX_PORT_3, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_3), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_3) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_4, + .haid = (RNF_PER_CHIP * CHIP_0) + CCIX_PORT_4, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0xC0000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0xC0000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_1) + CCIX_PORT_1, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_1), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_1) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + } +}; + +/* Chip-1 Config data */ +static const struct mod_cmn_rhodes_ccix_config ccix_config_table_chip_1[] = { + { + .ldid = CCIX_PORT_0, + .haid = (RNF_PER_CHIP * CHIP_1) + CCIX_PORT_0, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x00000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_0) + CCIX_PORT_5, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_0), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_0) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_2, + .haid = (RNF_PER_CHIP * CHIP_1) + CCIX_PORT_2, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x80000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x80000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_2) + CCIX_PORT_3, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_2), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_2) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_4, + .haid = (RNF_PER_CHIP * CHIP_1) + CCIX_PORT_4, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0xC0000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0xC0000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_3) + CCIX_PORT_1, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_3), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_3) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, +}; + +/* Chip-2 Config data */ +static const struct mod_cmn_rhodes_ccix_config ccix_config_table_chip_2[] = { + { + .ldid = CCIX_PORT_0, + .haid = (RNF_PER_CHIP * CHIP_2) + CCIX_PORT_0, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x00000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_3) + CCIX_PORT_5, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_3), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_3) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_2, + .haid = (RNF_PER_CHIP * CHIP_2) + CCIX_PORT_2, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x40000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x40000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_1) + CCIX_PORT_3, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_1), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_1) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_4, + .haid = (RNF_PER_CHIP * CHIP_2) + CCIX_PORT_4, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0xC0000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0xC0000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_0) + CCIX_PORT_1, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_0), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_0) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, +}; + +/* Chip-3 Config data */ +static const struct mod_cmn_rhodes_ccix_config ccix_config_table_chip_3[] = { + { + .ldid = CCIX_PORT_0, + .haid = (RNF_PER_CHIP * CHIP_3) + CCIX_PORT_0, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x00000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_1) + CCIX_PORT_5, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_1), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_1) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_2, + .haid = (RNF_PER_CHIP * CHIP_3) + CCIX_PORT_2, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x40000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x40000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_0) + CCIX_PORT_3, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_0), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_0) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, + { + .ldid = CCIX_PORT_4, + .haid = (RNF_PER_CHIP * CHIP_3) + CCIX_PORT_4, + .remote_rnf_count = RNF_PER_CHIP * (CHIP_COUNT - 1), + .remote_mmap_table = { + .base = UINT64_C(0x80000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_REGION_TYPE_CCIX, + }, + .ra_mmap_table = { + { + .base = UINT64_C(0x80000000000), + .size = UINT64_C(4) * FWK_TIB, + .remote_haid = (RNF_PER_CHIP * CHIP_2) + CCIX_PORT_1, + }, + { 0 } + }, + .remote_agentid_to_linkid_map = { + { + .remote_agentid_start = (RNF_PER_CHIP * CHIP_2), + .remote_agentid_end = (RNF_PER_CHIP * CHIP_2) + RNF_PER_CHIP - 1 + }, + }, + .smp_mode = true, + }, +}; + +static const struct fwk_element cmn_rhodes_device_table[] = { + [0] = { + .name = "Chip-0 CMN-Rhodes Mesh Config", + .data = &((struct mod_cmn_rhodes_config) { + .base = SCP_CMN_RHODES_BASE, + .mesh_size_x = 6, + .mesh_size_y = 6, + .hnd_node_id = NODE_ID_HND, + .snf_table = snf_table_0_2, + .snf_count = FWK_ARRAY_SIZE(snf_table_0_2), + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .ccix_config_table = ccix_config_table_chip_0, + .ccix_table_count = FWK_ARRAY_SIZE(ccix_config_table_chip_0), + .chip_addr_space = UINT64_C(4) * FWK_TIB, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + .hnf_cal_mode = true, + }) + }, + [1] = { + .name = "Chip-1 CMN-Rhodes Mesh Config", + .data = &((struct mod_cmn_rhodes_config) { + .base = SCP_CMN_RHODES_BASE, + .mesh_size_x = 6, + .mesh_size_y = 6, + .hnd_node_id = NODE_ID_HND, + .snf_table = snf_table_1_3, + .snf_count = FWK_ARRAY_SIZE(snf_table_1_3), + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .ccix_config_table = ccix_config_table_chip_1, + .ccix_table_count = FWK_ARRAY_SIZE(ccix_config_table_chip_1), + .chip_addr_space = UINT64_C(4) * FWK_TIB, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + .hnf_cal_mode = true, + }) + }, + [2] = { + .name = "Chip-2 CMN-Rhodes Mesh Config", + .data = &((struct mod_cmn_rhodes_config) { + .base = SCP_CMN_RHODES_BASE, + .mesh_size_x = 6, + .mesh_size_y = 6, + .hnd_node_id = NODE_ID_HND, + .snf_table = snf_table_0_2, + .snf_count = FWK_ARRAY_SIZE(snf_table_0_2), + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .ccix_config_table = ccix_config_table_chip_2, + .ccix_table_count = FWK_ARRAY_SIZE(ccix_config_table_chip_2), + .chip_addr_space = UINT64_C(4) * FWK_TIB, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + .hnf_cal_mode = true, + }) + }, + [3] = { + .name = "Chip-3 CMN-Rhodes Mesh Config", + .data = &((struct mod_cmn_rhodes_config) { + .base = SCP_CMN_RHODES_BASE, + .mesh_size_x = 6, + .mesh_size_y = 6, + .hnd_node_id = NODE_ID_HND, + .snf_table = snf_table_1_3, + .snf_count = FWK_ARRAY_SIZE(snf_table_1_3), + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .ccix_config_table = ccix_config_table_chip_3, + .ccix_table_count = FWK_ARRAY_SIZE(ccix_config_table_chip_3), + .chip_addr_space = UINT64_C(4) * FWK_TIB, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + .hnf_cal_mode = true, + }) + }, + [4] = { 0 } +}; + +static const struct fwk_element *cmn_rhodes_get_device_table(fwk_id_t module_id) +{ + return cmn_rhodes_device_table; +} + +const struct fwk_module_config config_cmn_rhodes = { + .get_element_table = cmn_rhodes_get_device_table, + .data = NULL +}; -- GitLab From cce7baae33d21449d44aa6e76288ba2b25ac78a6 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 29 Jan 2020 16:33:39 +0530 Subject: [PATCH 22/34] product/rddanielxlr: add configuration data for generic timer driver The configuration data for generic timer driver includes the base adresses of timer register, counter register and control register along with the initial frequency and the id of clock device on which the timer depends. Change-Id: Ida03265a9cb392d4b487560928fc089294080c6d Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_css_mmap.h | 3 ++ product/rddanielxlr/scp_ramfw/config_gtimer.c | 43 +++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_gtimer.c diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index 6eaaa0daa..7e6de297e 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -12,8 +12,11 @@ #define SCP_CMN_RHODES_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000) +#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000) #define SCP_SID_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A4A0000) +#define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000) +#define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000) #define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) #define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) diff --git a/product/rddanielxlr/scp_ramfw/config_gtimer.c b/product/rddanielxlr/scp_ramfw/config_gtimer.c new file mode 100644 index 000000000..e3325a171 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_gtimer.c @@ -0,0 +1,43 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_css_mmap.h" + +#include + +#include +#include +#include +#include + +/* + * Generic timer driver config + */ +static const struct fwk_element gtimer_dev_table[] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config) { + .hw_timer = SCP_REFCLK_CNTBASE0_BASE, + .hw_counter = SCP_REFCLK_CNTCTL_BASE, + .control = SCP_REFCLK_CNTCONTROL_BASE, + .frequency = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT) + }) + }, + [1] = { 0 }, +}; + +static const struct fwk_element *gtimer_get_dev_table(fwk_id_t module_id) +{ + return gtimer_dev_table; +} + +const struct fwk_module_config config_gtimer = { + .get_element_table = gtimer_get_dev_table, +}; -- GitLab From eb4a93090319cc87eb463667eb48dfc71e4dc584 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 11:57:37 +0530 Subject: [PATCH 23/34] product/rddanielxlr: add configuration data for timer hal Provide the configuration data for timer hal which includes the id for the timer element and the IRQ number. Change-Id: I3ccee22cfb78ecb164cd3c73fdb01d82c0aa735a Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/scp_rddanielxlr_irq.h | 15 +++++++ product/rddanielxlr/scp_ramfw/config_timer.c | 39 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 product/rddanielxlr/include/scp_rddanielxlr_irq.h create mode 100644 product/rddanielxlr/scp_ramfw/config_timer.c diff --git a/product/rddanielxlr/include/scp_rddanielxlr_irq.h b/product/rddanielxlr/include/scp_rddanielxlr_irq.h new file mode 100644 index 000000000..cc474a5f4 --- /dev/null +++ b/product/rddanielxlr/include/scp_rddanielxlr_irq.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_RDDANIELXLR_IRQ_H +#define SCP_RDDANIELXLR_IRQ_H + +enum scp_rddanielxlr_interrupt { + TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ +}; + +#endif /* SCP_RDDANIELXLR_IRQ_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_timer.c b/product/rddanielxlr/scp_ramfw/config_timer.c new file mode 100644 index 000000000..d6e9f2ea3 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_timer.c @@ -0,0 +1,39 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_rddanielxlr_irq.h" + +#include + +#include +#include +#include +#include + +/* + * Timer HAL config + */ +static const struct fwk_element timer_dev_table[] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config) { + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = TIMREFCLK_IRQ, + }), + .sub_element_count = 8, /* Number of alarms */ + }, + [1] = { 0 }, +}; + +static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) +{ + return timer_dev_table; +} + +const struct fwk_module_config config_timer = { + .get_element_table = timer_get_dev_table, +}; -- GitLab From 052084f132100251ecf1242f427a49347107b48a Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 29 Jan 2020 16:35:05 +0530 Subject: [PATCH 24/34] product/rddanielxlr: add configuration data for MHUv2 driver Provide the details of the MHUv2 channels used for messaging from the application cores to the SCP. Change-Id: I9f909502c79d553a9fa42cc9396e73266d481699 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/scp_css_mmap.h | 4 ++ .../rddanielxlr/include/scp_rddanielxlr_irq.h | 1 + .../rddanielxlr/include/scp_rddanielxlr_mhu.h | 19 +++++++++ product/rddanielxlr/scp_ramfw/config_mhu2.c | 39 +++++++++++++++++++ 4 files changed, 63 insertions(+) create mode 100644 product/rddanielxlr/include/scp_rddanielxlr_mhu.h create mode 100644 product/rddanielxlr/scp_ramfw/config_mhu2.c diff --git a/product/rddanielxlr/include/scp_css_mmap.h b/product/rddanielxlr/include/scp_css_mmap.h index 7e6de297e..c326636f3 100644 --- a/product/rddanielxlr/include/scp_css_mmap.h +++ b/product/rddanielxlr/include/scp_css_mmap.h @@ -18,6 +18,7 @@ #define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000) #define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000) #define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) +#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE + 0x1000000) #define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) #define SCP_PIK_CLUSTER_BASE(n) ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ @@ -32,4 +33,7 @@ #define SCP_PPU_BASE(n) (SCP_PIK_CLUSTER_BASE(n) + 0x2000) +#define SCP_MHU_SCP_AP_SND_S_CLUS0 (SCP_MHU_AP_BASE + 0x400000) +#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (SCP_MHU_AP_BASE + 0x410000) + #endif /* SCP_CSS_MMAP_H */ diff --git a/product/rddanielxlr/include/scp_rddanielxlr_irq.h b/product/rddanielxlr/include/scp_rddanielxlr_irq.h index cc474a5f4..e286e6bb9 100644 --- a/product/rddanielxlr/include/scp_rddanielxlr_irq.h +++ b/product/rddanielxlr/include/scp_rddanielxlr_irq.h @@ -10,6 +10,7 @@ enum scp_rddanielxlr_interrupt { TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + MHU_AP_SEC_IRQ = 83, /* MHU secure irq bewteen SCP and AP */ }; #endif /* SCP_RDDANIELXLR_IRQ_H */ diff --git a/product/rddanielxlr/include/scp_rddanielxlr_mhu.h b/product/rddanielxlr/include/scp_rddanielxlr_mhu.h new file mode 100644 index 000000000..1d65dbe16 --- /dev/null +++ b/product/rddanielxlr/include/scp_rddanielxlr_mhu.h @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MHU module device indexes. + */ + +#ifndef SCP_RDDANIELXLR_MHU_H +#define SCP_RDDANIELXLR_MHU_H + +enum scp_rddanielxlr_mhu_device_idx { + SCP_RDDANIELXLR_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, + SCP_RDDANIELXLR_MHU_DEVICE_IDX_COUNT +}; + +#endif /* SCP_RDDANIELXLR_MHU_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_mhu2.c b/product/rddanielxlr/scp_ramfw/config_mhu2.c new file mode 100644 index 000000000..130295b56 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_mhu2.c @@ -0,0 +1,39 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_css_mmap.h" +#include "scp_rddanielxlr_irq.h" +#include "scp_rddanielxlr_mhu.h" + +#include + +#include +#include +#include + +static const struct fwk_element mhu_element_table[] = { + [SCP_RDDANIELXLR_MHU_DEVICE_IDX_SCP_AP_S_CLUS0] = { + .name = "MHU_SCP_AP_S", + .sub_element_count = 1, + .data = &((struct mod_mhu2_channel_config) { + .irq = MHU_AP_SEC_IRQ, + .recv = SCP_MHU_SCP_AP_RCV_S_CLUS0, + .send = SCP_MHU_SCP_AP_SND_S_CLUS0, + .channel = 0, + }) + }, + [SCP_RDDANIELXLR_MHU_DEVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *mhu_get_element_table(fwk_id_t module_id) +{ + return mhu_element_table; +} + +const struct fwk_module_config config_mhu2 = { + .get_element_table = mhu_get_element_table, +}; -- GitLab From 81db4403adce6695b660a73a958ea94a4107709c Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 12:33:04 +0530 Subject: [PATCH 25/34] product/rddanielxlr: add configuration data for AP context module AP context module is used to zero out the shared memory region used by SCP and AP on every initializaion or interconnect reset. Provide the base address and size of the shared memory region and also the clock id of the interconnect to subscribe to. Change-Id: I6e4654689c6425aa533847d2865d23dcf47c1d11 Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/scp_software_mmap.h | 10 +++++++ .../rddanielxlr/scp_ramfw/config_apcontext.c | 29 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_apcontext.c diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h index d7ef18830..0a324075b 100644 --- a/product/rddanielxlr/include/scp_software_mmap.h +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -26,4 +26,14 @@ #define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + \ 0x06000000) +/* Secure Shared memory between AP and SCP */ +#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE) +#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB) + +/* AP Context Area */ +#define SCP_AP_CONTEXT_BASE (SCP_AP_SHARED_SECURE_BASE + \ + SCP_AP_SHARED_SECURE_SIZE - \ + SCP_AP_CONTEXT_SIZE) +#define SCP_AP_CONTEXT_SIZE (64) + #endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_apcontext.c b/product/rddanielxlr/scp_ramfw/config_apcontext.c new file mode 100644 index 000000000..5232cfc08 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_apcontext.c @@ -0,0 +1,29 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_software_mmap.h" + +#include + +#include +#include +#include + +/* + * AP Context module configuration + */ +static const struct mod_apcontext_config apcontext_data = { + .base = SCP_AP_CONTEXT_BASE, + .size = SCP_AP_CONTEXT_SIZE, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), +}; + +struct fwk_module_config config_apcontext = { + .data = &apcontext_data, +}; -- GitLab From 5240719f2ebd67de9f2e4b808baa21bf2db937f1 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 12:47:27 +0530 Subject: [PATCH 26/34] product/rddanielxlr: add configuration data for sds service module SDS module is used to pass runtime data from SCP firmware to the firmware on AP core using shared memory. Provide the base address and size for the same and also the payloads to be passed. Change-Id: I60956c7d06295c1990d4242e1b33f38d44a24722 Signed-off-by: Aditya Angadi --- product/rddanielxlr/include/rddanielxlr_sds.h | 72 ++++++++++++ .../rddanielxlr/include/scp_software_mmap.h | 4 + product/rddanielxlr/scp_ramfw/config_sds.c | 104 ++++++++++++++++++ 3 files changed, 180 insertions(+) create mode 100644 product/rddanielxlr/include/rddanielxlr_sds.h create mode 100644 product/rddanielxlr/scp_ramfw/config_sds.c diff --git a/product/rddanielxlr/include/rddanielxlr_sds.h b/product/rddanielxlr/include/rddanielxlr_sds.h new file mode 100644 index 000000000..4e03a1480 --- /dev/null +++ b/product/rddanielxlr/include/rddanielxlr_sds.h @@ -0,0 +1,72 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIELXLR_SDS_H +#define RDDANIELXLR_SDS_H + +#include + +/* + * Structure identifiers. + */ +enum rddanielxlr_sds_struct_id { + RDDANIELXLR_SDS_CPU_INFO = + 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIELXLR_SDS_FIRMWARE_VERSION = + 2 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIELXLR_SDS_PLATFORM_ID = + 3 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIELXLR_SDS_RESET_SYNDROME = + 4 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIELXLR_SDS_FEATURE_AVAILABILITY = + 5 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIELXLR_SDS_CPU_BOOTCTR = + 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIELXLR_SDS_CPU_FLAGS = + 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), +}; + +/* + * Structure sizes. + */ +#define RDDANIELXLR_SDS_CPU_INFO_SIZE 4 +#define RDDANIELXLR_SDS_FIRMWARE_VERSION_SIZE 4 +#define RDDANIELXLR_SDS_PLATFORM_ID_SIZE 8 +#define RDDANIELXLR_SDS_RESET_SYNDROME_SIZE 4 +#define RDDANIELXLR_SDS_FEATURE_AVAILABILITY_SIZE 4 +#define RDDANIELXLR_SDS_CPU_BOOTCTR_SIZE 256 +#define RDDANIELXLR_SDS_CPU_FLAGS_SIZE 256 + +/* + * Field masks and offsets for the RDDANIELXLR_SDS_AP_CPU_INFO structure. + */ +#define RDDANIELXLR_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF +#define RDDANIELXLR_SDS_CPU_INFO_PRIMARY_POS 0 + +/* + * Platform information + */ +struct rddaniel_sds_platid { + /* Subsystem part number */ + uint32_t platform_identifier; + /* Platform type information */ + uint32_t platform_type_identifier; +}; + +/* + * Field masks and offsets for the RDDANIELXLR_SDS_FEATURE_AVAILABILITY + * structure. + */ +#define RDDANIELXLR_SDS_FEATURE_FIRMWARE_MASK 0x1 +#define RDDANIELXLR_SDS_FEATURE_DMC_MASK 0x2 +#define RDDANIELXLR_SDS_FEATURE_MESSAGING_MASK 0x4 + +#define RDDANIELXLR_SDS_FEATURE_FIRMWARE_POS 0 +#define RDDANIELXLR_SDS_FEATURE_DMC_POS 1 +#define RDDANIELXLR_SDS_FEATURE_MESSAGING_POS 2 + +#endif /* RDDANIELXLR_SDS_H */ diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h index 0a324075b..025bd0f35 100644 --- a/product/rddanielxlr/include/scp_software_mmap.h +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -36,4 +36,8 @@ SCP_AP_CONTEXT_SIZE) #define SCP_AP_CONTEXT_SIZE (64) +/* SDS Memory Region */ +#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE) +#define SCP_SDS_MEM_SIZE (3520) + #endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_sds.c b/product/rddanielxlr/scp_ramfw/config_sds.c new file mode 100644 index 000000000..0ea38df5a --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_sds.c @@ -0,0 +1,104 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "rddanielxlr_sds.h" +#include "scp_pik.h" +#include "scp_software_mmap.h" + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +static const uint32_t version_packed = FWK_BUILD_VERSION; +static const uint32_t feature_flags; + +const struct mod_sds_config sds_module_config = { + .region_base_address = SCP_SDS_MEM_BASE, + .region_size = SCP_SDS_MEM_SIZE, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT) +}; + +static struct fwk_element sds_element_table[] = { + { + .name = "CPU Info", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIELXLR_SDS_CPU_INFO, + .size = RDDANIELXLR_SDS_CPU_INFO_SIZE, + .finalize = true, + }), + }, + { + .name = "Firmware version", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIELXLR_SDS_FIRMWARE_VERSION, + .size = RDDANIELXLR_SDS_FIRMWARE_VERSION_SIZE, + .payload = &version_packed, + .finalize = true, + }), + }, + { + .name = "Reset Syndrome", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIELXLR_SDS_RESET_SYNDROME, + .size = RDDANIELXLR_SDS_RESET_SYNDROME_SIZE, + .payload = (void *)(&SCP_PIK_PTR->RESET_SYNDROME), + .finalize = true, + }), + }, + { + .name = "Feature Availability", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIELXLR_SDS_FEATURE_AVAILABILITY, + .size = RDDANIELXLR_SDS_FEATURE_AVAILABILITY_SIZE, + .payload = &feature_flags, + .finalize = true, + }), + }, +#ifdef BUILD_HAS_MOD_TEST + { + .name = "Boot Counters", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIELXLR_SDS_CPU_BOOTCTR, + .size = RDDANIELXLR_SDS_CPU_BOOTCTR_SIZE, + .finalize = true, + }), + }, + { + .name = "CPU Flags", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIELXLR_SDS_CPU_FLAGS, + .size = RDDANIELXLR_SDS_CPU_FLAGS_SIZE, + .finalize = true, + }), + }, +#endif + { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) +{ + static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size"); + + return sds_element_table; +} + +struct fwk_module_config config_sds = { + .get_element_table = sds_get_element_table, + .data = &sds_module_config, +}; -- GitLab From 62ca3a3ae7889a134c60c025c67da88505a51360 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 14:38:04 +0530 Subject: [PATCH 27/34] product/rddanielxlr: add configuration data for scmi and smt services Provide configuration data to enable support request for PSCI services from the AP core to the SCMI platform for RD-DanielXLR pltform. At present only the PSCI service for power management is supported. Change-Id: I3aa8f531728cc5eb21a78377fea504ffd2005905 Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/rddanielxlr_scmi.h | 26 ++++++++ .../rddanielxlr/include/scp_software_mmap.h | 7 +++ product/rddanielxlr/scp_ramfw/config_scmi.c | 61 +++++++++++++++++++ product/rddanielxlr/scp_ramfw/config_smt.c | 55 +++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 product/rddanielxlr/include/rddanielxlr_scmi.h create mode 100644 product/rddanielxlr/scp_ramfw/config_scmi.c create mode 100644 product/rddanielxlr/scp_ramfw/config_smt.c diff --git a/product/rddanielxlr/include/rddanielxlr_scmi.h b/product/rddanielxlr/include/rddanielxlr_scmi.h new file mode 100644 index 000000000..f6d14bfbb --- /dev/null +++ b/product/rddanielxlr/include/rddanielxlr_scmi.h @@ -0,0 +1,26 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for SCMI and SMT module configurations. + */ + +#ifndef SCP_RDDANIELXLR_SCMI_H +#define SCP_RDDANIELXLR_SCMI_H + +/* SCMI agent identifiers */ +enum scp_rddanielxlr_scmi_agent_id { + /* 0 is reserved for the platform */ + SCP_SCMI_AGENT_ID_PSCI = 1, +}; + +/* SCMI service indexes */ +enum scp_rddanielxlr_scmi_service_idx { + SCP_RDDANIELXLR_SCMI_SERVICE_IDX_PSCI, + SCP_RDDANIELXLR_SCMI_SERVICE_IDX_COUNT, +}; + +#endif /* SCP_RDDANIELXLR_SCMI_H */ diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h index 025bd0f35..a9eff8d07 100644 --- a/product/rddanielxlr/include/scp_software_mmap.h +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -40,4 +40,11 @@ #define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE) #define SCP_SDS_MEM_SIZE (3520) +/* SCMI Secure Payload Areas */ +#define SCP_SCMI_PAYLOAD_SIZE (128) +#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + \ + SCP_SDS_MEM_SIZE) +#define SCP_SCMI_PAYLOAD_S_P2A_BASE (SCP_SCMI_PAYLOAD_S_A2P_BASE + \ + SCP_SCMI_PAYLOAD_SIZE) + #endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/rddanielxlr/scp_ramfw/config_scmi.c b/product/rddanielxlr/scp_ramfw/config_scmi.c new file mode 100644 index 000000000..424dbc296 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_scmi.c @@ -0,0 +1,61 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "rddanielxlr_scmi.h" + +#include + +#include +#include + +#include +#include +#include +#include +#include + +static const struct fwk_element service_table[] = { + [SCP_RDDANIELXLR_SCMI_SERVICE_IDX_PSCI] = { + .name = "SERVICE0", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_RDDANIELXLR_SCMI_SERVICE_IDX_PSCI), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI, + }), + }, + [SCP_RDDANIELXLR_SCMI_SERVICE_IDX_COUNT] = { 0 } +}; + +static const struct fwk_element *get_service_table(fwk_id_t module_id) +{ + return service_table; +} + +static struct mod_scmi_agent agent_table[] = { + [SCP_SCMI_AGENT_ID_PSCI] = { + .type = SCMI_AGENT_TYPE_PSCI, + .name = "PSCI", + }, +}; + +const struct fwk_module_config config_scmi = { + .get_element_table = get_service_table, + .data = &((struct mod_scmi_config) { + .protocol_count_max = 9, + .agent_count = FWK_ARRAY_SIZE(agent_table), + .agent_table = agent_table, + .vendor_identifier = "arm", + .sub_vendor_identifier = "arm", + }), +}; diff --git a/product/rddanielxlr/scp_ramfw/config_smt.c b/product/rddanielxlr/scp_ramfw/config_smt.c new file mode 100644 index 000000000..99f29ebc6 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_smt.c @@ -0,0 +1,55 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_power_domain.h" +#include "rddanielxlr_core.h" +#include "rddanielxlr_scmi.h" +#include "scp_rddanielxlr_mhu.h" +#include "scp_software_mmap.h" + +#include + +#include +#include +#include +#include + +#include + +static const struct fwk_element smt_element_table[] = { + [SCP_RDDANIELXLR_SCMI_SERVICE_IDX_PSCI] = { + .name = "PSCI", + .data = &((struct mod_smt_channel_config) { + .type = MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = MOD_SMT_POLICY_INIT_MAILBOX | MOD_SMT_POLICY_SECURE, + .mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_S_A2P_BASE, + .mailbox_size = SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_MHU2, + SCP_RDDANIELXLR_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, 0), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), + }) + }, + [SCP_RDDANIELXLR_SCMI_SERVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *smt_get_element_table(fwk_id_t module_id) +{ + unsigned int idx; + struct mod_smt_channel_config *config; + + for (idx = 0; idx < SCP_RDDANIELXLR_SCMI_SERVICE_IDX_COUNT; idx++) { + config = (struct mod_smt_channel_config *)(smt_element_table[idx].data); + config->pd_source_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, + rddanielxlr_core_get_core_count() + PD_STATIC_DEV_IDX_SYSTOP); + } + + return smt_element_table; +} + +const struct fwk_module_config config_smt = { + .get_element_table = smt_get_element_table, +}; -- GitLab From 22a4a6bf7b3634cc4ca0046c8414dfad925fa845 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Thu, 9 Apr 2020 19:58:31 +0530 Subject: [PATCH 28/34] product/rddanielxlr: add configuration data for scmi power domain There is no specific configuration data to be supplied to the scmi power domain module. Change-Id: I5514bd7d84336bb08f76d983a13093a47be4ba5d Signed-off-by: Aditya Angadi --- .../rddanielxlr/scp_ramfw/config_scmi_power_domain.c | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_scmi_power_domain.c diff --git a/product/rddanielxlr/scp_ramfw/config_scmi_power_domain.c b/product/rddanielxlr/scp_ramfw/config_scmi_power_domain.c new file mode 100644 index 000000000..2d344b267 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_scmi_power_domain.c @@ -0,0 +1,11 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* No elements, no module configuration data */ +struct fwk_module_config config_scmi_power_domain = { 0 }; -- GitLab From 49f03dc9ac12c12562070b107c032683cabd342a Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 14:48:07 +0530 Subject: [PATCH 29/34] product/rddanielxlr: add configuration data for scmi system power Provide the configuration data for scmi system power module to manage system states. Change-Id: Icdefbc8b1573fc07a06e20e37c4e3493254d1480 Signed-off-by: Aditya Angadi --- .../scp_ramfw/config_scmi_system_power.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_scmi_system_power.c diff --git a/product/rddanielxlr/scp_ramfw/config_scmi_system_power.c b/product/rddanielxlr/scp_ramfw/config_scmi_system_power.c new file mode 100644 index 000000000..20b225820 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_scmi_system_power.c @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +const struct fwk_module_config config_scmi_system_power = { + .data = &((struct mod_scmi_system_power_config) { + .system_view = MOD_SCMI_SYSTEM_VIEW_FULL, + .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0 + }), +}; -- GitLab From 1a2b3bdee86f577fc30cd5a66aa58b529534f01e Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 13 Jan 2020 13:41:33 +0530 Subject: [PATCH 30/34] product/rddanielxlr: add rddanielxlr system module The system module performs the function of initializing the SYSTOP domain, turning on the primary core, setting up of the SCMI services and SDS messaging stack. Change-Id: If344a8b2254dedf76f24c8ee23d2526cbeb9a990 Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/scp_rddanielxlr_irq.h | 10 + .../include/mod_rddanielxlr_system.h | 64 +++ .../module/rddanielxlr_system/src/Makefile | 11 + .../src/mod_rddanielxlr_system.c | 388 ++++++++++++++++++ 4 files changed, 473 insertions(+) create mode 100644 product/rddanielxlr/module/rddanielxlr_system/include/mod_rddanielxlr_system.h create mode 100644 product/rddanielxlr/module/rddanielxlr_system/src/Makefile create mode 100644 product/rddanielxlr/module/rddanielxlr_system/src/mod_rddanielxlr_system.c diff --git a/product/rddanielxlr/include/scp_rddanielxlr_irq.h b/product/rddanielxlr/include/scp_rddanielxlr_irq.h index e286e6bb9..ebfe2c990 100644 --- a/product/rddanielxlr/include/scp_rddanielxlr_irq.h +++ b/product/rddanielxlr/include/scp_rddanielxlr_irq.h @@ -10,6 +10,16 @@ enum scp_rddanielxlr_interrupt { TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + PPU_CORES0_IRQ = 50, /* Consolidated PPU Interrupt for cores + 1-32, 129-160 */ + PPU_CORES1_IRQ = 51, /* Consolidated PPU Interrupt for cores + 33-64, 161-192 */ + PPU_CORES2_IRQ = 52, /* Consolidated PPU Interrupt for cores + 65-96, 193-224 */ + PPU_CORES3_IRQ = 53, /* Consolidated PPU Interrupt for cores + 97-128, 225-256 */ + PPU_CLUSTERS_IRQ = 54, /* Consolidated clusters PPU */ + MHU_AP_SEC_IRQ = 83, /* MHU secure irq bewteen SCP and AP */ }; diff --git a/product/rddanielxlr/module/rddanielxlr_system/include/mod_rddanielxlr_system.h b/product/rddanielxlr/module/rddanielxlr_system/include/mod_rddanielxlr_system.h new file mode 100644 index 000000000..cc7d62e4c --- /dev/null +++ b/product/rddanielxlr/module/rddanielxlr_system/include/mod_rddanielxlr_system.h @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RD-Daniel System Support + */ + +#ifndef MOD_RDDANIELXLR_SYSTEM_H +#define MOD_RDDANIELXLR_SYSTEM_H + +#include + +/*! + * \addtogroup GroupRDDANIELXLRModule RDDANIELXLR Product Modules + * @{ + */ + +/*! + * \defgroup GroupRDDANIELXLRSystem RDDANIELXLR System Support + * @{ + */ + +/*! + * \brief Additional RDDANIELXLR system power states. + */ +enum mod_rddanielxlr_system_power_states { + MOD_RDDANIELXLR_SYSTEM_POWER_STATE_SLEEP0 = MOD_PD_STATE_COUNT, + MOD_RDDANIELXLR_SYSTEM_POWER_STATE_SLEEP1, + MOD_RDDANIELXLR_SYSTEM_POWER_STATE_COUNT +}; + +/*! + * \brief System power state masks. + */ +enum mod_rddanielxlr_system_power_state_masks { + MOD_RDDANIELXLR_SYSTEM_POWER_STATE_SLEEP0_MASK = + (1 << MOD_RDDANIELXLR_SYSTEM_POWER_STATE_SLEEP0), + MOD_RDDANIELXLR_SYSTEM_POWER_STATE_SLEEP1_MASK = + (1 << MOD_RDDANIELXLR_SYSTEM_POWER_STATE_SLEEP1), +}; + +/*! + * \brief Indices of the interfaces exposed by the module. + */ +enum mod_rddanielxlr_system_api_idx { + /*! API index for the driver interface of the SYSTEM POWER module */ + MOD_RDDANIELXLR_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER, + + /*! Number of exposed interfaces */ + MOD_RDDANIELXLR_SYSTEM_API_COUNT +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_RDDANIELXLR_SYSTEM_H */ diff --git a/product/rddanielxlr/module/rddanielxlr_system/src/Makefile b/product/rddanielxlr/module/rddanielxlr_system/src/Makefile new file mode 100644 index 000000000..68b740823 --- /dev/null +++ b/product/rddanielxlr/module/rddanielxlr_system/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := RDDANIELXLR SYSTEM +BS_LIB_SOURCES = mod_rddanielxlr_system.c + +include $(BS_DIR)/lib.mk diff --git a/product/rddanielxlr/module/rddanielxlr_system/src/mod_rddanielxlr_system.c b/product/rddanielxlr/module/rddanielxlr_system/src/mod_rddanielxlr_system.c new file mode 100644 index 000000000..748c8d927 --- /dev/null +++ b/product/rddanielxlr/module/rddanielxlr_system/src/mod_rddanielxlr_system.c @@ -0,0 +1,388 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RD-Daniel System Support. + */ + +#include "clock_soc.h" +#include "rddanielxlr_core.h" +#include "rddanielxlr_scmi.h" +#include "rddanielxlr_sds.h" +#include "scp_css_mmap.h" +#include "scp_pik.h" +#include "scp_rddanielxlr_irq.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +/* SCMI services required to enable the messaging stack */ +static unsigned int scmi_notification_table[] = { + SCP_RDDANIELXLR_SCMI_SERVICE_IDX_PSCI, +}; + +/* Module context */ +struct rddanielxlr_system_ctx { + /* Pointer to the SCP PIK registers */ + struct pik_scp_reg *pik_scp_reg; + + /* Pointer to the Interrupt Service Routine API of the PPU_V1 module */ + const struct ppu_v1_isr_api *ppu_v1_isr_api; + + /* Power domain module restricted API pointer */ + struct mod_pd_restricted_api *mod_pd_restricted_api; + + /* System Information HAL API pointer */ + struct mod_system_info_get_info_api *system_info_api; + /* SDS API pointer */ + const struct mod_sds_api *sds_api; +}; + +struct rddanielxlr_system_isr { + unsigned int interrupt; + void (*handler)(void); +}; + +static struct rddanielxlr_system_ctx rddanielxlr_system_ctx; +const struct fwk_module_config config_rddanielxlr_system = { 0 }; + +static const uint32_t feature_flags = (RDDANIELXLR_SDS_FEATURE_FIRMWARE_MASK | + RDDANIELXLR_SDS_FEATURE_DMC_MASK | + RDDANIELXLR_SDS_FEATURE_MESSAGING_MASK); + +static fwk_id_t sds_feature_availability_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, 3); + +/* + * SCMI Messaging stack + */ + +static int messaging_stack_ready(void) +{ + const struct mod_sds_structure_desc *sds_structure_desc = + fwk_module_get_data(sds_feature_availability_id); + + /* + * Write SDS Feature Availability to signal the completion of the messaging + * stack + */ + return rddanielxlr_system_ctx.sds_api->struct_write(sds_structure_desc->id, + 0, (void *)(&feature_flags), sds_structure_desc->size); +} + +/* + * PPU Interrupt Service Routines for cluster and core power domains + */ + +static void ppu_cores_isr(unsigned int first, uint32_t status) +{ + unsigned int core_idx; + + while (status != 0) { + core_idx = __builtin_ctz(status); + status &= ~(1 << core_idx); + + if ((first + core_idx) >= rddanielxlr_core_get_core_count()) + continue; + + rddanielxlr_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler( + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, first + core_idx)); + } +} + +static void ppu_cores_isr_0(void) +{ + ppu_cores_isr(0, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[0]); + ppu_cores_isr(128, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[4]); +} + +static void ppu_cores_isr_1(void) +{ + ppu_cores_isr(32, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[1]); + ppu_cores_isr(160, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[5]); +} + +static void ppu_cores_isr_2(void) +{ + ppu_cores_isr(64, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[2]); + ppu_cores_isr(192, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[6]); +} + +static void ppu_cores_isr_3(void) +{ + ppu_cores_isr(96, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[3]); + ppu_cores_isr(224, + rddanielxlr_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[7]); +} + +static void ppu_clusters_isr(void) +{ + uint32_t status = rddanielxlr_system_ctx.pik_scp_reg->CLUS_PPU_INT_STATUS; + unsigned int cluster_idx; + + while (status != 0) { + cluster_idx = __builtin_ctz(status); + + rddanielxlr_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler( + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + rddanielxlr_core_get_core_count() + cluster_idx)); + + status &= ~(1 << cluster_idx); + } +} + +/* + * PPU Interrupt Service Routine table + */ + +static struct rddanielxlr_system_isr isrs[] = { + [0] = { .interrupt = PPU_CORES0_IRQ, + .handler = ppu_cores_isr_0 }, + [1] = { .interrupt = PPU_CORES1_IRQ, + .handler = ppu_cores_isr_1 }, + [2] = { .interrupt = PPU_CORES2_IRQ, + .handler = ppu_cores_isr_2 }, + [3] = { .interrupt = PPU_CORES3_IRQ, + .handler = ppu_cores_isr_3 }, + [4] = { .interrupt = PPU_CLUSTERS_IRQ, + .handler = ppu_clusters_isr }, +}; + +/* + * System power's driver API + */ + +static int rddanielxlr_system_shutdown( + enum mod_pd_system_shutdown system_shutdown) +{ + NVIC_SystemReset(); + + return FWK_E_DEVICE; +} + +static const struct mod_system_power_driver_api + rddanielxlr_system_system_power_driver_api = { + .system_shutdown = rddanielxlr_system_shutdown, +}; + +/* + * Functions fulfilling the framework's module interface + */ + +static int rddanielxlr_system_mod_init(fwk_id_t module_id, unsigned int unused, + const void *unused2) +{ + int status; + unsigned int idx; + struct rddanielxlr_system_isr *isr; + + for (idx = 0; idx < FWK_ARRAY_SIZE(isrs); idx++) { + isr = &isrs[idx]; + status = fwk_interrupt_set_isr(isr->interrupt, isr->handler); + if (status != FWK_SUCCESS) + return status; + } + + rddanielxlr_system_ctx.pik_scp_reg = (struct pik_scp_reg *)SCP_PIK_SCP_BASE; + + return FWK_SUCCESS; +} + +static int rddanielxlr_system_bind(fwk_id_t id, unsigned int round) +{ + int status; + + if (round > 0) + return FWK_SUCCESS; + + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), + FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), + &rddanielxlr_system_ctx.mod_pd_restricted_api); + if (status != FWK_SUCCESS) + return status; + + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1), + FWK_ID_API(FWK_MODULE_IDX_PPU_V1, MOD_PPU_V1_API_IDX_ISR), + &rddanielxlr_system_ctx.ppu_v1_isr_api); + if (status != FWK_SUCCESS) + return status; + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_SYSTEM_INFO), + FWK_ID_API(FWK_MODULE_IDX_SYSTEM_INFO, + MOD_SYSTEM_INFO_GET_API_IDX), + &rddanielxlr_system_ctx.system_info_api); + if (status != FWK_SUCCESS) + return status; + + + return fwk_module_bind(fwk_module_id_sds, + FWK_ID_API(FWK_MODULE_IDX_SDS, 0), + &rddanielxlr_system_ctx.sds_api); +} + +static int rddanielxlr_system_process_bind_request(fwk_id_t requester_id, + fwk_id_t pd_id, fwk_id_t api_id, const void **api) +{ + *api = &rddanielxlr_system_system_power_driver_api; + return FWK_SUCCESS; +} + +static int rddanielxlr_system_start(fwk_id_t id) +{ + int status; + unsigned int i; + + status = fwk_notification_subscribe( + mod_clock_notification_id_state_changed, + FWK_ID_ELEMENT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT), + id); + if (status != FWK_SUCCESS) + return status; + + FWK_LOG_INFO( + "[RD-DANIELXLR SYSTEM] Requesting SYSTOP initialization...\n"); + + /* + * Subscribe to these SCMI channels in order to know when they have all + * initialized. + * At that point we can consider the SCMI stack to be initialized from + * the point of view of the PSCI agent. + */ + for (i = 0; i < FWK_ARRAY_SIZE(scmi_notification_table); i++) { + status = fwk_notification_subscribe( + mod_scmi_notification_id_initialized, + fwk_id_build_element_id(fwk_module_id_scmi, + scmi_notification_table[i]), + id); + if (status != FWK_SUCCESS) + return status; + } + + /* + * Subscribe to the SDS initialized notification so we can correctly let the + * PSCI agent know that the SCMI stack is initialized. + */ + status = fwk_notification_subscribe( + mod_sds_notification_id_initialized, + fwk_module_id_sds, + id); + if (status != FWK_SUCCESS) + return status; + + return + rddanielxlr_system_ctx.mod_pd_restricted_api->set_composite_state_async( + FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), false, + MOD_PD_COMPOSITE_STATE(MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON, + MOD_PD_STATE_OFF, MOD_PD_STATE_OFF)); +} + +int rddanielxlr_system_process_notification(const struct fwk_event *event, + struct fwk_event *resp_event) +{ + int status; + struct clock_notification_params *params; + struct mod_pd_restricted_api *mod_pd_restricted_api; + static unsigned int scmi_notification_count; + static bool sds_notification_received; + const struct mod_system_info *system_info; + uint8_t chip_id = 0; + + status = rddanielxlr_system_ctx.system_info_api->get_system_info( + &system_info); + if (status == FWK_SUCCESS) + chip_id = system_info->chip_id; + + assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE)); + + if (fwk_id_is_equal(event->id, mod_clock_notification_id_state_changed)) { + params = (struct clock_notification_params *)event->params; + + /* + * Initialize primary core when the system is initialized for the first + * time only + */ + if (params->new_state == MOD_CLOCK_STATE_RUNNING && chip_id == 0) { + FWK_LOG_INFO( + "[RD-DANIELXLR SYSTEM] Initializing the primary core...\n"); + + mod_pd_restricted_api = + rddanielxlr_system_ctx.mod_pd_restricted_api; + + status = mod_pd_restricted_api->set_composite_state_async( + FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), + false, + MOD_PD_COMPOSITE_STATE(MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON, + MOD_PD_STATE_ON, MOD_PD_STATE_ON)); + if (status != FWK_SUCCESS) + return status; + + /* Unsubscribe to the notification */ + return fwk_notification_unsubscribe(event->id, event->source_id, + event->target_id); + } else + FWK_LOG_INFO( + "[RD-DANIELXLR SYSTEM] Detected as Slave chip: %d, " + "wait for SCMI\n", chip_id); + + return FWK_SUCCESS; + } else if (fwk_id_is_equal(event->id, + mod_scmi_notification_id_initialized)) { + scmi_notification_count++; + } else if (fwk_id_is_equal(event->id, + mod_sds_notification_id_initialized)) { + sds_notification_received = true; + } else + return FWK_E_PARAM; + + if ((scmi_notification_count == FWK_ARRAY_SIZE(scmi_notification_table)) && + sds_notification_received) { + messaging_stack_ready(); + + scmi_notification_count = 0; + sds_notification_received = false; + } + + return FWK_SUCCESS; +} + +const struct fwk_module module_rddanielxlr_system = { + .name = "RDDANIELXLR_SYSTEM", + .type = FWK_MODULE_TYPE_DRIVER, + .api_count = MOD_RDDANIELXLR_SYSTEM_API_COUNT, + .init = rddanielxlr_system_mod_init, + .bind = rddanielxlr_system_bind, + .process_bind_request = rddanielxlr_system_process_bind_request, + .process_notification = rddanielxlr_system_process_notification, + .start = rddanielxlr_system_start, +}; -- GitLab From dba8f190b62a7a03d7bd2a8766931be38f96d07d Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 11:24:47 +0530 Subject: [PATCH 31/34] product/rddanielxlr: add configuration data for system power driver The system power driver manages the SYSTOP power domain. Provide the details such as the base adresses of System PPU's and the SOC IRQ's for the same. Change-Id: Ib36dbdfb37f984c5428c43a565bb8a34240247fb Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/scp_rddanielxlr_irq.h | 2 + .../scp_ramfw/config_system_power.c | 93 +++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/config_system_power.c diff --git a/product/rddanielxlr/include/scp_rddanielxlr_irq.h b/product/rddanielxlr/include/scp_rddanielxlr_irq.h index ebfe2c990..295eafdcf 100644 --- a/product/rddanielxlr/include/scp_rddanielxlr_irq.h +++ b/product/rddanielxlr/include/scp_rddanielxlr_irq.h @@ -10,6 +10,8 @@ enum scp_rddanielxlr_interrupt { TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ + PPU_CORES0_IRQ = 50, /* Consolidated PPU Interrupt for cores 1-32, 129-160 */ PPU_CORES1_IRQ = 51, /* Consolidated PPU Interrupt for cores diff --git a/product/rddanielxlr/scp_ramfw/config_system_power.c b/product/rddanielxlr/scp_ramfw/config_system_power.c new file mode 100644 index 000000000..9ca0a19b5 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/config_system_power.c @@ -0,0 +1,93 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "rddanielxlr_core.h" +#include "scp_rddanielxlr_irq.h" + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +static const uint8_t system_power_to_sys_ppu0_state[] = { + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_OFF, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, +}; + +static const uint8_t system_power_to_sys_ppu1_state[] = { + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_ON, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, +}; + +static struct fwk_element system_power_element_table[] = { + [0] = { + .name = "SYS-PPU-0", + .data = &((struct mod_system_power_dev_config) { + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu0_state, + }), + }, + + [1] = { + .name = "SYS-PPU-1", + .data = &((struct mod_system_power_dev_config) { + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu1_state, + }), + }, + + [2] = { 0 }, /* Termination description */ +}; + +static struct mod_system_power_config system_power_config = { + .soc_wakeup_irq = SOC_WAKEUP0_IRQ, + + /* System driver */ + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_RDDANIELXLR_SYSTEM), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_RDDANIELXLR_SYSTEM, + MOD_RDDANIELXLR_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER), + + /* Initial system state */ + .initial_system_power_state = MOD_PD_STATE_OFF, +}; + +static const struct fwk_element *rddanielxlr_system_get_element_table( + fwk_id_t unused) +{ + struct mod_system_power_dev_config *dev_config_table; + unsigned int i; + + /* The system PPUs are placed after the core and cluster PPUs */ + unsigned int ppu_idx_base = rddanielxlr_core_get_core_count() + + rddanielxlr_core_get_cluster_count(); + + for (i = 0; i < (FWK_ARRAY_SIZE(system_power_element_table) - 1); i++) { + dev_config_table = (struct mod_system_power_dev_config *) + system_power_element_table[i].data; + dev_config_table->sys_ppu_id = + fwk_id_build_element_id(fwk_module_id_ppu_v1, ppu_idx_base + i); + } + + return system_power_element_table; +} + +const struct fwk_module_config config_system_power = { + .get_element_table = rddanielxlr_system_get_element_table, + .data = &system_power_config, +}; -- GitLab From ff67a46594c2183c6fad8b9f11cbd722862870fd Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 8 Jan 2020 15:14:51 +0530 Subject: [PATCH 32/34] product/rddanielxlr: add support for MCP firmware in rddanielxlr MCP ROM and RAM firmware, does not provide any specific functionality yet. MCP ROM firmware loads the MCP RAM firmware which then executes a WFI to enter idle state. Change-Id: I3197b1aa35849ac5d732a4a1db7a2c2234ca87f1 Signed-off-by: Aditya Angadi --- .../include/mcp_rddanielxlr_mmap.h | 23 ++++++++ .../rddanielxlr/include/mcp_software_mmap.h | 19 ++++++ product/rddanielxlr/mcp_romfw/config_clock.c | 10 ++++ product/rddanielxlr/mcp_romfw/config_log.c | 58 +++++++++++++++++++ .../mcp_romfw/config_rddanielxlr_rom.c | 19 ++++++ product/rddanielxlr/mcp_romfw/firmware.mk | 25 ++++++++ product/rddanielxlr/mcp_romfw/fmw_memory.h | 32 ++++++++++ 7 files changed, 186 insertions(+) create mode 100644 product/rddanielxlr/include/mcp_rddanielxlr_mmap.h create mode 100644 product/rddanielxlr/include/mcp_software_mmap.h create mode 100644 product/rddanielxlr/mcp_romfw/config_clock.c create mode 100644 product/rddanielxlr/mcp_romfw/config_log.c create mode 100644 product/rddanielxlr/mcp_romfw/config_rddanielxlr_rom.c create mode 100644 product/rddanielxlr/mcp_romfw/firmware.mk create mode 100644 product/rddanielxlr/mcp_romfw/fmw_memory.h diff --git a/product/rddanielxlr/include/mcp_rddanielxlr_mmap.h b/product/rddanielxlr/include/mcp_rddanielxlr_mmap.h new file mode 100644 index 000000000..1064af067 --- /dev/null +++ b/product/rddanielxlr/include/mcp_rddanielxlr_mmap.h @@ -0,0 +1,23 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCP_RDDANIELXLR_MMAP_H +#define MCP_RDDANIELXLR_MMAP_H + +#include + +/* + * Top-level base addresses + */ +#define MCP_PERIPH_BASE UINT32_C(0x4C000000) + +/* + * Peripherals + */ +#define MCP_UART0_BASE (MCP_PERIPH_BASE + 0x2000) + +#endif /* MCP_RDDANIELXLR_MMAP_H */ diff --git a/product/rddanielxlr/include/mcp_software_mmap.h b/product/rddanielxlr/include/mcp_software_mmap.h new file mode 100644 index 000000000..01e932f1f --- /dev/null +++ b/product/rddanielxlr/include/mcp_software_mmap.h @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCP_RDDANIELXLR_MMAP_MCP_H +#define MCP_RDDANIELXLR_MMAP_MCP_H + +#define MCP_ROM_BASE 0x00000000 +#define MCP_RAM0_BASE 0x00800000 +#define MCP_RAM1_BASE 0x20000000 + +#define MCP_ROM_SIZE (64 * 1024) +#define MCP_RAM0_SIZE (64 * 1024) +#define MCP_RAM1_SIZE (64 * 1024) + +#endif /* MCP_RDDANIELXLR_MMAP_MCP_H */ diff --git a/product/rddanielxlr/mcp_romfw/config_clock.c b/product/rddanielxlr/mcp_romfw/config_clock.c new file mode 100644 index 000000000..4afc18468 --- /dev/null +++ b/product/rddanielxlr/mcp_romfw/config_clock.c @@ -0,0 +1,10 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +const struct fwk_module_config config_clock = { 0 }; diff --git a/product/rddanielxlr/mcp_romfw/config_log.c b/product/rddanielxlr/mcp_romfw/config_log.c new file mode 100644 index 000000000..ea1a8bd35 --- /dev/null +++ b/product/rddanielxlr/mcp_romfw/config_log.c @@ -0,0 +1,58 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mcp_rddanielxlr_mmap.h" + +#include +#include + +#include +#include +#include +#include +#include +#include + +/* + * PL011 module + */ +static const struct fwk_element pl011_element_desc_table[] = { + [0] = { + .name = "uart0", + .data = &((struct mod_pl011_device_config) { + .reg_base = MCP_UART0_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_pl011_table(fwk_id_t module_id) +{ + return pl011_element_desc_table; +} + +struct fwk_module_config config_pl011 = { + .get_element_table = get_pl011_table, +}; + +/* + * Log module + */ +static const struct mod_log_config log_data = { + .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0), + .banner = FWK_BANNER_MCP + FWK_BANNER_ROM_FIRMWARE + BUILD_VERSION_DESCRIBE_STRING "\n", +}; + +struct fwk_module_config config_log = { + .data = &log_data, +}; diff --git a/product/rddanielxlr/mcp_romfw/config_rddanielxlr_rom.c b/product/rddanielxlr/mcp_romfw/config_rddanielxlr_rom.c new file mode 100644 index 000000000..a8af750ac --- /dev/null +++ b/product/rddanielxlr/mcp_romfw/config_rddanielxlr_rom.c @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mcp_software_mmap.h" + +#include + +#include + +const struct fwk_module_config config_mscp_rom = { + .data = &((struct mscp_rom_config) { + .ramfw_ram_base = MCP_RAM0_BASE, + .ramfw_flash_size = 0, + }) +}; diff --git a/product/rddanielxlr/mcp_romfw/firmware.mk b/product/rddanielxlr/mcp_romfw/firmware.mk new file mode 100644 index 000000000..50126355d --- /dev/null +++ b/product/rddanielxlr/mcp_romfw/firmware.mk @@ -0,0 +1,25 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := no +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := \ + power_domain + +BS_FIRMWARE_MODULES := \ + pl011 \ + log \ + clock \ + mscp_rom + +BS_FIRMWARE_SOURCES := \ + config_log.c \ + config_clock.c \ + config_rddanielxlr_rom.c + +include $(BS_DIR)/firmware.mk diff --git a/product/rddanielxlr/mcp_romfw/fmw_memory.h b/product/rddanielxlr/mcp_romfw/fmw_memory.h new file mode 100644 index 000000000..2a663d439 --- /dev/null +++ b/product/rddanielxlr/mcp_romfw/fmw_memory.h @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * ROM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * ROM memory + */ +#define FIRMWARE_MEM0_SIZE MCP_ROM_SIZE +#define FIRMWARE_MEM0_BASE MCP_ROM_BASE + +/* + * RAM memory + */ +#define FIRMWARE_MEM1_SIZE MCP_RAM1_SIZE +#define FIRMWARE_MEM1_BASE MCP_RAM1_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_H */ -- GitLab From dd011ec5539b15376891cd2eec38b59cb8c56b8e Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 27 Jan 2020 09:29:46 +0530 Subject: [PATCH 33/34] product/rddanielxlr: add build support for scp ram firmware Add the makefile to build the RAM firmware and the corresponding linker script. Change-Id: I458a7303cf041b3d75417a10752b9c61fe8d8770 Signed-off-by: Aditya Angadi --- .../rddanielxlr/include/scp_software_mmap.h | 1 + product/rddanielxlr/scp_ramfw/firmware.mk | 64 +++++++++++++++++++ product/rddanielxlr/scp_ramfw/fmw_memory.h | 33 ++++++++++ 3 files changed, 98 insertions(+) create mode 100644 product/rddanielxlr/scp_ramfw/firmware.mk create mode 100644 product/rddanielxlr/scp_ramfw/fmw_memory.h diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h index a9eff8d07..366936624 100644 --- a/product/rddanielxlr/include/scp_software_mmap.h +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -15,6 +15,7 @@ /* SCP ROM and RAM firmware size loaded on main memory */ #define SCP_BOOT_ROM_SIZE (64 * 1024) #define SCP_DTC_RAM_SIZE (256 * 1024) +#define SCP_ITC_RAM_SIZE (256 * 1024) /* SCP RAM firmware base and size on the flash */ #define SCP_RAMFW_IMAGE_FLASH_BASE (SCP_NOR0_FLASH_BASE + 0x03D80000) diff --git a/product/rddanielxlr/scp_ramfw/firmware.mk b/product/rddanielxlr/scp_ramfw/firmware.mk new file mode 100644 index 000000000..b175cf695 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/firmware.mk @@ -0,0 +1,64 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := yes +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_NOTIFICATION_COUNT := 128 + +BS_FIRMWARE_MODULES := \ + armv7m_mpu \ + sid \ + system_info \ + pcid \ + pl011 \ + log \ + pik_clock \ + css_clock \ + clock \ + gtimer \ + timer \ + cmn_rhodes \ + ppu_v1 \ + system_power \ + mhu2 \ + smt \ + scmi \ + sds \ + system_pll \ + apcontext \ + power_domain \ + scmi_power_domain \ + scmi_system_power \ + rddanielxlr_system + +BS_FIRMWARE_SOURCES := \ + config_system_power.c \ + config_sid.c \ + config_system_info.c \ + rtx_config.c \ + config_armv7m_mpu.c \ + config_pl011.c \ + config_log.c \ + config_power_domain.c \ + config_ppu_v1.c \ + config_mhu2.c \ + config_smt.c \ + config_scmi.c \ + config_sds.c \ + config_timer.c \ + config_gtimer.c \ + config_cmn_rhodes.c \ + config_scmi_system_power.c \ + config_scmi_power_domain.c \ + config_system_pll.c \ + config_pik_clock.c \ + config_css_clock.c \ + config_clock.c \ + config_apcontext.c + +include $(BS_DIR)/firmware.mk diff --git a/product/rddanielxlr/scp_ramfw/fmw_memory.h b/product/rddanielxlr/scp_ramfw/fmw_memory.h new file mode 100644 index 000000000..446e743ef --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/fmw_memory.h @@ -0,0 +1,33 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "scp_mmap.h" +#include "scp_software_mmap.h" + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FIRMWARE_MEM0_SIZE SCP_ITC_RAM_SIZE +#define FIRMWARE_MEM0_BASE SCP_ITC_RAM_BASE + +/* + * RAM data memory + */ +#define FIRMWARE_MEM1_SIZE SCP_DTC_RAM_SIZE +#define FIRMWARE_MEM1_BASE SCP_DTC_RAM_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_H */ -- GitLab From f5db60d5eac01aa90c4617c59fead0e1cf00b3a3 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Mon, 27 Jan 2020 09:30:43 +0530 Subject: [PATCH 34/34] product/rddanielxlr: add the product.mk file for rddanielxlr platform Add the product.mk file for RD-Daniel Config-XLR platform and make it available to the scp build system as a product. Change-Id: I3deacb73195ff19fd519c7d314a40da4fb976595 Signed-off-by: Aditya Angadi --- product/rddanielxlr/product.mk | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 product/rddanielxlr/product.mk diff --git a/product/rddanielxlr/product.mk b/product/rddanielxlr/product.mk new file mode 100644 index 000000000..806dcc61e --- /dev/null +++ b/product/rddanielxlr/product.mk @@ -0,0 +1,13 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Platforms supported by the rddanielxlr product: RD-Daniel Config-XLR +# + +BS_PRODUCT_NAME := rddanielxlr +BS_FIRMWARE_LIST := scp_romfw \ + scp_ramfw \ + mcp_romfw -- GitLab