diff --git a/module/dvfs/include/mod_dvfs.h b/module/dvfs/include/mod_dvfs.h
index 8a925c64230b873aae61439eb32b6fcb118eb74a..9ab5f2a7e10b0e839285ed6120725c2078c1c056 100644
--- a/module/dvfs/include/mod_dvfs.h
+++ b/module/dvfs/include/mod_dvfs.h
@@ -38,6 +38,7 @@ struct mod_dvfs_frequency_limits {
 struct mod_dvfs_opp {
     uint64_t voltage; /*!< Power supply voltage in millivolts (mV) */
     uint64_t frequency; /*!< Clock rate in Hertz (Hz) */
+    uint64_t power; /*!< Power draw in milliwatts (mW) */
 };
 
 /*!
diff --git a/module/scmi_perf/src/mod_scmi_perf.c b/module/scmi_perf/src/mod_scmi_perf.c
index 356a9babe5ce43ab43524e81af3e752203e6646c..4b212ddbe11f6f6ddadb074938ac9fe3baa6fe10 100644
--- a/module/scmi_perf/src/mod_scmi_perf.c
+++ b/module/scmi_perf/src/mod_scmi_perf.c
@@ -324,7 +324,10 @@ static int scmi_perf_describe_levels_handler(fwk_id_t service_id,
         if (status != FWK_SUCCESS)
             goto exit;
 
-        perf_level.power_cost = opp.voltage;
+        if (opp.power != 0)
+            perf_level.power_cost = opp.power;
+        else
+            perf_level.power_cost = opp.voltage;
         perf_level.performance_level = opp.frequency;
         perf_level.attributes = latency;
 
diff --git a/product/juno/scp_ramfw/config_dvfs.c b/product/juno/scp_ramfw/config_dvfs.c
new file mode 100644
index 0000000000000000000000000000000000000000..df298a2c687d8471c6079d162270c1ee518eaaa7
--- /dev/null
+++ b/product/juno/scp_ramfw/config_dvfs.c
@@ -0,0 +1,391 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_assert.h>
+#include <fwk_element.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <config_dvfs.h>
+#include <config_psu.h>
+#include <juno_alarm_idx.h>
+#include <juno_clock.h>
+#include <juno_id.h>
+#include <mod_dvfs.h>
+
+/*
+ * The power cost figures from this file are built using the dynamic power
+ * consumption formula (P = CfV^2), where C represents the capacitance of one
+ * processing element in the domain (a core or shader core). This power figure
+ * is scaled linearly with the number of processing elements in the performance
+ * domain to give a rough representation of the overall power draw. The
+ * capacitance constants are given in mW/MHz/V^2 and were taken from the Linux
+ * device trees, which provide a dynamic-power-coefficient field in uW/MHz/V^2.
+ */
+
+static const struct mod_dvfs_domain_config cpu_group_little_r0 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VLITTLE),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_LITTLECLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_VLITTLE_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 2,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 450 * FWK_MHZ,
+            .voltage = 820,
+            .power = (0.14 * 450 * 0.820 * 0.820),
+        },
+        {
+            .frequency = 575 * FWK_MHZ,
+            .voltage = 850,
+            .power = (0.14 * 575 * 0.850 * 0.850),
+        },
+        {
+            .frequency = 700 * FWK_MHZ,
+            .voltage = 900,
+            .power = (0.14 * 700 * 0.900 * 0.900),
+        },
+        {
+            .frequency = 775 * FWK_MHZ,
+            .voltage = 950,
+            .power = (0.14 * 775 * 0.950 * 0.950),
+        },
+        {
+            .frequency = 850 * FWK_MHZ,
+            .voltage = 1000,
+            .power = (0.14 * 850 * 1.000 * 1.000),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config cpu_group_little_r1 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VLITTLE),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_LITTLECLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_VLITTLE_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 0,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 650 * FWK_MHZ,
+            .voltage = 800,
+            .power = (0.14 * 650 * 0.800 * 0.800),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config cpu_group_little_r2 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VLITTLE),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_LITTLECLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_VLITTLE_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 1,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 450 * FWK_MHZ,
+            .voltage = 820,
+            .power = (0.14 * 450 * 0.820 * 0.820),
+        },
+        {
+            .frequency = 800 * FWK_MHZ,
+            .voltage = 900,
+            .power = (0.14 * 800 * 0.900 * 0.900),
+        },
+        {
+            .frequency = 950 * FWK_MHZ,
+            .voltage = 1000,
+            .power = (0.14 * 950 * 1.000 * 1.000),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config cpu_group_big_r0 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VBIG),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_BIGCLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_BIG_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 2,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 450 * FWK_MHZ,
+            .voltage = 820,
+            .power = (0.53 * 450 * 0.820 * 0.820),
+        },
+        {
+            .frequency = 625 * FWK_MHZ,
+            .voltage = 850,
+            .power = (0.53 * 625 * 0.850 * 0.850),
+        },
+        {
+            .frequency = 800 * FWK_MHZ,
+            .voltage = 900,
+            .power = (0.53 * 800 * 0.900 * 0.900),
+        },
+        {
+            .frequency = 950 * FWK_MHZ,
+            .voltage = 950,
+            .power = (0.53 * 950 * 0.950 * 0.950),
+        },
+        {
+            .frequency = 1100 * FWK_MHZ,
+            .voltage = 1000,
+            .power = (0.53 * 1100 * 1.000 * 1.000),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config cpu_group_big_r1 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VBIG),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_BIGCLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_BIG_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 1,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 600 * FWK_MHZ,
+            .voltage = 800,
+            .power = (0.53 * 600 * 0.800 * 0.800),
+        },
+        {
+            .frequency = 900 * FWK_MHZ,
+            .voltage = 900,
+            .power = (0.53 * 900 * 0.900 * 0.900),
+        },
+        {
+            .frequency = 1150 * FWK_MHZ,
+            .voltage = 1000,
+            .power = (0.53 * 1150 * 1.000 * 1.000),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config cpu_group_big_r2 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VBIG),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_BIGCLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_BIG_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 1,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 600 * FWK_MHZ,
+            .voltage = 820,
+            .power = (0.45 * 600 * 0.820 * 0.820),
+        },
+        {
+            .frequency = 1000 * FWK_MHZ,
+            .voltage = 900,
+            .power = (0.45 * 1000 * 0.900 * 0.900),
+        },
+        {
+            .frequency = 1200 * FWK_MHZ,
+            .voltage = 1000,
+            .power = (0.45 * 1200 * 1.000 * 1.000),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config gpu_r0 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VGPU),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_GPUCLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_GPU_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 4,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 450 * FWK_MHZ,
+            .voltage = 820,
+            .power = (4.6875 * 450 * 0.820 * 0.820),
+        },
+        {
+            .frequency = 487500 * FWK_KHZ,
+            .voltage = 825,
+            .power = (4.6875 * 487.5 * 0.825 * 0.825),
+        },
+        {
+            .frequency = 525 * FWK_MHZ,
+            .voltage = 850,
+            .power = (4.6875 * 525 * 0.850 * 0.850),
+        },
+        {
+            .frequency = 562500 * FWK_KHZ,
+            .voltage = 875,
+            .power = (4.6875 * 562.5 * 0.875 * 0.875),
+        },
+        {
+            .frequency = 600 * FWK_MHZ,
+            .voltage = 900,
+            .power = (4.6875 * 600 * 0.900 * 0.900),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config gpu_r1 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VGPU),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_GPUCLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_GPU_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 4,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 450 * FWK_MHZ,
+            .voltage = 820,
+            .power = (4.6875 * 450 * 0.820 * 0.820),
+        },
+        {
+            .frequency = 487500 * FWK_KHZ,
+            .voltage = 825,
+            .power = (4.6875 * 487.5 * 0.825 * 0.825),
+        },
+        {
+            .frequency = 525 * FWK_MHZ,
+            .voltage = 850,
+            .power = (4.6875 * 525 * 0.850 * 0.850),
+        },
+        {
+            .frequency = 562500 * FWK_KHZ,
+            .voltage = 875,
+            .power = (4.6875 * 562.5 * 0.875 * 0.875),
+        },
+        {
+            .frequency = 600 * FWK_MHZ,
+            .voltage = 900,
+            .power = (4.6875 * 600 * 0.900 * 0.900),
+        },
+        { 0 }
+    }
+};
+
+static const struct mod_dvfs_domain_config gpu_r2 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU,
+        MOD_PSU_ELEMENT_IDX_VGPU),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+        JUNO_CLOCK_IDX_GPUCLK),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        JUNO_DVFS_ALARM_GPU_IDX),
+    .retry_ms = 1,
+    .latency = 1450,
+    .sustained_idx = 1,
+    .opps = (struct mod_dvfs_opp[]) {
+        {
+            .frequency = 450 * FWK_MHZ,
+            .voltage = 820,
+            .power = (4.6875 * 450 * 0.820 * 0.820),
+        },
+        {
+            .frequency = 487500 * FWK_KHZ,
+            .voltage = 900,
+            .power = (4.6875 * 600 * 0.900 * 0.900),
+        },
+        { 0 }
+    }
+};
+
+static const struct fwk_element element_table_r0[] = {
+    [DVFS_ELEMENT_IDX_LITTLE] = {
+        .name = "LITTLE_CPU",
+        .data = &cpu_group_little_r0,
+    },
+    [DVFS_ELEMENT_IDX_BIG] = {
+        .name = "BIG_CPU",
+        .data = &cpu_group_big_r0,
+    },
+    [DVFS_ELEMENT_IDX_GPU] = {
+        .name = "GPU",
+        .data = &gpu_r0,
+    },
+    { 0 }
+};
+
+static const struct fwk_element element_table_r1[] = {
+    [DVFS_ELEMENT_IDX_LITTLE] = {
+        .name = "CPU_LITTLE",
+        .data = &cpu_group_little_r1,
+    },
+    [DVFS_ELEMENT_IDX_BIG] = {
+        .name = "CPU_BIG",
+        .data = &cpu_group_big_r1,
+    },
+    [DVFS_ELEMENT_IDX_GPU] = {
+        .name = "GPU",
+        .data = &gpu_r1,
+    },
+    { 0 }
+};
+
+static const struct fwk_element element_table_r2[] = {
+    [DVFS_ELEMENT_IDX_LITTLE] = {
+        .name = "CPU_GROUP_LITTLE",
+        .data = &cpu_group_little_r2,
+    },
+    [DVFS_ELEMENT_IDX_BIG] = {
+        .name = "CPU_GROUP_BIG",
+        .data = &cpu_group_big_r2,
+    },
+    [DVFS_ELEMENT_IDX_GPU] = {
+        .name = "GPU",
+        .data = &gpu_r2,
+    },
+    { 0 }
+};
+
+static const struct fwk_element *dvfs_get_element_table(fwk_id_t module_id)
+{
+    int status;
+    enum juno_idx_revision revision;
+
+    status = juno_id_get_revision(&revision);
+    fwk_assert(status == FWK_SUCCESS);
+
+    if (revision == JUNO_IDX_REVISION_R0)
+        return element_table_r0;
+    if (revision == JUNO_IDX_REVISION_R1)
+        return element_table_r1;
+    return element_table_r2;
+}
+
+struct fwk_module_config config_dvfs = {
+    .get_element_table = dvfs_get_element_table,
+    .data = NULL,
+};
diff --git a/product/juno/scp_ramfw/config_dvfs.h b/product/juno/scp_ramfw/config_dvfs.h
new file mode 100644
index 0000000000000000000000000000000000000000..39481b9312d39d0c41a4085033b06df4251d7012
--- /dev/null
+++ b/product/juno/scp_ramfw/config_dvfs.h
@@ -0,0 +1,18 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONFIG_DVFS_H
+#define CONFIG_DVFS_H
+
+enum dvfs_element_idx {
+    DVFS_ELEMENT_IDX_BIG,
+    DVFS_ELEMENT_IDX_LITTLE,
+    DVFS_ELEMENT_IDX_GPU,
+    DVFS_ELEMENT_IDX_COUNT,
+};
+
+#endif /* CONFIG_DVFS_H */
diff --git a/product/juno/scp_ramfw/config_scmi.c b/product/juno/scp_ramfw/config_scmi.c
index d44f142b5526025e3226aa03df840819ea325da0..6425392401b64b63a228d695394c2371177a5517 100644
--- a/product/juno/scp_ramfw/config_scmi.c
+++ b/product/juno/scp_ramfw/config_scmi.c
@@ -86,7 +86,7 @@ static const struct mod_scmi_agent agent_table[] = {
 struct fwk_module_config config_scmi = {
     .get_element_table = get_element_table,
     .data = &(struct mod_scmi_config) {
-        .protocol_count_max = 3,
+        .protocol_count_max = 4,
         .agent_count = FWK_ARRAY_SIZE(agent_table) - 1,
         .agent_table = agent_table,
         .vendor_identifier = "arm",
diff --git a/product/juno/scp_ramfw/config_scmi_perf.c b/product/juno/scp_ramfw/config_scmi_perf.c
new file mode 100644
index 0000000000000000000000000000000000000000..0d0667bde8b433bb93af7a4f7d1aff2a02cd614a
--- /dev/null
+++ b/product/juno/scp_ramfw/config_scmi_perf.c
@@ -0,0 +1,47 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <config_dvfs.h>
+#include <juno_scmi.h>
+#include <mod_scmi.h>
+#include <mod_scmi_perf.h>
+
+static const struct mod_scmi_perf_domain_config domains[] = {
+    [DVFS_ELEMENT_IDX_LITTLE] = {
+        .permissions = &(const uint32_t[]) {
+            [JUNO_SCMI_AGENT_IDX_OSPM] = MOD_SCMI_PERF_PERMS_SET_LEVEL  |
+                                   MOD_SCMI_PERF_PERMS_SET_LIMITS,
+            [JUNO_SCMI_AGENT_IDX_PSCI] = 0 /* No Access */,
+        }
+    },
+    [DVFS_ELEMENT_IDX_BIG] = {
+        .permissions = &(const uint32_t[]) {
+            [JUNO_SCMI_AGENT_IDX_OSPM] = MOD_SCMI_PERF_PERMS_SET_LEVEL  |
+                                   MOD_SCMI_PERF_PERMS_SET_LIMITS,
+            [JUNO_SCMI_AGENT_IDX_PSCI] = 0 /* No Access */,
+        }
+    },
+    [DVFS_ELEMENT_IDX_GPU] = {
+        .permissions = &(const uint32_t[]) {
+            [JUNO_SCMI_AGENT_IDX_OSPM] = MOD_SCMI_PERF_PERMS_SET_LEVEL  |
+                                   MOD_SCMI_PERF_PERMS_SET_LIMITS,
+            [JUNO_SCMI_AGENT_IDX_PSCI] = 0 /* No Access */,
+        }
+    },
+};
+
+
+struct fwk_module_config config_scmi_perf = {
+    .get_element_table = NULL,
+    .data = &((struct mod_scmi_perf_config) {
+        .domains = &domains,
+    }),
+};
diff --git a/product/juno/scp_ramfw/firmware.mk b/product/juno/scp_ramfw/firmware.mk
index e3b599c765586764b09cd5170f8e8c1811db26dc..aec247a4dd1fb5160d83705bea4aeea63aa618e3 100644
--- a/product/juno/scp_ramfw/firmware.mk
+++ b/product/juno/scp_ramfw/firmware.mk
@@ -21,6 +21,7 @@ BS_FIRMWARE_MODULES := \
     clock \
     juno_cdcel937 \
     juno_hdlcd \
+    dvfs \
     gtimer \
     timer \
     juno_ddr_phy400 \
@@ -34,6 +35,7 @@ BS_FIRMWARE_MODULES := \
     smt \
     scmi \
     scmi_clock \
+    scmi_perf \
     scmi_power_domain \
     scmi_system_power \
     sds \
@@ -53,6 +55,7 @@ BS_FIRMWARE_SOURCES := \
     config_log.c \
     config_juno_soc_clock_ram.c \
     config_clock.c \
+    config_dvfs.c \
     config_juno_cdcel937.c \
     config_juno_hdlcd.c \
     juno_id.c \
@@ -67,6 +70,7 @@ BS_FIRMWARE_SOURCES := \
     config_smt.c \
     config_scmi.c \
     config_scmi_clock.c \
+    config_scmi_perf.c \
     config_scmi_system_power.c \
     config_i2c.c \
     config_juno_adc.c \
diff --git a/product/rdn1e1/scp_ramfw/config_dvfs.c b/product/rdn1e1/scp_ramfw/config_dvfs.c
index b3bccff8a20cb0c1f0c6cc4fdd488b67e7cb9854..1c17dfa58aa5aefb206be04c1d36bf58a9da0257 100644
--- a/product/rdn1e1/scp_ramfw/config_dvfs.c
+++ b/product/rdn1e1/scp_ramfw/config_dvfs.c
@@ -39,6 +39,8 @@ static struct mod_dvfs_opp opps[] = {
 static const struct mod_dvfs_domain_config cpu_group0 = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP0),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0, 0),
+    .retry_ms = 1,
     .latency = 1200,
     .sustained_idx = 2,
     .opps = opps,
@@ -47,6 +49,8 @@ static const struct mod_dvfs_domain_config cpu_group0 = {
 static const struct mod_dvfs_domain_config cpu_group1 = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP1),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0, 1),
+    .retry_ms = 1,
     .latency = 1200,
     .sustained_idx = 2,
     .opps = opps,
diff --git a/product/rdn1e1/scp_ramfw/config_timer.c b/product/rdn1e1/scp_ramfw/config_timer.c
index 200133cf775f6acb568d9e98084fc84c859e97c4..a06870c7aa39cff098362e3107b28db156bfabb5 100644
--- a/product/rdn1e1/scp_ramfw/config_timer.c
+++ b/product/rdn1e1/scp_ramfw/config_timer.c
@@ -52,7 +52,7 @@ static const struct fwk_element timer_dev_table[] = {
             .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0),
             .timer_irq = TIMREFCLK_IRQ,
         }),
-        .sub_element_count = 8, /* Number of alarms */
+        .sub_element_count = 10, /* Number of alarms */
     },
     [1] = { 0 },
 };
diff --git a/product/sgi575/scp_ramfw/config_dvfs.c b/product/sgi575/scp_ramfw/config_dvfs.c
index 8b2b34aa598f7d44646bb3c588dce4fac18ab056..d064eceec9bc4e29fb1862c3880726cdcd18763f 100644
--- a/product/sgi575/scp_ramfw/config_dvfs.c
+++ b/product/sgi575/scp_ramfw/config_dvfs.c
@@ -39,6 +39,8 @@ static struct mod_dvfs_opp opps[] = {
 static const struct mod_dvfs_domain_config cpu_group0 = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP0),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0, 0),
+    .retry_ms = 1,
     .latency = 1200,
     .sustained_idx = 2,
     .opps = opps,
@@ -47,6 +49,8 @@ static const struct mod_dvfs_domain_config cpu_group0 = {
 static const struct mod_dvfs_domain_config cpu_group1 = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP1),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0, 1),
+    .retry_ms = 1,
     .latency = 1200,
     .sustained_idx = 2,
     .opps = opps,
diff --git a/product/sgi575/scp_ramfw/config_timer.c b/product/sgi575/scp_ramfw/config_timer.c
index 9a05d29918036cbf3f64aa33a5050228780a117b..793b1ec7fbf37f6a06ba4e421633fc7f4ed9b5ac 100644
--- a/product/sgi575/scp_ramfw/config_timer.c
+++ b/product/sgi575/scp_ramfw/config_timer.c
@@ -52,7 +52,7 @@ static const struct fwk_element timer_dev_table[] = {
             .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0),
             .timer_irq = TIMREFCLK_IRQ,
         }),
-        .sub_element_count = 8, /* Number of alarms */
+        .sub_element_count = 10, /* Number of alarms */
     },
     [1] = { 0 },
 };
diff --git a/product/sgm775/scp_ramfw/config_dvfs.c b/product/sgm775/scp_ramfw/config_dvfs.c
index c61ca193217cebdcafc6abd985ab1262690dd481..e22ed07fc322021325fcd11be145485d433486c5 100644
--- a/product/sgm775/scp_ramfw/config_dvfs.c
+++ b/product/sgm775/scp_ramfw/config_dvfs.c
@@ -10,11 +10,15 @@
 #include <fwk_module.h>
 #include <fwk_module_idx.h>
 #include <config_dvfs.h>
+#include <config_timer.h>
 #include <mod_dvfs.h>
 
 static const struct mod_dvfs_domain_config cpu_group_little = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, 1),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        CONFIG_TIMER_DVFS_CPU_GROUP_LITTLE),
+    .retry_ms = 1,
     .latency = 1200,
     .sustained_idx = 2,
     .opps = (struct mod_dvfs_opp[]) {
@@ -45,6 +49,9 @@ static const struct mod_dvfs_domain_config cpu_group_little = {
 static const struct mod_dvfs_domain_config cpu_group_big = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, 0),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        CONFIG_TIMER_DVFS_CPU_GROUP_BIG),
+    .retry_ms = 1,
     .latency = 1200,
     .sustained_idx = 2,
     .opps = (struct mod_dvfs_opp[]) {
@@ -75,6 +82,9 @@ static const struct mod_dvfs_domain_config cpu_group_big = {
 static const struct mod_dvfs_domain_config gpu = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 2),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, 2),
+    .alarm_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0,
+        CONFIG_TIMER_DVFS_GPU),
+    .retry_ms = 1,
     .latency = 1200,
     .sustained_idx = 4,
     .opps = (struct mod_dvfs_opp[]) {
diff --git a/product/sgm775/scp_ramfw/config_timer.h b/product/sgm775/scp_ramfw/config_timer.h
index 372c0050316a160ab05e5a503d5afa4a0df24fbd..439208ea2adeb08a07aa2614b526baee335041c3 100644
--- a/product/sgm775/scp_ramfw/config_timer.h
+++ b/product/sgm775/scp_ramfw/config_timer.h
@@ -14,6 +14,9 @@ enum config_timer_element_idx {
 };
 
 enum config_timer_refclk_sub_element_idx {
+    CONFIG_TIMER_DVFS_CPU_GROUP_LITTLE,
+    CONFIG_TIMER_DVFS_CPU_GROUP_BIG,
+    CONFIG_TIMER_DVFS_GPU,
     CONFIG_TIMER_REFCLK_SUB_ELEMENT_IDX_COUNT,
 };