From d5593a7071c798304f410a1b95b82971a25cbd30 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Tue, 23 Jan 2024 14:49:48 +0000 Subject: [PATCH 1/7] tc4: Add CCSM addresses Add the base addresses of the CCSM block and the specific CCSMs for each CPU type and add this base address to the ATU configuration to allow SCP access. The CCSM ATU region size is set to 8MiB, as per specification. This commit also adds CCSM addresses for DSU, CME and the various GPU CCSM modules. Signed-off-by: Jackson Cooper-Driver --- product/totalcompute/tc4/include/scp_mmap.h | 12 ++++++++++++ product/totalcompute/tc4/include/tc4_atu.h | 3 +++ product/totalcompute/tc4/scp_css/config_atu.c | 7 +++++++ 3 files changed, 22 insertions(+) diff --git a/product/totalcompute/tc4/include/scp_mmap.h b/product/totalcompute/tc4/include/scp_mmap.h index 183ce8801..0012c5bfb 100644 --- a/product/totalcompute/tc4/include/scp_mmap.h +++ b/product/totalcompute/tc4/include/scp_mmap.h @@ -104,6 +104,18 @@ #define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) #define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) +/* CCSM registers */ +#define SCP_CCSM_BASE (SCP_ATU_LOG_ADDR_CCSM) +#define SCP_CCSM_DSU (SCP_CCSM_BASE + 0x000000) +#define SCP_CCSM_LIT (SCP_CCSM_BASE + 0x010000) +#define SCP_CCSM_CME (SCP_CCSM_BASE + 0x020000) +#define SCP_CCSM_MID (SCP_CCSM_BASE + 0x030000) +#define SCP_CCSM_BIG (SCP_CCSM_BASE + 0x040000) +#define SCP_CCSM_GPUTOP (SCP_CCSM_BASE + 0x100000) +#define SCP_CCSM_GPUSC (SCP_CCSM_BASE + 0x110000) +#define SCP_CCSM_GPUNE (SCP_CCSM_BASE + 0x120000) +#define SCP_CCSM_GPUCGP (SCP_CCSM_BASE + 0x130000) + /* AP Context Area */ #define SCP_AP_CONTEXT_BASE \ (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \ diff --git a/product/totalcompute/tc4/include/tc4_atu.h b/product/totalcompute/tc4/include/tc4_atu.h index 2c4534d30..78b89b9bc 100644 --- a/product/totalcompute/tc4/include/tc4_atu.h +++ b/product/totalcompute/tc4/include/tc4_atu.h @@ -35,6 +35,7 @@ #define SCP_ATU_LOG_ADDR_SHARED_NSRAM (SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_NS) #define SCP_ATU_LOG_ADDR_CLUSTER_UTIL (SCP_SYSTEM_ACCESS_ATU_INT_EXP_BASE_S) #define SCP_ATU_LOG_ADDR_PLL (SCP_SYSTEM_ACCESS_ATU_DEV_BASE_S) +#define SCP_ATU_LOG_ADDR_CCSM (SCP_SYSTEM_ACCESS_ATU_DEV_BASE_S + 0x100000) /* ATU Physical Addresses */ #define SCP_ATU_PHY_ADDR_GTCLK_AP (0x2A810000) @@ -44,6 +45,7 @@ #define SCP_ATU_PHY_ADDR_SHARED_NSRAM (0x06000000) #define SCP_ATU_PHY_ADDR_ROS_SOC (0x7FF70000) #define SCP_ATU_PHY_ADDR_PLL (0x43000000) +#define SCP_ATU_PHY_ADDR_CCSM (0x59800000) /* ATU Region Sizes */ #define SCP_ATU_REG_SIZE_GTCLK_AP (128 * FWK_KIB) @@ -53,5 +55,6 @@ #define SCP_ATU_REG_SIZE_ROS_SOC (64 * FWK_KIB) #define SCP_ATU_REG_SIZE_CLUSTER_UTIL (10 * FWK_MIB) #define SCP_ATU_REG_SIZE_PLL (64 * FWK_KIB) +#define SCP_ATU_REG_SIZE_CCSM (8 * FWK_MIB) #endif /* TC4_ATU_H */ diff --git a/product/totalcompute/tc4/scp_css/config_atu.c b/product/totalcompute/tc4/scp_css/config_atu.c index 7e367887a..69872ddd2 100644 --- a/product/totalcompute/tc4/scp_css/config_atu.c +++ b/product/totalcompute/tc4/scp_css/config_atu.c @@ -73,6 +73,13 @@ static const struct atu_region_map atu_regions[] = { .region_size = SCP_ATU_REG_SIZE_PLL, .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, }, + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_CCSM, + .phy_addr_base = SCP_ATU_PHY_ADDR_CCSM, + .region_size = SCP_ATU_REG_SIZE_CCSM, + .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, + }, }; #endif -- GitLab From 0ce2d67d02a0326a9490e4467a7359b94c7e7078 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Tue, 23 Jan 2024 14:51:27 +0000 Subject: [PATCH 2/7] tc4: Add config_ccsm.c This specifies the configuration of the CCSM module. It includes the various frequencies supported by the CPUs as well as other basic configuration. It will be used for DVFS by the clock module. Signed-off-by: Jackson Cooper-Driver Signed-off-by: Noe Galea-Sevilla --- product/totalcompute/tc4/include/clock_soc.h | 10 + .../totalcompute/tc4/scp_css/CMakeLists.txt | 3 +- .../totalcompute/tc4/scp_css/Firmware.cmake | 1 + .../totalcompute/tc4/scp_css/config_ccsm.c | 360 ++++++++++++++++++ .../totalcompute/tc4/scp_css/config_clock.c | 5 +- 5 files changed, 376 insertions(+), 3 deletions(-) create mode 100644 product/totalcompute/tc4/scp_css/config_ccsm.c diff --git a/product/totalcompute/tc4/include/clock_soc.h b/product/totalcompute/tc4/include/clock_soc.h index 7cb6897e9..971106d1f 100644 --- a/product/totalcompute/tc4/include/clock_soc.h +++ b/product/totalcompute/tc4/include/clock_soc.h @@ -53,6 +53,16 @@ enum clock_pik_idx { CLOCK_PIK_IDX_COUNT }; +/* + * CCSM clock indexes + */ +enum clock_ccsm_idx { + CLOCK_CCSM_IDX_CPU_GROUP_LITTLE, + CLOCK_CCSM_IDX_CPU_GROUP_MID, + CLOCK_CCSM_IDX_CPU_GROUP_BIG, + CLOCK_CCSM_IDX_COUNT, +}; + /*! * \brief Selectable clock sources for TC4 cluster clocks. */ diff --git a/product/totalcompute/tc4/scp_css/CMakeLists.txt b/product/totalcompute/tc4/scp_css/CMakeLists.txt index 0518f632a..8bfbd8e04 100644 --- a/product/totalcompute/tc4/scp_css/CMakeLists.txt +++ b/product/totalcompute/tc4/scp_css/CMakeLists.txt @@ -128,7 +128,8 @@ target_sources( "${CMAKE_CURRENT_SOURCE_DIR}/config_system_pll.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_css_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c") + "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_ccsm.c") if(SCP_ENABLE_RESOURCE_PERMISSIONS) target_sources(scp-css PRIVATE "config_resource_perms.c") diff --git a/product/totalcompute/tc4/scp_css/Firmware.cmake b/product/totalcompute/tc4/scp_css/Firmware.cmake index 7812fb2e4..789699dce 100644 --- a/product/totalcompute/tc4/scp_css/Firmware.cmake +++ b/product/totalcompute/tc4/scp_css/Firmware.cmake @@ -73,6 +73,7 @@ list(APPEND SCP_MODULES "scmi-perf") list(APPEND SCP_MODULES "mock-psu") list(APPEND SCP_MODULES "psu") list(APPEND SCP_MODULES "tc-system") +list(APPEND SCP_MODULES "ccsm") if (SCP_PLATFORM_VARIANT STREQUAL "1" OR SCP_PLATFORM_VARIANT STREQUAL "2") set(SCP_ENABLE_PLUGIN_HANDLER TRUE) diff --git a/product/totalcompute/tc4/scp_css/config_ccsm.c b/product/totalcompute/tc4/scp_css/config_ccsm.c new file mode 100644 index 000000000..77662553f --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_ccsm.c @@ -0,0 +1,360 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_mmap.h" +#include "tc4_core.h" + +#include + +#include +#include +#include +#include + +/*! The slowest rate at which the PLL hardware can operate. */ +#define TC4_PLL_MIN_RATE (100UL * FWK_MHZ) + +/*! The fastest rate at which the PLL hardware can operate. */ +#define TC4_PLL_MAX_RATE (4UL * FWK_GHZ) + +/*! The maximum precision that can be used when setting the PLL rate. */ +#define TC4_PLL_MIN_INTERVAL (100UL * FWK_MHZ) + +static const struct mod_ccsm_clock_rate_reg_value register_table_sc_pll[] = { + { .clock_rate_hz = 100 * FWK_MHZ, + .pll_settings_0 = 0x36010460, + .pll_settings_1 = 0x00000eee }, + { .clock_rate_hz = 200 * FWK_MHZ, + .pll_settings_0 = 0x16010460, + .pll_settings_1 = 0x00000eee }, + { .clock_rate_hz = 300 * FWK_MHZ, + .pll_settings_0 = 0x140104b0, + .pll_settings_1 = 0x00000fff }, + { .clock_rate_hz = 400 * FWK_MHZ, + .pll_settings_0 = 0x06010460, + .pll_settings_1 = 0x00000eee }, + { .clock_rate_hz = 500 * FWK_MHZ, + .pll_settings_0 = 0x040103f0, + .pll_settings_1 = 0x00000555 }, + { .clock_rate_hz = 600 * FWK_MHZ, + .pll_settings_0 = 0x040104b0, + .pll_settings_1 = 0x00000fff }, + { .clock_rate_hz = 700 * FWK_MHZ, + .pll_settings_0 = 0x03010460, + .pll_settings_1 = 0x00000eee }, + { .clock_rate_hz = 800 * FWK_MHZ, + .pll_settings_0 = 0x03010510, + .pll_settings_1 = 0x00000110 }, + { .clock_rate_hz = 900 * FWK_MHZ, + .pll_settings_0 = 0x02010440, + .pll_settings_1 = 0x00000666 }, + { .clock_rate_hz = 1000 * FWK_MHZ, + .pll_settings_0 = 0x020104b0, + .pll_settings_1 = 0x00000fff }, + { .clock_rate_hz = 1100 * FWK_MHZ, + .pll_settings_0 = 0x02010530, + .pll_settings_1 = 0x00000999 }, + { .clock_rate_hz = 1200 * FWK_MHZ, + .pll_settings_0 = 0x020105b0, + .pll_settings_1 = 0x00000333 }, + { .clock_rate_hz = 1300 * FWK_MHZ, + .pll_settings_0 = 0x01010410, + .pll_settings_1 = 0x00000ddd }, + { .clock_rate_hz = 1400 * FWK_MHZ, + .pll_settings_0 = 0x01010460, + .pll_settings_1 = 0x00000eee }, + { .clock_rate_hz = 1500 * FWK_MHZ, + .pll_settings_0 = 0x010104b0, + .pll_settings_1 = 0x00000fff }, + { .clock_rate_hz = 1600 * FWK_MHZ, + .pll_settings_0 = 0x01010510, + .pll_settings_1 = 0x00000110 }, + { .clock_rate_hz = 1700 * FWK_MHZ, + .pll_settings_0 = 0x01010560, + .pll_settings_1 = 0x00000221 }, + { .clock_rate_hz = 1800 * FWK_MHZ, + .pll_settings_0 = 0x010105b0, + .pll_settings_1 = 0x00000333 }, + { .clock_rate_hz = 1900 * FWK_MHZ, + .pll_settings_0 = 0x01010600, + .pll_settings_1 = 0x00000444 }, + { .clock_rate_hz = 2000 * FWK_MHZ, + .pll_settings_0 = 0x01010650, + .pll_settings_1 = 0x00000555 }, + { .clock_rate_hz = 2100 * FWK_MHZ, + .pll_settings_0 = 0x010106a0, + .pll_settings_1 = 0x00000666 }, + { .clock_rate_hz = 2200 * FWK_MHZ, + .pll_settings_0 = 0x010106f0, + .pll_settings_1 = 0x00000777 }, + { .clock_rate_hz = 2300 * FWK_MHZ, + .pll_settings_0 = 0x01010740, + .pll_settings_1 = 0x00000888 }, + { .clock_rate_hz = 2400 * FWK_MHZ, + .pll_settings_0 = 0x01010790, + .pll_settings_1 = 0x00000999 }, + { .clock_rate_hz = 2500 * FWK_MHZ, + .pll_settings_0 = 0x000103f0, + .pll_settings_1 = 0x00000555 }, + { .clock_rate_hz = 2600 * FWK_MHZ, + .pll_settings_0 = 0x00010410, + .pll_settings_1 = 0x00000ddd }, + { .clock_rate_hz = 2700 * FWK_MHZ, + .pll_settings_0 = 0x00010440, + .pll_settings_1 = 0x00000666 }, + { .clock_rate_hz = 2800 * FWK_MHZ, + .pll_settings_0 = 0x00010460, + .pll_settings_1 = 0x00000eee }, + { .clock_rate_hz = 2900 * FWK_MHZ, + .pll_settings_0 = 0x00010490, + .pll_settings_1 = 0x00000777 }, + { .clock_rate_hz = 3000 * FWK_MHZ, + .pll_settings_0 = 0x000104b0, + .pll_settings_1 = 0x00000fff }, + { .clock_rate_hz = 3100 * FWK_MHZ, + .pll_settings_0 = 0x000104e0, + .pll_settings_1 = 0x00000888 }, + { .clock_rate_hz = 3200 * FWK_MHZ, + .pll_settings_0 = 0x00010510, + .pll_settings_1 = 0x00000110 }, + { .clock_rate_hz = 3300 * FWK_MHZ, + .pll_settings_0 = 0x00010530, + .pll_settings_1 = 0x00000999 }, + { .clock_rate_hz = 3400 * FWK_MHZ, + .pll_settings_0 = 0x00010560, + .pll_settings_1 = 0x00000221 }, + { .clock_rate_hz = 3500 * FWK_MHZ, + .pll_settings_0 = 0x00010580, + .pll_settings_1 = 0x00000aaa }, + { .clock_rate_hz = 3600 * FWK_MHZ, + .pll_settings_0 = 0x000105b0, + .pll_settings_1 = 0x00000333 }, + { .clock_rate_hz = 3700 * FWK_MHZ, + .pll_settings_0 = 0x000105d0, + .pll_settings_1 = 0x00000bbb }, + { .clock_rate_hz = 3800 * FWK_MHZ, + .pll_settings_0 = 0x00010600, + .pll_settings_1 = 0x00000444 }, + { .clock_rate_hz = 3900 * FWK_MHZ, + .pll_settings_0 = 0x00010620, + .pll_settings_1 = 0x00000ccc }, + { .clock_rate_hz = 4000 * FWK_MHZ, + .pll_settings_0 = 0x00010650, + .pll_settings_1 = 0x00000555 }, +}; + +static const struct mod_ccsm_clock_rate default_clock_cpu_group_little = { + 1500 * FWK_MHZ, + 1400 * FWK_MHZ +}; + +static const struct mod_ccsm_clock_rate default_clock_cpu_group_mid = { + 1900 * FWK_MHZ, + 1700 * FWK_MHZ +}; + +static const struct mod_ccsm_clock_rate default_clock_cpu_group_big = { + 2200 * FWK_MHZ, + 2000 * FWK_MHZ +}; + +static const struct mod_ccsm_clock_rate default_clock_cpu_group_gpu = { + 1000 * FWK_MHZ, + 0 * FWK_MHZ +}; + +static const struct mod_ccsm_dm_config dm_config_default = { + .strategy = MOD_CCSM_DM_NOM_ONLY, + .dd = MOD_CCSM_DM_ARM_DD, + .soff = MOD_CCSM_DM_SW_SOFF_STOP, + .transition_pause = 100, + .mitigation_duration = 10000 +}; + +static const struct mod_ccsm_mod_config mod_config_default = { + .numerator_oc = 1, + .numerator_regular = 1, + .denominator = 1 +}; + +static const struct mod_ccsm_clock_rate rate_table_cpu_group_little[] = { + { /* Super Underdrive */ + .nominal_clock_rate_hz = 800 * FWK_MHZ, + .fallback_clock_rate_hz = 0 }, + { /* Underdrive */ + .nominal_clock_rate_hz = 1200 * FWK_MHZ, + .fallback_clock_rate_hz = 0 }, + { /* Nominal */ + .nominal_clock_rate_hz = 1500 * FWK_MHZ, + .fallback_clock_rate_hz = 1400 * FWK_MHZ }, + { /* Overdrive */ + .nominal_clock_rate_hz = 1800 * FWK_MHZ, + .fallback_clock_rate_hz = 1700 * FWK_MHZ }, + { /* Super Overdrive */ + .nominal_clock_rate_hz = 2200 * FWK_MHZ, + .fallback_clock_rate_hz = 1900 * FWK_MHZ }, +}; + +static const struct mod_ccsm_clock_rate rate_table_cpu_group_mid[] = { + { /* Super Underdrive */ + .nominal_clock_rate_hz = 900 * FWK_MHZ, + .fallback_clock_rate_hz = 0 }, + { /* Underdrive */ + .nominal_clock_rate_hz = 1400 * FWK_MHZ, + .fallback_clock_rate_hz = 0 }, + { /* Nominal */ + .nominal_clock_rate_hz = 1900 * FWK_MHZ, + .fallback_clock_rate_hz = 1700 * FWK_MHZ }, + { /* Overdrive */ + .nominal_clock_rate_hz = 2300 * FWK_MHZ, + .fallback_clock_rate_hz = 2000 * FWK_MHZ }, + { /* Super Overdrive */ + .nominal_clock_rate_hz = 2600 * FWK_MHZ, + .fallback_clock_rate_hz = 2400 * FWK_MHZ }, +}; + +static const struct mod_ccsm_clock_rate rate_table_cpu_group_big[] = { + { /* Super Underdrive */ + .nominal_clock_rate_hz = 1100 * FWK_MHZ, + .fallback_clock_rate_hz = 0 }, + { /* Underdrive */ + .nominal_clock_rate_hz = 1600 * FWK_MHZ, + .fallback_clock_rate_hz = 0 }, + { /* Nominal */ + .nominal_clock_rate_hz = 2200 * FWK_MHZ, + .fallback_clock_rate_hz = 2000 * FWK_MHZ }, + { /* Overdrive */ + .nominal_clock_rate_hz = 2600 * FWK_MHZ, + .fallback_clock_rate_hz = 2400 * FWK_MHZ }, + { /* Super Overdrive */ + .nominal_clock_rate_hz = 3000 * FWK_MHZ, + .fallback_clock_rate_hz = 2700 * FWK_MHZ }, +}; + +static const struct mod_ccsm_clock_rate rate_table_cpu_group_gpu[] = { + { .nominal_clock_rate_hz = 1000 * FWK_MHZ, + .fallback_clock_rate_hz = 0 * FWK_MHZ }, + { .nominal_clock_rate_hz = 1300 * FWK_MHZ, + .fallback_clock_rate_hz = 0 * FWK_MHZ }, +}; + +static const struct fwk_element ccsm_element_table[] = { + [CLOCK_CCSM_IDX_CPU_GROUP_LITTLE] = + { + .name = "CPU_CCSM_" TC4_GROUP_LITTLE_NAME, + .data = &((struct mod_ccsm_dev_config){ + .rate_lookup_table_is_provided = true, + .minimum_clock_rate_fallback_enable_hz = 1700 * FWK_MHZ, + .min_clock_rate_hz = TC4_PLL_MIN_RATE, + .max_clock_rate_hz = TC4_PLL_MAX_RATE, + .clock_rate_step_hz = TC4_PLL_MIN_INTERVAL, + /* FVP has been hardcoded to use the little CCSM + * as the clock selector is not currently available. + * This differs from the default configuration which + * uses the DSU CCSM for the little core. + * TODO: When the clock selectors have been introduced + * in the FVP, use them to select the clock + * specified here */ +#if defined(PLAT_FVP) + .base_address = SCP_CCSM_LIT, +#else + .base_address = SCP_CCSM_DSU, +#endif + .default_rates_table = &default_clock_cpu_group_little, + .droop_mitigation_default = &dm_config_default, + .modulator_default = &mod_config_default, + .pll_0_static_reg_value = 0x00003830, + .pll_1_static_reg_value = 0x00003830, + .modulator_count = 1, + .register_rate_table = register_table_sc_pll, + .register_rate_count = FWK_ARRAY_SIZE(register_table_sc_pll), + .rate_table = rate_table_cpu_group_little, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little), + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + }), + }, + [CLOCK_CCSM_IDX_CPU_GROUP_MID] = + { + .name = "CPU_CCSM_" TC4_GROUP_MID_NAME, + .data = &((struct mod_ccsm_dev_config){ + .rate_lookup_table_is_provided = true, + .minimum_clock_rate_fallback_enable_hz = 1700 * FWK_MHZ, + .min_clock_rate_hz = TC4_PLL_MIN_RATE, + .max_clock_rate_hz = TC4_PLL_MAX_RATE, + .clock_rate_step_hz = TC4_PLL_MIN_INTERVAL, + .base_address = SCP_CCSM_MID, + .default_rates_table = &default_clock_cpu_group_mid, + .droop_mitigation_default = &dm_config_default, + .modulator_default = &mod_config_default, + .pll_0_static_reg_value = 0x00003830, + .pll_1_static_reg_value = 0x00003830, + .modulator_count = 1, + .register_rate_table = register_table_sc_pll, + .register_rate_count = FWK_ARRAY_SIZE(register_table_sc_pll), + .rate_table = rate_table_cpu_group_mid, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + }), + }, + [CLOCK_CCSM_IDX_CPU_GROUP_BIG] = + { + .name = "CPU_CCSM_" TC4_GROUP_BIG_NAME, + .data = &((struct mod_ccsm_dev_config){ + .rate_lookup_table_is_provided = true, + .minimum_clock_rate_fallback_enable_hz = 1700 * FWK_MHZ, + .min_clock_rate_hz = TC4_PLL_MIN_RATE, + .max_clock_rate_hz = TC4_PLL_MAX_RATE, + .clock_rate_step_hz = TC4_PLL_MIN_INTERVAL, + .base_address = SCP_CCSM_BIG, + .default_rates_table = &default_clock_cpu_group_big, + .droop_mitigation_default = &dm_config_default, + .modulator_default = &mod_config_default, + .pll_0_static_reg_value = 0x00003830, + .pll_1_static_reg_value = 0x00003830, + .modulator_count = 1, + .register_rate_table = register_table_sc_pll, + .register_rate_count = FWK_ARRAY_SIZE(register_table_sc_pll), + .rate_table = rate_table_cpu_group_big, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big), + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + }), + }, + [CLOCK_CCSM_IDX_GPU] = + { + .name = "CCSM_GPU", + .data = &((struct mod_ccsm_dev_config){ + .rate_lookup_table_is_provided = true, + .minimum_clock_rate_fallback_enable_hz = 1700 * FWK_MHZ, + .min_clock_rate_hz = TC4_PLL_MIN_RATE, + .max_clock_rate_hz = TC4_PLL_MAX_RATE, + .clock_rate_step_hz = TC4_PLL_MIN_INTERVAL, + .base_address = SCP_CCSM_GPUTOP, + .default_rates_table = &default_clock_cpu_group_gpu, + .droop_mitigation_default = &dm_config_default, + .modulator_default = &mod_config_default, + .pll_0_static_reg_value = 0x00003830, + .pll_1_static_reg_value = 0x00003830, + .modulator_count = 1, + .register_rate_table = register_table_sc_pll, + .register_rate_count = FWK_ARRAY_SIZE(register_table_sc_pll), + .rate_table = rate_table_cpu_group_gpu, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gpu), + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + }), + }, + [CLOCK_CCSM_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *ccsm_get_element_table(fwk_id_t module_id) +{ + return ccsm_element_table; +}; + +const struct fwk_module_config config_ccsm = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(ccsm_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_clock.c b/product/totalcompute/tc4/scp_css/config_clock.c index 0254fdbbf..29b246827 100644 --- a/product/totalcompute/tc4/scp_css/config_clock.c +++ b/product/totalcompute/tc4/scp_css/config_clock.c @@ -27,6 +27,7 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, CLOCK_CSS_IDX_CPU_GROUP_GROUP_LITTLE), + CLOCK_CCSM_IDX_CPU_GROUP_LITTLE), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), @@ -38,7 +39,7 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_GROUP_MID), + CLOCK_CCSM_IDX_CPU_GROUP_MID), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), @@ -50,7 +51,7 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_GROUP_BIG), + CLOCK_CCSM_IDX_CPU_GROUP_BIG), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), -- GitLab From ed76ad8047e3076b2442a03c3b63c24da6560de4 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Fri, 22 Mar 2024 15:14:28 +0000 Subject: [PATCH 3/7] tc4: Add GPU CCSM config and use in clock module Add GPU specific configuration to control its CCSMs. These are then added to the clock module where they can be used by DVFS to control the GPU frequency. We also remove the existing system PLL configuration as this is no longer used. Signed-off-by: Jackson Cooper-Driver Signed-off-by: Noe Galea-Sevilla --- product/totalcompute/tc4/include/clock_soc.h | 2 +- product/totalcompute/tc4/scp_css/config_clock.c | 8 ++++---- .../totalcompute/tc4/scp_css/config_system_pll.c | 13 ------------- 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/product/totalcompute/tc4/include/clock_soc.h b/product/totalcompute/tc4/include/clock_soc.h index 971106d1f..f93d7ba5a 100644 --- a/product/totalcompute/tc4/include/clock_soc.h +++ b/product/totalcompute/tc4/include/clock_soc.h @@ -29,7 +29,6 @@ enum clock_pll_idx { CLOCK_PLL_IDX_DPU, CLOCK_PLL_IDX_PIX0, CLOCK_PLL_IDX_PIX1, - CLOCK_PLL_IDX_GPU, CLOCK_PLL_IDX_COUNT }; @@ -60,6 +59,7 @@ enum clock_ccsm_idx { CLOCK_CCSM_IDX_CPU_GROUP_LITTLE, CLOCK_CCSM_IDX_CPU_GROUP_MID, CLOCK_CCSM_IDX_CPU_GROUP_BIG, + CLOCK_CCSM_IDX_GPU, CLOCK_CCSM_IDX_COUNT, }; diff --git a/product/totalcompute/tc4/scp_css/config_clock.c b/product/totalcompute/tc4/scp_css/config_clock.c index 29b246827..bbcd86c12 100644 --- a/product/totalcompute/tc4/scp_css/config_clock.c +++ b/product/totalcompute/tc4/scp_css/config_clock.c @@ -98,11 +98,11 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .name = "GPU", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_GPU), + FWK_MODULE_IDX_CCSM, + CLOCK_CCSM_IDX_GPU), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + FWK_MODULE_IDX_CCSM, + MOD_CCSM_CLOCK_API), }), }, { 0 }, /* Termination description. */ diff --git a/product/totalcompute/tc4/scp_css/config_system_pll.c b/product/totalcompute/tc4/scp_css/config_system_pll.c index 37f1da535..d47dbe639 100644 --- a/product/totalcompute/tc4/scp_css/config_system_pll.c +++ b/product/totalcompute/tc4/scp_css/config_system_pll.c @@ -112,19 +112,6 @@ static const struct fwk_element system_pll_element_table[ .defer_initialization = false, }), }, - [CLOCK_PLL_IDX_GPU] = - { - .name = "GPU_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_GPU, - .status_reg = NULL, - .initial_rate = 800 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - .defer_initialization = false, - }), - }, [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ }; -- GitLab From bdbfd34a11e4f765a52e34863ea9b7766ff6e9b2 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Tue, 23 Jan 2024 14:54:08 +0000 Subject: [PATCH 4/7] tc4: Use CCSM instead of CSS clock Use the CCSM module instead of the CSS clock module for controlling the clock frequencies of the TC4 CPUs. Signed-off-by: Jackson Cooper-Driver --- product/totalcompute/tc4/include/clock_soc.h | 3 - .../totalcompute/tc4/scp_css/config_clock.c | 20 +- .../tc4/scp_css/config_css_clock.c | 249 ------------------ 3 files changed, 10 insertions(+), 262 deletions(-) diff --git a/product/totalcompute/tc4/include/clock_soc.h b/product/totalcompute/tc4/include/clock_soc.h index f93d7ba5a..d76737ded 100644 --- a/product/totalcompute/tc4/include/clock_soc.h +++ b/product/totalcompute/tc4/include/clock_soc.h @@ -87,9 +87,6 @@ enum mod_clusclock_source_tc4 { * CSS clock indexes. */ enum clock_css_idx { - CLOCK_CSS_IDX_CPU_GROUP_GROUP_LITTLE, - CLOCK_CSS_IDX_CPU_GROUP_GROUP_MID, - CLOCK_CSS_IDX_CPU_GROUP_GROUP_BIG, CLOCK_CSS_IDX_DPU, CLOCK_CSS_IDX_COUNT }; diff --git a/product/totalcompute/tc4/scp_css/config_clock.c b/product/totalcompute/tc4/scp_css/config_clock.c index bbcd86c12..d46a83c84 100644 --- a/product/totalcompute/tc4/scp_css/config_clock.c +++ b/product/totalcompute/tc4/scp_css/config_clock.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -25,12 +26,11 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .name = "CPU_GROUP_" TC4_GROUP_LITTLE_NAME, .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_GROUP_LITTLE), + FWK_MODULE_IDX_CCSM, CLOCK_CCSM_IDX_CPU_GROUP_LITTLE), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), + FWK_MODULE_IDX_CCSM, + MOD_CCSM_CLOCK_API), }), }, [CLOCK_IDX_CPU_GROUP_GROUP_MID] = @@ -38,11 +38,11 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .name = "CPU_GROUP_" TC4_GROUP_MID_NAME, .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, + FWK_MODULE_IDX_CCSM, CLOCK_CCSM_IDX_CPU_GROUP_MID), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), + FWK_MODULE_IDX_CCSM, + MOD_CCSM_CLOCK_API), }), }, [CLOCK_IDX_CPU_GROUP_GROUP_BIG] = @@ -50,11 +50,11 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .name = "CPU_GROUP_" TC4_GROUP_BIG_NAME, .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, + FWK_MODULE_IDX_CCSM, CLOCK_CCSM_IDX_CPU_GROUP_BIG), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), + FWK_MODULE_IDX_CCSM, + MOD_CCSM_CLOCK_API), }), }, [CLOCK_IDX_DPU] = diff --git a/product/totalcompute/tc4/scp_css/config_css_clock.c b/product/totalcompute/tc4/scp_css/config_css_clock.c index 2d932d316..61546e79c 100644 --- a/product/totalcompute/tc4/scp_css/config_css_clock.c +++ b/product/totalcompute/tc4/scp_css/config_css_clock.c @@ -17,261 +17,12 @@ #include #include -static const struct mod_css_clock_rate rate_table_cpu_group_little[5] = { - { - /* Super Underdrive */ - .rate = 768 * FWK_MHZ, - .pll_rate = 768 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Underdrive */ - .rate = 1153 * FWK_MHZ, - .pll_rate = 1153 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Nominal */ - .rate = 1537 * FWK_MHZ, - .pll_rate = 1537 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Overdrive */ - .rate = 1844 * FWK_MHZ, - .pll_rate = 1844 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Super Overdrive */ - .rate = 2152 * FWK_MHZ, - .pll_rate = 2152 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, -}; - -static const struct mod_css_clock_rate rate_table_cpu_group_mid[5] = { - { - /* Super Underdrive */ - .rate = 946 * FWK_MHZ, - .pll_rate = 946 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Underdrive */ - .rate = 1419 * FWK_MHZ, - .pll_rate = 1419 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Nominal */ - .rate = 1893 * FWK_MHZ, - .pll_rate = 1893 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Overdrive */ - .rate = 2271 * FWK_MHZ, - .pll_rate = 2271 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Super Overdrive */ - .rate = 2650 * FWK_MHZ, - .pll_rate = 2650 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, -}; - -static const struct mod_css_clock_rate rate_table_cpu_group_big[5] = { - { - /* Super Underdrive */ - .rate = 1088 * FWK_MHZ, - .pll_rate = 1088 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Underdrive */ - .rate = 1632 * FWK_MHZ, - .pll_rate = 1632 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Nominal */ - .rate = 2176 * FWK_MHZ, - .pll_rate = 2176 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Overdrive */ - .rate = 2612 * FWK_MHZ, - .pll_rate = 2612 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Super Overdrive */ - .rate = 3047 * FWK_MHZ, - .pll_rate = 3047 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, -}; - -static const fwk_id_t member_table_cpu_group_little[2] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), -}; - -static const fwk_id_t member_table_cpu_group_mid[4] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5), -}; - -static const fwk_id_t member_table_cpu_group_big[2] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7), -}; - static const fwk_id_t member_table_dpu[1] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_DPU), }; static const struct fwk_element css_clock_element_table[ CLOCK_CSS_IDX_COUNT + 1] = { - [CLOCK_CSS_IDX_CPU_GROUP_GROUP_LITTLE] = - { - .name = "CPU_GROUP_LITTLE", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_little, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little), - .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_GROUP_LITTLE), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_little, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_little), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 1537 * FWK_MHZ, - .modulation_supported = true, - }), - }, - [CLOCK_CSS_IDX_CPU_GROUP_GROUP_MID] = - { - .name = "CPU_GROUP_MID", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_mid, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), - .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_GROUP_MID), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_mid, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_mid), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 1893 * FWK_MHZ, - .modulation_supported = true, - }), - }, - [CLOCK_CSS_IDX_CPU_GROUP_GROUP_BIG] = - { - .name = "CPU_GROUP_BIG", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_big, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big), - .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_GROUP_BIG), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_big, - .member_count = - FWK_ARRAY_SIZE(member_table_cpu_group_big), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 2176 * FWK_MHZ, - .modulation_supported = true, - }), - }, [CLOCK_CSS_IDX_DPU] = { .name = "DPU", -- GitLab From b5c55e2e3ec753cb47c58e380ca732a714d84db3 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Thu, 6 Jun 2024 16:44:15 +0100 Subject: [PATCH 5/7] tc4: Use SC_PLL for DPU, PIXEL0/1 The DPU and PIXEL clock frequencies are controlled with the SC_PLL. Make use of this PLL in the TC4 clock in order to allow for changing of these clock frequencies. Signed-off-by: Jackson Cooper-Driver --- product/totalcompute/tc4/include/clock_soc.h | 6 +- product/totalcompute/tc4/include/scp_mmap.h | 34 ++--- product/totalcompute/tc4/include/tc4_atu.h | 7 +- .../totalcompute/tc4/scp_css/CMakeLists.txt | 3 +- .../totalcompute/tc4/scp_css/Firmware.cmake | 3 +- .../totalcompute/tc4/scp_css/config_clock.c | 27 ++-- .../tc4/scp_css/config_css_clock.c | 60 --------- .../totalcompute/tc4/scp_css/config_sc_pll.c | 63 +++++++++ .../tc4/scp_css/config_system_pll.c | 126 ------------------ 9 files changed, 97 insertions(+), 232 deletions(-) delete mode 100644 product/totalcompute/tc4/scp_css/config_css_clock.c create mode 100644 product/totalcompute/tc4/scp_css/config_sc_pll.c delete mode 100644 product/totalcompute/tc4/scp_css/config_system_pll.c diff --git a/product/totalcompute/tc4/include/clock_soc.h b/product/totalcompute/tc4/include/clock_soc.h index d76737ded..4b2087280 100644 --- a/product/totalcompute/tc4/include/clock_soc.h +++ b/product/totalcompute/tc4/include/clock_soc.h @@ -18,14 +18,12 @@ #define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) +#define CLOCK_RATE_COMPANION_REFCLK (38.4 * FWK_MHZ) + /* * PLL clock indexes. */ enum clock_pll_idx { - CLOCK_PLL_IDX_CPU_GROUP_LITTLE, - CLOCK_PLL_IDX_CPU_GROUP_MID, - CLOCK_PLL_IDX_CPU_GROUP_BIG, - CLOCK_PLL_IDX_SYS, CLOCK_PLL_IDX_DPU, CLOCK_PLL_IDX_PIX0, CLOCK_PLL_IDX_PIX1, diff --git a/product/totalcompute/tc4/include/scp_mmap.h b/product/totalcompute/tc4/include/scp_mmap.h index 0012c5bfb..4cb9c0414 100644 --- a/product/totalcompute/tc4/include/scp_mmap.h +++ b/product/totalcompute/tc4/include/scp_mmap.h @@ -92,29 +92,21 @@ #endif #define SCP_PLL_BASE (SCP_ATU_LOG_ADDR_PLL) -#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) -#define SCP_PLL_GPU (SCP_PLL_BASE + 0x00000008) -#define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014) -#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018) -#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C) -#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) - -#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) -#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) -#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) -#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) +#define SCP_PLL_DPU (SCP_PLL_BASE + 0x00000) +#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x10000) +#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x20000) /* CCSM registers */ -#define SCP_CCSM_BASE (SCP_ATU_LOG_ADDR_CCSM) -#define SCP_CCSM_DSU (SCP_CCSM_BASE + 0x000000) -#define SCP_CCSM_LIT (SCP_CCSM_BASE + 0x010000) -#define SCP_CCSM_CME (SCP_CCSM_BASE + 0x020000) -#define SCP_CCSM_MID (SCP_CCSM_BASE + 0x030000) -#define SCP_CCSM_BIG (SCP_CCSM_BASE + 0x040000) -#define SCP_CCSM_GPUTOP (SCP_CCSM_BASE + 0x100000) -#define SCP_CCSM_GPUSC (SCP_CCSM_BASE + 0x110000) -#define SCP_CCSM_GPUNE (SCP_CCSM_BASE + 0x120000) -#define SCP_CCSM_GPUCGP (SCP_CCSM_BASE + 0x130000) +#define SCP_CCSM_BASE (SCP_ATU_LOG_ADDR_CCSM) +#define SCP_CCSM_DSU (SCP_CCSM_BASE + 0x000000) +#define SCP_CCSM_LIT (SCP_CCSM_BASE + 0x010000) +#define SCP_CCSM_CME (SCP_CCSM_BASE + 0x020000) +#define SCP_CCSM_MID (SCP_CCSM_BASE + 0x030000) +#define SCP_CCSM_BIG (SCP_CCSM_BASE + 0x040000) +#define SCP_CCSM_GPUTOP (SCP_CCSM_BASE + 0x100000) +#define SCP_CCSM_GPUSC (SCP_CCSM_BASE + 0x110000) +#define SCP_CCSM_GPUNE (SCP_CCSM_BASE + 0x120000) +#define SCP_CCSM_GPUCGP (SCP_CCSM_BASE + 0x130000) /* AP Context Area */ #define SCP_AP_CONTEXT_BASE \ diff --git a/product/totalcompute/tc4/include/tc4_atu.h b/product/totalcompute/tc4/include/tc4_atu.h index 78b89b9bc..26b59c398 100644 --- a/product/totalcompute/tc4/include/tc4_atu.h +++ b/product/totalcompute/tc4/include/tc4_atu.h @@ -44,8 +44,9 @@ #define SCP_ATU_PHY_ADDR_SHARED_SRAM (0x04000000) #define SCP_ATU_PHY_ADDR_SHARED_NSRAM (0x06000000) #define SCP_ATU_PHY_ADDR_ROS_SOC (0x7FF70000) -#define SCP_ATU_PHY_ADDR_PLL (0x43000000) -#define SCP_ATU_PHY_ADDR_CCSM (0x59800000) +/* Note: resides on companion die so 40-bit address */ +#define SCP_ATU_PHY_ADDR_PLL (0x400ED00000) +#define SCP_ATU_PHY_ADDR_CCSM (0x59800000) /* ATU Region Sizes */ #define SCP_ATU_REG_SIZE_GTCLK_AP (128 * FWK_KIB) @@ -54,7 +55,7 @@ #define SCP_ATU_REG_SIZE_SHARED_NSRAM (512 * FWK_KIB) #define SCP_ATU_REG_SIZE_ROS_SOC (64 * FWK_KIB) #define SCP_ATU_REG_SIZE_CLUSTER_UTIL (10 * FWK_MIB) -#define SCP_ATU_REG_SIZE_PLL (64 * FWK_KIB) +#define SCP_ATU_REG_SIZE_PLL (192 * FWK_KIB) #define SCP_ATU_REG_SIZE_CCSM (8 * FWK_MIB) #endif /* TC4_ATU_H */ diff --git a/product/totalcompute/tc4/scp_css/CMakeLists.txt b/product/totalcompute/tc4/scp_css/CMakeLists.txt index 8bfbd8e04..8439a63c6 100644 --- a/product/totalcompute/tc4/scp_css/CMakeLists.txt +++ b/product/totalcompute/tc4/scp_css/CMakeLists.txt @@ -125,9 +125,8 @@ target_sources( "${CMAKE_CURRENT_SOURCE_DIR}/config_psu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_ppu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_psu.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_system_pll.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_sc_pll.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_css_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_ccsm.c") diff --git a/product/totalcompute/tc4/scp_css/Firmware.cmake b/product/totalcompute/tc4/scp_css/Firmware.cmake index 789699dce..47789e8b5 100644 --- a/product/totalcompute/tc4/scp_css/Firmware.cmake +++ b/product/totalcompute/tc4/scp_css/Firmware.cmake @@ -60,9 +60,8 @@ list(APPEND SCP_MODULES "mhu3") list(APPEND SCP_MODULES "transport") list(APPEND SCP_MODULES "scmi") list(APPEND SCP_MODULES "sds") -list(APPEND SCP_MODULES "system-pll") +list(APPEND SCP_MODULES "sc-pll") list(APPEND SCP_MODULES "pik-clock") -list(APPEND SCP_MODULES "css-clock") list(APPEND SCP_MODULES "clock") list(APPEND SCP_MODULES "power-domain") list(APPEND SCP_MODULES "scmi-power-domain") diff --git a/product/totalcompute/tc4/scp_css/config_clock.c b/product/totalcompute/tc4/scp_css/config_clock.c index d46a83c84..85c7f93cb 100644 --- a/product/totalcompute/tc4/scp_css/config_clock.c +++ b/product/totalcompute/tc4/scp_css/config_clock.c @@ -9,11 +9,10 @@ #include "config_power_domain.h" #include "tc4_core.h" -#include -#include #include -#include +#include #include +#include #include #include @@ -62,23 +61,23 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .name = "DPU", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_DPU), + FWK_MODULE_IDX_SC_PLL, + CLOCK_PLL_IDX_DPU), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), + FWK_MODULE_IDX_SC_PLL, + MOD_SC_PLL_API_TYPE_DEFAULT), }), }, [CLOCK_IDX_PIXEL_0] = { .name = "PIXEL_0", .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SC_PLL, CLOCK_PLL_IDX_PIX0), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + FWK_MODULE_IDX_SC_PLL, + MOD_SC_PLL_API_TYPE_DEFAULT), }), }, [CLOCK_IDX_PIXEL_1] = @@ -86,11 +85,11 @@ static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { .name = "PIXEL_1", .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, + FWK_MODULE_IDX_SC_PLL, CLOCK_PLL_IDX_PIX1), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + FWK_MODULE_IDX_SC_PLL, + MOD_SC_PLL_API_TYPE_DEFAULT), }), }, [CLOCK_IDX_GPU] = diff --git a/product/totalcompute/tc4/scp_css/config_css_clock.c b/product/totalcompute/tc4/scp_css/config_css_clock.c deleted file mode 100644 index 61546e79c..000000000 --- a/product/totalcompute/tc4/scp_css/config_css_clock.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" - -#include -#include -#include - -#include -#include -#include -#include -#include - -static const fwk_id_t member_table_dpu[1] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_DPU), -}; - -static const struct fwk_element css_clock_element_table[ - CLOCK_CSS_IDX_COUNT + 1] = { - [CLOCK_CSS_IDX_DPU] = - { - .name = "DPU", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_NON_INDEXED, - .clock_default_source = - MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, - .clock_switching_source = - MOD_PIK_CLOCK_ACLKDPU_SOURCE_SYSREFCLK, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_DPU), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_dpu, - .member_count = FWK_ARRAY_SIZE(member_table_dpu), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 600 * FWK_MHZ, - .modulation_supported = false, - }), - }, - [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) -{ - return css_clock_element_table; -} - -const struct fwk_module_config config_css_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(css_clock_get_element_table), -}; diff --git a/product/totalcompute/tc4/scp_css/config_sc_pll.c b/product/totalcompute/tc4/scp_css/config_sc_pll.c new file mode 100644 index 000000000..06f279af1 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_sc_pll.c @@ -0,0 +1,63 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_mmap.h" + +#include + +#define SC_PLL_CONTROL_REG0_OFFSET (0x0) +#define SC_PLL_CONTROL_REG1_OFFSET (0x4) + +#define SC_PLL_DPU_RATE_MIN (400 * FWK_MHZ) +#define SC_PLL_DPU_RATE_MAX (800 * FWK_MHZ) +#define SC_PLL_DPU_RATE_INIT (600 * FWK_MHZ) + +#define SC_PLL_PIX0_RATE_MIN (12.5 * FWK_MHZ) +#define SC_PLL_PIX0_RATE_MAX (673 * FWK_MHZ) +#define SC_PLL_PIX0_RATE_INIT (594 * FWK_MHZ) + +#define SC_PLL_PIX1_RATE_MIN (12.5 * FWK_MHZ) +#define SC_PLL_PIX1_RATE_MAX (594 * FWK_MHZ) +#define SC_PLL_PIX1_RATE_INIT (594 * FWK_MHZ) + +#define FOR_EACH_SC_PLL(_func) _func(DPU), _func(PIX0), _func(PIX1) + +#define SC_PLL_ELEMENT_INIT(_pll_name) \ + [CLOCK_PLL_IDX_##_pll_name] = { \ + .name = #_pll_name "_PLL", \ + .data = &((struct mod_sc_pll_dev_config){ \ + .control_reg0 = \ + (void *)(SCP_PLL_##_pll_name + SC_PLL_CONTROL_REG0_OFFSET), \ + .control_reg1 = \ + (void *)(SCP_PLL_##_pll_name + SC_PLL_CONTROL_REG1_OFFSET), \ + .initial_rate = SC_PLL_##_pll_name##_RATE_INIT, \ + .ref_rate = CLOCK_RATE_COMPANION_REFCLK, \ + .dev_param = &((struct mod_sc_pll_dev_param){ \ + .postdiv1_min = 0, \ + .postdiv1_max = 7, \ + .postdiv2_min = 0, \ + .postdiv2_max = 7, \ + .pll_rate_min = SC_PLL_##_pll_name##_RATE_MIN, \ + .pll_rate_max = SC_PLL_##_pll_name##_RATE_MAX, \ + }), \ + }), \ + } + +static const struct fwk_element tc4_pll_element_table[] = { + FOR_EACH_SC_PLL(SC_PLL_ELEMENT_INIT), + { 0 }, +}; + +static const struct fwk_element *tc4_pll_get_element_table(fwk_id_t module_id) +{ + return tc4_pll_element_table; +} + +const struct fwk_module_config config_sc_pll = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tc4_pll_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_system_pll.c b/product/totalcompute/tc4/scp_css/config_system_pll.c deleted file mode 100644 index d47dbe639..000000000 --- a/product/totalcompute/tc4/scp_css/config_system_pll.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_mmap.h" -#include "scp_pik.h" - -#include - -#include -#include -#include -#include - -static const struct fwk_element system_pll_element_table[ - CLOCK_PLL_IDX_COUNT + 1] = - { - [CLOCK_PLL_IDX_CPU_GROUP_LITTLE] = - { - .name = "CPU_PLL_GROUP_LITTLE", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_CPU0, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(0), - .initial_rate = 1537 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_CPU_GROUP_MID] = - { - .name = "CPU_PLL_GROUP_MID", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_CPU1, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(4), - .initial_rate = 1893 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_CPU_GROUP_BIG] = - { - .name = "CPU_PLL_GROUP_BIG", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_CPU2, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(4), - .initial_rate = 2176 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_SYS] = - { - .name = "SYS_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_SYSPLL, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_SYSPLL_LOCK, - .initial_rate = 2000 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_DPU] = - { - .name = "DPU_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_DISPLAY, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_DISPLAYPLL_LOCK, - .initial_rate = 600 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_PIX0] = - { - .name = "PIX0_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_PIX0, - .status_reg = NULL, - .initial_rate = 594 * FWK_MHZ, - .min_rate = 12500 * FWK_KHZ, - .max_rate = 594 * FWK_MHZ, - .min_step = 25 * FWK_KHZ, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_PIX1] = - { - .name = "PIX1_PLL", - .data = &( - (struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_PIX1, - .status_reg = NULL, - .initial_rate = 594 * FWK_MHZ, - .min_rate = 12500 * FWK_KHZ, - .max_rate = 594 * FWK_MHZ, - .min_step = 25 * FWK_KHZ, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ - }; - -static const struct fwk_element *system_pll_get_element_table( - fwk_id_t module_id) -{ - return system_pll_element_table; -} - -const struct fwk_module_config config_system_pll = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table), -}; -- GitLab From 91496c841e52ec1594e70423bf9e2aad5c2f539a Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Mon, 4 Mar 2024 17:44:14 +0000 Subject: [PATCH 6/7] tc4: Remove PIK clock configuration for CPUs The CCSMs are now used for TC4 core clock control so we should not have any configuration for the CPU PIK clocks. Signed-off-by: Jackson Cooper-Driver --- product/totalcompute/tc4/include/clock_soc.h | 13 +- .../tc4/scp_css/config_pik_clock.c | 124 ------------------ 2 files changed, 1 insertion(+), 136 deletions(-) diff --git a/product/totalcompute/tc4/include/clock_soc.h b/product/totalcompute/tc4/include/clock_soc.h index 4b2087280..adae65980 100644 --- a/product/totalcompute/tc4/include/clock_soc.h +++ b/product/totalcompute/tc4/include/clock_soc.h @@ -34,14 +34,6 @@ enum clock_pll_idx { * PIK clock indexes. */ enum clock_pik_idx { - CLOCK_PIK_IDX_CLUS0_CPU0, - CLOCK_PIK_IDX_CLUS0_CPU1, - CLOCK_PIK_IDX_CLUS0_CPU2, - CLOCK_PIK_IDX_CLUS0_CPU3, - CLOCK_PIK_IDX_CLUS0_CPU4, - CLOCK_PIK_IDX_CLUS0_CPU5, - CLOCK_PIK_IDX_CLUS0_CPU6, - CLOCK_PIK_IDX_CLUS0_CPU7, CLOCK_PIK_IDX_GIC, CLOCK_PIK_IDX_PCLKSCP, CLOCK_PIK_IDX_SYSPERCLK, @@ -84,10 +76,7 @@ enum mod_clusclock_source_tc4 { /* * CSS clock indexes. */ -enum clock_css_idx { - CLOCK_CSS_IDX_DPU, - CLOCK_CSS_IDX_COUNT -}; +enum clock_css_idx { CLOCK_CSS_IDX_DPU, CLOCK_CSS_IDX_COUNT }; /* * Clock indexes. diff --git a/product/totalcompute/tc4/scp_css/config_pik_clock.c b/product/totalcompute/tc4/scp_css/config_pik_clock.c index 7cf8a7393..9acd37a56 100644 --- a/product/totalcompute/tc4/scp_css/config_pik_clock.c +++ b/product/totalcompute/tc4/scp_css/config_pik_clock.c @@ -21,33 +21,6 @@ /* * Rate lookup tables */ -static const struct mod_pik_clock_rate rate_table_cpu_group_little[1] = { - { - .rate = 1537 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via CPU PLL */ - }, -}; - -static const struct mod_pik_clock_rate rate_table_cpu_group_mid[1] = { - { - .rate = 1893 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via CPU PLL */ - }, -}; - -static const struct mod_pik_clock_rate rate_table_cpu_group_big[1] = { - { - .rate = 2176 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via CPU PLL */ - }, -}; - static const struct mod_pik_clock_rate rate_table_gicclk[1] = { { .rate = 2000 * FWK_MHZ, @@ -95,103 +68,6 @@ static const struct mod_pik_clock_rate rate_table_dpu[1] = { static const struct fwk_element pik_clock_element_table[ CLOCK_PIK_IDX_COUNT + 1] = { - - [CLOCK_PIK_IDX_CLUS0_CPU0] = { - .name = "CLUS0_CPU0", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[0].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_little, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU1] = { - .name = "CLUS0_CPU1", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[1].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_little, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU2] = { - .name = "CLUS0_CPU2", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[2].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_mid, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU3] = { - .name = "CLUS0_CPU3", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[3].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_mid, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU4] = { - .name = "CLUS0_CPU4", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[4].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[4].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[4].MOD, - .rate_table = rate_table_cpu_group_mid, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU5] = { - .name = "CLUS0_CPU5", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[5].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[5].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[5].MOD, - .rate_table = rate_table_cpu_group_mid, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU6] = { - .name = "CLUS0_CPU6", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[6].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[6].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[6].MOD, - .rate_table = rate_table_cpu_group_big, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU7] = { - .name = "CLUS0_CPU7", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR->CORECLK[7].CTRL, - .divext_reg = &CLUSTER_PIK_PTR->CORECLK[7].DIV, - .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[7].MOD, - .rate_table = rate_table_cpu_group_big, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big), - }), - }, [CLOCK_PIK_IDX_GIC] = { .name = "GIC", .data = &((struct mod_pik_clock_dev_config) { -- GitLab From 36006efb84fee49fad515a0eb2a0cf9a4e70b0b9 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Thu, 6 Jun 2024 16:52:29 +0100 Subject: [PATCH 7/7] tc4: Remove PIK clock This is not present in TC4 and any components which were attempting to use it have now been moved to use the correct PLL control. Therefore, this module is no longer used and can be removed. Signed-off-by: Jackson Cooper-Driver --- .../totalcompute/tc4/scp_css/CMakeLists.txt | 1 - .../totalcompute/tc4/scp_css/Firmware.cmake | 1 - .../tc4/scp_css/config_pik_clock.c | 143 ------------------ 3 files changed, 145 deletions(-) delete mode 100644 product/totalcompute/tc4/scp_css/config_pik_clock.c diff --git a/product/totalcompute/tc4/scp_css/CMakeLists.txt b/product/totalcompute/tc4/scp_css/CMakeLists.txt index 8439a63c6..0fc3fdebf 100644 --- a/product/totalcompute/tc4/scp_css/CMakeLists.txt +++ b/product/totalcompute/tc4/scp_css/CMakeLists.txt @@ -126,7 +126,6 @@ target_sources( "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_ppu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_psu.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_sc_pll.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" "${CMAKE_CURRENT_SOURCE_DIR}/config_ccsm.c") diff --git a/product/totalcompute/tc4/scp_css/Firmware.cmake b/product/totalcompute/tc4/scp_css/Firmware.cmake index 47789e8b5..6a8385607 100644 --- a/product/totalcompute/tc4/scp_css/Firmware.cmake +++ b/product/totalcompute/tc4/scp_css/Firmware.cmake @@ -61,7 +61,6 @@ list(APPEND SCP_MODULES "transport") list(APPEND SCP_MODULES "scmi") list(APPEND SCP_MODULES "sds") list(APPEND SCP_MODULES "sc-pll") -list(APPEND SCP_MODULES "pik-clock") list(APPEND SCP_MODULES "clock") list(APPEND SCP_MODULES "power-domain") list(APPEND SCP_MODULES "scmi-power-domain") diff --git a/product/totalcompute/tc4/scp_css/config_pik_clock.c b/product/totalcompute/tc4/scp_css/config_pik_clock.c deleted file mode 100644 index 9acd37a56..000000000 --- a/product/totalcompute/tc4/scp_css/config_pik_clock.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "cpu_pik.h" -#include "dpu_pik.h" -#include "scp_pik.h" -#include "system_pik.h" - -#include - -#include -#include -#include -#include - -/* - * Rate lookup tables - */ -static const struct mod_pik_clock_rate rate_table_gicclk[1] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_pclkscp[1] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_sysperclk[1] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_uartclk[1] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_dpu[1] = { - { - .rate = 600 * FWK_MHZ, - .source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via display PLL */ - }, -}; - -static const struct fwk_element pik_clock_element_table[ - CLOCK_PIK_IDX_COUNT + 1] = { - [CLOCK_PIK_IDX_GIC] = { - .name = "GIC", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, - .rate_table = rate_table_gicclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_PCLKSCP] = { - .name = "PCLKSCP", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->PCLKSCP_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->PCLKSCP_DIV1, - .rate_table = rate_table_pclkscp, - .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_SYSPERCLK] = { - .name = "SYSPERCLK", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, - .rate_table = rate_table_sysperclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_UARTCLK] = { - .name = "UARTCLK", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->UARTCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->UARTCLK_DIV1, - .rate_table = rate_table_uartclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_DPU] = { - .name = "DPU", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = true, - .control_reg = &DPU_PIK_PTR->ACLKDP_CTRL, - .divsys_reg = &DPU_PIK_PTR->ACLKDP_DIV1, - .divext_reg = &DPU_PIK_PTR->ACLKDP_DIV2, - .rate_table = rate_table_dpu, - .rate_count = FWK_ARRAY_SIZE(rate_table_dpu), - .initial_rate = 600 * FWK_MHZ, - .defer_initialization = true, - }), - }, - [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) -{ - return pik_clock_element_table; -} - -const struct fwk_module_config config_pik_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), -}; -- GitLab