From 836f3510dfd5d99a4dedc372559432a34264fc18 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 19 Jun 2024 14:21:23 +0530 Subject: [PATCH 01/50] rdv3r1: add sid module config data for scpfw The SID peripheral provides information about the platform and its configuration. So, add the configuration data for sid module in scp ramfw. The configuration data includes the expected value of its PID/CID registers for identification. PID5, PID6 and PID7 are not implemented by this peripheral and this is indicated using the valid register bitmap. Signed-off-by: Nancy . Change-Id: Id44cd8f06b13437651e8d7cadeca0b9edf77f82c --- .../neoverse-rd/rdv3r1/scp_ramfw/config_sid.c | 56 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 22 ++++++++ 2 files changed, 78 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_sid.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_sid.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_sid.c new file mode 100644 index 000000000..460be46ac --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_sid.c @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'sid'. + */ + +#include "scp_css_mmap.h" + +#include + +#include +#include +#include + +#define RD_V3_R1_PART_NUMBER 0x7C5 + +static const struct fwk_element subsystem_table[] = { + { .name = "RD-V3-R1", + .data = + &(struct mod_sid_subsystem_config){ + .part_number = RD_V3_R1_PART_NUMBER, + } }, + { 0 }, +}; + +const struct fwk_module_config config_sid = { + .data = &(struct mod_sid_config) { + .sid_base = SCP_SID_BASE, + .valid_pcid_registers = + MOD_PCID_REGISTER_PID0 | + MOD_PCID_REGISTER_PID1 | + MOD_PCID_REGISTER_PID2 | + MOD_PCID_REGISTER_PID3 | + MOD_PCID_REGISTER_PID4 | + MOD_PCID_REGISTER_CID0 | + MOD_PCID_REGISTER_CID1 | + MOD_PCID_REGISTER_CID2 | + MOD_PCID_REGISTER_CID3, + .pcid_expected = { + .PID0 = 0xBC, + .PID1 = 0xB0, + .PID2 = 0x0B, + .PID3 = 0x00, + .PID4 = 0x04, + .CID0 = 0x0D, + .CID1 = 0xF0, + .CID2 = 0x05, + .CID3 = 0xB1, + }, + }, + .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(subsystem_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h new file mode 100644 index 000000000..c2e796b50 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address definitions for the SCP's sub-system and access extending + * into the rest of the CSS. + */ + +#ifndef SCP_CSS_MMAP_H +#define SCP_CSS_MMAP_H + +// clang-format off + +/* SCP sub-system peripherals */ +#define SCP_SID_BASE (0x1A4A0000) + +// clang-format on + +#endif /* SCP_CSS_MMAP_H */ -- GitLab From b5da535aa4c117c8c625cf2d4c9651deee793e6d Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 19 Jun 2024 14:26:40 +0530 Subject: [PATCH 02/50] rdv3r1: add system info module config data in scpfw System Info module provides API to obtain platform configuration data in a platform independent manner. So, add configuration data for system info module in scp ramfw. The configuration data specifies the SID module as the driver to obtain the platform configuration data. Signed-off-by: Nancy . Change-Id: Ib1c5cb8b8a6ca1d78fc92a85533302db34057673 --- .../rdv3r1/scp_ramfw/config_system_info.c | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_system_info.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_info.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_info.c new file mode 100644 index 000000000..45fbbd448 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_info.c @@ -0,0 +1,27 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'system_info'. + */ + +#include +#include + +#include +#include +#include + +#include + +const struct fwk_module_config config_system_info = { + .data = &((struct mod_system_info_config){ + .system_info_driver_module_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SID), + .system_info_driver_data_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SID, + MOD_SID_SYSTEM_INFO_DRIVER_DATA_API_IDX), + }), +}; -- GitLab From 01cd495e479f2822f64ce1ea0c5911977fb9c6c9 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 20 Jun 2024 14:52:14 +0530 Subject: [PATCH 03/50] rdv3r1: add config data for pl011 UART module in scpfw PL011 controller is used as a console port for debug and log messages. Add config data of this controller in scp ramfw, including base address and input clock frequency for the PL011 module to use. Signed-off-by: Nancy . Change-Id: I27175436c9ebd7a4eae36a0e3bcdfb3ec5fa8541 --- .../rdv3r1/scp_ramfw/config_pl011.c | 37 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 1 + 2 files changed, 38 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_pl011.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_pl011.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_pl011.c new file mode 100644 index 000000000..5fe98ec21 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_pl011.c @@ -0,0 +1,37 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'pl011'. + */ + +#include "scp_css_mmap.h" + +#include + +#include +#include +#include +#include + +static const struct fwk_element pl011_table[] = { + { + .name = "scp_uart", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + .pd_id = FWK_ID_NONE_INIT, + }, + }, + { 0 }, +}; + +const struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(pl011_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index c2e796b50..bd2766a18 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -16,6 +16,7 @@ /* SCP sub-system peripherals */ #define SCP_SID_BASE (0x1A4A0000) +#define SCP_UART_BASE (0x44002000) // clang-format on -- GitLab From 5b520a8933b83e588517598abd979340df36a0ad Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 19 Sep 2024 15:07:07 +0530 Subject: [PATCH 04/50] rdv3r1: configure I/O stream for scpfw Configure the macros FMW_IO_STDIN_ID and FWM_IO_STDOUT_ID exposed by the I/O framework to set the SCP UART as the system entity responsible for handling I/O for the scp firmware. Signed-off-by: Nancy . Change-Id: Ib098975dce884143bf21153ffb9ef8139c5d5718 --- .../rdv3r1/scp_ramfw/include/fmw_io.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_io.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_io.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_io.h new file mode 100644 index 000000000..ec7f58908 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_io.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_IO_H +#define FMW_IO_H + +#include +#include + +#define FMW_IO_STDIN_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) +#define FMW_IO_STDOUT_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) + +#endif /* FMW_IO_H */ -- GitLab From ae123d60af4d9bef2eba4329e45fc96e280dba27 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Fri, 22 Nov 2024 20:28:12 +0000 Subject: [PATCH 05/50] rdv3r1: add initial M7 definitions Add Cortex-M7 processor capability definitions and initial IRQ number definitions. Signed-off-by: Nancy . Change-Id: Ieafb198c564e487200d60955eae7c564d59ed6a7 --- .../rdv3r1/scp_ramfw/include/fmw_cmsis.h | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h new file mode 100644 index 000000000..b97d34c1e --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h @@ -0,0 +1,44 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include + +#define __CHECK_DEVICE_DEFINES +#define __CM7_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U +#define __DTCM_PRESENT 1U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U + +/* System Clock Frequency (Core Clock) */ +extern uint32_t SystemCoreClock; + +typedef enum IRQn { + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + IRQn_MAX = INT16_MAX, +} IRQn_Type; + +#include + +#endif /* FMW_CMSIS_H */ -- GitLab From 2468b816f52ca6403226906e1b0e2cbc7919da45 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 25 Jun 2024 14:11:46 +0530 Subject: [PATCH 06/50] rdv3r1: add helpers to obtain platform topology in scpfw Add functions to obtain the platform topology information such as core count and cluster count. These functions can be used in module config data to obtain platform topology. Signed-off-by: Nancy . Change-Id: I59fb1d58819808a27e850d84ce05a6e7c32f130d --- .../rdv3r1/scp_ramfw/include/platform_core.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/platform_core.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/platform_core.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/platform_core.h new file mode 100644 index 000000000..fbde7b8c9 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/platform_core.h @@ -0,0 +1,48 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Platform generic definitions. + */ + +#ifndef PLATFORM_CORE_H +#define PLATFORM_CORE_H + +#include + +/* Actual number of core and clusters implemented */ +#define CORES_PER_CLUSTER 1 +#define NUMBER_OF_CLUSTERS 14 + +/* Maximum number of clusters supported */ +#define MAX_NUM_CLUSTERS 70 + +/* Maximum number of LCP sub-system instances supported */ +#define MAX_NUM_LCP 7 + +/* Number of chips supported on the platform. */ +enum platform_chip_id { PLATFORM_CHIP_0, PLATFORM_CHIP_1, PLATFORM_CHIP_COUNT }; + +static inline unsigned int platform_get_cluster_count(void) +{ + return NUMBER_OF_CLUSTERS; +} + +static inline unsigned int platform_get_core_per_cluster_count( + unsigned int cluster) +{ + fwk_assert(cluster < platform_get_cluster_count()); + + return CORES_PER_CLUSTER; +} + +static inline unsigned int platform_get_core_count(void) +{ + return platform_get_core_per_cluster_count(0) * + platform_get_cluster_count(); +} + +#endif /* PLATFORM_CORE_H */ -- GitLab From 50aedc615d3241e12daf94882ef54612d24664d1 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 26 Nov 2024 07:06:55 +0000 Subject: [PATCH 07/50] rdv3r1: add definitions for address translation windows 0 and 1 There are two address translation windows that allow SCP firmware to map regions of other subsystem memory space into SCP's address space. The size of both of these translation windows is 1GB. All accesses through the address translation windows are further mapped via the ATU and so all the addresses accessed through the address translation windows are treated as logical addresses which are then mapped to physical address by the ATU. Address translation window 0 (ATW0) is used for mapping the cluster utility MMAP region in the AP address map. The cluster utility region address space includes two addressable regions - the AP cluster peripherals and the LCP peripherals. The AP cluster peripherals are mapped in the AP address map at 0x140000000. The LCP peripherals are mapped in the AP address map at 0x160000000. Address translation window 1 (ATW1) is used for mapping the CMN peripheral address region. Add initial definitions of ATW0 and ATW1 and all the mapping that are addressable through it. Signed-off-by: Nancy . Change-Id: Ic2a44779135dccb73b7a6ca91e6224eec00e7a7c --- .../rdv3r1/scp_ramfw/include/scp_atw0_mmap.h | 103 ++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_atw1_mmap.h | 30 +++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 4 + .../scp_ramfw/include/scp_cu_ap_periph.h | 40 +++++++ .../scp_ramfw/include/scp_cu_lcp_periph.h | 112 ++++++++++++++++++ 5 files changed, 289 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw0_mmap.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw1_mmap.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_ap_periph.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_lcp_periph.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw0_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw0_mmap.h new file mode 100644 index 000000000..7ad842f0a --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw0_mmap.h @@ -0,0 +1,103 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address definitions for the carveouts in SCP's Address Translation + * Window 0 (ATW0). + */ + +#ifndef SCP_ATW0_MMAP_H +#define SCP_ATW0_MMAP_H + +#include "platform_core.h" +#include "scp_css_mmap.h" + +// clang-format off + +/* + * Offsets within SCP's Address Translation Window 0. + * + * +----------------------------------------+ SCP_ADDRESS_TRANSLATION_WINDOW0_END + * | | [SCP_ADDRESS_TRANSLATION_WINDOW0_BASE + 1GB] + * | | + * ~ Unmapped Space ~ + * | | + * | | + * +----------------------------------------+ + * | | + * | Peripheral SRAM (1MB) | + * | | + * +----------------------------------------+ SCP_ATW0_AP_PERIPHERAL_SRAM_BASE + * | | + * | Cluster Utility LCP Peripherals | + * | (LCP Group) | + * | | + * +----------------------------------------+ SCP_ATW0_CU_LCP_PERIPH_REGION_BASE + * | | + * | Cluster Utility AP Peripherals | + * | (AP Access Group) | + * | | + * +----------------------------------------+ SCP_ATW0_CU_AP_PERIPH_REGION_BASE + * [SCP_ADDRESS_TRANSLATION_WINDOW0_BASE] + * + */ + +// clang-format on + +/* + * Definitions related to AP Peripheral Region (also referred to as 'AP Access + * Group') in the cluster utility (CU) MMAP address space. + * + * For each cluster on the platform, there is a AP Peripheral Group (or AP + * Access Group) of size SCP_CU_AP_PERIPH_SIZE. All the AP peripheral group + * instances are sequentially placed starting from + * SCP_ATW0_CU_AP_PERIPH_REGION_BASE and the total size of this region is + * SCP_ATW0_CU_AP_PERIPH_REGION_SIZE. The base address of a AP peripheral group + * can be determined using SCP_CU_AP_PERIPH_BASE_N. + * + * ATU is used to map the entire AP peripheral region with the logical base + * address of SCP_ATW0_CU_AP_PERIPH_REGION_BASE and size + * SCP_ATW0_CU_AP_PERIPH_REGION_SIZE. This region is mapped to physical address + * of 0x140000000 in the AP memory map. + * + */ +#define SCP_CU_AP_PERIPH_SIZE (0x200000) +#define SCP_ATW0_CU_AP_PERIPH_REGION_BASE (SCP_ADDRESS_TRANSLATION_WINDOW0_BASE) +#define SCP_ATW0_CU_AP_PERIPH_REGION_SIZE \ + (MAX_NUM_CLUSTERS * SCP_CU_AP_PERIPH_SIZE) +#define SCP_CU_AP_PERIPH_BASE_N(n) \ + (SCP_ATW0_CU_AP_PERIPH_REGION_BASE + (n * SCP_CU_AP_PERIPH_SIZE)) + +/* + * Definitions related to LCP Peripheral Region (also referred to as 'LCP + * Group') in the cluster utility (CU) MMAP address space. + * + * For each cluster on the platform, there is a LCP peripheral (or LCP Group) of + * size SCP_CU_LCP_PERIPH_SIZE. All the LCP peripheral instances are + * sequentially placed starting from SCP_ATW0_CU_LCP_PERIPH_REGION_BASE and the + * total size of this region is SCP_ATW0_CU_LCP_PERIPH_REGION_SIZE. The base + * address of a LCP peripheral can be determined using SCP_CU_LCP_PERIPH_BASE_N. + * + * ATU is used to map the entire LCP peripheral region with the logical base + * address of SCP_ATW0_CU_LCP_PERIPH_REGION_BASE and size + * SCP_ATW0_CU_LCP_PERIPH_REGION_SIZE. This region is mapped to physical address + * of 0x160000000 in the AP memory map. + * + */ +#define SCP_CU_LCP_PERIPH_SIZE (0x200000) +#define SCP_ATW0_CU_LCP_PERIPH_REGION_BASE \ + (SCP_ATW0_CU_AP_PERIPH_REGION_BASE + SCP_ATW0_CU_AP_PERIPH_REGION_SIZE) +#define SCP_ATW0_CU_LCP_PERIPH_REGION_SIZE \ + (MAX_NUM_LCP * SCP_CU_LCP_PERIPH_SIZE) +#define SCP_CU_LCP_PERIPH_BASE_N(n) \ + (SCP_ATW0_CU_LCP_PERIPH_REGION_BASE + (n * SCP_CU_LCP_PERIPH_SIZE)) + +/* Logical address to access AP shared SRAM via ATU */ +#define SCP_ATW0_AP_PERIPHERAL_SRAM_BASE \ + (SCP_ATW0_CU_LCP_PERIPH_REGION_BASE + SCP_ATW0_CU_LCP_PERIPH_REGION_SIZE) +#define SCP_ATW0_AP_PERIPHERAL_SRAM_SIZE (1 * FWK_MIB) + +#endif /* SCP_ATW0_MMAP_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw1_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw1_mmap.h new file mode 100644 index 000000000..572a3c199 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_atw1_mmap.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address definitions for the carveouts in SCP's Address Translation + * Window 1 (ATW1). + */ + +#ifndef SCP_ATW1_MMAP_H +#define SCP_ATW1_MMAP_H + +#include "scp_css_mmap.h" + +/* + * Offsets within SCP's Address Translation Window 1. + * __________________________ + * | | + * | CMN 1G | + * |__________________________| 0xA0000000 + */ +#define SCP_ATW1_CMN_BASE (SCP_ADDRESS_TRANSLATION_WINDOW1_BASE) +#define SCP_ATW1_CMN_SIZE (1 * FWK_GIB) + +/* CMN config space is mapped in the SCP address translation window 1 */ +#define SCP_CMN_BASE SCP_ATW1_CMN_BASE + +#endif /* SCP_ATW1_MMAP_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index bd2766a18..5f863a0d1 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -18,6 +18,10 @@ #define SCP_SID_BASE (0x1A4A0000) #define SCP_UART_BASE (0x44002000) +/* SCP addresses mapped via ATU into address translation windows */ +#define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) +#define SCP_ADDRESS_TRANSLATION_WINDOW1_BASE (0xA0000000) + // clang-format on #endif /* SCP_CSS_MMAP_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_ap_periph.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_ap_periph.h new file mode 100644 index 000000000..1b64a10f4 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_ap_periph.h @@ -0,0 +1,40 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address and offset definitions for the various addressable regions + * within the AP Peripheral memory region in the Cluster Utility memory + * map space. + */ + +#ifndef SCP_CU_AP_PERIPH_H +#define SCP_CU_AP_PERIPH_H + +#include "scp_atw0_mmap.h" + +/* + * Offsets of various blocks within a AP peripheral space (also referred to + * as 'AP Access Group') in the cluster utility MMAP memory region. These + * offsets are applicable to each cluster in the system. + */ + +#define SCP_CU_AP_PERIPH_CORE_MANAGER_OFFSET (0x4000) +#define SCP_CU_AP_PERIPH_CLUSTER_PPU_OFFSET (0x130000) +#define SCP_CU_AP_PERIPH_CORE_PPU_OFFSET (0x180000) + +/* Core Manager base address for a cluster 'n' */ +#define SCP_CU_AP_PERIPH_CORE_MANAGER_BASE_N(n) \ + (SCP_CU_AP_PERIPH_BASE_N(n) + SCP_CU_AP_PERIPH_CORE_MANAGER_OFFSET) + +/* Cluster PPU base address for a cluster 'n' */ +#define SCP_CU_AP_PERIPH_CLUSTER_PPU_BASE(n) \ + (SCP_CU_AP_PERIPH_BASE_N(n) + SCP_CU_AP_PERIPH_CLUSTER_PPU_OFFSET) + +/* Application core PPU base address for a core 'n' */ +#define SCP_CU_AP_PERIPH_CORE_PPU_BASE(n) \ + (SCP_CU_AP_PERIPH_BASE_N(n) + SCP_CU_AP_PERIPH_CORE_PPU_OFFSET) + +#endif /* SCP_CU_AP_PERIPH_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_lcp_periph.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_lcp_periph.h new file mode 100644 index 000000000..7901a8436 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cu_lcp_periph.h @@ -0,0 +1,112 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address and offset definitions for the various addressable regions + * within the LCP Peripheral memory region in the Cluster Utility memory + * map space. + */ + +#ifndef SCP_CU_LCP_PERIPH_H +#define SCP_CU_LCP_PERIPH_H + +#include "scp_atw0_mmap.h" + +#include + +#include + +// clang-format off +struct lcp_extended_control_reg { + FWK_RW uint32_t LCP_CFG; + uint8_t RESERVED0[0x10-0x4]; + FWK_RW uint32_t LCP_RST_SYN; + uint8_t RESERVED1[0x18-0x14]; + FWK_RW uint32_t LCP_EXTEND_RST_SYN; + uint8_t RESERVED2[0x100-0x1C]; + FWK_RW uint32_t LCP_SMCF_TRIGGER_CTRL; + uint8_t RESERVED3[0x900-0x104]; + FWK_RW uint32_t LCP_TCM_ACC_CTRL; + uint8_t RESERVED4[0x910-0x904]; + FWK_RW uint32_t LCP_CTRL_CFG; + uint8_t RESERVED5[0x1000-0x914]; +}; + +struct lcp_external_control_reg { + FWK_RW uint32_t RST_CTRL; + uint8_t RESERVED0[0x10-0x4]; + FWK_RW uint32_t RST_SYN; + uint8_t RESERVED1[0x20-0x14]; + FWK_RW uint32_t UART_CTRL; + uint8_t RESERVED2[0x30-0x24]; + FWK_R uint32_t COMB_IRQ_STAT; + uint8_t RESERVED3[0x38-0x34]; + FWK_RW uint32_t COMB_IRQ_MASK; + uint8_t RESERVED4[0x40-0x3C]; + FWK_R uint32_t LCP_APCONSOLIDATED_IRQ_STAT; + uint8_t RESERVED5[0x48-0x44]; + FWK_RW uint32_t LCP_APCONSOLIDATED_IRQ_MASK; + uint8_t RESERVED6[0x50-0x4C]; + FWK_R uint32_t COREPPU_IRQ_STAT; + uint8_t RESERVED7[0x58-0x54]; + FWK_RW uint32_t COREPPU_IRQ_MASK; + uint8_t RESERVED8[0x60-0x5C]; + FWK_R uint32_t MGI_IRQ_STAT; + uint8_t RESERVED9[0x68-0x64]; + FWK_RW uint32_t MGI_IRQ_MASK; + uint8_t RESERVED10[0x1000-0x6C]; +}; + +struct lcp_control_reg { + uint8_t RESERVED0[0x120-0x0]; + FWK_RW uint32_t CPUWAIT; + uint8_t RESERVED1[0x1000-0x124]; +}; +// clang-format on + +/* + * Offsets of various blocks within a LCP peripheral space (also referred to + * as 'LCP Group') in the cluster utility MMAP memory region. These offsets + * are applicable to each LCP sub-system in the system. + */ + +#define SCP_LCP_PERIPH_CONTROL_OFFSET (0x21000) +#define SCP_LCP_PERIPH_EXTERNAL_CONTROL_OFFSET (0x30000) +#define SCP_LCP_PERIPH_EXTENDED_CONTROL_OFFSET (0x42000) + +#define SCP_LCP_EXTENDED_CONTROL_PTR(IDX) \ + ((struct lcp_extended_control_reg \ + *)(SCP_CU_LCP_PERIPH_BASE_N(IDX) + SCP_LCP_PERIPH_EXTENDED_CONTROL_OFFSET)) + +#define SCP_LCP_EXTERNAL_CONTROL_PTR(IDX) \ + ((struct lcp_external_control_reg \ + *)(SCP_CU_LCP_PERIPH_BASE_N(IDX) + SCP_LCP_PERIPH_EXTERNAL_CONTROL_OFFSET)) + +#define SCP_LCP_CONTROL_PTR(IDX) \ + ((struct lcp_control_reg \ + *)(SCP_CU_LCP_PERIPH_BASE_N(IDX) + SCP_LCP_PERIPH_CONTROL_OFFSET)) + +/* + * LCP external control register block bit-field definitions. + */ +#define LCP_PERIPH_EXTRCTRL_UART_CTRL_EN_SHIFT (0) +#define LCP_PERIPH_EXTRCTRL_UART_CTRL_EN_MASK (1) +#define LCP_PERIPH_EXTRCTRL_UART_CTRL_EN_VAL (1) + +/* + * LCP control register block bit-field definitions. + */ +#define LCP_PERIPH_CONTROL_CPU_WAIT_CPU0WAIT_SHIFT (0) +#define LCP_PERIPH_CONTROL_CPU_WAIT_CPU0WAIT_MASK (1) +#define LCP_PERIPH_CONTROL_CPU_WAIT_CPU0WAIT_VAL (1) + +/* + * LCP extended control register block bit-field definitions. + */ +#define LCP_PERIPH_EXTDCTRL_LCP_CONFIG_CTRL_RATIO_SHIFT (16) +#define LCP_PERIPH_EXTDCTRL_LCP_CONFIG_CTRL_RATIO_MASK (0xFF) + +#endif /* SCP_CU_LCP_PERIPH_H */ -- GitLab From 01854bcfdd6030559f4c0478c2d6d5bc3cdafcf5 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 20 Jun 2024 15:16:25 +0530 Subject: [PATCH 08/50] rdv3r1: add config data for MPU module in scpfw Add config data for armv7m_mpu module in scp ramfw. The SCP RAMs, trusted RAM and non-trusted memory regions are specified. Signed-off-by: Nancy . Change-Id: Ie278e50665382f5da5d5db1305f04f11a47288bb --- .../rdv3r1/scp_ramfw/config_armv7m_mpu.c | 100 ++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 8 ++ .../rdv3r1/scp_ramfw/include/scp_fw_mmap.h | 42 ++++++++ 3 files changed, 150 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_armv7m_mpu.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_armv7m_mpu.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_armv7m_mpu.c new file mode 100644 index 000000000..8f52b8dcb --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_armv7m_mpu.c @@ -0,0 +1,100 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'armv7m_mpu'. + */ + +#include "scp_css_mmap.h" +#include "scp_fw_mmap.h" + +#include + +#include +#include + +#include + +static const ARM_MPU_Region_t regions[] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 0, + 1, + 0, + ARM_MPU_REGION_SIZE_4GB), + }, + { + /* 0x0000_0000 - 0x0003_FFFF */ + .RBAR = ARM_MPU_RBAR(1, SCP_ITC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 0, + ARM_MPU_AP_PRO, + 0, + 0, + 1, + 0, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, + { + /* 0x2000_0000 - 0x2003_FFFF */ + .RBAR = ARM_MPU_RBAR(2, SCP_DTC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 0, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, + { + /* + * SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE is mapped to 0x0000_0000 - + * 0x0000_1FFF in AP memory map. + */ + .RBAR = ARM_MPU_RBAR(3, SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_8KB), + }, + { + /* + * SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_BASE is mapped to 0x0000_2000 - + * 0x0000_3000 in AP memory map. + */ + .RBAR = ARM_MPU_RBAR(4, SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_4KB), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index 5f863a0d1..d544d2d63 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -14,6 +14,14 @@ // clang-format off +/* Base address and size of SCP's ITCM */ +#define SCP_ITC_RAM_BASE (0x00000000) +#define SCP_ITC_RAM_SIZE (256 * 1024) + +/* Base address and size of SCP's DTCM */ +#define SCP_DTC_RAM_BASE (0x20000000) +#define SCP_DTC_RAM_SIZE (256 * 1024) + /* SCP sub-system peripherals */ #define SCP_SID_BASE (0x1A4A0000) #define SCP_UART_BASE (0x44002000) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h new file mode 100644 index 000000000..5f044a29f --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h @@ -0,0 +1,42 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address and size definitions for the various SCP's firmware defined + * memory carveouts. + */ + +#ifndef SCP_FW_MMAP_H +#define SCP_FW_MMAP_H + +#include "scp_atw0_mmap.h" +#include "scp_css_mmap.h" + +#include + +#include +#include + +/* + * AP Peripheral SRAM in the AP memory map with base address of 0x00000000 is + * mapped in the SCP's address translation window 0 (0x60000000 - 0x9FFFFFFF) + * at the offset 'SCP_ATW0_AP_PERIPHERAL_SRAM_BASE' via ATU configuration. + */ + +/* Secure SRAM size reserved by AP */ +#define SCP_AP_PERIPHERAL_SRAM_TRUSTED_RESERVED (0x19000) + +/* AP Peripheral trusted SRAM base in SCP's memory map */ +#define SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE \ + (SCP_ATW0_AP_PERIPHERAL_SRAM_BASE + SCP_AP_PERIPHERAL_SRAM_TRUSTED_RESERVED) +#define SCP_AP_PERIPHERAL_SRAM_TRUSTED_SIZE (4 * FWK_KIB) + +/* AP Peripheral non-trusted SRAM base in SCP's memory map */ +#define SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_BASE \ + (SCP_ATW0_AP_PERIPHERAL_SRAM_BASE) +#define SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_SIZE (4 * FWK_KIB) + +#endif /* SCP_FW_MMAP_H */ -- GitLab From 4a835605f47da1940b8c263bb4755823a591b579 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 20 Jun 2024 15:22:02 +0530 Subject: [PATCH 09/50] rdv3r1: add SCP power control block register declaration SCP's power control block includes registers for various system configuration and status. Add the register space declaration for this block. Signed-off-by: Nancy . Change-Id: I48aedd8a5e6f2aca7ed8305739657206bb696c47 --- .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 1 + .../rdv3r1/scp_ramfw/include/scp_pwrctrl.h | 105 ++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_pwrctrl.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index d544d2d63..b2017ff31 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -25,6 +25,7 @@ /* SCP sub-system peripherals */ #define SCP_SID_BASE (0x1A4A0000) #define SCP_UART_BASE (0x44002000) +#define SCP_POWER_CONTROL_BASE (0x50000000) /* SCP addresses mapped via ATU into address translation windows */ #define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_pwrctrl.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_pwrctrl.h new file mode 100644 index 000000000..b8d7c0bc1 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_pwrctrl.h @@ -0,0 +1,105 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP Power Control registers + */ + +#ifndef SCP_PWRCTRL_H +#define SCP_PWRCTRL_H + +#include "scp_css_mmap.h" + +#include + +#include + +/*! + * \brief SCP Power Control register definitions + */ + +// clang-format off +struct scp_power_control_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x200 - 0x01C]; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP0; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP1; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP2; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP3; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP4; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP5; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP6; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP7; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP0; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP1; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP2; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP3; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP4; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP5; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP6; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP7; + uint8_t RESERVED2[0x810 - 0x248]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED3[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED4[0x830 - 0x828]; + FWK_RW uint32_t GTSYNCCLK_CTRL; + FWK_RW uint32_t GTSYNCCLK_DIV1; + uint8_t RESERVED5[0x840 - 0x838]; + FWK_RW uint32_t LCPCLK_CTRL; + FWK_RW uint32_t LCPCLK_DIV1; + uint8_t RESERVED6[0xA00 - 0x848]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLEAR; + uint8_t RESERVED7[0xC10 - 0xA0C]; + FWK_W uint32_t SMCF_MGI_TRIGGER; + uint8_t RESERVED8[0xC20 - 0xC14]; + FWK_R uint32_t SRAMECC_ERRFR; + FWK_R uint32_t SRAMECC_ERRFR_H; + FWK_RW uint32_t SRAMECC_ERRCTRL; + FWK_RW uint32_t SRAMECC_ERRCTRL_H; + FWK_RW uint32_t SRAMECC_ERRSTATUS; + FWK_RW uint32_t SRAMECC_ERRSTATUS_H; + FWK_RW uint32_t SRAMECC_ERRADDR; + FWK_RW uint32_t SRAMECC_ERRADDR_H; + uint8_t RESERVED9[0xC48 - 0xC40]; + FWK_RW uint32_t SRAMECC_ERRMISC1; + FWK_RW uint32_t SRAMECC_ERRMISC1_H; + uint8_t RESERVED10[0xC60 - 0xC50]; + FWK_R uint32_t SYSNCI_PMU_CONS_INT_STATUS; + FWK_R uint32_t SYSNCI_CONS_INT_STATUS; + FWK_R uint32_t INTNCI_PMU_CONS_INT_STATUS; + FWK_R uint32_t INTNCI_CONS_INT_STATUS; + FWK_R uint32_t PERIPHNCI_PMU_CONS_INT_STATUS; + FWK_R uint32_t PERIPHNCI_CONS_INT_STATUS; + uint8_t RESERVED11[0xFC0 - 0xC7A]; + FWK_R uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED12[0xFD0 - 0xFC4]; + FWK_R uint32_t PERIPHERAL_ID4; + FWK_R uint32_t PERIPHERAL_ID5; + FWK_R uint32_t PERIPHERAL_ID6; + FWK_R uint32_t PERIPHERAL_ID7; + FWK_R uint32_t PERIPHERAL_ID0; + FWK_R uint32_t PERIPHERAL_ID1; + FWK_R uint32_t PERIPHERAL_ID2; + FWK_R uint32_t PERIPHERAL_ID3; + FWK_R uint32_t COMPONENT_ID0; + FWK_R uint32_t COMPONENT_ID1; + FWK_R uint32_t COMPONENT_ID2; + FWK_R uint32_t COMPONENT_ID3; +}; +// clang-format on + +/* Pointer to SCP Power Control register block */ +#define SCP_PWRCTRL_PTR ((struct scp_power_control_reg *)SCP_POWER_CONTROL_BASE) + +#endif /* SCP_PWRCTRL_H */ -- GitLab From f2b7cd9e47b5ed22450cca0f4d6cfadabe2be8c2 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Mon, 24 Jun 2024 11:37:34 +0530 Subject: [PATCH 10/50] rdv3r1: add core manager register block declaration Core Manager block includes registers for configuration and clock control for application cores and the associated clusters. Add the register space declaration and the base address macro for the core manager block. Signed-off-by: Nancy . Change-Id: Ia912e4a58fc200f7d36230284af92cf1ac5d2ad0 --- .../rdv3r1/scp_ramfw/include/core_manager.h | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/core_manager.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/core_manager.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/core_manager.h new file mode 100644 index 000000000..0fd11f81b --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/core_manager.h @@ -0,0 +1,81 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Core Manager and clock control registers + */ + +#ifndef CORE_MANAGER_H +#define CORE_MANAGER_H + +#include "scp_cu_ap_periph.h" + +#include + +#include + +// clang-format off +struct core_manager_reg { + uint8_t RESERVED0[0x10 - 0x00]; + FWK_RW uint32_t PE_STATIC_CONFIG; + uint8_t RESERVED1[0x18 - 0x14]; + FWK_RW uint32_t PE_RVBARADDR_LW; + FWK_RW uint32_t PE_RVBARADDR_UP; + uint8_t RESERVED2[0x030-0x020]; + FWK_R uint32_t PE_STATUS; + uint8_t RESERVED3[0x800-0x034]; + FWK_RW uint32_t CLUS_MGRCLK_CTRL; + FWK_RW uint32_t CLUS_MGRCLK_DIV1; + uint8_t RESERVED4[0x820 - 0x808]; + FWK_RW uint32_t CLUS_EXP1CLK_CTRL; + FWK_RW uint32_t CLUS_EXP1CLK_DIV; + uint8_t RESERVED5[0x830 - 0x828]; + FWK_RW uint32_t CLUS_EXP2CLK_CTRL; + FWK_RW uint32_t CLUS_EXP2CLK_DIV; + uint8_t RESERVED6[0x840 - 0x838]; + FWK_RW uint32_t CLUS_GICCLK_CTRL; + FWK_RW uint32_t CLUS_GICCLK_DIV1; + uint8_t RESERVED7[0x850 -0x848]; + FWK_RW uint32_t CLUS_PERIPHCLK_CTRL; + FWK_RW uint32_t CLUS_PERIPHCLK_DIV1; + uint8_t RESERVED8[0x860 - 0x858]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + FWK_RW uint32_t CORECLK_MOD1; + uint8_t RESERVED9[0xA00 - 0x086C]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED10[0x0FB4 - 0x0A0C]; + FWK_R uint32_t CAP3; + FWK_R uint32_t CAP2; + FWK_R uint32_t CAP1; + FWK_R uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; +// clang-format on + +#define SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(IDX) \ + ((struct core_manager_reg *)SCP_CU_AP_PERIPH_CORE_MANAGER_BASE_N(IDX)) + +/* AP Peripheral PE_STATIC_CONFIG definitions */ +#define CORE_MANAGER_PE_STATIC_CONFIG_L0GPTSZ_SHIFT (9) +#define CORE_MANAGER_PE_STATIC_CONFIG_L0GPTSZ_MASK (0xF) +#define CORE_MANAGER_PE_STATIC_CONFIG_L0GPTSZ_16GB (4) + +#endif /* CORE_MANAGER_H */ -- GitLab From c36b516f97bfbc91a823b4203cea2e6c6acad8f6 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Mon, 24 Jun 2024 11:40:05 +0530 Subject: [PATCH 11/50] rdv3r1: add System PIK register space declaration System Power Integration Kit (PIK) control register block includes registers for clock control of clocks in SYSTOP power domain. Add the register space declaration for System PIK. Signed-off-by: Nancy . Change-Id: I911fca1bbc405a88680a5a680e7b6eac409b2477 --- .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 1 + .../rdv3r1/scp_ramfw/include/system_pik.h | 89 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/system_pik.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index b2017ff31..4a92b12c4 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -26,6 +26,7 @@ #define SCP_SID_BASE (0x1A4A0000) #define SCP_UART_BASE (0x44002000) #define SCP_POWER_CONTROL_BASE (0x50000000) +#define SCP_SYSTEM_PIK_BASE (0x50040000) /* SCP addresses mapped via ATU into address translation windows */ #define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/system_pik.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/system_pik.h new file mode 100644 index 000000000..db6116e62 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/system_pik.h @@ -0,0 +1,89 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP System PIK registers + */ + +#ifndef SYSTEM_PIK_H +#define SYSTEM_PIK_H + +#include "scp_css_mmap.h" + +#include + +#include + +/*! + * \brief System PIK register definitions + */ + +// clang-format off +struct system_pik_reg { + uint8_t RESERVED0[0x820 - 0x0]; + FWK_RW uint32_t INTCLK_CTRL; + FWK_RW uint32_t INTCLK_DIV1; + uint8_t RESERVED1[0x850 - 0x828]; + FWK_RW uint32_t GICCLK_CTRL; + FWK_RW uint32_t GICCLK_DIV1; + uint8_t RESERVED2[0x860 - 0x858]; + FWK_RW uint32_t SCPPIKCLK_CTRL; + FWK_RW uint32_t SCPPIKCLK_DIV1; + uint8_t RESERVED3[0x870 - 0x868]; + FWK_RW uint32_t SYSPERCLK_CTRL; + FWK_RW uint32_t SYSPERCLK_DIV1; + uint8_t RESERVED4[0x8A0 - 0x878]; + FWK_RW uint32_t APUARTCLK_CTRL; + FWK_RW uint32_t APUARTCLK_DIV1; + uint8_t RESERVED5[0x8B0 - 0x8A8]; + FWK_RW uint32_t IONCICLK_CTRL; + FWK_RW uint32_t IONCICLK_DIV1; + uint8_t RESERVED6[0x900 - 0x8B8]; + FWK_RW uint32_t TCUCLK_CTRL; + FWK_RW uint32_t TCUCLK_DIV1; + uint8_t RESERVED7[0x940 - 0x908]; + FWK_RW uint32_t TCU_CLK_ENABLE; + FWK_RW uint32_t NCI_CLK_ENABLE; + uint8_t RESERVED8[0xA00 - 0x948]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB10 - 0xA0C]; + FWK_RW uint32_t IOMACRO_OVERRIDE; + FWK_RW uint32_t RSSPSI_STATUS; + FWK_RW uint32_t RSSSAM_STATUS0; + FWK_RW uint32_t RSSSAM_STATUS1; + FWK_RW uint32_t RSSLCM_STATUS; + uint8_t RESERVED10[0xFC0 - 0xB24]; + FWK_R uint32_t PIK_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; +// clang-format on + +#define SYSTEM_PIK_PTR ((struct system_pik_reg *)SCP_SYSTEM_PIK_BASE) + +/* + * Bit field definitions for System PIK registers. + */ + +/* IOMACRO_OVERRIDE */ +#define IOMACRO_OVERRIDE_TCU_L0GPTSZ_SHIFT (2) +#define IOMACRO_OVERRIDE_TCU_L0GPTSZ_MASK (0xF) +#define IOMACRO_OVERRIDE_TCU_L0GPTSZ_16GB (0x4) + +#endif /* SYSTEM_PIK_H */ -- GitLab From 09703f498e073a771f5b3090b42d9859785f495b Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Mon, 24 Jun 2024 11:45:57 +0530 Subject: [PATCH 12/50] rdv3r1: add config data for PIK clock driver in scpfw The configuration data for PIK clock devices includes register address of its control and dividers, the rate table and the initial rate. The clock controller devices for all the CPUs, interconnect, systop, gic, scp, uart and other clocks are included in the configuration data. Signed-off-by: Nancy . Change-Id: I73e03e59013ac2b67a986dcc1d584412c180080c --- .../neoverse-rd/rdv3r1/include/css_common.h | 25 +++ .../rdv3r1/scp_ramfw/config_pik_clock.c | 208 ++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_clock.h | 47 ++++ 3 files changed, 280 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/include/css_common.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h diff --git a/product/neoverse-rd/rdv3r1/include/css_common.h b/product/neoverse-rd/rdv3r1/include/css_common.h new file mode 100644 index 000000000..67e77b8c9 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/include/css_common.h @@ -0,0 +1,25 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Common CSS definitions shared across SCP, MCP and LCP. + */ + +#ifndef CSS_COMMON_H +#define CSS_COMMON_H + +#include + +/* REFCLK input clock speed */ +#define CLOCK_RATE_REFCLK (125UL * FWK_MHZ) + +/* + * System Counter per-tick increment value required for 1GHz clock speed as + * required for SBSA compliance. That is, (1GHz / CLOCK_RATE_REFCLK) = 8. + */ +#define SYSCNT_INCR 8 + +#endif /* CSS_COMMON_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c new file mode 100644 index 000000000..5f311e0f1 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c @@ -0,0 +1,208 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'pik_clock'. + */ + +#include "core_manager.h" +#include "scp_clock.h" +#include "scp_pwrctrl.h" +#include "system_pik.h" + +#include + +#include +#include +#include +#include + +#include + +#define CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(n) \ + [CFGD_MOD_PIK_CLOCK_EIDX_CPU##n] = { \ + .name = "PIK CLK CPU" #n, \ + .data = &((struct mod_pik_clock_dev_config){ \ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, \ + .is_group_member = false, \ + .control_reg = \ + &SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(n)->CORECLK_CTRL, \ + .divext_reg = \ + &SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(n)->CORECLK_DIV1, \ + .rate_table = rate_table_cpu_clk, \ + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_clk), \ + .initial_rate = 0, \ + }), \ + } + +/* CPU clock rate table */ +static const struct mod_pik_clock_rate rate_table_cpu_clk[] = { + { + .rate = 0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +/* Cache Coherent Interconnect clock rate table */ +static const struct mod_pik_clock_rate rate_table_int_clk[] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_INTCLK_SOURCE_INTPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +/* SCP CORE clock rate table */ +static const struct mod_pik_clock_rate rate_table_scp_clk[] = { + { + .rate = 800 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (800 * FWK_MHZ), + }, +}; + +/* GIC clock rate table */ +static const struct mod_pik_clock_rate rate_table_gic_clk[] = { + { + .rate = 1000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (1000 * FWK_MHZ), + }, +}; + +/* SCP PIK clock rate table */ +static const struct mod_pik_clock_rate rate_table_scp_pik_clk[] = { + { + .rate = 400 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (400 * FWK_MHZ), + }, +}; + +/* System Peripheral clock rate table */ +static const struct mod_pik_clock_rate rate_table_sysper_clk[] = { + { + .rate = 500 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (500 * FWK_MHZ), + }, +}; + +/* UART clock rate table */ +static const struct mod_pik_clock_rate rate_table_uart_clk[] = { + { + .rate = 250 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ), + }, +}; + +static const struct fwk_element pik_clock_table[] = { + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(0), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(1), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(2), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(3), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(4), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(5), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(6), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(7), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(8), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(9), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(10), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(11), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(12), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(13), + [CFGD_MOD_PIK_CLOCK_EIDX_CMN] = { + .name = "PIK CLK CMN", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->INTCLK_CTRL, + .divext_reg = &SYSTEM_PIK_PTR->INTCLK_DIV1, + .rate_table = rate_table_int_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_int_clk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_SCP] = { + .name = "PIK CLK SCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCP_PWRCTRL_PTR->CORECLK_CTRL, + .divsys_reg = &SCP_PWRCTRL_PTR->CORECLK_DIV1, + .rate_table = rate_table_scp_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp_clk), + .initial_rate = 800 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_GIC] = { + .name = "PIK CLK GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, + .rate_table = rate_table_gic_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_gic_clk), + .initial_rate = 1000 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_SCP_PIK] = { + .name = "PIK CLK SCP PIK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->SCPPIKCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->SCPPIKCLK_DIV1, + .rate_table = rate_table_scp_pik_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp_pik_clk), + .initial_rate = 400 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_SYSPERCLK] = { + .name = "PIK CLK SYSPER", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, + .rate_table = rate_table_sysper_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sysper_clk), + .initial_rate = 500 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_UARTCLK] = { + .name = "PIK CLK UART", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->APUARTCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->APUARTCLK_DIV1, + .rate_table = rate_table_uart_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_uart_clk), + .initial_rate = 250 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) +{ + return pik_clock_table; +} + +const struct fwk_module_config config_pik_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h new file mode 100644 index 000000000..f5b0f82cc --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h @@ -0,0 +1,47 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP clock definitions. + */ + +#ifndef SCP_CLOCK_H +#define SCP_CLOCK_H + +#include "css_common.h" + +#include + +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) + +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CFGD_MOD_PIK_CLOCK_EIDX_CPU0, + CFGD_MOD_PIK_CLOCK_EIDX_CPU1, + CFGD_MOD_PIK_CLOCK_EIDX_CPU2, + CFGD_MOD_PIK_CLOCK_EIDX_CPU3, + CFGD_MOD_PIK_CLOCK_EIDX_CPU4, + CFGD_MOD_PIK_CLOCK_EIDX_CPU5, + CFGD_MOD_PIK_CLOCK_EIDX_CPU6, + CFGD_MOD_PIK_CLOCK_EIDX_CPU7, + CFGD_MOD_PIK_CLOCK_EIDX_CPU8, + CFGD_MOD_PIK_CLOCK_EIDX_CPU9, + CFGD_MOD_PIK_CLOCK_EIDX_CPU10, + CFGD_MOD_PIK_CLOCK_EIDX_CPU11, + CFGD_MOD_PIK_CLOCK_EIDX_CPU12, + CFGD_MOD_PIK_CLOCK_EIDX_CPU13, + CFGD_MOD_PIK_CLOCK_EIDX_CMN, + CFGD_MOD_PIK_CLOCK_EIDX_SCP, + CFGD_MOD_PIK_CLOCK_EIDX_GIC, + CFGD_MOD_PIK_CLOCK_EIDX_SCP_PIK, + CFGD_MOD_PIK_CLOCK_EIDX_SYSPERCLK, + CFGD_MOD_PIK_CLOCK_EIDX_UARTCLK, + CFGD_MOD_PIK_CLOCK_EIDX_COUNT +}; + +#endif /* SCP_CLOCK_H */ -- GitLab From 92c10c3691f0fa170ae676dce5e053e94526e03a Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Fri, 29 Nov 2024 11:53:06 +0000 Subject: [PATCH 13/50] product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c Signed-off-by: Nancy . Change-Id: I59e600aa4ebb8a5a292f4eb283a8f61380682443 --- product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c index 5f311e0f1..718a8d09d 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_pik_clock.c @@ -30,8 +30,7 @@ .is_group_member = false, \ .control_reg = \ &SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(n)->CORECLK_CTRL, \ - .divext_reg = \ - &SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(n)->CORECLK_DIV1, \ + .divext_reg = &SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(n)->CORECLK_DIV1, \ .rate_table = rate_table_cpu_clk, \ .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_clk), \ .initial_rate = 0, \ -- GitLab From 9f8e4d3f601c256763a3d2cfcc15fd81f0c7c359 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 20 Nov 2024 22:52:04 +0530 Subject: [PATCH 14/50] rdv3r1: add config data for power domain module in scpfw Provide the configuration data of all the available power domains to the power domain HAL. The configuration data includes details of all the supported CPU, cluster and the SYSTOP power domain. Signed-off-by: Nancy . Change-Id: I16176c5b88bdde520bf97088c056577c162fa4dd --- .../rdv3r1/scp_ramfw/config_power_domain.c | 98 +++++++++++++++++++ .../scp_ramfw/include/scp_cfgd_power_domain.h | 29 ++++++ 2 files changed, 127 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_power_domain.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_power_domain.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_power_domain.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_power_domain.c new file mode 100644 index 000000000..31ddbc957 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_power_domain.c @@ -0,0 +1,98 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'power_domain'. + */ + +#include "platform_core.h" +#include "scp_cfgd_power_domain.h" + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Mask for the cluster valid power states */ +#define CLUSTER_VALID_STATE_MASK (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) + +/* Mask for the core valid power states */ +#define CORE_VALID_STATE_MASK (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) + +/* Mask of the allowed states for the systop power domain */ +static const uint32_t systop_allowed_state_mask_table[] = { + [0] = MOD_PD_STATE_ON_MASK +}; + +/* + * Mask of the allowed states for the cluster power domain depending on the + * system states. + */ +static const uint32_t cluster_pd_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = CLUSTER_VALID_STATE_MASK, +}; + +/* Mask of the allowed states for a core depending on the cluster states. */ +static const uint32_t core_pd_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MOD_PD_STATE_ON] = CORE_VALID_STATE_MASK, +}; + +/* Power module specific configuration data (none) */ +static const struct mod_power_domain_config platform_power_domain_config = { + 0 +}; + +static struct fwk_element pd_static_element_table[] = { + [PD_STATIC_DEV_IDX_SYSTOP] = { + .name = "SYSTOP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .parent_idx = PD_STATIC_DEV_IDX_NONE, + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) + }), + }, +}; + +static const struct fwk_element *platform_power_domain_get_element_table( + fwk_id_t module_id) +{ + return create_power_domain_element_table( + platform_get_core_count(), + platform_get_cluster_count(), + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER, + core_pd_allowed_state_mask_table, + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table), + cluster_pd_allowed_state_mask_table, + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table), + pd_static_element_table, + FWK_ARRAY_SIZE(pd_static_element_table)); +} + +const struct fwk_module_config config_power_domain = { + .data = &platform_power_domain_config, + .elements = + FWK_MODULE_DYNAMIC_ELEMENTS(platform_power_domain_get_element_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_power_domain.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_power_domain.h new file mode 100644 index 000000000..4c1a43de1 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_power_domain.h @@ -0,0 +1,29 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for power domain module configuration data in SCP-firmware. + */ + +#ifndef SCP_CFGD_POWER_DOMAIN_H +#define SCP_CFGD_POWER_DOMAIN_H + +#include + +/* + * Power domain indices for the statically defined domains used for: + * - Indexing the domains in the platform_power_domain_static_element_table + * - Indexing the SYSTOP children in the power domain tree + * + * When calculating a power domain element index, use the formula: + * core_count + cluster_count + pd_static_dev_idx + */ +enum pd_static_dev_idx { + PD_STATIC_DEV_IDX_SYSTOP, + PD_STATIC_DEV_IDX_NONE = UINT32_MAX +}; + +#endif /* SCP_CFGD_POWER_DOMAIN_H */ -- GitLab From e68e60615d7cd73fdcc5a1aadb9edd26853fce7e Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 20 Nov 2024 22:55:57 +0530 Subject: [PATCH 15/50] rdv3r1: add config data for ppu v1 module in scpfw Provide the configuration data of all the available ppu instances to the PPU v1 driver. The PPU instances of CPUs, Clusters and the SYSTOP are included in the configuration data. Signed-off-by: Nancy . Change-Id: I70ccad9e71b02718adafb2ccc0fd5c4667afe479 --- .../rdv3r1/scp_ramfw/config_ppu_v1.c | 149 ++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 1 + 2 files changed, 150 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_ppu_v1.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_ppu_v1.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_ppu_v1.c new file mode 100644 index 000000000..f98101c45 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_ppu_v1.c @@ -0,0 +1,149 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'ppu_v1'. + */ + +#include "platform_core.h" +#include "scp_cfgd_power_domain.h" +#include "scp_css_mmap.h" +#include "scp_cu_ap_periph.h" + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Maximum PPU core name size including the null terminator */ +#define PPU_CORE_NAME_SIZE 20 + +/* Maximum PPU cluster name size including the null terminator */ +#define PPU_CLUS_NAME_SIZE 7 + +/* Module configuration data */ +static struct mod_ppu_v1_config ppu_v1_config_data = { + .pd_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), +}; + +/* List of static PPU elements */ +static struct fwk_element ppu_element_table[] = { + { + .name = "SYS0", + .data = &((struct mod_ppu_v1_pd_config){ + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS0_BASE, + .default_power_on = true, + .observer_id = FWK_ID_NONE_INIT, + }), + }, +}; + +static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) +{ + struct fwk_element *element_table, *element; + struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; + unsigned int core_idx; + unsigned int cluster_idx; + unsigned int core_count; + unsigned int cluster_count; + unsigned int core_element_count = 0; + + core_count = platform_get_core_count(); + cluster_count = platform_get_cluster_count(); + + /* + * Allocate element descriptors based on: + * Number of cores + * + Number of cluster descriptors + * + Number of system power domain descriptors + * + 1 terminator descriptor + */ + element_table = fwk_mm_calloc( + core_count + cluster_count + FWK_ARRAY_SIZE(ppu_element_table) + 1, + sizeof(struct fwk_element)); + + pd_config_table = fwk_mm_calloc( + core_count + cluster_count, sizeof(struct mod_ppu_v1_pd_config)); + + for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { + for (core_idx = 0; + core_idx < platform_get_core_per_cluster_count(cluster_idx); + core_idx++) { + element = &element_table[core_element_count]; + pd_config = &pd_config_table[core_element_count]; + + element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); + + snprintf( + (char *)element->name, + PPU_CORE_NAME_SIZE, + "CLUS%uCORE%u", + cluster_idx, + core_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CORE; + pd_config->ppu.reg_base = + SCP_CU_AP_PERIPH_CORE_PPU_BASE(cluster_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->cluster_id = FWK_ID_ELEMENT( + FWK_MODULE_IDX_PPU_V1, (core_count + cluster_idx)); + pd_config->observer_id = FWK_ID_NONE; + core_element_count++; + } + + element = &element_table[core_count + cluster_idx]; + pd_config = &pd_config_table[core_count + cluster_idx]; + + element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); + + snprintf( + (char *)element->name, PPU_CLUS_NAME_SIZE, "CLUS%u", cluster_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CLUSTER; + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->observer_id = FWK_ID_NONE; + pd_config->observer_api = FWK_ID_NONE; + pd_config->ppu.reg_base = + SCP_CU_AP_PERIPH_CLUSTER_PPU_BASE(cluster_idx); + } + + fwk_str_memcpy( + &element_table[core_count + cluster_count], + ppu_element_table, + sizeof(ppu_element_table)); + + /* + * Configure pd_source_id with the SYSTOP identifier from the power domain + * module which is dynamically defined based on the number of cores. + */ + ppu_v1_config_data.pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + core_count + cluster_count + PD_STATIC_DEV_IDX_SYSTOP); + + return element_table; +} + +const struct fwk_module_config config_ppu_v1 = { + .data = &ppu_v1_config_data, + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(ppu_v1_get_element_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index 4a92b12c4..96f2bff04 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -27,6 +27,7 @@ #define SCP_UART_BASE (0x44002000) #define SCP_POWER_CONTROL_BASE (0x50000000) #define SCP_SYSTEM_PIK_BASE (0x50040000) +#define SCP_PPU_SYS0_BASE (0x50041000) /* SCP addresses mapped via ATU into address translation windows */ #define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) -- GitLab From 2845d23889e0012ac99f56e86b93de4d6dbc3c7a Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 6 Nov 2024 06:33:35 +0000 Subject: [PATCH 16/50] rdv3r1: add config data for clock HAL module in scpfw Provide the configuration data for clock HAL which includes the clock driver id, api id and the power domain source for the CPUs and the coherent interconnect clock. Signed-off-by: Nancy . Change-Id: I48349d17ad098c11c25f7c21d8af279c4f7c69a4 --- .../rdv3r1/scp_ramfw/config_clock.c | 97 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_clock.h | 22 +++++ 2 files changed, 119 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_clock.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_clock.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_clock.c new file mode 100644 index 000000000..abe698e9e --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_clock.c @@ -0,0 +1,97 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'clock'. + */ + +#include "platform_core.h" +#include "scp_cfgd_power_domain.h" +#include "scp_clock.h" + +#include +#include +#include + +#include +#include +#include +#include + +/* + * Helper macro to instantiate 'clock' module element config data. + */ +#define CFGD_MOD_CLOCK_ELEMENT_CPU(n) \ + [CFGD_MOD_CLOCK_EIDX_CPU##n] = { \ + .name = "CPU" #n, \ + .data = &((struct mod_clock_dev_config){ \ + .driver_id = FWK_ID_ELEMENT_INIT( \ + FWK_MODULE_IDX_PIK_CLOCK, CFGD_MOD_PIK_CLOCK_EIDX_CPU##n), \ + .api_id = FWK_ID_API_INIT( \ + FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CLOCK), \ + .default_on = true, \ + }), \ + } + +/* + * Module 'clock' element configuration data. + */ +static const struct fwk_element clock_dev_table[] = { + CFGD_MOD_CLOCK_ELEMENT_CPU(0), + CFGD_MOD_CLOCK_ELEMENT_CPU(1), + CFGD_MOD_CLOCK_ELEMENT_CPU(2), + CFGD_MOD_CLOCK_ELEMENT_CPU(3), + CFGD_MOD_CLOCK_ELEMENT_CPU(4), + CFGD_MOD_CLOCK_ELEMENT_CPU(5), + CFGD_MOD_CLOCK_ELEMENT_CPU(6), + CFGD_MOD_CLOCK_ELEMENT_CPU(7), + CFGD_MOD_CLOCK_ELEMENT_CPU(8), + CFGD_MOD_CLOCK_ELEMENT_CPU(9), + CFGD_MOD_CLOCK_ELEMENT_CPU(10), + CFGD_MOD_CLOCK_ELEMENT_CPU(11), + CFGD_MOD_CLOCK_ELEMENT_CPU(12), + CFGD_MOD_CLOCK_ELEMENT_CPU(13), + [CFGD_MOD_CLOCK_EIDX_CMN] = { + .name = "CMN-Cyprus", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, + CFGD_MOD_PIK_CLOCK_EIDX_CMN), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CLOCK), + }), + }, + { 0 }, +}; + +static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id) +{ + struct mod_clock_dev_config *dev_config; + unsigned int i; + + for (i = 0; i < CFGD_MOD_CLOCK_EIDX_COUNT; i++) { + dev_config = (struct mod_clock_dev_config *)clock_dev_table[i].data; + dev_config->pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + platform_get_core_count() + platform_get_cluster_count() + + PD_STATIC_DEV_IDX_SYSTOP); + } + + return clock_dev_table; +} + +const struct fwk_module_config config_clock = { + .data = + &(struct mod_clock_config){ + .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), + .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION), + }, + + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(clock_get_dev_desc_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h index f5b0f82cc..8fc76a081 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_clock.h @@ -44,4 +44,26 @@ enum clock_pik_idx { CFGD_MOD_PIK_CLOCK_EIDX_COUNT }; +/* + * Module 'clock' element indexes + */ +enum cfgd_mod_clock_element_idx { + CFGD_MOD_CLOCK_EIDX_CPU0, + CFGD_MOD_CLOCK_EIDX_CPU1, + CFGD_MOD_CLOCK_EIDX_CPU2, + CFGD_MOD_CLOCK_EIDX_CPU3, + CFGD_MOD_CLOCK_EIDX_CPU4, + CFGD_MOD_CLOCK_EIDX_CPU5, + CFGD_MOD_CLOCK_EIDX_CPU6, + CFGD_MOD_CLOCK_EIDX_CPU7, + CFGD_MOD_CLOCK_EIDX_CPU8, + CFGD_MOD_CLOCK_EIDX_CPU9, + CFGD_MOD_CLOCK_EIDX_CPU10, + CFGD_MOD_CLOCK_EIDX_CPU11, + CFGD_MOD_CLOCK_EIDX_CPU12, + CFGD_MOD_CLOCK_EIDX_CPU13, + CFGD_MOD_CLOCK_EIDX_CMN, + CFGD_MOD_CLOCK_EIDX_COUNT +}; + #endif /* SCP_CLOCK_H */ -- GitLab From ac3b2fa255aa017a9c9c4711b350cb27042505df Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 25 Jun 2024 14:44:07 +0530 Subject: [PATCH 17/50] rdv3r1: add config data for cmn cyprus driver in scpfw CMN-Cyprus is the interconnect used in RD-V3-R1 platform. Add config data such as base address, memory region map, SNF table and mesh size. Signed-off-by: Nancy . Change-Id: Ib132ead31d0b8ccb8bbd1075b01b0016878eae74 --- .../rdv3r1/scp_ramfw/config_cmn_cyprus.c | 635 ++++++++++++++++++ .../rdv3r1/scp_ramfw/include/cmn_node_id.h | 54 ++ 2 files changed, 689 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_cmn_cyprus.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/cmn_node_id.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_cmn_cyprus.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_cmn_cyprus.c new file mode 100644 index 000000000..07fba3cf0 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_cmn_cyprus.c @@ -0,0 +1,635 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'cmn_cyprus'. + */ + +#include "cmn_node_id.h" +#include "platform_core.h" +#include "scp_atw1_mmap.h" + +#include + +#include +#include +#include +#include + +#include +#include +#include + +// clang-format off + +/* Coordinates of the bottom-left node in the mesh */ +#define MESH_START_POS \ + { \ + .pos_x = 0, \ + .pos_y = 0, \ + .port_num = 0, \ + .device_num = 0 \ + } + +/* Coordinates of the top-right node in the mesh */ +#define MESH_END_POS \ + { \ + .pos_x = (MESH_SIZE_X - 1), \ + .pos_y = (MESH_SIZE_Y - 1), \ + .port_num = 1, \ + .device_num = 1 \ + } + +// clang-format on + +/* + * List of nodes to be isolated in the mesh. + */ +struct isolated_hns_node_info isolated_hns_nodes[]= { + { + /* HN-S 64 NODE ID: 680 */ + .hns_pos = { + .pos_x = 5, + .pos_y = 5, + .port_num = 0, + .device_num = 0, + }, + .hns_base = (uintptr_t)0xb5700000, + .hns_mpam_s_base = (uintptr_t)0xb5500000, + .hns_mpam_ns_base = (uintptr_t)0xb5600000, + }, + { + /* HN-S 65 MPAM_NS NODE ID: 681 */ + .hns_pos = { + .pos_x = 5, + .pos_y = 5, + .port_num = 0, + .device_num = 1, + }, + .hns_base = (uintptr_t)0xb5740000, + .hns_mpam_s_base = (uintptr_t)0xb5540000, + .hns_mpam_ns_base = (uintptr_t)0xb5640000, + }, + { + /* HN-S 66 NODE ID: 808 */ + .hns_pos = { + .pos_x = 6, + .pos_y = 5, + .port_num = 0, + .device_num = 0, + }, + .hns_base = (uintptr_t)0xb9700000, + .hns_mpam_s_base = (uintptr_t)0xb9500000, + .hns_mpam_ns_base = (uintptr_t)0xb9600000, + }, + { + /* HN-S 67 MPAM_NS NODE ID: 809 */ + .hns_pos = { + .pos_x = 6, + .pos_y = 5, + .port_num = 0, + .device_num = 1, + }, + .hns_base = (uintptr_t)0xb9740000, + .hns_mpam_s_base = (uintptr_t)0xb9540000, + .hns_mpam_ns_base = (uintptr_t)0xb9640000, + }, { + /* HN-S 68 NODE ID: 936 */ + .hns_pos = { + .pos_x = 7, + .pos_y = 5, + .port_num = 0, + .device_num = 0, + }, + .hns_base = (uintptr_t)0xbd700000, + .hns_mpam_s_base = (uintptr_t)0xbd500000, + .hns_mpam_ns_base = (uintptr_t)0xbd600000, + }, + { + /* HN-S 69 MPAM_NS NODE ID: 937 */ + .hns_pos = { + .pos_x = 7, + .pos_y = 5, + .port_num = 0, + .device_num = 1, + }, + .hns_base = (uintptr_t)0xbd740000, + .hns_mpam_s_base = (uintptr_t)0xbd540000, + .hns_mpam_ns_base = (uintptr_t)0xbd640000, + }, +}; + +/* + * HN-F to SN-F mapping table. + */ +// clang-format off +static const unsigned int snf_table[] = { + MEM_CNTRL00_ID, + MEM_CNTRL01_ID, + MEM_CNTRL02_ID, + MEM_CNTRL03_ID, + MEM_CNTRL04_ID, + MEM_CNTRL05_ID, + MEM_CNTRL06_ID, + MEM_CNTRL07_ID, + MEM_CNTRL08_ID, + MEM_CNTRL09_ID, + MEM_CNTRL10_ID, + MEM_CNTRL11_ID, +}; +// clang-format on + +/* + * CCG ports in the mesh. + */ +enum rdv3r1_cmn_cyprus_ccg_port { + CCG_PORT_00, + CCG_PORT_01, + CCG_PORT_02, + CCG_PORT_03, + CCG_PORT_04, + CCG_PORT_05, + CCG_PORT_06, + CCG_PORT_07, + CCG_PORT_08, + CCG_PORT_09, + CCG_PORT_10, + CCG_PORT_11, + CCG_PORT_12, + CCG_PORT_13, + CCG_PORT_14, + CCG_PORT_15, + CCG_PORT_16, + CCG_PORT_17, + CCG_PORT_18, + CCG_PORT_19, + CCG_PORT_20, + CCG_PORT_21, + CCG_PORT_22, + CCG_PORT_23, + CCG_PORT_24, + CCG_PORT_25, + CCG_PER_CHIP, +}; + +/* + * Request Node System Address Map (RNSAM) configuration. + */ +static const struct mod_cmn_cyprus_mem_region_map mmap[] = { + { + /* + * System cache backed region + * Map: 0x0000_0000_0000 - 0x03FF_FFFF_FFFF (4 TiB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_SYSCACHE, + .hns_pos_start = MESH_START_POS, + .hns_pos_end = MESH_END_POS, + }, + { + /* + * Shared SRAM + * Map: 0x0000_0000_0000 - 0x0000_07FF_FFFF (128 MB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_SYSCACHE_SUB, + .node_id = NODE_ID_SBSX, + }, + { + /* + * Boot Flash + * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB) + */ + .base = UINT64_C(0x0008000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNT1, + }, + { + /* + * Peripherals + * Map: 0x00_1000_0000 - 0x00_1EFF_FFFF (240 MB) + */ + .base = UINT64_C(0x0010000000), + .size = UINT64_C(240) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Shared RSM SRAM + * Map: 0x00_1F00_0000 - 0x00_1F3F_FFFF (4 MB) + */ + .base = UINT64_C(0x001F000000), + .size = UINT64_C(4) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_SYSCACHE_SUB, + .node_id = NODE_ID_SBSX, + }, + { + /* + * Peripherals + * Map: 0x00_1F40_0000 - 0x00_5FFF_FFFF (1036 MB) + */ + .base = UINT64_C(0x001F400000), + .size = UINT64_C(1036) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * CMN_CYPRUS GPV + * Map: 0x01_0000_0000 - 0x01_3FFF_FFFF (1 GB) + */ + .base = UINT64_C(0x0100000000), + .size = UINT64_C(1) * FWK_GIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Cluster Utility Memory region + * Map: 0x1_4000_0000 - 0x1_5FFF_FFFF (512 MB) + */ + .base = UINT64_C(0x140000000), + .size = UINT64_C(512) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * LCP0 + * Map: 0x1_6000_0000 - 0x1_601F_FFFF (2 MB) + */ + .base = UINT64_C(0x160000000), + .size = UINT64_C(2) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNI0, + }, + { + /* + * LCP1 + * Map: 0x1_6020_0000 - 0x1_603F_FFFF (2 MB) + */ + .base = UINT64_C(0x160200000), + .size = UINT64_C(2) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNI1, + }, + { + /* + * LCP2 + * Map: 0x1_6040_0000 - 0x1_605F_FFFF (2 MB) + */ + .base = UINT64_C(0x160400000), + .size = UINT64_C(2) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNI2, + }, + { + /* + * LCP3 + * Map: 0x1_6060_0000 - 0x1_607F_FFFF (2 MB) + */ + .base = UINT64_C(0x160600000), + .size = UINT64_C(2) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNI3, + }, + { + /* + * LCP4 + * Map: 0x1_6080_0000 - 0x1_609F_FFFF (2 MB) + */ + .base = UINT64_C(0x160800000), + .size = UINT64_C(2) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNI4, + }, + { + /* + * LCP5 + * Map: 0x1_60A0_0000 - 0x1_60BF_FFFF (2 MB) + */ + .base = UINT64_C(0x160A00000), + .size = UINT64_C(2) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNI5, + }, + { + /* + * LCP6 + * Map: 0x1_60C0_0000 - 0x1_60DF_FFFF (2 MB) + */ + .base = UINT64_C(0x160C00000), + .size = UINT64_C(2) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HNI6, + }, + { + /* + * Peripherals - Memory Controller + * Map: 0x1_8000_0000 - 0x1_8FFF_FFFF (256 MB) + */ + .base = UINT64_C(0x180000000), + .size = UINT64_C(256) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals, NCI GPV Memory Map 0 + * Map: 0x01_C000_0000 - 0x01_C7FF_FFFF (128 MB) + */ + .base = UINT64_C(0x01C0000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = IOVB_NODE_ID0, + }, + { + /* + * Peripherals, NCI GPV Memory Map 1 + * Map: 0x01_C800_0000 - 0x01_CFFF_FFFF (128 MB) + */ + .base = UINT64_C(0x01C8000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = IOVB_NODE_ID1, + }, + { + /* + * Peripherals, NCI GPV Memory Map 2 + * Map: 0x01_D000_0000 - 0x01_D7FF_FFFF (128 MB) + */ + .base = UINT64_C(0x01D0000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = IOVB_NODE_ID2, + }, + { + /* + * GPC_SMMU region + * Map: 0x02_4000_0000 - 0x02_47FF_FFFF (128 MB) + */ + .base = UINT64_C(0x240000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Non Secure NOR Flash 0/1 + * Map: 0x06_5000_0000 - 0x06_57FF_FFFF (128 MB) + */ + .base = UINT64_C(0x0650000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Ethernet Controller PL91x + * Map: 0x06_5C00_0000 - 0x06_5FFF_FFFF (64 MB) + */ + .base = UINT64_C(0x065C000000), + .size = UINT64_C(64) * FWK_MIB, + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, +}; + +/* Number of CCG nodes per CML Port Aggregation group (CPAG) */ +#define CCG_PER_CPAG 2 + +/* List of LDIDs of CCG nodes in the CPAG */ +#define CCG_LDID_LIST(...) ((unsigned int[]){ __VA_ARGS__ }) + +/* Home Agent ID */ +#define GET_HAID(chip_id, ccg_port) ((CCG_PER_CHIP * chip_id) + ccg_port) + +/* List of Home Agent IDs of CCG nodes in the CPAG */ +#define CCG_HAID_LIST(chip_id, ccg_port_x, ccg_port_y) \ + ((unsigned int[]){ GET_HAID(chip_id, ccg_port_x), \ + GET_HAID(chip_id, ccg_port_y) }) + +/*! + * \brief Define a Remote hashed region. + * + * \param pri_base Primary HTG region base address. + * \param pri_size Primary HTG region size. + * \param sec_base Secondary HTG region base address. + * \param sec_size Secondary HTG region size. + * \param start_pos HN-S node start position of the HTG. + * \param end_pos HN-S node end position of the HTG. + */ +// clang-format off +#define REMOTE_HASHED_REGION( \ + pri_base, pri_size, sec_base, sec_size, start_pos, end_pos) \ + { \ + .base = (pri_base), \ + .size = (pri_size), \ + .sec_region_base = (sec_base), \ + .sec_region_size = (sec_size), \ + .type = MOD_CMN_CYPRUS_MEM_REGION_TYPE_REMOTE_HASHED, \ + .hns_pos_start = start_pos, \ + .hns_pos_end = end_pos, \ + } +// clang-format on + +/* Peripheral memory size for a chip (64 GiB) */ +#define PERIPH_MEM_SIZE (UINT64_C(1) << 36) +/* Peripheral memory base for a chip */ +#define CHIP_PERIPH_MEM_BASE(chip_id) (chip_id * PERIPH_MEM_SIZE) + +/* Second DRAM block base */ +#define DRAM2_BASE UINT64_C(0x20000000000) +/* Second DRAM block size (1 TiB) */ +#define DRAM2_SIZE (UINT64_C(1) << 40) +/* Second DRAM block base for a chip */ +#define CHIP_DRAM2_BASE(chip_id) (DRAM2_BASE + (DRAM2_SIZE * chip_id)) + +/* + * RD-V3-R1 Multichip configuration data + * + * Cross chip CCG connections between the chips: + * + * +-------------------------------------------------+ + * | CCG20 CCG21 CCG22 CCG23 CCG24 CCG25 | + * | | + * |CCG08 CCG14| + * | | + * |CCG09 CCG15| + * | | + * |CCG10 CCG16| + * | CHIP 0 | + * |CCG11 CCG17| + * | | + * |CCG12 CCG18| + * | | + * |CCG13 CCG19| + * | | + * | CCG00 CCG01 CCG02 CCG03 CCG04 CCG05 CCG06 CCG07 | + * +---+-----+-----+-----+-----+-----+-----+-----+---+ + * | | | | | | | | + * | | | | | | | | + * +---+-----+-----+-----+-----+-----+-----+-----+---+ + * | CCG07 CCG06 CCG05 CCG04 CCG03 CCG02 CCG01 CCG00 | + * | | + * |CCG08 CCG14| + * | | + * |CCG09 CCG15| + * | | + * |CCG10 CCG16| + * | CHIP 1 | + * |CCG11 CCG17| + * | | + * |CCG12 CCG18| + * | | + * |CCG13 CCG19| + * | | + * | CCG20 CCG21 CCG22 CCG23 CCG24 CCG25 | + * +-------------------------------------------------+ + */ + +/* Chip 0 CML configuration */ +static const struct mod_cmn_cyprus_cml_config chip0_cml_config[] = { + { + /* Chip 0 to Chip 1 */ + .ccg_ldid = CCG_LDID_LIST(CCG_PORT_00, CCG_PORT_01), + .haid = CCG_HAID_LIST(PLATFORM_CHIP_0, CCG_PORT_00, CCG_PORT_01), + .remote_mmap_table = { + { + /* + * Chip 1 peripheral address space and DRAM. + * Map: 0x10_0000_0000 - 0x1F_FFFF_FFFF (primary) + * 0x300_0000_0000 - 0x3FF_FFFF_FFFF (secondary) + */ + .region_mmap = REMOTE_HASHED_REGION(CHIP_PERIPH_MEM_BASE(1), + PERIPH_MEM_SIZE, CHIP_DRAM2_BASE(1), + DRAM2_SIZE, MESH_START_POS, MESH_END_POS), + .target_haid = CCG_HAID_LIST(PLATFORM_CHIP_1, CCG_PORT_07, + CCG_PORT_06), + }, + }, + .remote_chip_id = PLATFORM_CHIP_1, + .enable_smp_mode = true, + .enable_direct_connect_mode = true, + .enable_cpa_mode = true, + .cpag_config = { + .cpag_id = 0, + .ccg_count = CCG_PER_CPAG, + }, + }, +}; + +/* Chip 0 CML configuration */ +static const struct mod_cmn_cyprus_cml_config chip1_cml_config[] = { + { + /* Chip 1 to Chip 0 */ + .ccg_ldid = CCG_LDID_LIST(CCG_PORT_07, CCG_PORT_06), + .haid = CCG_HAID_LIST(PLATFORM_CHIP_1, CCG_PORT_07, CCG_PORT_06), + .remote_mmap_table = { + { + /* + * Chip 0 peripheral address space and DRAM. + * Map: 0x0 - 0x0F_FFFF_FFFF (primary) + * 0x200_0000_0000 - 0x2FF_FFFF_FFFF (secondary) + */ + .region_mmap = REMOTE_HASHED_REGION(CHIP_PERIPH_MEM_BASE(0), + PERIPH_MEM_SIZE, CHIP_DRAM2_BASE(0), + DRAM2_SIZE, MESH_START_POS, MESH_END_POS), + .target_haid = CCG_HAID_LIST(PLATFORM_CHIP_0, CCG_PORT_00, + CCG_PORT_01), + }, + }, + .remote_chip_id = PLATFORM_CHIP_0, + .enable_smp_mode = true, + .enable_direct_connect_mode = true, + .enable_cpa_mode = true, + .cpag_config = { + .cpag_id = 0, + .ccg_count = CCG_PER_CPAG, + }, + }, +}; + +static struct mod_cmn_cyprus_config cmn_config_table[] = { + [PLATFORM_CHIP_0] = { + .periphbase = SCP_CMN_BASE, + .mesh_size_x = MESH_SIZE_X, + .mesh_size_y = MESH_SIZE_Y, + .hnf_sam_config = { + .snf_table = snf_table, + .snf_count = FWK_ARRAY_SIZE(snf_table), + .hnf_sam_mode = MOD_CMN_CYPRUS_HNF_SAM_MODE_RANGE_BASED_HASHING, + .hashed_mode_config = { + .sn_mode = MOD_CMN_CYPRUS_HNF_SAM_HASHED_MODE_3_SN, + .top_address_bit0 = 32, + .top_address_bit1 = 33, + }, + }, + .isolated_hns_table = isolated_hns_nodes, + .isolated_hns_count = FWK_ARRAY_SIZE(isolated_hns_nodes), + .rnsam_scg_config = { + .scg_hashing_mode = MOD_CMN_CYPRUS_RNSAM_SCG_HIERARCHICAL_HASHING, + .hier_hash_cfg = { + .num_cluster_groups = 4, + }, + }, + .hns_cal_mode = true, + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .chip_addr_space = UINT64_C(64) * FWK_GIB, + .cml_config_table = chip0_cml_config, + .cml_table_count = + FWK_ARRAY_SIZE(chip0_cml_config), + .cml_poll_timeout_us = UINT32_C(100), + .enable_lcn = true, + }, + [PLATFORM_CHIP_1] = { + .periphbase = SCP_CMN_BASE, + .mesh_size_x = MESH_SIZE_X, + .mesh_size_y = MESH_SIZE_Y, + .hnf_sam_config = { + .snf_table = snf_table, + .snf_count = FWK_ARRAY_SIZE(snf_table), + .hnf_sam_mode = MOD_CMN_CYPRUS_HNF_SAM_MODE_RANGE_BASED_HASHING, + .hashed_mode_config = { + .sn_mode = MOD_CMN_CYPRUS_HNF_SAM_HASHED_MODE_3_SN, + .top_address_bit0 = 32, + .top_address_bit1 = 33, + }, + }, + .isolated_hns_table = isolated_hns_nodes, + .isolated_hns_count = FWK_ARRAY_SIZE(isolated_hns_nodes), + .rnsam_scg_config = { + .scg_hashing_mode = MOD_CMN_CYPRUS_RNSAM_SCG_HIERARCHICAL_HASHING, + .hier_hash_cfg = { + .num_cluster_groups = 4, + }, + }, + .hns_cal_mode = true, + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .chip_addr_space = UINT64_C(64) * FWK_GIB, + .cml_config_table = chip1_cml_config, + .cml_table_count = + FWK_ARRAY_SIZE(chip1_cml_config), + .cml_poll_timeout_us = UINT32_C(100), + .enable_lcn = true, + }, +}; + +struct mod_cmn_cyprus_config_table cmn_config = { + .chip_config_data = cmn_config_table, + .chip_count = PLATFORM_CHIP_COUNT, + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), +}; + +const struct fwk_module_config config_cmn_cyprus = { + .data = (void *)&cmn_config, +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/cmn_node_id.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/cmn_node_id.h new file mode 100644 index 000000000..5ebe835a0 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/cmn_node_id.h @@ -0,0 +1,54 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * CMN node ID. + */ + +#ifndef CMN_NODE_ID +#define CMN_NODE_ID + +#define MEM_CNTRL00_ID 8 +#define MEM_CNTRL01_ID 16 +#define MEM_CNTRL02_ID 24 +#define MEM_CNTRL03_ID 32 +#define MEM_CNTRL04_ID 40 +#define MEM_CNTRL05_ID 48 +#define MEM_CNTRL06_ID 1032 +#define MEM_CNTRL07_ID 1040 +#define MEM_CNTRL08_ID 1048 +#define MEM_CNTRL09_ID 1056 +#define MEM_CNTRL10_ID 1064 +#define MEM_CNTRL11_ID 1072 + +#define NODE_ID_HND 1084 + +#define NODE_ID_HNT1 1024 + +#define NODE_ID_HNP0 176 +#define NODE_ID_HNP1 432 +#define NODE_ID_HNP2 688 + +#define NODE_ID_HNI0 128 +#define NODE_ID_HNI1 256 +#define NODE_ID_HNI2 384 +#define NODE_ID_HNI3 512 +#define NODE_ID_HNI4 640 +#define NODE_ID_HNI5 768 +#define NODE_ID_HNI6 896 +#define NODE_ID_HNI7 948 +#define NODE_ID_HNI8 956 + +#define NODE_ID_SBSX 952 + +#define MESH_SIZE_X 9 +#define MESH_SIZE_Y 8 + +#define IOVB_NODE_ID0 NODE_ID_HNP0 +#define IOVB_NODE_ID1 NODE_ID_HNP1 +#define IOVB_NODE_ID2 NODE_ID_HNP2 + +#endif /* CMN_NODE_ID */ -- GitLab From 19ac524b5d84a29d7926ba0f3e4d802709868ca5 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 25 Jun 2024 14:49:33 +0530 Subject: [PATCH 18/50] rdv3r1: add config data for generic timer in scpfw The configuration data for generic timer driver includes the base addresses of timer register, counter register and control register along with the initial frequency and the id of clock device on which the timer depends. Signed-off-by: Nancy . Change-Id: Id776810f2024754b612012179c25fdb4ae9a908e --- .../rdv3r1/scp_ramfw/config_gtimer.c | 59 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 3 + 2 files changed, 62 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_gtimer.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_gtimer.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_gtimer.c new file mode 100644 index 000000000..9f59b77ad --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_gtimer.c @@ -0,0 +1,59 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'gtimer'. + */ + +#include "scp_clock.h" +#include "scp_css_mmap.h" +#include "syscnt_impdef.h" + +#include + +#include +#include +#include +#include +#include + +/* + * System counter implementation defined register config data. + */ +static struct mod_gtimer_syscounter_impdef_config syscnt_impdef_cfg[] = { + { + .offset = NEOVERSE_RD_SYSCNT_IMPDEF0_CNTENCR, + .value = 0, + }, + { + .offset = NEOVERSE_RD_SYSCNT_IMPDEF0_CNTINCR, + .value = SYSCNT_INCR, + } +}; + +/* Generic timer driver config */ +static const struct fwk_element gtimer_dev_table[] = { + [0] = { .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config){ + .hw_timer = SCP_REFCLK_CNTBASE0_BASE, + .hw_counter = SCP_REFCLK_CNTCTL_BASE, + .control = SCP_REFCLK_CNTCONTROL_BASE, + .frequency = (CLOCK_RATE_REFCLK * SYSCNT_INCR), + .clock_id = FWK_ID_NONE_INIT, + .syscnt_impdef_cfg = syscnt_impdef_cfg, + .syscnt_impdef_cfg_cnt = FWK_ARRAY_SIZE(syscnt_impdef_cfg), + }) }, + [1] = { 0 }, +}; + +const struct fwk_module_config config_gtimer = { + .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(gtimer_dev_table), +}; + +struct fwk_time_driver fmw_time_driver(const void **ctx) +{ + return mod_gtimer_driver(ctx, config_gtimer.elements.table[0].data); +} diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index 96f2bff04..2b1722012 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -23,7 +23,10 @@ #define SCP_DTC_RAM_SIZE (256 * 1024) /* SCP sub-system peripherals */ +#define SCP_REFCLK_CNTCONTROL_BASE (0x1A430000) #define SCP_SID_BASE (0x1A4A0000) +#define SCP_REFCLK_CNTCTL_BASE (0x44000000) +#define SCP_REFCLK_CNTBASE0_BASE (0x44001000) #define SCP_UART_BASE (0x44002000) #define SCP_POWER_CONTROL_BASE (0x50000000) #define SCP_SYSTEM_PIK_BASE (0x50040000) -- GitLab From 177e7d87410a26b81c28731eb69b19fb0fd87df2 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 25 Jun 2024 15:04:21 +0530 Subject: [PATCH 19/50] rdv3r1: add config data for timer HAL in scpfw Provide the configuration data for timer HAL which includes the id for the timer element and the IRQ number. Signed-off-by: Nancy . Change-Id: Ibc3e22e0e340346afc0ae2bfc61b248f79934027 --- .../rdv3r1/scp_ramfw/config_timer.c | 43 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/fmw_cmsis.h | 3 ++ .../rdv3r1/scp_ramfw/include/scp_cfgd_timer.h | 19 ++++++++ 3 files changed, 65 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_timer.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_timer.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_timer.c new file mode 100644 index 000000000..e677ea323 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_timer.c @@ -0,0 +1,43 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'timer'. + */ + +#include "scp_cfgd_timer.h" + +#include + +#include +#include +#include +#include + +#include + +/* Timer HAL config */ +static const struct fwk_element timer_dev_table[] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config) { + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = REFCLK_GTIMER_IRQ, + }), + .sub_element_count = + SCP_CFGD_MOD_TIMER_SEIDX_ALARM_COUNT, /* Number of alarms */ + }, + [1] = { 0 }, +}; + +static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) +{ + return timer_dev_table; +} + +const struct fwk_module_config config_timer = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(timer_get_dev_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h index b97d34c1e..23d2672bd 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h @@ -36,6 +36,9 @@ typedef enum IRQn { PendSV_IRQn = -2, SysTick_IRQn = -1, + /* SCP REFCLK Physical Timer */ + REFCLK_GTIMER_IRQ = 32, + IRQn_MAX = INT16_MAX, } IRQn_Type; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h new file mode 100644 index 000000000..ad6e98b7e --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for timer module configuration data in SCP firmware. + */ + +#ifndef SCP_CFGD_TIMER_H +#define SCP_CFGD_TIMER_H + +/* Sub-element indexes (alarms) for SCP timer device */ +enum scp_cfgd_mod_timer_alarm_idx { + SCP_CFGD_MOD_TIMER_SEIDX_ALARM_COUNT, +}; + +#endif /* SCP_CFGD_TIMER_H */ -- GitLab From f6892e98367e30ef7733771704cd84714c245c31 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 25 Jun 2024 15:12:07 +0530 Subject: [PATCH 20/50] rdv3r1: add config data for mhuv3 driver in scpfw The instances of the MHUv3 doorbell channel are being initially added as configuration data for the MHUv3 module. The configuration data for these channels include the interrupt number and the base addresses of the corresponding Postbox and Mailbox. Signed-off-by: Nancy . Change-Id: I8bca554da48caaece9c735d93996deea1d7badf3 --- .../rdv3r1/scp_ramfw/config_mhu3.c | 69 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/fmw_cmsis.h | 4 ++ .../rdv3r1/scp_ramfw/include/scp_cfgd_mhu3.h | 21 ++++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 4 ++ 4 files changed, 98 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_mhu3.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_mhu3.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_mhu3.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_mhu3.c new file mode 100644 index 000000000..2eaaa7d5c --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_mhu3.c @@ -0,0 +1,69 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'mhu3'. + */ + +#include "scp_cfgd_mhu3.h" +#include "scp_css_mmap.h" + +#include + +#include +#include +#include +#include + +#include + +/* AP<-->SCP Secure MHUv3 channel configuration */ +struct mod_mhu3_channel_config scp2ap_s_ch_config[] = { + /* PBX CH 0, FLAG 0, MBX CH 0, FLAG 0 */ + MOD_MHU3_INIT_DBCH(0, 0, 0, 0), +}; + +/* SCP<-->RSS MHUv3 channel configuration */ +struct mod_mhu3_channel_config scp2rss_ch_config[] = { + /* PBX CH 1, FLAG 0, MBX CH 1, FLAG 0 */ + MOD_MHU3_INIT_DBCH(1, 0, 1, 0), +}; + +/* Module element table */ +static const struct fwk_element mhu_element_table[] = { + [SCP_CFGD_MOD_MHU3_EIDX_SCP_AP_S] = { + .name = "SCP2AP_NS_MHU", + .sub_element_count = FWK_ARRAY_SIZE(scp2ap_s_ch_config), + .data = &(struct mod_mhu3_device_config) { + .irq = (unsigned int) MHU3_AP2SCP_IRQ_S, + .in = SCP_AP2SCP_MHUV3_RCV_S_BASE, + .out = SCP_SCP2AP_MHUV3_SEND_S_BASE, + .channels = &scp2ap_s_ch_config[0], + .timer_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + }, + }, + [SCP_CFGD_MOD_MHU3_EIDX_SCP_RSS] = { + .name = "SCP2RSS_MHU", + .sub_element_count = FWK_ARRAY_SIZE(scp2rss_ch_config), + .data = &(struct mod_mhu3_device_config) { + .irq = (unsigned int) MHU3_RSS2SCP_IRQ, + .in = SCP_RSS2SCP_MHUV3_RCV_BASE, + .out = SCP_SCP2RSS_MHUV3_SEND_BASE, + .channels = &scp2rss_ch_config[0], + .timer_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), + }, + }, + [SCP_CFGD_MOD_MHU3_EIDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return mhu_element_table; +} + +struct fwk_module_config config_mhu3 = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h index 23d2672bd..bf28546d5 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_cmsis.h @@ -38,6 +38,10 @@ typedef enum IRQn { /* SCP REFCLK Physical Timer */ REFCLK_GTIMER_IRQ = 32, + /* MHUv3 secure IRQ between SCP and AP */ + MHU3_AP2SCP_IRQ_S = 83, + /* MHUv3 secure IRQ between SCP and RSS */ + MHU3_RSS2SCP_IRQ = 86, IRQn_MAX = INT16_MAX, } IRQn_Type; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_mhu3.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_mhu3.h new file mode 100644 index 000000000..8d9df0fdf --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_mhu3.h @@ -0,0 +1,21 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for MHUv3 module configuration data in SCP firmware. + */ + +#ifndef SCP_CFGD_MHU3_H +#define SCP_CFGD_MHU3_H + +/* MHUv3 device indices */ +enum scp_cfgd_mod_mhu3_device_idx { + SCP_CFGD_MOD_MHU3_EIDX_SCP_AP_S, + SCP_CFGD_MOD_MHU3_EIDX_SCP_RSS, + SCP_CFGD_MOD_MHU3_EIDX_COUNT +}; + +#endif /* SCP_CFGD_MHU3_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index 2b1722012..308e63cdb 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -28,6 +28,10 @@ #define SCP_REFCLK_CNTCTL_BASE (0x44000000) #define SCP_REFCLK_CNTBASE0_BASE (0x44001000) #define SCP_UART_BASE (0x44002000) +#define SCP_SCP2AP_MHUV3_SEND_S_BASE (0x45020000) +#define SCP_AP2SCP_MHUV3_RCV_S_BASE (0x45030000) +#define SCP_SCP2RSS_MHUV3_SEND_BASE (0x46000000) +#define SCP_RSS2SCP_MHUV3_RCV_BASE (0x46010000) #define SCP_POWER_CONTROL_BASE (0x50000000) #define SCP_SYSTEM_PIK_BASE (0x50040000) #define SCP_PPU_SYS0_BASE (0x50041000) -- GitLab From 4b6d7e3609096b0a641e9ea0fb7c41c44eda2ccc Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 26 Jun 2024 14:12:55 +0530 Subject: [PATCH 21/50] rdv3r1: add config data for apcontext module in scpfw Provide the configuration data for apcontext module which includes the base address and the size of the memory region to be cleared. Signed-off-by: Nancy . Change-Id: Ia02637520ebd715e2aa4e61707eacea612c97aa0 --- .../rdv3r1/scp_ramfw/config_apcontext.c | 26 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_fw_mmap.h | 9 +++++++ 2 files changed, 35 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c new file mode 100644 index 000000000..f82c0c203 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c @@ -0,0 +1,26 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'apcontext'. + */ + +#include "scp_fw_mmap.h" + +#include + +#include +#include + +static const struct mod_apcontext_config apcontext_data = { + .base = SCP_AP_CONTEXT_BASE, + .size = SCP_AP_CONTEXT_SIZE, + .clock_id = FWK_ID_NONE_INIT, +}; + +struct fwk_module_config config_apcontext = { + .data = &apcontext_data, +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h index 5f044a29f..4774c58d6 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h @@ -39,4 +39,13 @@ (SCP_ATW0_AP_PERIPHERAL_SRAM_BASE) #define SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_SIZE (4 * FWK_KIB) +/* + * AP Context Memory Region inside Secure AP Peripheral SRAM that is shared + * between AP and SCP. + */ +#define SCP_AP_CONTEXT_SIZE (64) +#define SCP_AP_CONTEXT_BASE \ + (SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE + \ + SCP_AP_PERIPHERAL_SRAM_TRUSTED_SIZE - SCP_AP_CONTEXT_SIZE) + #endif /* SCP_FW_MMAP_H */ -- GitLab From b619d8fe4f99cb67bdde3b8e526337d9c47b354e Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 26 Jun 2024 14:17:29 +0530 Subject: [PATCH 22/50] rdv3r1: add config data for sds module in scpfw SDS module is used to pass runtime data from SCP firmware to the AP core firmware using shared memory. Provide the base address, size and the payloads to be passed as configuration data for the SDS module. Signed-off-by: Nancy . Change-Id: Ibcebcf8fb8ae91ee18caf0c867a0a62e272b37ac --- .../neoverse-rd/rdv3r1/scp_ramfw/config_sds.c | 117 ++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_cfgd_sds.h | 55 ++++++++ .../rdv3r1/scp_ramfw/include/scp_fw_mmap.h | 7 ++ 3 files changed, 179 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_sds.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c new file mode 100644 index 000000000..3c37368ff --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c @@ -0,0 +1,117 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'sds'. + */ + +#include "scp_cfgd_sds.h" +#include "scp_fw_mmap.h" + +#include + +#include +#include +#include +#include +#include + +#include + +static const uint32_t version_packed = FWK_BUILD_VERSION; +static const uint32_t feature_flags; + +static const struct mod_sds_region_desc sds_regions[] = { + [SCP_CFGD_MOD_SDS_REGION_IDX_SECURE] = { + .base = (void*)SCP_SDS_SECURE_BASE, + .size = SCP_SDS_SECURE_SIZE, + }, +}; + +static_assert( + FWK_ARRAY_SIZE(sds_regions) == SCP_CFGD_MOD_SDS_REGION_IDX_COUNT, + "Mismatch between number of SDS regions and number of regions " + "provided by the SDS configuration."); + +const struct mod_sds_config sds_module_config = { + .regions = sds_regions, + .region_count = SCP_CFGD_MOD_SDS_REGION_IDX_COUNT, + .clock_id = FWK_ID_NONE_INIT, +}; + +static struct fwk_element sds_element_table[] = { + [SCP_CFGD_MOD_SDS_EIDX_CPU_INFO] = { + .name = "CPU Info", + .data = &((struct mod_sds_structure_desc){ + .id = SDS_AP_CPU_INFO_STRUCT_ID, + .size = SCP_CFGD_MOD_SDS_CPU_INFO_SIZE, + .region_id = SCP_CFGD_MOD_SDS_REGION_IDX_SECURE, + .finalize = true, + }), + }, + [SCP_CFGD_MOD_SDS_EIDX_ROM_VERSION] = { + .name = "ROM firmware version", + .data = &((struct mod_sds_structure_desc){ + .id = SDS_ROM_VERSION_STRUCT_ID, + .size = SCP_CFGD_MOD_SDS_ROM_VERSION_SIZE, + .payload = &version_packed, + .region_id = SCP_CFGD_MOD_SDS_REGION_IDX_SECURE, + .finalize = true, + }), + }, + [SCP_CFGD_MOD_SDS_EIDX_RAM_VERSION] = { + .name = "RAM firmware version", + .data = &((struct mod_sds_structure_desc){ + .id = SDS_RAM_VERSION_STRUCT_ID, + .size = SCP_CFGD_MOD_SDS_RAM_VERSION_SIZE, + .payload = &version_packed, + .region_id = SCP_CFGD_MOD_SDS_REGION_IDX_SECURE, + .finalize = true, + }), + }, + [SCP_CFGD_MOD_SDS_EIDX_RESET_SYNDROME] = { + .name = "Reset Syndrome", + .data = &((struct mod_sds_structure_desc){ + .id = SDS_RESET_SYNDROME_STRUCT_ID, + .size = SCP_CFGD_MOD_SDS_RESET_SYNDROME_SIZE, + .region_id = SCP_CFGD_MOD_SDS_REGION_IDX_SECURE, + .finalize = true, + }), + }, + [SCP_CFGD_MOD_SDS_EIDX_FEATURE_AVAILABILITY] = { + .name = "Feature Availability", + .data = &((struct mod_sds_structure_desc){ + .id = SDS_FEATURE_AVAIL_STRUCT_ID, + .size = SCP_CFGD_MOD_SDS_FEATURE_AVAILABILITY_SIZE, + .payload = &feature_flags, + .region_id = SCP_CFGD_MOD_SDS_REGION_IDX_SECURE, + .finalize = true, + }), + }, + [SCP_CFGD_MOD_SDS_EIDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static_assert( + SCP_SDS_SECURE_SIZE > SCP_CFGD_MOD_SDS_CPU_INFO_SIZE + + SCP_CFGD_MOD_SDS_ROM_VERSION_SIZE + + SCP_CFGD_MOD_SDS_RAM_VERSION_SIZE + + SCP_CFGD_MOD_SDS_RESET_SYNDROME_SIZE + + SCP_CFGD_MOD_SDS_FEATURE_AVAILABILITY_SIZE, + "SDS structures too large for SDS SRAM.\n"); + +static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) +{ + static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size"); + + return sds_element_table; +} + +struct fwk_module_config config_sds = { + .data = &sds_module_config, + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(sds_get_element_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_sds.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_sds.h new file mode 100644 index 000000000..ef0baa20e --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_sds.h @@ -0,0 +1,55 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for SDS module configuration data in SCP firmware. + */ + +#ifndef SCP_CFGD_SDS_H +#define SCP_CFGD_SDS_H + +#include + +#include + +#define SDS_STRUCT_ID(idx) (idx | 1 << MOD_SDS_ID_VERSION_MAJOR_POS) + +/* SDS structure identifiers. */ +enum scp_cfgd_mod_sds_struct_id { + SDS_AP_CPU_INFO_STRUCT_ID = SDS_STRUCT_ID(1), + SDS_ROM_VERSION_STRUCT_ID = SDS_STRUCT_ID(2), + SDS_RAM_VERSION_STRUCT_ID = SDS_STRUCT_ID(3), + SDS_RESET_SYNDROME_STRUCT_ID = SDS_STRUCT_ID(5), + SDS_FEATURE_AVAIL_STRUCT_ID = SDS_STRUCT_ID(6), +}; + +/* Memory region identifiers that hold the SDS structures. */ +enum scp_cfgd_mod_sds_region_idx { + SCP_CFGD_MOD_SDS_REGION_IDX_SECURE, + SCP_CFGD_MOD_SDS_REGION_IDX_COUNT, +}; + +/* Module 'sds' element indexes (SDS region descriptors) */ +enum scp_cfgd_mod_sds_element_idx { + SCP_CFGD_MOD_SDS_EIDX_CPU_INFO, + SCP_CFGD_MOD_SDS_EIDX_ROM_VERSION, + SCP_CFGD_MOD_SDS_EIDX_RAM_VERSION, + SCP_CFGD_MOD_SDS_EIDX_RESET_SYNDROME, + SCP_CFGD_MOD_SDS_EIDX_FEATURE_AVAILABILITY, + SCP_CFGD_MOD_SDS_EIDX_COUNT +}; + +/* SDS region descriptor structure sizes. */ +#define SCP_CFGD_MOD_SDS_CPU_INFO_SIZE 4 +#define SCP_CFGD_MOD_SDS_ROM_VERSION_SIZE 4 +#define SCP_CFGD_MOD_SDS_RAM_VERSION_SIZE 4 +#define SCP_CFGD_MOD_SDS_RESET_SYNDROME_SIZE 4 +#define SCP_CFGD_MOD_SDS_FEATURE_AVAILABILITY_SIZE 4 + +/* Flags to indicate the available features */ +#define PLATFORM_SDS_FEATURE_FIRMWARE_MASK 0x1 + +#endif /* SCP_CFGD_SDS_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h index 4774c58d6..faf3de235 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h @@ -39,6 +39,13 @@ (SCP_ATW0_AP_PERIPHERAL_SRAM_BASE) #define SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_SIZE (4 * FWK_KIB) +/* + * SDS Memory Region inside Secure AP Peripheral SRAM that is shared between + * AP and SCP. + */ +#define SCP_SDS_SECURE_BASE (SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE) +#define SCP_SDS_SECURE_SIZE (3520) + /* * AP Context Memory Region inside Secure AP Peripheral SRAM that is shared * between AP and SCP. -- GitLab From 9024c0d6a05e70b1e8a75e6452949ea0d908da2b Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 6 Nov 2024 06:36:32 +0000 Subject: [PATCH 23/50] rdv3r1: add config data for transport module in scpfw Add the configuration data for the transport module. Two instances of transport channel are included - one for for communicating PSCI messages with the AP core and the other for sending handshake/synchronization messages from SCP platform module to RSS. Signed-off-by: Nancy . Change-Id: I903ca56671e577b567582e5c74750cf997ac4008 --- .../rdv3r1/scp_ramfw/config_transport.c | 98 +++++++++++++++++++ .../scp_ramfw/include/scp_cfgd_transport.h | 22 +++++ .../rdv3r1/scp_ramfw/include/scp_fw_mmap.h | 4 + 3 files changed, 124 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_transport.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c new file mode 100644 index 000000000..f95be4ff9 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c @@ -0,0 +1,98 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'transport'. + */ + +#include "scp_cfgd_mhu3.h" +#include "scp_cfgd_transport.h" +#include "scp_fw_mmap.h" + +#include +#include + +#include +#include +#include +#include + +#include + +/* Secure transport channel with mailbox initialization policy */ +#define TRANSPORT_CH_SEC_MBX_INIT \ + (MOD_TRANSPORT_POLICY_INIT_MAILBOX | MOD_TRANSPORT_POLICY_SECURE) + +/* Subsystem initialized notification id (platform notification) */ +#define PLATFORM_SCP_NOTIFICATION_ID \ + FWK_ID_NOTIFICATION_INIT( \ + FWK_MODULE_IDX_SCP_PLATFORM, \ + MOD_SCP_PLATFORM_NOTIFICATION_IDX_SUBSYS_INITIALIZED) + +/* Module 'transport' element configuration table */ +static const struct fwk_element element_table[] = { + /* + * Channel for receiving PSCI messages from application core over the secure + * AP to SCP MHU mailbox. + */ + [SCP_CFGD_MOD_TRANSPORT_EIDX_PSCI] = { + .name = "PSCI", + .data = &(( + struct mod_transport_channel_config) { + .transport_type = MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_OUT_BAND, + .policies = TRANSPORT_CH_SEC_MBX_INIT, + .channel_type = MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .out_band_mailbox_address = + (uintptr_t) SCP_SCMI_PAYLOAD_S_A2P_BASE, + .out_band_mailbox_size = SCP_SCMI_PAYLOAD_SIZE, + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU3, + SCP_CFGD_MOD_MHU3_EIDX_SCP_AP_S, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU3, + MOD_MHU3_API_IDX_TRANSPORT_DRIVER), + }), + }, + /* + * Channel for SCP platform module to send synchronization messages to the + * RSS during boot over the SCP to RSS MHU mailbox. + */ + [SCP_CFGD_MOD_TRANSPORT_EIDX_SYSTEM] = { + .name = "SCP_PLATFORM_TRANSPORT", + .data = &(( + struct mod_transport_channel_config) { + .transport_type = MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_NONE, + .policies = MOD_TRANSPORT_POLICY_NONE, + .channel_type = MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .signal_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_SCP_PLATFORM, + MOD_SCP_PLATFORM_API_IDX_TRANSPORT_SIGNAL), + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU3, + SCP_CFGD_MOD_MHU3_EIDX_SCP_RSS, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU3, + MOD_MHU3_API_IDX_TRANSPORT_DRIVER), + }), + }, + [SCP_CFGD_MOD_TRANSPORT_EIDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *transport_get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +const struct fwk_module_config config_transport = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(transport_get_element_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_transport.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_transport.h new file mode 100644 index 000000000..3b1dc9f68 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_transport.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for transport module configuration data in SCP + * firmware. + */ + +#ifndef SCP_CFGD_TRANSPORT_H +#define SCP_CFGD_TRANSPORT_H + +/* Module 'transport' element indexes */ +enum scp_cfgd_mod_transport_element_idx { + SCP_CFGD_MOD_TRANSPORT_EIDX_PSCI, + SCP_CFGD_MOD_TRANSPORT_EIDX_SYSTEM, + SCP_CFGD_MOD_TRANSPORT_EIDX_COUNT, +}; + +#endif /* SCP_CFGD_TRANSPORT_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h index faf3de235..3f7fdc82f 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_fw_mmap.h @@ -55,4 +55,8 @@ (SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE + \ SCP_AP_PERIPHERAL_SRAM_TRUSTED_SIZE - SCP_AP_CONTEXT_SIZE) +/* SCMI Secure Payload Area */ +#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_SECURE_BASE + SCP_SDS_SECURE_SIZE) +#define SCP_SCMI_PAYLOAD_SIZE (128) + #endif /* SCP_FW_MMAP_H */ -- GitLab From 7fa1df95071fb73604d3a11ee25943166802e6f3 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 26 Jun 2024 15:30:29 +0530 Subject: [PATCH 24/50] rdv3r1: add config data for scmi module in scpfw SCMI messages for PSCI operations are delivered via a transport channel to a SCMI agent. Add configuration data for SCMI module to setup this interface. Signed-off-by: Nancy . Change-Id: I508404db37c8bc2c0a26b137cb2c225365e0100b --- .../rdv3r1/scp_ramfw/config_scmi.c | 67 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_cfgd_scmi.h | 29 ++++++++ 2 files changed, 96 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_scmi.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi.c new file mode 100644 index 000000000..49c148723 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi.c @@ -0,0 +1,67 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'scmi'. + */ + +#include "scp_cfgd_scmi.h" +#include "scp_cfgd_transport.h" + +#include +#include + +#include +#include +#include +#include +#include + +static const struct fwk_element service_table[] = { + [SCP_CFGD_MOD_SCMI_EIDX_PSCI] = { + .name = "SCMI_PSCI", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_TRANSPORT, + SCP_CFGD_MOD_TRANSPORT_EIDX_PSCI), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_API_IDX_SCMI_TO_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_IDX_PSCI, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }), + }, + [SCP_CFGD_MOD_SCMI_EIDX_COUNT] = { 0 } +}; + +static const struct fwk_element *get_service_table(fwk_id_t module_id) +{ + return service_table; +} + +static struct mod_scmi_agent agent_table[] = { + [SCP_SCMI_AGENT_IDX_PSCI] = { + .type = SCMI_AGENT_TYPE_PSCI, + .name = "PSCI", + }, +}; + +const struct fwk_module_config config_scmi = { + .data = + &(struct mod_scmi_config){ + .protocol_count_max = 4, + .protocol_requester_count_max = 2, + .agent_count = FWK_ARRAY_SIZE(agent_table) - 1, + .agent_table = agent_table, + .vendor_identifier = "arm", + .sub_vendor_identifier = "arm", + }, + + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_service_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_scmi.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_scmi.h new file mode 100644 index 000000000..19ce6d1ab --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_scmi.h @@ -0,0 +1,29 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for SCMI module configuration data in SCP firmware. + */ + +#ifndef SCP_CFGD_SCMI_H +#define SCP_CFGD_SCMI_H + +#include + +/* SCMI agent identifier indexes in the SCMI agent table */ +enum scp_scmi_agent_idx { + /* 0 is reserved for the platform */ + SCP_SCMI_AGENT_IDX_PSCI = 1, + SCP_SCMI_AGENT_IDX_COUNT, +}; + +/* Module 'scmi' element indexes (SCMI services supported) */ +enum scp_cfgd_mod_scmi_element_idx { + SCP_CFGD_MOD_SCMI_EIDX_PSCI, + SCP_CFGD_MOD_SCMI_EIDX_COUNT, +}; + +#endif /* SCP_CFGD_SCMI_H */ -- GitLab From b5938a612373be6f4c57aa995870acaa5fd02305 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 19 Nov 2024 08:20:38 +0000 Subject: [PATCH 25/50] rdv3r1: add config data for atu driver in scpfw Add config data for ATU driver module in scp ramfw. The config data selects 'managed' mode of operation, that is, SCP configures the ATU with required region mappings. The regions that have to be setup at boot as listed in the config data. Signed-off-by: Nancy . Change-Id: Icce5ca10364debd579ebc94be94cd8b6567dcb82 --- .../neoverse-rd/rdv3r1/scp_ramfw/config_atu.c | 121 ++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_css_mmap.h | 1 + 2 files changed, 122 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_atu.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_atu.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_atu.c new file mode 100644 index 000000000..eb5c86ab2 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_atu.c @@ -0,0 +1,121 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'atu'. + */ + +#include "scp_atw0_mmap.h" +#include "scp_atw1_mmap.h" +#include "scp_css_mmap.h" + +#include +#include + +#include +#include +#include +#include + +/* Peripheral address space size per chip */ +#define CHIP_ADDR_SIZE (64ULL * FWK_GIB) +/* Return peripheral address space offset based on chip id */ +#define CHIP_ADDR_OFFSET(chip_id) (chip_id * CHIP_ADDR_SIZE) + +/* Indices for ATU module elements */ +enum cfgd_mod_atu_element_idx { + CFGD_MOD_ATU_EIDX_ATU0, + CFGD_MOD_ATU_EIDX_COUNT +}; + +/* Indices for translation regions to be configured in the ATU */ +enum atu_regions_idx { + /* ATU region to access CMN CFGM */ + ATU_REGION_IDX_CMN = 0, + /* ATU region to access AP Cluster Utility space */ + ATU_REGION_IDX_CLUSTER_UTIL, + /* ATU region to access LCP Cluster space */ + ATU_REGION_IDX_CLUSTER_LCP, + /* ATU region to access AP shared SRAM */ + ATU_REGION_IDX_SHARED_SRAM, + /* ATU region count */ + ATU_REGION_IDX_COUNT, +}; + +struct atu_region_map atu_regions[ATU_REGION_IDX_COUNT] = { + [ATU_REGION_IDX_CMN] = { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCP_PLATFORM), + .log_addr_base = SCP_ATW1_CMN_BASE, + .phy_addr_base = 0x100000000, + .region_size = SCP_ATW1_CMN_SIZE, + .attributes = ATU_ENCODE_ATTRIBUTES_ROOT_PAS, + }, + [ATU_REGION_IDX_CLUSTER_UTIL] = { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCP_PLATFORM), + .log_addr_base = SCP_ATW0_CU_AP_PERIPH_REGION_BASE, + .phy_addr_base = 0x140000000, + .region_size = SCP_ATW0_CU_AP_PERIPH_REGION_SIZE, + .attributes = ATU_ENCODE_ATTRIBUTES_ROOT_PAS, + }, + [ATU_REGION_IDX_CLUSTER_LCP] = { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCP_PLATFORM), + .log_addr_base = SCP_ATW0_CU_LCP_PERIPH_REGION_BASE, + .phy_addr_base = 0x160000000, + .region_size = SCP_ATW0_CU_LCP_PERIPH_REGION_SIZE, + .attributes = ATU_ENCODE_ATTRIBUTES_ROOT_PAS, + }, + [ATU_REGION_IDX_SHARED_SRAM] = { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCP_PLATFORM), + .log_addr_base = SCP_ATW0_AP_PERIPHERAL_SRAM_BASE, + .phy_addr_base = 0x00000000, + .region_size = SCP_ATW0_AP_PERIPHERAL_SRAM_SIZE, + .attributes = ATU_ENCODE_ATTRIBUTES_ROOT_PAS, + }, +}; + +static const struct fwk_element element_table[] = { + [CFGD_MOD_ATU_EIDX_ATU0] = { + .name = "SCP_ATU", + .data = &(struct mod_atu_device_config) { + .is_atu_delegated = false, + .atu_base = SCP_ATU_BASE, + .atu_region_config_table = atu_regions, + .atu_region_count = FWK_ARRAY_SIZE(atu_regions), + }, + }, + [CFGD_MOD_ATU_EIDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + int status; + uint8_t i; + uint8_t chip_id; + const struct mod_sid_info *system_info; + + /* Get system info from the SID driver */ + status = mod_sid_get_system_info(&system_info); + if (status != FWK_SUCCESS) { + fwk_trap(); + } + + /* Node Number indicates the chip id in a multichip system */ + chip_id = system_info->node_number; + + /* + * For each ATU region, add chip address space offset to the physical + * address, based on the current chip id. + */ + for (i = 0; i < FWK_ARRAY_SIZE(atu_regions); i++) { + atu_regions[i].phy_addr_base += CHIP_ADDR_OFFSET(chip_id); + } + + return element_table; +} + +struct fwk_module_config config_atu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h index 308e63cdb..753befd7f 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_css_mmap.h @@ -33,6 +33,7 @@ #define SCP_SCP2RSS_MHUV3_SEND_BASE (0x46000000) #define SCP_RSS2SCP_MHUV3_RCV_BASE (0x46010000) #define SCP_POWER_CONTROL_BASE (0x50000000) +#define SCP_ATU_BASE (0x50010000) #define SCP_SYSTEM_PIK_BASE (0x50040000) #define SCP_PPU_SYS0_BASE (0x50041000) -- GitLab From d9f60d02b6de6aa8eca7ae08a21e0c8afb68c5c5 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 26 Jun 2024 15:40:44 +0530 Subject: [PATCH 26/50] rdv3r1: add config data for scmi power domain in scpfw There is no specific configuration data to be supplied to the scmi power domain module. So, leave the config empty. Signed-off-by: Nancy . Change-Id: I1be1d70a4fe10f48a32394cf6e357d3313593189 --- .../rdv3r1/scp_ramfw/config_scmi_power_domain.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_power_domain.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_power_domain.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_power_domain.c new file mode 100644 index 000000000..26d40c7f7 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_power_domain.c @@ -0,0 +1,14 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'scmi_power_domain'. + */ + +#include + +/* No elements, no module configuration data */ +struct fwk_module_config config_scmi_power_domain = { 0 }; -- GitLab From 2961385fd560ed7765cdfa552133e09790aad471 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 26 Jun 2024 15:47:19 +0530 Subject: [PATCH 27/50] rdv3r1: add config data for scmi system power module in scpfw Provide the configuration data for scmi system power module in scp ramfw to manage system states. Signed-off-by: Nancy . Change-Id: Ifd8474cb9badd7165b42462da08956b4206b06ab --- .../scp_ramfw/config_scmi_system_power.c | 30 +++++++++++++++++++ .../rdv3r1/scp_ramfw/include/scp_cfgd_timer.h | 3 ++ 2 files changed, 33 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_system_power.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_system_power.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_system_power.c new file mode 100644 index 000000000..387429e58 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scmi_system_power.c @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'scmi_system_power'. + */ + +#include "scp_cfgd_timer.h" + +#include +#include + +#include + +const struct fwk_module_config config_scmi_system_power = { + .data = &((struct mod_scmi_system_power_config){ + .system_view = MOD_SCMI_SYSTEM_VIEW_FULL, + .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0, +#ifdef BUILD_HAS_SCMI_NOTIFICATIONS + .alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + SCP_CFGD_SCMI_NOTIFICATION_ALARM_IDX), + .graceful_timeout = 1000, /* ms */ +#endif + }), +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h index ad6e98b7e..5f9d4e7fa 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/scp_cfgd_timer.h @@ -13,6 +13,9 @@ /* Sub-element indexes (alarms) for SCP timer device */ enum scp_cfgd_mod_timer_alarm_idx { +#ifdef BUILD_HAS_SCMI_NOTIFICATIONS + SCP_CFGD_SCMI_NOTIFICATION_ALARM_IDX, +#endif SCP_CFGD_MOD_TIMER_SEIDX_ALARM_COUNT, }; -- GitLab From 4671ead8ecfe6d207b280c29e7901faae0305925 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 26 Jun 2024 15:51:34 +0530 Subject: [PATCH 28/50] rdv3r1: add system power module config data in scpfw The system power driver manages the SYSTOP power domain. The configuration data includes the system PPU id, system PPU API id, system PPU power state table, system shutdown driver id, system shutdown driver API id and the initial system power state after power-on. Signed-off-by: Nancy . Change-Id: I915cfbfc4ed2b425e9a0b58f1a2dc84436203afd --- .../rdv3r1/scp_ramfw/config_system_power.c | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_system_power.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_power.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_power.c new file mode 100644 index 000000000..398f16664 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_power.c @@ -0,0 +1,89 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'system_power'. + */ + +#include "platform_core.h" + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* Indices for system power module elements */ +enum cfgd_mod_system_power_element_idx { + CFGD_MOD_SYSTEM_POWER_EIDX_SYS_PPU, + CFGD_MOD_SYSTEM_POWER_EIDX_COUNT +}; + +static const uint8_t sys_pwr_state_table[] = { + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_OFF, +}; + +static struct fwk_element element_table[] = { + [CFGD_MOD_SYSTEM_POWER_EIDX_SYS_PPU] = { + .name = "SYS-PPU-0", + .data = &((struct mod_system_power_dev_config) { + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = sys_pwr_state_table, + }), + }, + [CFGD_MOD_SYSTEM_POWER_EIDX_COUNT] = { 0 }, /* Termination description */ +}; + +static const struct fwk_element *system_power_get_element_table(fwk_id_t unused) +{ + unsigned int ppu_idx_base; + unsigned int core_count; + unsigned int cluster_count; + unsigned int i; + struct mod_system_power_dev_config *dev_config; + + core_count = platform_get_core_count(); + cluster_count = platform_get_cluster_count(); + + /* The system PPUs are placed after the core and cluster PPUs */ + ppu_idx_base = core_count + cluster_count; + + /* Configure System PPU id */ + for (i = 0; i < (FWK_ARRAY_SIZE(element_table) - 1); i++) { + dev_config = + (struct mod_system_power_dev_config *)element_table[i].data; + + dev_config->sys_ppu_id = + fwk_id_build_element_id(fwk_module_id_ppu_v1, ppu_idx_base + i); + } + + return element_table; +} + +static struct mod_system_power_config system_power_config = { + .soc_wakeup_irq = FWK_INTERRUPT_NONE, + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCP_PLATFORM), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SCP_PLATFORM, + MOD_SCP_PLATFORM_API_IDX_SYSTEM_POWER_DRIVER), + .initial_system_power_state = MOD_PD_STATE_ON, +}; + +const struct fwk_module_config config_system_power = { + .data = &system_power_config, + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_power_get_element_table), +}; -- GitLab From 035e55342ddd6d56033fd2019b68cff436c325cb Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Mon, 11 Nov 2024 06:57:42 +0000 Subject: [PATCH 29/50] rdv3r1: add platform module for scpfw Add SCP Platform module. This module performs the following functions: - SCP-RSS handshake. - Notifies modules that have subscribed to relavant event that the subsystem initialization is complete. Those modules on receiving the event notification can complete any pending setup that depend on access to any address space outside of the SCP subsystem. - Setup LCP. Enable LCP0 UART access and release all LCPs from reset. - Turn on primary AP core. Signed-off-by: Nancy . Change-Id: I18ecc66459ab7e3e003a6336fe67c4089c7472ca --- .../module/scp_platform/CMakeLists.txt | 22 ++ .../module/scp_platform/Module.cmake | 10 + .../include/internal/scp_platform.h | 103 +++++++++ .../scp_platform/include/mod_scp_platform.h | 88 ++++++++ .../scp_platform/src/mod_scp_platform.c | 207 ++++++++++++++++++ .../module/scp_platform/src/platform_lcp.c | 88 ++++++++ .../scp_platform/src/platform_power_mgmt.c | 69 ++++++ .../module/scp_platform/src/platform_rse.c | 141 ++++++++++++ 8 files changed, 728 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/CMakeLists.txt create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/Module.cmake create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/internal/scp_platform.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/mod_scp_platform.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/mod_scp_platform.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_lcp.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_power_mgmt.c create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_rse.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/CMakeLists.txt b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/CMakeLists.txt new file mode 100644 index 000000000..15549194a --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/CMakeLists.txt @@ -0,0 +1,22 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_sources( + ${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_scp_platform.c" + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/platform_lcp.c" + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/platform_power_mgmt.c" + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/platform_rse.c") + +target_link_libraries( + ${SCP_MODULE_TARGET} + PRIVATE module-power-domain module-system-info + module-system-power module-transport module-timer) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/Module.cmake b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/Module.cmake new file mode 100644 index 000000000..4faf2676b --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "scp-platform") + +set(SCP_MODULE_TARGET "module-scp-platform") diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/internal/scp_platform.h b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/internal/scp_platform.h new file mode 100644 index 000000000..af932c43d --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/internal/scp_platform.h @@ -0,0 +1,103 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP sub-system support. + */ + +#ifndef SCP_PLATFORM_H +#define SCP_PLATFORM_H + +#include + +#define MOD_NAME "[SCP_PLATFORM]" + +/* + * RSE communication interface helper functions. + */ + +/*! + * \brief Helper function to return platform system transport signal API. + * + * \param None. + * + * \return Pointer to the scp platform transport signal API. + */ +const void *get_platform_transport_signal_api(void); + +/*! + * \brief Helper function to notify RSE and wait for response. + * + * \details Notify RSE that SYSTOP is powered up so it can enable GPC bypass in + * the system control block and load the LCP firmware into all the instances of + * the LCP in the platform. + * + * \param None. + * + * \retval ::FWK_SUCCESS Operation succeeded. + * \return One of the standard error codes for implementation-defined errors. + */ +int notify_rse_and_wait_for_response(void); + +/*! + * \brief Helper function to bind to transport and timer module APIs. + * + * \param config Pointer to the module config data. + * + * \retval ::FWK_SUCCESS Operation succeeded. + * \return One of the standard error codes for implementation-defined errors. + */ +int platform_rse_bind(const struct mod_scp_platform_config *config); + +/* + * LCP interface helper functions. + */ + +/*! + * \brief Helper function to setup LCP. + * + * \details Enable UART access for LCP0 and release all the LCPs. + * + * \param None. + * + * \return Nothing. + */ +void platform_setup_lcp(void); + +/* + * Power Management interface helper functions. + */ + +/*! + * \brief Helper function to return platform system power driver API. + * + * \param None. + * + * \return Pointer to the scp platform system power driver API. + */ +const void *get_platform_system_power_driver_api(void); + +/*! + * \brief Helper function to bind to power domain restricted API. + * + * \param None. + * + * \retval ::FWK_SUCCESS Operation succeeded. + * \return One of the standard error codes for implementation-defined errors. + */ +int platform_power_mgmt_bind(void); + +/*! + * \brief Power on the given AP core. + * + * \param core_idx AP core index. + * + * \retval ::FWK_SUCCESS Operation succeeded. + * \return One of the standard error codes for implementation-defined errors. + */ +int init_ap_core(uint8_t core_idx); + +#endif /* SCP_PLATFORM_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/mod_scp_platform.h b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/mod_scp_platform.h new file mode 100644 index 000000000..277718f39 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/include/mod_scp_platform.h @@ -0,0 +1,88 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP Platform Support + */ + +#ifndef MOD_SCP_PLATFORM_H +#define MOD_SCP_PLATFORM_H + +#include +#include + +#include + +/*! + * \addtogroup GroupPLATFORMModule PLATFORM Product Modules + * @{ + */ + +/*! + * \defgroup GroupSCPPlatform SCP Platform Support + * @{ + */ + +/*! + * \brief Indices of the interfaces exposed by the module. + */ +enum mod_scp_platform_api_idx { + /*! Interface of the System Power module */ + MOD_SCP_PLATFORM_API_IDX_SYSTEM_POWER_DRIVER, + + /*! Interface for Transport module */ + MOD_SCP_PLATFORM_API_IDX_TRANSPORT_SIGNAL, + + /*! Number of exposed interfaces */ + MOD_SCP_PLATFORM_API_COUNT +}; + +/*! + * \brief Notification indices. + */ +enum mod_scp_platform_notification_idx { + /*! SCP subsystem initialization completion notification */ + MOD_SCP_PLATFORM_NOTIFICATION_IDX_SUBSYS_INITIALIZED, + + /*! Number of notifications defined by the module */ + MOD_SCP_PLATFORM_NOTIFICATION_COUNT, +}; + +/*! + * \brief Identifier for the + * ::MOD_SCP_PLATFORM_NOTIFICATION_IDX_SUBSYS_INITIALIZED notification. + */ +static const fwk_id_t mod_scp_platform_notification_subsys_init = + FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SCP_PLATFORM, + MOD_SCP_PLATFORM_NOTIFICATION_IDX_SUBSYS_INITIALIZED); + +/*! + * \brief SCP platform configuration data. + */ +struct mod_scp_platform_config { + /*! Timer identifier */ + fwk_id_t timer_id; + + /*! Transport channel identifier */ + fwk_id_t transport_id; + + /*! + * Maximum amount of time, in microseconds, to wait for the RSE handshake + * event. + */ + uint32_t rse_sync_wait_us; +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_SCP_PLATFORM_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/mod_scp_platform.c b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/mod_scp_platform.c new file mode 100644 index 000000000..beadc2134 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/mod_scp_platform.c @@ -0,0 +1,207 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP platform sub-system initialization support. + */ + +#include "core_manager.h" +#include "platform_core.h" + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Module context */ +struct scp_platform_ctx { + /* Module config data */ + const struct mod_scp_platform_config *config; + + /* System Information HAL API pointer */ + struct mod_system_info_get_info_api *system_info_api; +}; + +/* Module context data */ +struct scp_platform_ctx scp_platform_ctx; + +static void platform_update_gpt_size(void) +{ + uint8_t core_idx; + uint8_t core_count; + + core_count = platform_get_core_count(); + + /* Configure the L0 GPT size for all AP cores */ + for (core_idx = 0; core_idx < core_count; core_idx++) { + SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(core_idx)->PE_STATIC_CONFIG &= + ~(CORE_MANAGER_PE_STATIC_CONFIG_L0GPTSZ_MASK + << CORE_MANAGER_PE_STATIC_CONFIG_L0GPTSZ_SHIFT); + SCP_CU_AP_PERIPH_CORE_MANAGER_PTR(core_idx)->PE_STATIC_CONFIG |= + (CORE_MANAGER_PE_STATIC_CONFIG_L0GPTSZ_16GB + << CORE_MANAGER_PE_STATIC_CONFIG_L0GPTSZ_SHIFT); + } +} + +/* + * Framework handlers. + */ +static int scp_platform_init( + fwk_id_t module_id, + unsigned int unused, + const void *data) +{ + const struct mod_scp_platform_config *config; + + config = (struct mod_scp_platform_config *)data; + + if (!fwk_id_type_is_valid(config->timer_id) || + !fwk_id_type_is_valid(config->transport_id)) { + return FWK_E_DATA; + } + + /* Save the config data in the module context */ + scp_platform_ctx.config = config; + + return FWK_SUCCESS; +} + +static int scp_platform_bind(fwk_id_t id, unsigned int round) +{ + int status; + fwk_id_t mod_system_info_api_id_get_info; + + if (round > 0) { + return FWK_SUCCESS; + } + + /* Bind to modules required to handshake with RSE */ + status = platform_rse_bind(scp_platform_ctx.config); + if (status != FWK_SUCCESS) { + return status; + } + + /* Bind to modules required for power management */ + status = platform_power_mgmt_bind(); + if (status != FWK_SUCCESS) { + return status; + } + + mod_system_info_api_id_get_info = + FWK_ID_API(FWK_MODULE_IDX_SYSTEM_INFO, MOD_SYSTEM_INFO_GET_API_IDX); + + /* Bind to System Info HAL API */ + return fwk_module_bind( + fwk_module_id_system_info, + mod_system_info_api_id_get_info, + &scp_platform_ctx.system_info_api); +} + +static int scp_platform_process_bind_request( + fwk_id_t requester_id, + fwk_id_t target_id, + fwk_id_t api_id, + const void **api) +{ + int status; + enum mod_scp_platform_api_idx api_idx; + + api_idx = (enum mod_scp_platform_api_idx)fwk_id_get_api_idx(api_id); + + switch (api_idx) { + case MOD_SCP_PLATFORM_API_IDX_SYSTEM_POWER_DRIVER: + *api = get_platform_system_power_driver_api(); + status = FWK_SUCCESS; + break; + + case MOD_SCP_PLATFORM_API_IDX_TRANSPORT_SIGNAL: + *api = get_platform_transport_signal_api(); + status = FWK_SUCCESS; + break; + + default: + status = FWK_E_PARAM; + } + + return status; +} + +static int scp_platform_start(fwk_id_t id) +{ + int status; + const struct mod_system_info *system_info; + struct fwk_event event = { 0 }; + unsigned int event_count; + + /* Notify RSE that SYSTOP is powered up and wait for RSE doorbell */ + status = notify_rse_and_wait_for_response(); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR(MOD_NAME "Error! SCP-RSE handshake failed"); + return FWK_E_PANIC; + } + + /* SCP subsystem initialization completion notification */ + event.id = mod_scp_platform_notification_subsys_init; + event.source_id = id; + + /* + * RSE has now setup GPC bypass in the system control block. Notify other + * modules that are waiting to access memory regions outside the SCP + * subsystem (which otherwise would have generated a fault). + */ + status = fwk_notification_notify(&event, &event_count); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR(MOD_NAME "Error! Subsystem init notification failed"); + return FWK_E_PANIC; + } + + /* Configure LCP0 UART access and release all LCPs */ + platform_setup_lcp(); + + /* Update L0GPTSZ for all cores */ + platform_update_gpt_size(); + + /* Determine the chip information */ + status = scp_platform_ctx.system_info_api->get_system_info(&system_info); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR(MOD_NAME "Error! Failed to obtain system info"); + return FWK_E_PANIC; + } + + if (system_info->chip_id != 0) { + /* Nothing to be done for secondary chips */ + return FWK_SUCCESS; + } + + FWK_LOG_INFO(MOD_NAME "Initializing the primary core..."); + + status = init_ap_core(0); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR(MOD_NAME "Error! Failed to initialize primary core"); + fwk_trap(); + } + + return FWK_SUCCESS; +} + +const struct fwk_module module_scp_platform = { + .type = FWK_MODULE_TYPE_DRIVER, + .api_count = MOD_SCP_PLATFORM_API_COUNT, + .notification_count = MOD_SCP_PLATFORM_NOTIFICATION_COUNT, + .init = scp_platform_init, + .bind = scp_platform_bind, + .process_bind_request = scp_platform_process_bind_request, + .start = scp_platform_start, +}; diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_lcp.c b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_lcp.c new file mode 100644 index 000000000..3b52d9145 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_lcp.c @@ -0,0 +1,88 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP Platform Support - LCP interface + */ + +#include "platform_core.h" +#include "scp_css_mmap.h" +#include "scp_cu_lcp_periph.h" + +#include + +#include +#include + +#include +#include + +static uint8_t get_lcp_count() +{ + uint32_t lcp_cfg_reg; + uint8_t lcp_ctrl_ratio; + + /* + * All LCPs are assumed to have the same LCP control ratio value. + * So, read from LCP0. + */ + lcp_cfg_reg = SCP_LCP_EXTENDED_CONTROL_PTR(0)->LCP_CFG; + + /* Read the number of APs controlled by this LCP */ + lcp_ctrl_ratio = + (((lcp_cfg_reg >> LCP_PERIPH_EXTDCTRL_LCP_CONFIG_CTRL_RATIO_SHIFT) & + LCP_PERIPH_EXTDCTRL_LCP_CONFIG_CTRL_RATIO_MASK) + + 1); + + return (platform_get_core_count() / lcp_ctrl_ratio); +} + +static void enable_lcp_uart(uint8_t lcp_idx) +{ + FWK_RW uint32_t *lcp_uart_ctrl_reg; + + fwk_assert(lcp_idx < get_lcp_count()); + + lcp_uart_ctrl_reg = + (FWK_RW uint32_t *)&(SCP_LCP_EXTERNAL_CONTROL_PTR(lcp_idx)->UART_CTRL); + + /* Enable access to the LCP UART and the LCP UART interrupt routing */ + *lcp_uart_ctrl_reg |= + (LCP_PERIPH_EXTRCTRL_UART_CTRL_EN_VAL + << LCP_PERIPH_EXTRCTRL_UART_CTRL_EN_SHIFT); +} + +static void release_lcp(uint8_t lcp_idx) +{ + FWK_RW uint32_t *cpu_wait_reg; + + fwk_assert(lcp_idx < get_lcp_count()); + + cpu_wait_reg = (FWK_RW uint32_t *)&(SCP_LCP_CONTROL_PTR(lcp_idx)->CPUWAIT); + + /* Deassert CPUWAIT to start LCP execution */ + *cpu_wait_reg &= + ~(LCP_PERIPH_CONTROL_CPU_WAIT_CPU0WAIT_VAL + << LCP_PERIPH_CONTROL_CPU_WAIT_CPU0WAIT_SHIFT); +} + +void platform_setup_lcp(void) +{ + uint8_t lcp_idx; + + /* + * Enable UART access for LCP0 only. If all the LCPs are allowed to access + * the UART at the same time, the output will be unreadable. Hence, + * restrict the LCP UART to single LCP for now. + */ + lcp_idx = 0; + enable_lcp_uart(lcp_idx); + + /* Release all the LCPs */ + for (lcp_idx = 0; lcp_idx < get_lcp_count(); lcp_idx++) { + release_lcp(lcp_idx); + } +} diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_power_mgmt.c b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_power_mgmt.c new file mode 100644 index 000000000..26518faac --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_power_mgmt.c @@ -0,0 +1,69 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP Platform Support - Power Management + */ + +#include + +#include +#include + +#include +#include +#include + +#include + +/* Module 'power_domain' restricted API pointer */ +static struct mod_pd_restricted_api *pd_restricted_api; + +/* System shutdown function */ +static int platform_shutdown(enum mod_pd_system_shutdown system_shutdown) +{ + while (1) { + __WFI(); + } + + return FWK_E_DEVICE; +} + +/* Module 'system_power' driver interface */ +const struct mod_system_power_driver_api platform_system_pwr_drv_api = { + .system_shutdown = platform_shutdown, +}; + +const void *get_platform_system_power_driver_api(void) +{ + return &platform_system_pwr_drv_api; +} + +int platform_power_mgmt_bind(void) +{ + return fwk_module_bind( + fwk_module_id_power_domain, + mod_pd_api_id_restricted, + &pd_restricted_api); +} + +int init_ap_core(uint8_t core_idx) +{ + bool resp_requested; + uint32_t pd_state; + fwk_id_t pd_id; + + pd_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, core_idx); + + /* Notification event at the end of request processing is not required */ + resp_requested = false; + + /* Composite Power Domain state to be set for the AP */ + pd_state = MOD_PD_COMPOSITE_STATE( + MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON, MOD_PD_STATE_ON, MOD_PD_STATE_ON); + + return pd_restricted_api->set_state(pd_id, resp_requested, pd_state); +} diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_rse.c b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_rse.c new file mode 100644 index 000000000..88da09b9f --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/scp_platform/src/platform_rse.c @@ -0,0 +1,141 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP Platform Support - implements support for communication with RSE. + */ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* Platform RSE context */ +struct platform_rse_ctx { + /* Pointer to the module config data */ + const struct mod_scp_platform_config *config; + + /* Transport API to send/respond to a message */ + const struct mod_transport_firmware_api *transport_api; + + /* Timer API */ + const struct mod_timer_api *timer_api; + + /* Flag to indicate that the RSE doorbell has been received */ + volatile bool rse_doorbell_received; +}; + +static struct platform_rse_ctx ctx; + +/* Utility function to check if SCP platform has received doorbell from RSE */ +static bool is_rse_doorbell_received(void *unused) +{ + return ctx.rse_doorbell_received; +} + +/* + * Module 'transport' signal interface implementation. + */ +static int signal_error(fwk_id_t unused) +{ + FWK_LOG_ERR(MOD_NAME "Error! Invalid response received from RSE"); + + ctx.transport_api->release_transport_channel_lock(ctx.config->transport_id); + + return FWK_SUCCESS; +} + +static int signal_message(fwk_id_t unused) +{ + FWK_LOG_INFO(MOD_NAME "Received doorbell event from RSE"); + + ctx.transport_api->release_transport_channel_lock(ctx.config->transport_id); + + /* Set the flag to indicate that the RSE initialization is complete */ + ctx.rse_doorbell_received = true; + + return FWK_SUCCESS; +} + +const struct mod_transport_firmware_signal_api platform_transport_signal_api = { + .signal_error = signal_error, + .signal_message = signal_message, +}; + +/* + * Helper function to retrieve the 'transport' module signal API. + */ +const void *get_platform_transport_signal_api(void) +{ + return &platform_transport_signal_api; +} + +/* + * RSE has to be notified that SYSTOP is powered up and so it can enable GPC + * bypass in the system control block and load the LCP firmware into all the + * instances of the LCP in the platform. + */ +int notify_rse_and_wait_for_response(void) +{ + int status; + + /* + * Trigger doorbell to RSE to indicate that the SYSTOP domain is ON. + */ + status = ctx.transport_api->trigger_interrupt(ctx.config->transport_id); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR(MOD_NAME + "Error! Failed to send SYSTOP enabled message to RSE"); + return status; + } + + /* + * Wait till a doorbell from RSE is received. This doorbell event indicates + * that the RSE has initialized the GPC, completed the peripheral NI-Tower + * setup and loaded the LCP ramfw images to LCP ITCM. + */ + status = ctx.timer_api->wait( + ctx.config->timer_id, + ctx.config->rse_sync_wait_us, + is_rse_doorbell_received, + NULL); + if (status != FWK_SUCCESS) { + FWK_LOG_ERR(MOD_NAME "Error! No response from RSE for SYSTOP sync"); + } + + return status; +} + +/* + * Bind to timer and transport module to communicate with RSE. + */ +int platform_rse_bind(const struct mod_scp_platform_config *config) +{ + int status; + fwk_id_t timer_api_id; + fwk_id_t transport_api_id; + + ctx.config = config; + + timer_api_id = FWK_ID_API(FWK_MODULE_IDX_TIMER, MOD_TIMER_API_IDX_TIMER); + status = fwk_module_bind(config->timer_id, timer_api_id, &ctx.timer_api); + if (status != FWK_SUCCESS) { + return status; + } + + transport_api_id = + FWK_ID_API(FWK_MODULE_IDX_TRANSPORT, MOD_TRANSPORT_API_IDX_FIRMWARE); + return fwk_module_bind( + config->transport_id, transport_api_id, &ctx.transport_api); +} -- GitLab From 2e2797aadf52e8b5cf83b40e63a5b8e95bd7f891 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 27 Jun 2024 11:44:56 +0530 Subject: [PATCH 30/50] rdv3r1: add config data for scp platform module in scpfw Provide configuration data for the scp_platform module which includes the transport channel id, timer id and the timeout value. Signed-off-by: Nancy . Change-Id: If75dda2e5703a14a93f5eb855e2cc8075fee0907 --- .../rdv3r1/scp_ramfw/config_scp_platform.c | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_scp_platform.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_scp_platform.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scp_platform.c new file mode 100644 index 000000000..b2baae48c --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_scp_platform.c @@ -0,0 +1,31 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'scp_platform'. + */ + +#include "scp_cfgd_transport.h" + +#include + +#include +#include +#include + +#define RSE_SYNC_WAIT_TIMEOUT_US (800 * 1000) + +static const struct mod_scp_platform_config platform_config_data = { + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + .rse_sync_wait_us = RSE_SYNC_WAIT_TIMEOUT_US, + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_TRANSPORT, + SCP_CFGD_MOD_TRANSPORT_EIDX_SYSTEM), +}; + +struct fwk_module_config config_scp_platform = { + .data = &platform_config_data, +}; -- GitLab From dd2f83c7eca71434473dc213f71cdaabc0835ffc Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 19 Nov 2024 11:04:22 +0000 Subject: [PATCH 31/50] rdv3r1: add system pik module for scpfw Add a module to initialize the System PIK registers. This module is an initial implementation and currently supports configuring the L0 GPT size in the IOMACRO_OVERRIDE register. Signed-off-by: Nancy . Change-Id: I061e4bfea50560073a0ac39b52ddf7d705885a0f --- .../module/system_pik/CMakeLists.txt | 16 +++++ .../scp_ramfw/module/system_pik/Module.cmake | 9 +++ .../system_pik/include/mod_system_pik.h | 35 ++++++++++ .../module/system_pik/src/mod_system_pik.c | 64 +++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/CMakeLists.txt create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/Module.cmake create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/include/mod_system_pik.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/src/mod_system_pik.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/CMakeLists.txt b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/CMakeLists.txt new file mode 100644 index 000000000..23995f7c3 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/CMakeLists.txt @@ -0,0 +1,16 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_system_pik.c") + +#target_link_libraries(${SCP_MODULE_TARGET} +# PRIVATE module-timer) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/Module.cmake b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/Module.cmake new file mode 100644 index 000000000..cc9d71339 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/Module.cmake @@ -0,0 +1,9 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "system-pik") +set(SCP_MODULE_TARGET "module_system_pik") diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/include/mod_system_pik.h b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/include/mod_system_pik.h new file mode 100644 index 000000000..edd9d0227 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/include/mod_system_pik.h @@ -0,0 +1,35 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MOD_SYSTEM_PIK_H +#define MOD_SYSTEM_PIK_H + +#include "system_pik.h" + +#include +#include + +#include +#include +#include + +/*! + * \brief System PIK module configuration data. + */ +struct mod_system_pik_device_config { + /*! Base address of the system PIK register block */ + uintptr_t system_pik_base; + + /*! Overide signal for Level 0 GPT entry size (GPCCR_EL3.L0GPTSZ) */ + uint32_t l0_gpt_size; +}; + +/*! + * \} + */ + +#endif /* MOD_SYSTEM_PIK_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/src/mod_system_pik.c b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/src/mod_system_pik.c new file mode 100644 index 000000000..0a8a6b90d --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/module/system_pik/src/mod_system_pik.c @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * System PIK device driver. + */ + +#include + +#include +#include +#include + +/* System PIK module context */ +struct mod_system_pik_ctx { + /*! Base address of the system PIK register block */ + struct system_pik_reg *system_pik_reg; +}; + +struct mod_system_pik_ctx system_pik_ctx; + +/* + * Framework handlers + */ +static int mod_system_pik_init( + fwk_id_t module_id, + unsigned int device_count, + const void *data) +{ + struct mod_system_pik_device_config *config = + (struct mod_system_pik_device_config *)data; + + system_pik_ctx.system_pik_reg = + (struct system_pik_reg *)config->system_pik_base; + + /* + * Apply all the boot time configuration. + */ + + if (config->l0_gpt_size != 0) { + system_pik_ctx.system_pik_reg->IOMACRO_OVERRIDE &= + ~(IOMACRO_OVERRIDE_TCU_L0GPTSZ_MASK + << IOMACRO_OVERRIDE_TCU_L0GPTSZ_SHIFT); + system_pik_ctx.system_pik_reg->IOMACRO_OVERRIDE |= + (config->l0_gpt_size << IOMACRO_OVERRIDE_TCU_L0GPTSZ_SHIFT); + } + + return FWK_SUCCESS; +} + +static int mod_system_pik_start(fwk_id_t id) +{ + return FWK_SUCCESS; +} + +/* System PIK module definition */ +const struct fwk_module module_system_pik = { + .type = FWK_MODULE_TYPE_DRIVER, + .init = mod_system_pik_init, + .start = mod_system_pik_start, +}; -- GitLab From a78ab0694c208cdc50816a3c5b20e9ba3a77d00f Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 19 Nov 2024 11:13:15 +0000 Subject: [PATCH 32/50] rdv3r1: add config data for system pik module in scpfw Provide System PIK module configuration data in scp ramfw. Signed-off-by: Nancy . Change-Id: I61f7d6ac1f12152d2e633541bfbccb99d538af1d --- .../rdv3r1/scp_ramfw/config_system_pik.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/config_system_pik.c diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_pik.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_pik.c new file mode 100644 index 000000000..5b384af92 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_system_pik.c @@ -0,0 +1,26 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'system_pik'. + */ + +#include "system_pik.h" + +#include + +#include +#include +#include + +static const struct mod_system_pik_device_config system_pik_data = { + .system_pik_base = (uintptr_t)SYSTEM_PIK_PTR, + .l0_gpt_size = IOMACRO_OVERRIDE_TCU_L0GPTSZ_16GB, +}; + +struct fwk_module_config config_system_pik = { + .data = &system_pik_data, +}; -- GitLab From 9518231804b7bbd79048f6e413d44209848b6a53 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 14 Nov 2024 15:19:34 +0000 Subject: [PATCH 33/50] rdv3r1: let modules subscribe to platform notification Three modules are dependent on the security engine on the platform to setup the GPC in the control block to be enabled so that these modules can access addresses outside the SCP subsystem address space. These three modules are apcontext, sds and transport. So update the config data of these modules to subscribe to the platform notification. Signed-off-by: Nancy . Change-Id: I1f5ed416197b10d95cb7b10aa75163380cb82f76 --- .../neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c | 5 +++++ product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c | 5 +++++ .../neoverse-rd/rdv3r1/scp_ramfw/config_transport.c | 12 ++++++------ 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c index f82c0c203..545a38cbb 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_apcontext.c @@ -11,6 +11,7 @@ #include "scp_fw_mmap.h" #include +#include #include #include @@ -19,6 +20,10 @@ static const struct mod_apcontext_config apcontext_data = { .base = SCP_AP_CONTEXT_BASE, .size = SCP_AP_CONTEXT_SIZE, .clock_id = FWK_ID_NONE_INIT, + .platform_notification = { + .notification_id = mod_scp_platform_notification_subsys_init, + .source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCP_PLATFORM), + }, }; struct fwk_module_config config_apcontext = { diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c index 3c37368ff..6ce71a1cc 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_sds.c @@ -11,6 +11,7 @@ #include "scp_cfgd_sds.h" #include "scp_fw_mmap.h" +#include #include #include @@ -40,6 +41,10 @@ const struct mod_sds_config sds_module_config = { .regions = sds_regions, .region_count = SCP_CFGD_MOD_SDS_REGION_IDX_COUNT, .clock_id = FWK_ID_NONE_INIT, + .platform_notification = { + .notification_id = mod_scp_platform_notification_subsys_init, + .source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCP_PLATFORM), + }, }; static struct fwk_element sds_element_table[] = { diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c b/product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c index f95be4ff9..15dc45925 100644 --- a/product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/config_transport.c @@ -13,6 +13,7 @@ #include "scp_fw_mmap.h" #include +#include #include #include @@ -26,12 +27,6 @@ #define TRANSPORT_CH_SEC_MBX_INIT \ (MOD_TRANSPORT_POLICY_INIT_MAILBOX | MOD_TRANSPORT_POLICY_SECURE) -/* Subsystem initialized notification id (platform notification) */ -#define PLATFORM_SCP_NOTIFICATION_ID \ - FWK_ID_NOTIFICATION_INIT( \ - FWK_MODULE_IDX_SCP_PLATFORM, \ - MOD_SCP_PLATFORM_NOTIFICATION_IDX_SUBSYS_INITIALIZED) - /* Module 'transport' element configuration table */ static const struct fwk_element element_table[] = { /* @@ -57,6 +52,11 @@ static const struct fwk_element element_table[] = { FWK_ID_API_INIT( FWK_MODULE_IDX_MHU3, MOD_MHU3_API_IDX_TRANSPORT_DRIVER), + .platform_notification = { + .notification_id = mod_scp_platform_notification_subsys_init, + .source_id = FWK_ID_MODULE_INIT( + FWK_MODULE_IDX_SCP_PLATFORM), + }, }), }, /* -- GitLab From 35281ef84edca1df86f765d32a5daf0acf336c47 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 27 Jun 2024 11:52:02 +0530 Subject: [PATCH 34/50] rdv3r1: add build support for scp firmware Add linker script and cmake files to enable building of SCP runtime firmware for rdv3r1 platform. Signed-off-by: Nancy . Change-Id: Ie75af346882585fb32c75ca0577c709aee105830 --- .../rdv3r1/scp_ramfw/CMakeLists.txt | 60 +++++++++++++++++ .../rdv3r1/scp_ramfw/Firmware.cmake | 65 +++++++++++++++++++ .../rdv3r1/scp_ramfw/Toolchain-ArmClang.cmake | 17 +++++ .../rdv3r1/scp_ramfw/Toolchain-Clang.cmake | 17 +++++ .../rdv3r1/scp_ramfw/Toolchain-GNU.cmake | 18 +++++ .../rdv3r1/scp_ramfw/include/fmw_memory.h | 30 +++++++++ .../scp_ramfw/include/fmw_notification.h | 16 +++++ 7 files changed, 223 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/CMakeLists.txt create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/Firmware.cmake create mode 100755 product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-ArmClang.cmake create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-Clang.cmake create mode 100755 product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-GNU.cmake create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_memory.h create mode 100644 product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_notification.h diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/CMakeLists.txt b/product/neoverse-rd/rdv3r1/scp_ramfw/CMakeLists.txt new file mode 100644 index 000000000..b278c71bd --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/CMakeLists.txt @@ -0,0 +1,60 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cmake-lint: disable=E1122 + +# +# Create the firmware target. +# +add_executable(rdv3r1-bl2) + +target_include_directories( + rdv3r1-bl2 + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include" + "${CMAKE_CURRENT_SOURCE_DIR}/../include" + "${CMAKE_CURRENT_SOURCE_DIR}/../../common/include") + +target_sources( + rdv3r1-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_system_power.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_armv7m_mpu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_atu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_power_domain.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_ppu_v1.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_mhu3.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_transport.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_sds.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_timer.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_gtimer.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_system_power.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_cmn_cyprus.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_apcontext.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_power_domain.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_system_info.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scp_platform.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_system_pik.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_sid.c") + +# +# Some of our firmware includes require CMSIS. +# + +target_link_libraries(rdv3r1-bl2 PUBLIC cmsis::core-m) + +# +# We explicitly add the CMSIS include directories to our interfaceinclude +# directories. Each module target adds these include directories totheir own, +# allowing them to include any firmware includes we expose. +# + +target_include_directories( + rdv3r1-bl2 + PUBLIC $) diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/Firmware.cmake b/product/neoverse-rd/rdv3r1/scp_ramfw/Firmware.cmake new file mode 100644 index 000000000..b9693f293 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/Firmware.cmake @@ -0,0 +1,65 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Configure the build system. +# + +set(SCP_FIRMWARE "rdv3r1-bl2") + +set(SCP_FIRMWARE_TARGET "rdv3r1-bl2") + +set(SCP_TOOLCHAIN_INIT "GNU") + +set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +# Disable Interprocedural optimization +set(SCP_ENABLE_IPO_INIT FALSE) + +set(SCP_ARCHITECTURE "arm-m") + +set(SCP_ENABLE_NEWLIB_NANO FALSE) + +set(SCP_ENABLE_OUTBAND_MSG_SUPPORT TRUE) + +set(SCP_ENABLE_ATU_MANAGE TRUE) + +set(SCP_ENABLE_SCMI_NOTIFICATIONS TRUE) + +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/module/scp_platform" + "${CMAKE_CURRENT_LIST_DIR}/module/system_pik") + +# The order of the modules in the following list is the order in which the +# modules are initialized, bound, started during the pre-runtime phase. +# Any change in the order will cause firmware initialization errors. + +list(APPEND SCP_MODULES "armv7m-mpu") +list(APPEND SCP_MODULES "pl011") +list(APPEND SCP_MODULES "system-pik") +list(APPEND SCP_MODULES "sid") +list(APPEND SCP_MODULES "atu") +list(APPEND SCP_MODULES "ppu-v1") +list(APPEND SCP_MODULES "system-power") +list(APPEND SCP_MODULES "power-domain") +list(APPEND SCP_MODULES "pik-clock") +list(APPEND SCP_MODULES "clock") +list(APPEND SCP_MODULES "gtimer") +list(APPEND SCP_MODULES "timer") +list(APPEND SCP_MODULES "cmn-cyprus") +list(APPEND SCP_MODULES "mhu3") +list(APPEND SCP_MODULES "transport") +list(APPEND SCP_MODULES "pcid") +list(APPEND SCP_MODULES "system-info") +list(APPEND SCP_MODULES "apcontext") +list(APPEND SCP_MODULES "scmi") +list(APPEND SCP_MODULES "sds") +list(APPEND SCP_MODULES "scmi-power-domain") +list(APPEND SCP_MODULES "scmi-system-power") +list(APPEND SCP_MODULES "scp-platform") diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-ArmClang.cmake b/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-ArmClang.cmake new file mode 100755 index 000000000..2ab30d850 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-ArmClang.cmake @@ -0,0 +1,17 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/ArmClang-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-Clang.cmake b/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-Clang.cmake new file mode 100644 index 000000000..0d52f0281 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-Clang.cmake @@ -0,0 +1,17 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/Clang-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-GNU.cmake b/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-GNU.cmake new file mode 100755 index 000000000..62d475fac --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/Toolchain-GNU.cmake @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") + +set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_memory.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_memory.h new file mode 100644 index 000000000..33f456783 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_memory.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "scp_css_mmap.h" + +#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FMW_MEM0_SIZE SCP_ITC_RAM_SIZE +#define FMW_MEM0_BASE SCP_ITC_RAM_BASE + +/* + * RAM data memory + */ +#define FMW_MEM1_SIZE SCP_DTC_RAM_SIZE +#define FMW_MEM1_BASE SCP_DTC_RAM_BASE + +#endif /* FMW_MEMORY_H */ diff --git a/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_notification.h b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_notification.h new file mode 100644 index 000000000..3f1717c53 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/scp_ramfw/include/fmw_notification.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP RAM firmware notification configuration. + */ + +#ifndef FMW_NOTIFICATION_H +#define FMW_NOTIFICATION_H + +#define FMW_NOTIFICATION_MAX 128 + +#endif /* FMW_NOTIFICATION_H */ -- GitLab From e3f3aa6154432051e305ab1ef0b5daeaea2d38ad Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 28 Nov 2024 11:41:46 +0000 Subject: [PATCH 35/50] mod/gtimer: fix check of gtimer control register frame base address Check the correctness of gtimer control register frame base address specified in the module config data only if 'skip_cntcontrol_init' parameter in the module config data is set to false. Signed-off-by: Nancy . Change-Id: I6861ce4c2730e8739213dd27c5dc3fd999665970 --- module/gtimer/src/mod_gtimer.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/module/gtimer/src/mod_gtimer.c b/module/gtimer/src/mod_gtimer.c index 675b1af1e..928562299 100644 --- a/module/gtimer/src/mod_gtimer.c +++ b/module/gtimer/src/mod_gtimer.c @@ -213,12 +213,11 @@ static int gtimer_device_init(fwk_id_t element_id, unsigned int unused, ctx = mod_gtimer_ctx.table + fwk_id_get_element_idx(element_id); ctx->config = data; - if (ctx->config->hw_timer == 0 || - ctx->config->hw_counter == 0 || - ctx->config->control == 0 || - ctx->config->frequency < GTIMER_FREQUENCY_MIN_HZ || - ctx->config->frequency > GTIMER_FREQUENCY_MAX_HZ) { - + if ((ctx->config->hw_timer == 0 || ctx->config->hw_counter == 0 || + ctx->config->frequency < GTIMER_FREQUENCY_MIN_HZ || + ctx->config->frequency > GTIMER_FREQUENCY_MAX_HZ) || + ((ctx->config->skip_cntcontrol_init == 0) && + (ctx->config->control == 0))) { return FWK_E_DEVICE; } -- GitLab From f3692e7a150e4413e3215035401577d36d763f7b Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 11:49:42 +0530 Subject: [PATCH 36/50] rdv3r1: add config data for clock module in mcpfw The clock module config data is empty for mcp firmware since this module is required only to resolve build time dependencies across other modules Signed-off-by: Nancy . Change-Id: I8ed76a7c584acf88b898c6446ac6800b6b8e862a --- product/neoverse-rd/rdv3r1/mcp_ramfw/config_clock.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/config_clock.c diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/config_clock.c b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_clock.c new file mode 100644 index 000000000..fc7b39abb --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_clock.c @@ -0,0 +1,13 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'clock'. + */ + +#include + +const struct fwk_module_config config_clock = { 0 }; -- GitLab From 8ae00ade85c25a685431de549e1683597d39ac78 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 11:57:32 +0530 Subject: [PATCH 37/50] rdv3r1: add config data for pl011 UART module in mcpfw PL011 controller is used as a console port for debug and log messages. Add configuration data of this controller including base address and input clock frequency for the PL011 module to use. Signed-off-by: Nancy . Change-Id: I4e036afe06bb8441fd69e14fc1ea97d73ad7d6d3 --- .../rdv3r1/mcp_ramfw/config_pl011.c | 34 +++++++++++++++++++ .../rdv3r1/mcp_ramfw/include/mcp_css_mmap.h | 22 ++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/config_pl011.c create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/config_pl011.c b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_pl011.c new file mode 100644 index 000000000..355330192 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_pl011.c @@ -0,0 +1,34 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'pl011'. + */ + +#include "mcp_css_mmap.h" + +#include + +#include +#include +#include +#include + +struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS({ + [0] = { + .name = "mcp-uart", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = MCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + }, + }, + [1] = { 0 }, + }), +}; diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h new file mode 100644 index 000000000..7034759d3 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address definitions for the MCP's sub-system and access extending + * into the rest of the CSS. + */ + +#ifndef MCP_CSS_MMAP_H +#define MCP_CSS_MMAP_H + +// clang-format off + +/* SCP sub-system peripherals */ +#define MCP_UART_BASE (0x4C002000) + +// clang-format on + +#endif /* MCP_CSS_MMAP_H */ -- GitLab From 703072d2c7aa5e6b929dd45605ecefbf59b062e5 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 12:01:00 +0530 Subject: [PATCH 38/50] rdv3r1: configure I/O stream for mcpfw Configure the macros FMW_IO_STDIN_ID and FWM_IO_STDOUT_ID exposed by the I/O framework to set the MCP UART as the system entity responsible for handling I/O for the mcp firmware. Signed-off-by: Nancy . Change-Id: I595a06bd64db6f24b39f9ecc73c29929d048ffa1 --- .../rdv3r1/mcp_ramfw/include/fmw_io.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_io.h diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_io.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_io.h new file mode 100644 index 000000000..ec7f58908 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_io.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_IO_H +#define FMW_IO_H + +#include +#include + +#define FMW_IO_STDIN_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) +#define FMW_IO_STDOUT_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) + +#endif /* FMW_IO_H */ -- GitLab From cabb313a286b7600e46ffb860ba0f34fd9ce3c04 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 12:13:31 +0530 Subject: [PATCH 39/50] rdv3r1: add config data for MPU module in mcpfw Add config data for armv7m_mpu module in mcp ramfw. The ITC RAM and DTC RAM memory regions are specified. Signed-off-by: Nancy . Change-Id: I4085a89c7f1f936f7ea59d8d868648eb9d88f605 --- .../rdv3r1/mcp_ramfw/config_armv7m_mpu.c | 67 +++++++++++++++++++ .../rdv3r1/mcp_ramfw/include/mcp_css_mmap.h | 8 +++ 2 files changed, 75 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/config_armv7m_mpu.c diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/config_armv7m_mpu.c b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_armv7m_mpu.c new file mode 100644 index 000000000..9be6a7975 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_armv7m_mpu.c @@ -0,0 +1,67 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mcp_css_mmap.h" + +#include + +#include +#include + +#include + +/* Number of regions to be configured in MCP's MPU */ +#define MCP_MPU_REGION_COUNT 3 + +static const ARM_MPU_Region_t regions[MCP_MPU_REGION_COUNT] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 0, + 1, + 0, + ARM_MPU_REGION_SIZE_4GB), + }, + { + /* 0x0000_0000 - 0x0003_FFFF */ + .RBAR = ARM_MPU_RBAR(1, MCP_ITC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 0, + ARM_MPU_AP_PRO, + 0, + 0, + 1, + 0, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, + { + /* 0x2000_0000 - 2003_FFFF */ + .RBAR = ARM_MPU_RBAR(2, MCP_DTC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 0, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h index 7034759d3..07eae52d3 100644 --- a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h @@ -14,6 +14,14 @@ // clang-format off +/* Base address and size of MCP's ITCM */ +#define MCP_ITC_RAM_BASE (0x00000000) +#define MCP_ITC_RAM_SIZE (256 * 1024) + +/* Base address and size of MCP's DTCM */ +#define MCP_DTC_RAM_BASE (0x20000000) +#define MCP_DTC_RAM_SIZE (256 * 1024) + /* SCP sub-system peripherals */ #define MCP_UART_BASE (0x4C002000) -- GitLab From b7b059f95019125e1d2afa50b12bd46d6819250d Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Wed, 27 Nov 2024 22:07:41 +0000 Subject: [PATCH 40/50] rdv3r1: add initial M7 definitions for MCP sub-system Add Cortex-M7 processor capability definitions and initial IRQ number definitions for the MCP sub-system. Signed-off-by: Nancy . Change-Id: I5c6d5eb7e19cf23c5d356b3fecc17fd4145df3f4 --- .../rdv3r1/mcp_ramfw/include/fmw_cmsis.h | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h new file mode 100644 index 000000000..af1cfe4a1 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h @@ -0,0 +1,43 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include + +#define __CHECK_DEVICE_DEFINES +#define __CM7_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U +#define __DTCM_PRESENT 1U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + +typedef enum IRQn { + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + IRQn_MAX = INT16_MAX, +} IRQn_Type; + +#include + +#endif /* FMW_CMSIS_H */ -- GitLab From 3fe6482ce069001ff4d7e8240cc2c07d6ebccb8d Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 12:32:20 +0530 Subject: [PATCH 41/50] rdv3r1: add generic timer module config data for mcpfw The configuration data for generic timer driver includes the base addresses of timer register, counter register and control register along with the initial frequency and the id of clock device on which the timer depends. However, the MCP does not configure the control register. Signed-off-by: Nancy . Change-Id: Id67623579d7c89e4e5c0ccf9185f6e48ce819034 --- .../rdv3r1/mcp_ramfw/config_gtimer.c | 47 +++++++++++++++++++ .../rdv3r1/mcp_ramfw/include/mcp_clock.h | 18 +++++++ .../rdv3r1/mcp_ramfw/include/mcp_css_mmap.h | 2 + 3 files changed, 67 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/config_gtimer.c create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_clock.h diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/config_gtimer.c b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_gtimer.c new file mode 100644 index 000000000..fac913083 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_gtimer.c @@ -0,0 +1,47 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'gtimer'. + */ + +#include "mcp_clock.h" +#include "mcp_css_mmap.h" + +#include + +#include +#include +#include +#include +#include + +/* + * Generic timer driver config + */ +static const struct fwk_element gtimer_dev_table[] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config) { + .hw_timer = MCP_REFCLK_CNTBASE0_BASE, + .hw_counter = MCP_REFCLK_CNTCTL_BASE, + .control = (uintptr_t)NULL, + .frequency = (CLOCK_RATE_REFCLK * SYSCNT_INCR), + .clock_id = FWK_ID_NONE_INIT, + .skip_cntcontrol_init = true, + }), + }, + [1] = { 0 }, +}; + +const struct fwk_module_config config_gtimer = { + .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(gtimer_dev_table), +}; + +struct fwk_time_driver fmw_time_driver(const void **ctx) +{ + return mod_gtimer_driver(ctx, config_gtimer.elements.table[0].data); +} diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_clock.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_clock.h new file mode 100644 index 000000000..81a81992e --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_clock.h @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MCP clock definitions. + */ + +#ifndef MCP_CLOCK_H +#define MCP_CLOCK_H + +#include "css_common.h" + +#include + +#endif /* MCP_CLOCK_H */ diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h index 07eae52d3..7664bb237 100644 --- a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_css_mmap.h @@ -23,6 +23,8 @@ #define MCP_DTC_RAM_SIZE (256 * 1024) /* SCP sub-system peripherals */ +#define MCP_REFCLK_CNTCTL_BASE (0x4C000000) +#define MCP_REFCLK_CNTBASE0_BASE (0x4C001000) #define MCP_UART_BASE (0x4C002000) // clang-format on -- GitLab From 04a607a605ce3ef467913ebad185aafc2e7d79d6 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 13:55:08 +0530 Subject: [PATCH 42/50] rdv3r1: add config data for timer HAL in mcpfw Provide the configuration data for timer HAL which includes the id for the timer element and the IRQ number. Signed-off-by: Nancy . Change-Id: I80861f8bb7cef25fcb74c1831da5fc59a0a33f5d --- .../rdv3r1/mcp_ramfw/config_timer.c | 48 +++++++++++++++++++ .../rdv3r1/mcp_ramfw/include/fmw_cmsis.h | 2 + .../rdv3r1/mcp_ramfw/include/mcp_cfgd_timer.h | 19 ++++++++ 3 files changed, 69 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/config_timer.c create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_cfgd_timer.h diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/config_timer.c b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_timer.c new file mode 100644 index 000000000..6af6214d7 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/config_timer.c @@ -0,0 +1,48 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'timer'. + */ + +#include "mcp_cfgd_timer.h" + +#include + +#include +#include +#include +#include + +#include + +/* Module 'timer' element count */ +#define MOD_TIMER_ELEMENT_COUNT 2 + +/* + * Timer HAL config + */ +static const struct fwk_element timer_dev_table[MOD_TIMER_ELEMENT_COUNT] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config) { + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = REFCLK_GTIMER_IRQ, + }), + .sub_element_count = + MCP_CFGD_MOD_TIMER_SEIDX_ALARM_COUNT, /* Number of alarms */ + }, + [1] = { 0 }, +}; + +static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) +{ + return timer_dev_table; +} + +const struct fwk_module_config config_timer = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(timer_get_dev_table), +}; diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h index af1cfe4a1..6eb5f3b68 100644 --- a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_cmsis.h @@ -35,6 +35,8 @@ typedef enum IRQn { PendSV_IRQn = -2, SysTick_IRQn = -1, + REFCLK_GTIMER_IRQ = 34, /* MCP REFCLK Physical Timer interrupt */ + IRQn_MAX = INT16_MAX, } IRQn_Type; diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_cfgd_timer.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_cfgd_timer.h new file mode 100644 index 000000000..9ae1c9452 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/mcp_cfgd_timer.h @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for timer module configuration data in MCP firmware. + */ + +#ifndef MCP_CFGD_TIMER_H +#define MCP_CFGD_TIMER_H + +/* Sub-element indexes (alarms) for MCP timer device */ +enum mcp_cfgd_mod_timer_subelement_idx { + MCP_CFGD_MOD_TIMER_SEIDX_ALARM_COUNT, +}; + +#endif /* MCP_CFGD_TIMER_H */ -- GitLab From db5b868b9a6de812deb6d6652b9ad87e8492fbab Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 15:26:03 +0530 Subject: [PATCH 43/50] rdv3r1: add platform module for mcpfw Add an initial implementation of the MCP platform module that indicates the completion of the MCP RAM boot stage. This module is expected to get additional functionality in subsequent additions to the MCP RAM firmware. Signed-off-by: Nancy . Signed-off-by: Lokesh B V Change-Id: I32a29d406e2022e91679f3eccd809ad5daaad4be --- .../rdv3r1/module/mcp_platform/CMakeLists.txt | 10 +++++ .../rdv3r1/module/mcp_platform/Module.cmake | 10 +++++ .../mcp_platform/src/mod_mcp_platform.c | 38 +++++++++++++++++++ 3 files changed, 58 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/module/mcp_platform/CMakeLists.txt create mode 100644 product/neoverse-rd/rdv3r1/module/mcp_platform/Module.cmake create mode 100644 product/neoverse-rd/rdv3r1/module/mcp_platform/src/mod_mcp_platform.c diff --git a/product/neoverse-rd/rdv3r1/module/mcp_platform/CMakeLists.txt b/product/neoverse-rd/rdv3r1/module/mcp_platform/CMakeLists.txt new file mode 100644 index 000000000..0b2153c8d --- /dev/null +++ b/product/neoverse-rd/rdv3r1/module/mcp_platform/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_mcp_platform.c") diff --git a/product/neoverse-rd/rdv3r1/module/mcp_platform/Module.cmake b/product/neoverse-rd/rdv3r1/module/mcp_platform/Module.cmake new file mode 100644 index 000000000..e7a5ba500 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/module/mcp_platform/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "mcp-platform") + +set(SCP_MODULE_TARGET "module-mcp-platform") diff --git a/product/neoverse-rd/rdv3r1/module/mcp_platform/src/mod_mcp_platform.c b/product/neoverse-rd/rdv3r1/module/mcp_platform/src/mod_mcp_platform.c new file mode 100644 index 000000000..ff784db20 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/module/mcp_platform/src/mod_mcp_platform.c @@ -0,0 +1,38 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#define MOD_NAME "[MCP_PLATFORM] " + +/* + * Framework handlers. + */ +static int mod_mcp_platform_init( + fwk_id_t module_id, + unsigned int element_count, + const void *unused) +{ + return FWK_SUCCESS; +} + +static int mod_mcp_platform_start(fwk_id_t id) +{ + FWK_LOG_INFO(MOD_NAME "MCP RAM firmware initialized"); + return FWK_SUCCESS; +} + +const struct fwk_module module_mcp_platform = { + .type = FWK_MODULE_TYPE_SERVICE, + .init = mod_mcp_platform_init, + .start = mod_mcp_platform_start, +}; + +const struct fwk_module_config config_mcp_platform = { 0 }; -- GitLab From f947a318c537dd0d1a313f4f0cdf2f61dadcf8b5 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Tue, 24 Sep 2024 15:42:52 +0530 Subject: [PATCH 44/50] rdv3r1: add build support for mcp firmware Add linker script and cmake files to enable building of MCP runtime firmware for RD-V3-R1 platform. Signed-off-by: Nancy . Signed-off-by: Lokesh B V Change-Id: Iec87a10e0d310cc91665aa1760c59eac1e93a8ae --- .../rdv3r1/mcp_ramfw/CMakeLists.txt | 43 +++++++++++++++++++ .../rdv3r1/mcp_ramfw/Firmware.cmake | 41 ++++++++++++++++++ .../rdv3r1/mcp_ramfw/Toolchain-ArmClang.cmake | 19 ++++++++ .../rdv3r1/mcp_ramfw/Toolchain-Clang.cmake | 17 ++++++++ .../rdv3r1/mcp_ramfw/Toolchain-GNU.cmake | 18 ++++++++ .../rdv3r1/mcp_ramfw/include/fmw_log.h | 13 ++++++ .../rdv3r1/mcp_ramfw/include/fmw_memory.h | 30 +++++++++++++ .../mcp_ramfw/include/fmw_notification.h | 16 +++++++ 8 files changed, 197 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/CMakeLists.txt create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/Firmware.cmake create mode 100755 product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-ArmClang.cmake create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-Clang.cmake create mode 100755 product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-GNU.cmake create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_log.h create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_memory.h create mode 100644 product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_notification.h diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/CMakeLists.txt b/product/neoverse-rd/rdv3r1/mcp_ramfw/CMakeLists.txt new file mode 100644 index 000000000..ba2d5975b --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/CMakeLists.txt @@ -0,0 +1,43 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Create the firmware target. +# +add_executable(rdv3r1-mcp-bl2) + +target_include_directories( + rdv3r1-mcp-bl2 + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include" + "${CMAKE_CURRENT_SOURCE_DIR}/../../common/include" + "${CMAKE_CURRENT_SOURCE_DIR}/../include") + +# cmake-lint: disable=E1122 + +target_sources( + rdv3r1-mcp-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv7m_mpu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_timer.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_gtimer.c") + +# +# Some of our firmware includes require CMSIS. +# + +target_link_libraries(rdv3r1-mcp-bl2 PUBLIC cmsis::core-m) + +# +# We explicitly add the CMSIS include directories to our interface include +# directories. Each module target adds these include directories to their own, +# allowing them to include any firmware includes we expose. +# + +target_include_directories( + rdv3r1-mcp-bl2 + PUBLIC $) diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/Firmware.cmake b/product/neoverse-rd/rdv3r1/mcp_ramfw/Firmware.cmake new file mode 100644 index 000000000..efceadbfc --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/Firmware.cmake @@ -0,0 +1,41 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Configure the build system. +# + +set(SCP_FIRMWARE "rdv3r1-mcp-bl2") + +set(SCP_ENABLE_NEWLIB_NANO FALSE) + +set(SCP_FIRMWARE_TARGET "rdv3r1-mcp-bl2") + +set(SCP_TOOLCHAIN_INIT "GNU") + +set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +# Disable Interprocedural optimization +set(SCP_ENABLE_IPO_INIT FALSE) + +set(SCP_ARCHITECTURE "arm-m") + +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/mcp_platform") + +# The order of the modules in the following list is the order in which the +# modules are initialized, bound, started during the pre-runtime phase. +# Any change in the order will cause firmware initialization errors. + +list(APPEND SCP_MODULES "armv7m-mpu") +list(APPEND SCP_MODULES "pl011") +list(APPEND SCP_MODULES "clock") +list(APPEND SCP_MODULES "timer") +list(APPEND SCP_MODULES "gtimer") +list(APPEND SCP_MODULES "mcp-platform") diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-ArmClang.cmake b/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-ArmClang.cmake new file mode 100755 index 000000000..c8fedcad5 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-ArmClang.cmake @@ -0,0 +1,19 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cmake-lint: disable=C0301 + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/ArmClang-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-Clang.cmake b/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-Clang.cmake new file mode 100644 index 000000000..0d52f0281 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-Clang.cmake @@ -0,0 +1,17 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/Clang-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-GNU.cmake b/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-GNU.cmake new file mode 100755 index 000000000..62d475fac --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/Toolchain-GNU.cmake @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m7") +set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") + +set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_log.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_log.h new file mode 100644 index 000000000..3216309f6 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_log.h @@ -0,0 +1,13 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_LOG_H +#define FMW_LOG_H + +#include + +#endif /* FMW_LOG_H */ diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_memory.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_memory.h new file mode 100644 index 000000000..6db21bd16 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_memory.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "mcp_css_mmap.h" + +#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FMW_MEM0_SIZE MCP_ITC_RAM_SIZE +#define FMW_MEM0_BASE MCP_ITC_RAM_BASE + +/* + * RAM data memory + */ +#define FMW_MEM1_SIZE MCP_DTC_RAM_SIZE +#define FMW_MEM1_BASE MCP_DTC_RAM_BASE + +#endif /* FMW_MEMORY_H */ diff --git a/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_notification.h b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_notification.h new file mode 100644 index 000000000..297d77220 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/mcp_ramfw/include/fmw_notification.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware notification configuration. + */ + +#ifndef FMW_NOTIFICATION_H +#define FMW_NOTIFICATION_H + +#define FMW_NOTIFICATION_MAX 128 + +#endif /* FMW_NOTIFICATION_H */ -- GitLab From e851864be7c958c55d5bc63f8f09d74a40a6d625 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 21 Nov 2024 14:24:04 +0530 Subject: [PATCH 45/50] rdv3r1: add config data for pl011 UART module in lcpfw PL011 controller is used as a console port for debug and log messages. Add configuration data of this controller including base address and input clock frequency for the PL011 module to use. Signed-off-by: Nancy . Signed-off-by: Shriram K Change-Id: I13707d9aa2393620c69cc352dbd8646309689e6c --- .../rdv3r1/lcp_ramfw/config_pl011.c | 31 +++++++++++++++++++ .../rdv3r1/lcp_ramfw/include/lcp_css_mmap.h | 23 ++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/config_pl011.c create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/config_pl011.c b/product/neoverse-rd/rdv3r1/lcp_ramfw/config_pl011.c new file mode 100644 index 000000000..9a4298478 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/config_pl011.c @@ -0,0 +1,31 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "lcp_css_mmap.h" + +#include + +#include +#include +#include +#include + +struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS({ + [0] = { + .name = "lcp-uart", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = LCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + }, + }, + + [1] = { 0 }, + }), +}; diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h new file mode 100644 index 000000000..ed491259f --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h @@ -0,0 +1,23 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address definitions for the LCP's sub-system. + */ + +#ifndef LCP_CSS_MMAP_H +#define LCP_CSS_MMAP_H + +#include + +// clang-format off + +/* LCP sub-system peripherals */ +#define LCP_UART_BASE (0xB5080000) + +// clang-format on + +#endif /* LCP_CSS_MMAP_H */ -- GitLab From 4b56ca3539c6808d5f4f5ff355b1fc3e71de11fc Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 21 Nov 2024 14:26:46 +0530 Subject: [PATCH 46/50] rdv3r1: configure I/O stream for lcpfw Configure the macros FMW_IO_STDIN_ID and FWM_IO_STDOUT_ID exposed by the I/O framework to set the LCP UART as the system entity responsible for handling I/O for the mcp firmware. Signed-off-by: Shriram K Signed-off-by: Nancy . Change-Id: I8316a40d50cd89b7d861f86db5d7aa5641401952 --- .../rdv3r1/lcp_ramfw/include/fmw_io.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_io.h diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_io.h b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_io.h new file mode 100644 index 000000000..ec7f58908 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_io.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_IO_H +#define FMW_IO_H + +#include +#include + +#define FMW_IO_STDIN_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) +#define FMW_IO_STDOUT_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) + +#endif /* FMW_IO_H */ -- GitLab From 462033358d612d03a0b7f6d4de835da26c1ad74e Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Fri, 29 Nov 2024 13:55:46 +0000 Subject: [PATCH 47/50] rdv3r1: add initial M7 definitions for LCP sub-system Add Cortex-M55 processor capability definitions and initial IRQ number definitions for the LCP sub-system. Signed-off-by: Nancy . Change-Id: I696cfd45e941d69908216d1d1065587fe6d1356c --- .../rdv3r1/lcp_ramfw/include/fmw_cmsis.h | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_cmsis.h diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_cmsis.h b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_cmsis.h new file mode 100644 index 000000000..365a3d783 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_cmsis.h @@ -0,0 +1,51 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include + +#define __CHECK_DEVICE_DEFINES +#define __CM55_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __VTOR_PRESENT 1U +#define __PMU_PRESENT 0U +#define __DSP_PRESENT 0U +#define __ICACHE_PRESENT 0U +#define __DCACHE_PRESENT 0U +#define __DTCM_PRESENT 0U +#define __NVIC_PRIO_BITS 3U +#define __SAUREGION_PRESENT 0U +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + WDG_RST_RQST_IRQ = 0, /* Watchdog reset request */ + WDG_INT_IRQ = 1, /* Watchdog interrupt */ + TIMER_IRQ = 2, /* Timer */ + + IRQn_MAX = INT16_MAX, +} IRQn_Type; + +#include + +extern uint32_t SystemCoreClock; + +#endif /* FMW_CMSIS_H */ -- GitLab From eeae14ee9577a1a4ea9971fb822a73d9236beb44 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 21 Nov 2024 14:38:38 +0530 Subject: [PATCH 48/50] rdv3r1: add config data for MPU module in lcpfw Add config data for armv8m_mpu module in lcpfw. The ITC RAM and DTC RAM, SRAM and peripheral memory regions are specified. Signed-off-by: Shriram K Signed-off-by: Nancy . Change-Id: I8e04f70c4c4bd6d5b7c612645c1a6d7b2de1d5d8 --- .../rdv3r1/lcp_ramfw/config_armv8m_mpu.c | 86 +++++++++++++++++++ .../rdv3r1/lcp_ramfw/include/lcp_css_mmap.h | 21 +++++ 2 files changed, 107 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/config_armv8m_mpu.c diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/config_armv8m_mpu.c b/product/neoverse-rd/rdv3r1/lcp_ramfw/config_armv8m_mpu.c new file mode 100644 index 000000000..19baa390f --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/config_armv8m_mpu.c @@ -0,0 +1,86 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "lcp_css_mmap.h" +#include "mod_armv8m_mpu.h" + +#include +#include + +#include + +static const uint8_t attributes[] = { + /* Device memory, non Gathering, non Re-ordering, non Early Write + Acknowledgement */ + [MPU_ATTR_0] = + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE), + /* Normal memory, non Cacheable */ + [MPU_ATTR_1] = + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE), +}; + +static const ARM_MPU_Region_t regions[] = { + { + /* LCP_CORE_TCM_REGION*/ + .RBAR = ARM_MPU_RBAR( + LCP_CORE_ITCM_REGION_START, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 0 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_CORE_ITCM_REGION_END, MPU_ATTR_1), + }, + { + /* LCP_CORE_DTCM_REGION*/ + .RBAR = ARM_MPU_RBAR( + LCP_CORE_DTCM_REGION_START, /* BASE */ + ARM_MPU_SH_INNER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_CORE_DTCM_REGION_END, MPU_ATTR_1), + }, + { + /* LCP_CORE_PERIPERAL_REGION */ + .RBAR = ARM_MPU_RBAR( + LCP_CORE_PERIPHERAL_REGION_START, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_CORE_PERIPHERAL_REGION_END, MPU_ATTR_0), + }, + { + /* LCP_SRAM_REGION*/ + .RBAR = ARM_MPU_RBAR( + LCP_SRAM_REGION_START, /* BASE */ + ARM_MPU_SH_OUTER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_SRAM_REGION_END, MPU_ATTR_1), + }, + { + /* LCP_DEVICE_REGION */ + .RBAR = ARM_MPU_RBAR( + LCP_DEVICE_REGION_START, /* BASE */ + ARM_MPU_SH_OUTER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(LCP_DEVICE_REGION_END, MPU_ATTR_0), + }, +}; + +const struct fwk_module_config config_armv8m_mpu = { + .data = &((struct mod_armv8m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + .attributes_count = FWK_ARRAY_SIZE(attributes), + .attributes = attributes, + }), +}; diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h index ed491259f..cd120b9ea 100644 --- a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/lcp_css_mmap.h @@ -15,6 +15,27 @@ // clang-format off +#define LCP_ITCM_S_BASE (0x10000000) +#define LCP_ITCM_SIZE (64 * 1024) + +#define LCP_DTCM_S_BASE (0x30000000) +#define LCP_DTCM_SIZE (32 * 1024) + +#define LCP_CORE_ITCM_REGION_START LCP_ITCM_S_BASE +#define LCP_CORE_ITCM_REGION_END (LCP_ITCM_S_BASE + LCP_ITCM_SIZE - 1) + +#define LCP_CORE_DTCM_REGION_START LCP_DTCM_S_BASE +#define LCP_CORE_DTCM_REGION_END (LCP_DTCM_S_BASE + LCP_DTCM_SIZE - 1) + +#define LCP_CORE_PERIPHERAL_REGION_START (0x30010000) +#define LCP_CORE_PERIPHERAL_REGION_END (0x6FFFFFFF) + +#define LCP_SRAM_REGION_START (0x70000000) +#define LCP_SRAM_REGION_END (0xB007FFFF) + +#define LCP_DEVICE_REGION_START (0xB0080000) +#define LCP_DEVICE_REGION_END (0xFFFFFFFF) + /* LCP sub-system peripherals */ #define LCP_UART_BASE (0xB5080000) -- GitLab From 0c141087d16bd47f0ec3331a27a88053288d55f7 Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 21 Nov 2024 14:44:08 +0530 Subject: [PATCH 49/50] rdv3r1: add platform module for lcpfw Add an initial implementation of the LCP platform module that indicates the completion of the LCP RAM boot stage. This module is expected to get additional functionality in subsequent additions to the LCP RAM firmware. Signed-off-by: Shriram K Signed-off-by: Nancy . Change-Id: I5ba37189ba7e5d8c9aaf6928f9e2312e5072e44f --- .../rdv3r1/module/lcp_platform/CMakeLists.txt | 11 ++++++ .../rdv3r1/module/lcp_platform/Module.cmake | 10 +++++ .../lcp_platform/src/mod_lcp_platform.c | 39 +++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/module/lcp_platform/CMakeLists.txt create mode 100644 product/neoverse-rd/rdv3r1/module/lcp_platform/Module.cmake create mode 100644 product/neoverse-rd/rdv3r1/module/lcp_platform/src/mod_lcp_platform.c diff --git a/product/neoverse-rd/rdv3r1/module/lcp_platform/CMakeLists.txt b/product/neoverse-rd/rdv3r1/module/lcp_platform/CMakeLists.txt new file mode 100644 index 000000000..9b03a67c5 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/module/lcp_platform/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_lcp_platform.c") diff --git a/product/neoverse-rd/rdv3r1/module/lcp_platform/Module.cmake b/product/neoverse-rd/rdv3r1/module/lcp_platform/Module.cmake new file mode 100644 index 000000000..91ff0e233 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/module/lcp_platform/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "lcp-platform") + +set(SCP_MODULE_TARGET "module-lcp-platform") diff --git a/product/neoverse-rd/rdv3r1/module/lcp_platform/src/mod_lcp_platform.c b/product/neoverse-rd/rdv3r1/module/lcp_platform/src/mod_lcp_platform.c new file mode 100644 index 000000000..7ffe48664 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/module/lcp_platform/src/mod_lcp_platform.c @@ -0,0 +1,39 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#define MOD_NAME "[LCP_PLATFORM] " + +/* + * Framework handlers. + */ +static int mod_lcp_platform_init( + fwk_id_t module_id, + unsigned int element_count, + const void *unused) +{ + return FWK_SUCCESS; +} + +static int mod_lcp_platform_start(fwk_id_t id) +{ + FWK_LOG_INFO(MOD_NAME "LCP RAM firmware initialized"); + return FWK_SUCCESS; +} + +const struct fwk_module module_lcp_platform = { + .type = FWK_MODULE_TYPE_SERVICE, + .init = mod_lcp_platform_init, + .start = mod_lcp_platform_start, +}; + +const struct fwk_module_config config_lcp_platform = { 0 }; -- GitLab From 920bc63480abc3144fe47575688c4533f7dcfbfd Mon Sep 17 00:00:00 2001 From: "Nancy ." Date: Thu, 21 Nov 2024 14:47:59 +0530 Subject: [PATCH 50/50] rdv3r1: add build support for lcp firmware Add linker script and cmake files to enable building of LCP runtime firmware for RD-V3-R1 platform. Signed-off-by: Pranav Madhu Signed-off-by: Shriram K Signed-off-by: Nancy . Change-Id: I493dc6c5ed55dfd4d2a66b3859202bdd93987958 --- .../rdv3r1/lcp_ramfw/CMakeLists.txt | 38 +++++++++++++++++++ .../rdv3r1/lcp_ramfw/Firmware.cmake | 37 ++++++++++++++++++ .../rdv3r1/lcp_ramfw/Toolchain-ArmClang.cmake | 20 ++++++++++ .../rdv3r1/lcp_ramfw/Toolchain-Clang.cmake | 17 +++++++++ .../rdv3r1/lcp_ramfw/Toolchain-GNU.cmake | 18 +++++++++ .../rdv3r1/lcp_ramfw/include/fmw_log.h | 25 ++++++++++++ .../rdv3r1/lcp_ramfw/include/fmw_memory.h | 30 +++++++++++++++ .../lcp_ramfw/include/fmw_notification.h | 16 ++++++++ 8 files changed, 201 insertions(+) create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/CMakeLists.txt create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/Firmware.cmake create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-ArmClang.cmake create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-Clang.cmake create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-GNU.cmake create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_log.h create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_memory.h create mode 100644 product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_notification.h diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/CMakeLists.txt b/product/neoverse-rd/rdv3r1/lcp_ramfw/CMakeLists.txt new file mode 100644 index 000000000..4fa7d3d0f --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/CMakeLists.txt @@ -0,0 +1,38 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Create the firmware target. +# + +add_executable(rdv3r1-lcp-bl2) + +target_include_directories( + rdv3r1-lcp-bl2 PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}" + "${CMAKE_CURRENT_SOURCE_DIR}/include") + +# cmake-lint: disable=E1122 + +target_sources( + rdv3r1-lcp-bl2 + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_armv8m_mpu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c") + +# +# Some of our firmware includes require CMSIS. +# + +target_link_libraries(rdv3r1-lcp-bl2 PUBLIC cmsis::core-m) + +# +# We explicitly add the CMSIS include directories to our interface include +# directories. Each module target adds these include directories to their own, +# allowing them to include any firmware includes we expose. +# + +target_include_directories(rdv3r1-lcp-bl2 + PUBLIC $) diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/Firmware.cmake b/product/neoverse-rd/rdv3r1/lcp_ramfw/Firmware.cmake new file mode 100644 index 000000000..e53d0c10e --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/Firmware.cmake @@ -0,0 +1,37 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Configure the build system. +# + +set(SCP_FIRMWARE "rdv3r1-lcp-bl2") + +set(SCP_FIRMWARE_TARGET "rdv3r1-lcp-bl2") + +set(SCP_TOOLCHAIN_INIT "GNU") + +set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +set(SCP_ENABLE_IPO_INIT FALSE) + +set(SCP_ARCHITECTURE "arm-m") + +set(SCP_ENABLE_DEBUGGER_INIT FALSE) + +list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/lcp_platform") + +# The order of the modules in the following list is the order in which the +# modules are initialized, bound, started during the pre-runtime phase. +# any change in the order will cause firmware initialization errors. + +list(APPEND SCP_MODULES "armv8m-mpu") +list(APPEND SCP_MODULES "pl011") +list(APPEND SCP_MODULES "lcp-platform") diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-ArmClang.cmake b/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-ArmClang.cmake new file mode 100644 index 000000000..6b9101327 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-ArmClang.cmake @@ -0,0 +1,20 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cmake-lint: disable=C0301 + +include_guard() + +# No Helium, no FPU, No DSP features +set(CMAKE_SYSTEM_ARCH "armv8.1-m.main") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/ArmClang-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-Clang.cmake b/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-Clang.cmake new file mode 100644 index 000000000..257cb663f --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-Clang.cmake @@ -0,0 +1,17 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/Clang-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-GNU.cmake b/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-GNU.cmake new file mode 100644 index 000000000..661973a85 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/Toolchain-GNU.cmake @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m55+nodsp") +set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") + +set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") + +set(CMAKE_TOP_DIR "${CMAKE_CURRENT_LIST_DIR}/../../../..") +include("${CMAKE_TOP_DIR}/cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_log.h b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_log.h new file mode 100644 index 000000000..a99ada447 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_log.h @@ -0,0 +1,25 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware logs configuration. + */ + +#ifndef FMW_LOG_H +#define FMW_LOG_H + +/* Enable custom banner */ +#define FMW_LOG_CUSTOM_BANNER + +#define FMW_LOG_CUSTOM_BANNER_STRING \ + "" \ + " _ ___ ___ __ _ ", \ + "| | / __| _ \\___ / _(_)_ _ _ ____ __ ____ _ _ _ ___ ", \ + "| |_| (__| _/___| _| | '_| ' \\ V V / _` | '_/ -_)", \ + "|____\\___|_| |_| |_|_| |_|_|_\\_/\\_/\\__,_|_| \\___|", "", \ + BUILD_VERSION_DESCRIBE_STRING, "", + +#endif /* FMW_LOG_H */ diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_memory.h b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_memory.h new file mode 100644 index 000000000..779931bad --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_memory.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "lcp_css_mmap.h" + +#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FMW_MEM0_SIZE LCP_ITCM_SIZE +#define FMW_MEM0_BASE LCP_ITCM_S_BASE + +/* + * RAM data memory + */ +#define FMW_MEM1_SIZE LCP_DTCM_SIZE +#define FMW_MEM1_BASE LCP_DTCM_S_BASE + +#endif /* FMW_MEMORY_H */ diff --git a/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_notification.h b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_notification.h new file mode 100644 index 000000000..297d77220 --- /dev/null +++ b/product/neoverse-rd/rdv3r1/lcp_ramfw/include/fmw_notification.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware notification configuration. + */ + +#ifndef FMW_NOTIFICATION_H +#define FMW_NOTIFICATION_H + +#define FMW_NOTIFICATION_MAX 128 + +#endif /* FMW_NOTIFICATION_H */ -- GitLab