From 49696e4bd425b13c71c4d6716235eb6180051482 Mon Sep 17 00:00:00 2001 From: Noe Galea-Sevilla Date: Tue, 9 Jan 2024 10:26:19 +0000 Subject: [PATCH 01/13] totalcompute/tc4: Introduce TC24 * Add initial TC4 implementation based on TC3. * TC4 has a single-stage boot. This commit combines TC3 boot stages into a single one. * Add ATU platform support. * Set the primary cluster and core to be powered by power domain. This makes all the cores to be aligned, as all the other cores are powered by power domain as well. * Combine scp_boot and scp_runtime transport config files from TC3 into a single config file for TC4. * Combine scp_boot and scp_runtime mhu3 config files from TC3 into a single config file for TC4. * Add core/cluster macros. There is no need for these values to be determined via inline functions and indeed doing so prevents static initialisation. Co-developed-by: Boyan Karatotev Co-developed-by: Jackson Cooper-Driver Co-developed-by: Tintu Thomas Co-developed-by: Jing Han Signed-off-by: Noe Galea-Sevilla --- product/totalcompute/tc4/include/clock_soc.h | 101 +++++ .../tc4/include/config_power_domain.h | 28 ++ product/totalcompute/tc4/include/cpu_pik.h | 51 +++ product/totalcompute/tc4/include/dpu_pik.h | 48 ++ product/totalcompute/tc4/include/fmw_cmsis.h | 165 +++++++ .../tc4/include/plat_mod_tc_system.h | 18 + product/totalcompute/tc4/include/scp_mmap.h | 134 ++++++ product/totalcompute/tc4/include/tc4_atu.h | 57 +++ product/totalcompute/tc4/include/tc4_core.h | 17 + product/totalcompute/tc4/include/tc4_dvfs.h | 22 + .../totalcompute/tc4/include/tc4_mock_ppu.h | 20 + .../totalcompute/tc4/include/tc4_mock_psu.h | 22 + product/totalcompute/tc4/include/tc4_ppu_v1.h | 11 + product/totalcompute/tc4/include/tc4_psu.h | 22 + product/totalcompute/tc4/include/tc4_scmi.h | 92 ++++ product/totalcompute/tc4/include/tc4_timer.h | 22 + .../totalcompute/tc4/include/tc4_transport.h | 25 ++ product/totalcompute/tc4/include/tc_core.h | 17 + .../tc4/module/tc4_bl1/CMakeLists.txt | 18 + .../tc4/module/tc4_bl1/Module.cmake | 9 + .../tc4/module/tc4_bl1/include/mod_tc4_bl1.h | 73 +++ .../tc4/module/tc4_bl1/src/mod_tc4_bl1.c | 225 ++++++++++ .../tc4/module/tc4_power_model/CMakeLists.txt | 16 + .../tc4/module/tc4_power_model/Module.cmake | 10 + .../include/mod_tc4_power_model.h | 59 +++ .../tc4_power_model/src/mod_tc4_power_model.c | 92 ++++ product/totalcompute/tc4/product.mk | 9 + .../tc4/scp_css/Buildoptions.cmake | 22 + .../totalcompute/tc4/scp_css/CMakeLists.txt | 162 +++++++ .../totalcompute/tc4/scp_css/Firmware.cmake | 80 ++++ .../tc4/scp_css/Toolchain-ArmClang.cmake | 20 + .../tc4/scp_css/Toolchain-Clang.cmake | 17 + .../tc4/scp_css/Toolchain-GNU.cmake | 18 + .../tc4/scp_css/config_armv8m_mpu.c | 86 ++++ product/totalcompute/tc4/scp_css/config_atu.c | 101 +++++ .../totalcompute/tc4/scp_css/config_clock.c | 138 ++++++ .../tc4/scp_css/config_css_clock.c | 309 +++++++++++++ .../totalcompute/tc4/scp_css/config_dvfs.c | 255 +++++++++++ .../tc4/scp_css/config_fch_polled.c | 226 ++++++++++ .../totalcompute/tc4/scp_css/config_gtimer.c | 44 ++ .../totalcompute/tc4/scp_css/config_mhu3.c | 96 ++++ .../tc4/scp_css/config_mock_ppu.c | 52 +++ .../tc4/scp_css/config_mock_psu.c | 82 ++++ .../totalcompute/tc4/scp_css/config_mpmm.c | 296 +++++++++++++ .../tc4/scp_css/config_pik_clock.c | 267 +++++++++++ .../tc4/scp_css/config_power_domain.c | 125 ++++++ .../totalcompute/tc4/scp_css/config_ppu_v1.c | 133 ++++++ product/totalcompute/tc4/scp_css/config_psu.c | 70 +++ .../tc4/scp_css/config_reg_sensor.c | 49 ++ .../tc4/scp_css/config_resource_perms.c | 115 +++++ .../totalcompute/tc4/scp_css/config_scmi.c | 119 +++++ .../tc4/scp_css/config_scmi_perf.c | 123 +++++ product/totalcompute/tc4/scp_css/config_sds.c | 85 ++++ .../totalcompute/tc4/scp_css/config_sensor.c | 44 ++ .../tc4/scp_css/config_system_pll.c | 139 ++++++ .../tc4/scp_css/config_system_power.c | 76 ++++ .../totalcompute/tc4/scp_css/config_tc4_bl1.c | 26 ++ .../tc4/scp_css/config_tc4_power_model.c | 36 ++ .../tc4/scp_css/config_thermal_mgmt.c | 71 +++ .../totalcompute/tc4/scp_css/config_timer.c | 42 ++ .../tc4/scp_css/config_traffic_cop.c | 96 ++++ .../tc4/scp_css/config_transport.c | 419 ++++++++++++++++++ product/totalcompute/tc4/scp_css/fmw_memory.h | 22 + .../tc4/scp_css/fmw_notification.h | 16 + 64 files changed, 5460 insertions(+) create mode 100644 product/totalcompute/tc4/include/clock_soc.h create mode 100644 product/totalcompute/tc4/include/config_power_domain.h create mode 100644 product/totalcompute/tc4/include/cpu_pik.h create mode 100644 product/totalcompute/tc4/include/dpu_pik.h create mode 100644 product/totalcompute/tc4/include/fmw_cmsis.h create mode 100644 product/totalcompute/tc4/include/plat_mod_tc_system.h create mode 100644 product/totalcompute/tc4/include/scp_mmap.h create mode 100644 product/totalcompute/tc4/include/tc4_atu.h create mode 100644 product/totalcompute/tc4/include/tc4_core.h create mode 100644 product/totalcompute/tc4/include/tc4_dvfs.h create mode 100644 product/totalcompute/tc4/include/tc4_mock_ppu.h create mode 100644 product/totalcompute/tc4/include/tc4_mock_psu.h create mode 100644 product/totalcompute/tc4/include/tc4_ppu_v1.h create mode 100644 product/totalcompute/tc4/include/tc4_psu.h create mode 100644 product/totalcompute/tc4/include/tc4_scmi.h create mode 100644 product/totalcompute/tc4/include/tc4_timer.h create mode 100644 product/totalcompute/tc4/include/tc4_transport.h create mode 100644 product/totalcompute/tc4/include/tc_core.h create mode 100644 product/totalcompute/tc4/module/tc4_bl1/CMakeLists.txt create mode 100644 product/totalcompute/tc4/module/tc4_bl1/Module.cmake create mode 100644 product/totalcompute/tc4/module/tc4_bl1/include/mod_tc4_bl1.h create mode 100644 product/totalcompute/tc4/module/tc4_bl1/src/mod_tc4_bl1.c create mode 100644 product/totalcompute/tc4/module/tc4_power_model/CMakeLists.txt create mode 100644 product/totalcompute/tc4/module/tc4_power_model/Module.cmake create mode 100644 product/totalcompute/tc4/module/tc4_power_model/include/mod_tc4_power_model.h create mode 100644 product/totalcompute/tc4/module/tc4_power_model/src/mod_tc4_power_model.c create mode 100644 product/totalcompute/tc4/product.mk create mode 100644 product/totalcompute/tc4/scp_css/Buildoptions.cmake create mode 100644 product/totalcompute/tc4/scp_css/CMakeLists.txt create mode 100644 product/totalcompute/tc4/scp_css/Firmware.cmake create mode 100644 product/totalcompute/tc4/scp_css/Toolchain-ArmClang.cmake create mode 100644 product/totalcompute/tc4/scp_css/Toolchain-Clang.cmake create mode 100644 product/totalcompute/tc4/scp_css/Toolchain-GNU.cmake create mode 100644 product/totalcompute/tc4/scp_css/config_armv8m_mpu.c create mode 100644 product/totalcompute/tc4/scp_css/config_atu.c create mode 100644 product/totalcompute/tc4/scp_css/config_clock.c create mode 100644 product/totalcompute/tc4/scp_css/config_css_clock.c create mode 100644 product/totalcompute/tc4/scp_css/config_dvfs.c create mode 100644 product/totalcompute/tc4/scp_css/config_fch_polled.c create mode 100644 product/totalcompute/tc4/scp_css/config_gtimer.c create mode 100644 product/totalcompute/tc4/scp_css/config_mhu3.c create mode 100644 product/totalcompute/tc4/scp_css/config_mock_ppu.c create mode 100644 product/totalcompute/tc4/scp_css/config_mock_psu.c create mode 100644 product/totalcompute/tc4/scp_css/config_mpmm.c create mode 100644 product/totalcompute/tc4/scp_css/config_pik_clock.c create mode 100644 product/totalcompute/tc4/scp_css/config_power_domain.c create mode 100644 product/totalcompute/tc4/scp_css/config_ppu_v1.c create mode 100644 product/totalcompute/tc4/scp_css/config_psu.c create mode 100644 product/totalcompute/tc4/scp_css/config_reg_sensor.c create mode 100644 product/totalcompute/tc4/scp_css/config_resource_perms.c create mode 100644 product/totalcompute/tc4/scp_css/config_scmi.c create mode 100644 product/totalcompute/tc4/scp_css/config_scmi_perf.c create mode 100644 product/totalcompute/tc4/scp_css/config_sds.c create mode 100644 product/totalcompute/tc4/scp_css/config_sensor.c create mode 100644 product/totalcompute/tc4/scp_css/config_system_pll.c create mode 100644 product/totalcompute/tc4/scp_css/config_system_power.c create mode 100644 product/totalcompute/tc4/scp_css/config_tc4_bl1.c create mode 100644 product/totalcompute/tc4/scp_css/config_tc4_power_model.c create mode 100644 product/totalcompute/tc4/scp_css/config_thermal_mgmt.c create mode 100644 product/totalcompute/tc4/scp_css/config_timer.c create mode 100644 product/totalcompute/tc4/scp_css/config_traffic_cop.c create mode 100644 product/totalcompute/tc4/scp_css/config_transport.c create mode 100644 product/totalcompute/tc4/scp_css/fmw_memory.h create mode 100644 product/totalcompute/tc4/scp_css/fmw_notification.h diff --git a/product/totalcompute/tc4/include/clock_soc.h b/product/totalcompute/tc4/include/clock_soc.h new file mode 100644 index 000000000..fdf9868e8 --- /dev/null +++ b/product/totalcompute/tc4/include/clock_soc.h @@ -0,0 +1,101 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CLOCK_SOC_H +#define CLOCK_SOC_H + +#include + +#if !defined(PLAT_FVP) +# define CLOCK_RATE_GTCLK (1000UL * FWK_MHZ) +#else +# define CLOCK_RATE_GTCLK (125UL * FWK_MHZ) +#endif + +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) + +/* + * PLL clock indexes. + */ +enum clock_pll_idx { + CLOCK_PLL_IDX_CPU_NEVIS, + CLOCK_PLL_IDX_CPU_GELAS, + CLOCK_PLL_IDX_CPU_TRAVIS, + CLOCK_PLL_IDX_SYS, + CLOCK_PLL_IDX_DPU, + CLOCK_PLL_IDX_PIX0, + CLOCK_PLL_IDX_PIX1, + CLOCK_PLL_IDX_GPU, + CLOCK_PLL_IDX_COUNT +}; + +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CLOCK_PIK_IDX_CLUS0_CPU0, + CLOCK_PIK_IDX_CLUS0_CPU1, + CLOCK_PIK_IDX_CLUS0_CPU2, + CLOCK_PIK_IDX_CLUS0_CPU3, + CLOCK_PIK_IDX_CLUS0_CPU4, + CLOCK_PIK_IDX_CLUS0_CPU5, + CLOCK_PIK_IDX_CLUS0_CPU6, + CLOCK_PIK_IDX_CLUS0_CPU7, + CLOCK_PIK_IDX_GIC, + CLOCK_PIK_IDX_PCLKSCP, + CLOCK_PIK_IDX_SYSPERCLK, + CLOCK_PIK_IDX_UARTCLK, + CLOCK_PIK_IDX_DPU, + CLOCK_PIK_IDX_COUNT +}; + +/*! + * \brief Selectable clock sources for TC4 cluster clocks. + */ +enum mod_clusclock_source_tc4 { + /*! The clock is gated */ + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_GATED = 0x0, + /*! The clock source is set to the system reference clock */ + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_SYSREFCLK = 0x1, + /*! The clock source is set to a private cluster PLL */ + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0 = 0x2, + /*! The clock source is set to a private cluster PLL */ + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1 = 0x4, + /*! The clock source is set to a private cluster PLL */ + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2 = 0x8, + /*! The clock source is set to a private cluster PLL */ + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL3 = 0x10, + /*! Number of valid clock sources */ + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_MAX +}; + +/* + * CSS clock indexes. + */ +enum clock_css_idx { + CLOCK_CSS_IDX_CPU_GROUP_NEVIS, + CLOCK_CSS_IDX_CPU_GROUP_GELAS, + CLOCK_CSS_IDX_CPU_GROUP_TRAVIS, + CLOCK_CSS_IDX_DPU, + CLOCK_CSS_IDX_COUNT +}; + +/* + * Clock indexes. + */ +enum clock_idx { + CLOCK_IDX_CPU_GROUP_NEVIS, + CLOCK_IDX_CPU_GROUP_GELAS, + CLOCK_IDX_CPU_GROUP_TRAVIS, + CLOCK_IDX_DPU, + CLOCK_IDX_PIXEL_0, + CLOCK_IDX_PIXEL_1, + CLOCK_IDX_GPU, + CLOCK_IDX_COUNT +}; + +#endif /* CLOCK_SOC_H */ diff --git a/product/totalcompute/tc4/include/config_power_domain.h b/product/totalcompute/tc4/include/config_power_domain.h new file mode 100644 index 000000000..e9ba4dc02 --- /dev/null +++ b/product/totalcompute/tc4/include/config_power_domain.h @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_POWER_DOMAIN_H +#define CONFIG_POWER_DOMAIN_H + +#include + +/* + * Power domain indices for the statically defined domains used for: + * - Indexing the domains in the tc4_power_domain_static_element_table + * - Indexing the SYSTOP children in the power domain tree + * + * When calculating a power domain element index, use the formula: + * core_count + cluster_count + pd_static_dev_idx + */ +enum pd_static_dev_idx { + PD_STATIC_DEV_IDX_GPUTOP, + PD_STATIC_DEV_IDX_SYSTOP, + PD_STATIC_DEV_IDX_COUNT, + PD_STATIC_DEV_IDX_NONE = UINT32_MAX +}; + +#endif /* CONFIG_POWER_DOMAIN_H */ diff --git a/product/totalcompute/tc4/include/cpu_pik.h b/product/totalcompute/tc4/include/cpu_pik.h new file mode 100644 index 000000000..462063ca5 --- /dev/null +++ b/product/totalcompute/tc4/include/cpu_pik.h @@ -0,0 +1,51 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CPU_PIK_H +#define CPU_PIK_H + +#include "scp_mmap.h" + +#include + +#include + +#define MAX_PIK_SUPPORTED_CPUS 8 + +/*! + * \brief PE Static Configuration register definitions + */ +struct static_config_reg { + FWK_RW uint32_t STATIC_CONFIG; + FWK_RW uint32_t RVBARADDR_LW; + FWK_RW uint32_t RVBARADDR_UP; + uint32_t RESERVED; +}; + +/*! + * \brief AP cores clock control register definitions + */ +struct coreclk_reg { + FWK_RW uint32_t DIV; + FWK_RW uint32_t CTRL; + FWK_RW uint32_t MOD; + uint32_t RESERVED; +}; +/*! + * \brief CPU (v9) PIK register definitions + */ +struct pik_cpu_reg { + FWK_RW uint32_t CLUSTER_CONFIG; + uint8_t RESERVED0[0x100 - 0x4]; + struct static_config_reg STATIC_CONFIG[MAX_PIK_SUPPORTED_CPUS]; + uint8_t RESERVED1[0x900 - 0x1a0]; + struct coreclk_reg CORECLK[MAX_PIK_SUPPORTED_CPUS]; +}; + +#define CLUSTER_PIK_PTR ((struct pik_cpu_reg *)SCP_PIK_CLUSTER_BASE) + +#endif /* CPU_PIK_H */ diff --git a/product/totalcompute/tc4/include/dpu_pik.h b/product/totalcompute/tc4/include/dpu_pik.h new file mode 100644 index 000000000..5992fd0fa --- /dev/null +++ b/product/totalcompute/tc4/include/dpu_pik.h @@ -0,0 +1,48 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DPU_PIK_H +#define DPU_PIK_H + +#include "scp_mmap.h" + +#include + +#include + +/*! + * \brief DPU PIK register definitions + */ +struct pik_dpu_reg { + FWK_R uint8_t RESERVED0[0x830]; + FWK_RW uint32_t ACLKDP_CTRL; + FWK_RW uint32_t ACLKDP_DIV1; + FWK_RW uint32_t ACLKDP_DIV2; + uint8_t RESERVED1[0xA00 - 0x83C]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED2[0xFC0 - 0xA0C]; + FWK_RW uint32_t PCL_CONFIG; + uint8_t RESERVED3[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define DPU_PIK_PTR ((struct pik_dpu_reg *)SCP_PIK_DPU_BASE) + +#endif /* DPU_PIK_H */ diff --git a/product/totalcompute/tc4/include/fmw_cmsis.h b/product/totalcompute/tc4/include/fmw_cmsis.h new file mode 100644 index 000000000..03a55b7d1 --- /dev/null +++ b/product/totalcompute/tc4/include/fmw_cmsis.h @@ -0,0 +1,165 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include + +#define __CHECK_DEVICE_DEFINES +#define __CM85_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __VTOR_PRESENT 1U +#define __PMU_PRESENT 0U +#define __DSP_PRESENT 0U +#define __ICACHE_PRESENT 0U +#define __DCACHE_PRESENT 0U +#define __DTCM_PRESENT 0U +#define __NVIC_PRIO_BITS 3U +#define __SAUREGION_PRESENT 0U +#define __Vendor_SysTickConfig 0U + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + +typedef enum IRQn { + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + WDG_RST_RQST_IRQ = 0, /* Watchdog reset request */ + WDG_INT_IRQ = 1, /* Watchdog interrupt */ + SLOWCLK_TIMER_IRQ = 2, /* Slow clock timer */ + TIMER0_IRQ = 3, /* Timer 0 */ + TIMER1_IRQ = 4, /* Timer 1 */ + TIMER2_IRQ = 5, /* Timer 2 */ + RESERVED6_IRQ = 6, /* Reserved */ + RESERVED7_IRQ = 7, /* Reserved */ + RESERVED8_IRQ = 8, /* Reserved */ + MPC_COMBD_S_IRQ = 9, /* MPC Combined Secure */ + PPC_COMBD_S_IRQ = 10, /* PPC Combined Secure */ + MSC_COMBD_S_IRQ = 11, /* MSC Combined Secure */ + BRIDGE_ERR_COMBD_S_IRQ = 12, /* Bridge Error Combined Secure */ + RESERVED13_IRQ = 13, /* Reserved */ + PPU_COMBINED_IRQ = 14, /* PPU Combined */ + + SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ + + TIMER3_AON_IRQ = 27, /* Timer 3 AON */ + CPU0_CTI_IRQ0 = 28, /* CPU0 CTI IRQ0 */ + CPU0_CTI_IRQ1 = 29, /* CPU0 CTI IRQ1 */ + + TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + + SCP_AP_MHU0_SEND_IRQ = 88, /* MHU0 SCP AP Sender */ + AP_SCP_MHU0_REC_IRQ = 89, /* MHU0 AP SCP Receiver */ + SCP_AP_MHU1_SEND_IRQ = 90, /* MHU1 SCP AP Sender */ + AP_SCP_MHU1_REC_IRQ = 91, /* MHU1 AP SCP Receiver */ + SCP_AP_MHU2_SEND_IRQ = 92, /* MHU2 SCP AP Sender */ + AP_SCP_MHU2_REC_IRQ = 93, /* MHU2 AP SCP Receiver */ + SCP_AP_MHU3_SEND_IRQ = 94, /* MHU3 SCP AP Sender */ + AP_SCP_MHU3_REC_IRQ = 95, /* MHU3 AP SCP Receiver */ + SCP_AP_MHU4_SEND_IRQ = 96, /* MHU4 SCP AP Sender */ + AP_SCP_MHU4_REC_IRQ = 97, /* MHU4 AP SCP Receiver */ + SCP_AP_MHU5_SEND_IRQ = 98, /* MHU5 SCP AP Sender */ + AP_SCP_MHU5_REC_IRQ = 99, /* MHU5 AP SCP Receiver */ + SCP_AP_MHU6_SEND_IRQ = 100, /* MHU6 SCP AP Sender */ + AP_SCP_MHU6_REC_IRQ = 101, /* MHU6 AP SCP Receiver */ + + ATU_IRQ = 116, /* ATU IRQ */ + + CLUS_PPU_IRQ = 121, /* Cluster PPU */ + CORE0_PPU_IRQ = 122, /* Core0 PPU */ + CORE1_PPU_IRQ = 123, /* Core1 PPU */ + CORE2_PPU_IRQ = 124, /* Core2 PPU */ + CORE3_PPU_IRQ = 125, /* Core3 PPU */ + CORE4_PPU_IRQ = 126, /* Core4 PPU */ + CORE5_PPU_IRQ = 127, /* Core5 PPU */ + CORE6_PPU_IRQ = 128, /* Core6 PPU */ + CORE7_PPU_IRQ = 129, /* Core7 PPU */ + CORE8_PPU_IRQ = 130, /* Core8 PPU */ + CORE9_PPU_IRQ = 131, /* Core9 PPU */ + CORE10_PPU_IRQ = 132, /* Core10 PPU */ + CORE11_PPU_IRQ = 133, /* Core11 PPU */ + CORE12_PPU_IRQ = 134, /* Core12 PPU */ + CORE13_PPU_IRQ = 135, /* Core13 PPU */ + CORE14_PPU_IRQ = 136, /* Core14 PPU */ + CORE15_PPU_IRQ = 137, /* Core15 PPU */ + + GPU_PPU_IRQ = 163, /* GPU PPU */ + + SOC_SYS_TIM0_S_IRQ = 250, /* SoC System Timer 0 Secure */ + SOC_SYS_TIM1_NS_IRQ = 251, /* SoC System Timer 1 Non Secure */ + + WATCHDOG0_S_IRQ = 253, /* Watchdog 0 Secure */ + WATCHDOG1_S_IRQ = 254, /* Watchdog 1 Secure */ + WATCHDOG0_NS_IRQ = 255, /* Watchdog 0 Non Secure */ + WATCHDOG1_NS_IRQ = 256, /* Watchdog 1 Non Secure */ + DMC0_COMBD_RAS_IRQ = 257, /* DMC0 Combined RAS */ + DMC0_COMBD_PMU_IRQ = 258, /* DMC0 Combined PMU */ + DMC0_COMBD_MISC_IRQ = 259, /* DMC0 Combined MISC */ + DMC1_COMBD_RAS_IRQ = 260, /* DMC1 Combined RAS */ + DMC1_COMBD_PMU_IRQ = 261, /* DMC1 Combined PMU */ + DMC1_COMBD_MISC_IRQ = 262, /* DMC1 Combined MISC */ + DMC2_COMBD_RAS_IRQ = 263, /* DMC2 Combined RAS */ + DMC2_COMBD_PMU_IRQ = 264, /* DMC2 Combined PMU */ + DMC2_COMBD_MISC_IRQ = 265, /* DMC2 Combined MISC */ + DMC3_COMBD_RAS_IRQ = 266, /* DMC3 Combined RAS */ + DMC3_COMBD_PMU_IRQ = 267, /* DMC3 Combined PMU */ + DMC3_COMBD_MISC_IRQ = 268, /* DMC3 Combined MISC */ + + GIC_ECC_FATAL_IRQ = 281, /* GIC ECC Fatal */ + GIC_AXIM_ERR_IRQ = 282, /* GIC Axim Error */ + + MCN0_COMBD_S_IRQ = 321, /* MCN0 Combined Secure */ + MCN0_COMBD_NS_IRQ = 322, /* MCN0 Combined Non Secure */ + MCN1_COMBD_S_IRQ = 323, /* MCN1 Combined Secure */ + MCN1_COMBD_NS_IRQ = 324, /* MCN1 Combined Non Secure */ + MCN2_COMBD_S_IRQ = 325, /* MCN2 Combined Secure */ + MCN2_COMBD_NS_IRQ = 326, /* MCN2 Combined Non Secure */ + MCN3_COMBD_S_IRQ = 327, /* MCN3 Combined Secure */ + MCN3_COMBD_NS_IRQ = 328, /* MCN3 Combined Non Secure */ + + DATA_NCI_PMU_SYSCLK_IRQ = 337, /* Data NCI PMU SysClk */ + DATA_NCI_PMU_PERIPHCLK_IRQ = 338, /* Data NCI PMU Periphclk */ + DATA_NCI_PMU_GPU_COREGRPCLK_IRQ = 339, /* Data NCI PMU GPU core group clk */ + DATA_NCI_PMU_SMSCLK_IRQ = 340, /* Data NCI PMU smsclk */ + DATA_NCI_PMU_ROS_NCICLK_IRQ = 341, /* Data NCI PMU RoS nciclk */ + PERIPH_NCI_PMU_SYSCLK_IRQ = 342, /* Peripheral NCI PMU SysClk */ + PERIPH_NCI_PMU_PERIPHCLK_IRQ = 343, /* Peripheral NCI PMU Periphclk */ + PERIPH_NCI_PMU_GPU_CLK_IRQ = 344, /* Peripheral NCI PMU GPU clk */ + PERIPH_NCI_PMU_DSU_PPUCLK_IRQ = 345, /* Peripheral NCI DSU PPU clk */ + PERIPH_NCI_PMU_SMSCLK_IRQ = 346, /* Peripheral NCI PMU smsclk */ + + DATA_PD_SYSTOP_S_IRQ = 353, /* Data PD SYSTOP Secure */ + DATA_PD_SYSTOP_NS_IRQ = 354, /* Data PD SYSTOP Non Secure */ + DATA_PD_GPUGLBL_S_IRQ = 355, /* Data PD GPU glbl Secure */ + DATA_PD_GPUGLBL_NS_IRQ = 356, /* Data PD GPU glbl Non Secure */ + PERIPH_PD_SYSTOP_S_IRQ = 357, /* Peripheral PD SYSTOP Secure */ + PERIPH_PD_SYSTOP_NS_IRQ = 358, /* Peripheral PD SYSTOP Non Secure */ + PERIPH_PD_GPUGLBL_S_IRQ = 359, /* Peripheral PD GPU glbl Secure */ + PERIPH_PD_GPUGLBL_NS_IRQ = 360, /* Peripheral PD GPU glbl Non Secure */ + PERIPH_PD_DSUTOP_S_IRQ = 361, /* Peripheral PD DSUTOP Secure */ + PERIPH_PD_DSUTOP_NS_IRQ = 362, /* Peripheral PD DSUTOP Non Secure */ + + SCP_RSS_MHU0_SEN_IRQ = 431, /* SCP RSS MHU0 Sender */ + RSS_SCP_MHU0_REC_IRQ = 432, /* RSS SCP MHU0 Receiver */ + + IRQn_MAX = INT16_MAX, +} IRQn_Type; + +#include + +#endif /* FMW_CMSIS_H */ diff --git a/product/totalcompute/tc4/include/plat_mod_tc_system.h b/product/totalcompute/tc4/include/plat_mod_tc_system.h new file mode 100644 index 000000000..6af984a39 --- /dev/null +++ b/product/totalcompute/tc4/include/plat_mod_tc_system.h @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MOD_TC_SYSTEM_H +#define PLAT_MOD_TC_SYSTEM_H + +#include + +#include + +#define PD_INIT_STATE_PRIMARY_CLUSTER (MOD_PD_STATE_OFF) +#define PD_INIT_STATE_PRIMARY_CORE (MOD_PD_STATE_OFF) + +#endif /* PLAT_MOD_TC_SYSTEM_H */ diff --git a/product/totalcompute/tc4/include/scp_mmap.h b/product/totalcompute/tc4/include/scp_mmap.h new file mode 100644 index 000000000..cb3acbafc --- /dev/null +++ b/product/totalcompute/tc4/include/scp_mmap.h @@ -0,0 +1,134 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_MMAP_H +#define SCP_MMAP_H + +#include "tc4_atu.h" + +/* SCP TCM size */ +#define SCP_ITCM_SIZE (256 * 1024) +#define SCP_DTCM_SIZE (256 * 1024) + +/* SCP TCM base addresses */ +#define SCP_ITCM_NS_BASE 0x00000000 +#define SCP_ITCM_S_BASE 0x10000000 +#define SCP_DTCM_NS_BASE 0x20000000 +#define SCP_DTCM_S_BASE 0x30000000 + +/* SCP Boot and Runtime base addresses */ +#define SCP_BOOT_BASE SCP_ITCM_S_BASE +#define SCP_RUNTIME_BASE SCP_DTCM_NS_BASE + +/* SCP Boot and Runtime maximum sizes */ +#define SCP_BOOT_SIZE SCP_ITCM_SIZE +#define SCP_RUNTIME_SIZE SCP_DTCM_SIZE + +/* SCP trusted and non-trusted RAM base address */ +#define SCP_TRUSTED_RAM_BASE (SCP_ATU_LOG_ADDR_SHARED_SRAM) +#define SCP_NONTRUSTED_RAM_BASE (SCP_ATU_LOG_ADDR_SHARED_NSRAM) + +/* Secure Shared memory between AP and SCP */ +#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE) +#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB) + +/* Non-secure Shared memory between AP and SCP */ +#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE) +#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB) + +#define SCP_PERIPHERAL_BASE UINT32_C(0x44000000) +#define SCP_PIK_SYSTEM_BASE UINT32_C(0x57000000) + +/* System Control Register Block Base Address */ +#define SCP_SYSTEM_CONTROL_BASE UINT32_C(0x58021000) + +/* Base address of the SCP ATU */ +#define SCP_ATU_BASE (0x50150000) + +#define SCP_UART_BOARD_BASE (0x4A040000) + +#define SCP_PIK_SCP_BASE (SCP_PIK_SYSTEM_BASE + 0x200000) + +#define SCP_GTCLK_CNTCONTROL_BASE (SCP_ATU_LOG_ADDR_GTCLK) +#define SCP_GTCLK_CNTCTL_BASE (SCP_ATU_LOG_ADDR_GTCLK_AP) +#define SCP_GTCLK_CNTBASE0_BASE (SCP_GTCLK_CNTCTL_BASE + 0x10000) + +#define SCP_PIK_CLUSTER_BASE (SCP_PIK_SYSTEM_BASE + 0x40000) +#define SCP_PIK_DPU_BASE (SCP_PIK_SYSTEM_BASE + 0x7C0000) +#define SCP_PIK_GPU_BASE (SCP_PIK_SYSTEM_BASE + 0x80000) + +#define SCP_UTILITY_BUS_BASE \ + (SCP_ATU_LOG_ADDR_CLUSTER_UTIL) +#define SCP_PPU_CLUSTER_BASE (SCP_UTILITY_BUS_BASE + 0x30000) +#define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + (n * 0x100000)) + +/* AMEVCNTR1 address offset from AMU base address */ +#define SCP_AMU_AMEVCNTR1_OFFSET 0x100 + +#define SCP_MPMM_BASE (SCP_UTILITY_BUS_BASE + 0xB0000) +#define SCP_MPMM_CORE_BASE(CPU_IDX) (SCP_MPMM_BASE + ((CPU_IDX)*0x100000)) +#define SCP_AMU_BASE (SCP_UTILITY_BUS_BASE + 0x90000) +#define SCP_AMU_CORE_BASE(CPU_IDX) (SCP_AMU_BASE + ((CPU_IDX)*0x100000)) +#define SCP_AMU_AMEVCNTR0X(CPU_IDX) (SCP_AMU_CORE_BASE(CPU_IDX) + 0x0) +#define SCP_AMU_AMEVCNTR1X(CPU_IDX) \ + (SCP_AMU_CORE_BASE(CPU_IDX) + SCP_AMU_AMEVCNTR1_OFFSET) + +#define SCP_MHU_SCP_AP_RCV_NS UINT32_C(0x401f0000) +#define SCP_MHU_SCP_AP_SND_NS UINT32_C(0x401e0000) +#define SCP_MHU_SCP_AP_RCV_S UINT32_C(0x40170000) +#define SCP_MHU_SCP_AP_SND_S UINT32_C(0x40160000) + +#if defined(PLAT_FVP) +#define SCP_MHU_SCP_RSS_RCV_S_CLUS0 0x5a010000 +#define SCP_MHU_SCP_RSS_SND_S_CLUS0 0x5a000000 + +#define SCP_MHU_SCP_RSS_NUM_DBCH (4) +#endif + +#define SCP_PLL_BASE (SCP_ATU_LOG_ADDR_PLL) +#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) +#define SCP_PLL_GPU (SCP_PLL_BASE + 0x00000008) +#define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014) +#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018) +#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C) +#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) + +#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) +#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) +#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) +#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) + +/* AP Context Area */ +#define SCP_AP_CONTEXT_BASE \ + (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \ + SCP_AP_CONTEXT_SIZE) +#define SCP_AP_CONTEXT_SIZE (64) + +/* SDS Memory Region */ +#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE) +#define SCP_SDS_MEM_SIZE (3520) + +/* SCMI Secure Payload Areas */ +#define SCP_SCMI_PAYLOAD_SIZE (128) +#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + SCP_SDS_MEM_SIZE) +#define SCP_SCMI_PAYLOAD_S_P2A_BASE \ + (SCP_SCMI_PAYLOAD_S_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) + +/* SDS Memory Region of RSE - Reserved */ +#define RSE_SDS_MEM_BASE (SCP_SCMI_PAYLOAD_S_P2A_BASE + SCP_SCMI_PAYLOAD_SIZE) +#define RSE_SDS_MEM_SIZE (64) + +/* SCMI Non-Secure Payload Areas */ + +#define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE) +#define SCP_SCMI_PAYLOAD_NS_P2A_BASE \ + (SCP_SCMI_PAYLOAD_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) + +#define SCMI_FAST_CHANNEL_BASE \ + (SCP_SCMI_PAYLOAD_NS_P2A_BASE + (3 * SCP_SCMI_PAYLOAD_SIZE)) + +#endif /* SCP_MMAP_H */ diff --git a/product/totalcompute/tc4/include/tc4_atu.h b/product/totalcompute/tc4/include/tc4_atu.h new file mode 100644 index 000000000..2c4534d30 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_atu.h @@ -0,0 +1,57 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TC4_ATU_H +#define TC4_ATU_H + +/* ATU Region allocations */ +#define START_REGION_FOR_MOD_ATU (0) +#define MAX_REGIONS_FOR_MOD_ATU (8) +#define END_REGION_FOR_MOD_ATU \ + (START_REGION_FOR_MOD_ATU + MAX_REGIONS_FOR_MOD_ATU - 1) + +/* ATU System Acccess Ports */ +#define SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_NS UINT32_C(0x60000000) +#define SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_S UINT32_C(0x70000000) +#define SCP_SYSTEM_ACCESS_ATU_DATA1_BASE_NS UINT32_C(0x80000000) +#define SCP_SYSTEM_ACCESS_ATU_DATA1_BASE_S UINT32_C(0x90000000) +#define SCP_SYSTEM_ACCESS_ATU_INT_EXP_BASE_NS UINT32_C(0xA0000000) +#define SCP_SYSTEM_ACCESS_ATU_INT_EXP_BASE_S UINT32_C(0xB0000000) +#define SCP_SYSTEM_ACCESS_ATU_DEV_BASE_NS UINT32_C(0xC0000000) +#define SCP_SYSTEM_ACCESS_ATU_DEV_BASE_S UINT32_C(0xD0000000) + +/* ATU Logical Addresses */ +#define SCP_ATU_LOG_ADDR_GTCLK_AP \ + (SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_S + 0x0A810000) +#define SCP_ATU_LOG_ADDR_GTCLK (SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_S + 0x0A430000) +#define SCP_ATU_LOG_ADDR_SHARED_SRAM \ + (SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_S + 0x04000000) +#define SCP_ATU_LOG_ADDR_ROS_SOC_BASE \ + (SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_S + 0x0FF70000) +#define SCP_ATU_LOG_ADDR_SHARED_NSRAM (SCP_SYSTEM_ACCESS_ATU_DATA0_BASE_NS) +#define SCP_ATU_LOG_ADDR_CLUSTER_UTIL (SCP_SYSTEM_ACCESS_ATU_INT_EXP_BASE_S) +#define SCP_ATU_LOG_ADDR_PLL (SCP_SYSTEM_ACCESS_ATU_DEV_BASE_S) + +/* ATU Physical Addresses */ +#define SCP_ATU_PHY_ADDR_GTCLK_AP (0x2A810000) +#define SCP_ATU_PHY_ADDR_GTCLK (0x47000000) +#define SCP_ATU_PHY_ADDR_CLUSTER_UTIL (0x5F000000) +#define SCP_ATU_PHY_ADDR_SHARED_SRAM (0x04000000) +#define SCP_ATU_PHY_ADDR_SHARED_NSRAM (0x06000000) +#define SCP_ATU_PHY_ADDR_ROS_SOC (0x7FF70000) +#define SCP_ATU_PHY_ADDR_PLL (0x43000000) + +/* ATU Region Sizes */ +#define SCP_ATU_REG_SIZE_GTCLK_AP (128 * FWK_KIB) +#define SCP_ATU_REG_SIZE_GTCLK (128 * FWK_KIB) +#define SCP_ATU_REG_SIZE_SHARED_SRAM (512 * FWK_KIB) +#define SCP_ATU_REG_SIZE_SHARED_NSRAM (512 * FWK_KIB) +#define SCP_ATU_REG_SIZE_ROS_SOC (64 * FWK_KIB) +#define SCP_ATU_REG_SIZE_CLUSTER_UTIL (10 * FWK_MIB) +#define SCP_ATU_REG_SIZE_PLL (64 * FWK_KIB) + +#endif /* TC4_ATU_H */ diff --git a/product/totalcompute/tc4/include/tc4_core.h b/product/totalcompute/tc4/include/tc4_core.h new file mode 100644 index 000000000..5f1c2a2c5 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_core.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TC4_CORE_H +#define TC4_CORE_H + +#include + +#define TC4_CORES_PER_CLUSTER (8) +#define TC4_NUMBER_OF_CLUSTERS (1) +#define TC4_NUMBER_OF_CORES (TC4_CORES_PER_CLUSTER * TC4_NUMBER_OF_CLUSTERS) + +#endif /* TC4_CORE_H */ diff --git a/product/totalcompute/tc4/include/tc4_dvfs.h b/product/totalcompute/tc4/include/tc4_dvfs.h new file mode 100644 index 000000000..90c61f635 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_dvfs.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for DVFS module configuration. + */ + +#ifndef TC4_DVFS_H +#define TC4_DVFS_H + +enum dvfs_element_idx { + DVFS_ELEMENT_IDX_NEVIS, + DVFS_ELEMENT_IDX_GELAS, + DVFS_ELEMENT_IDX_TRAVIS, + DVFS_ELEMENT_IDX_GPU, + DVFS_ELEMENT_IDX_COUNT +}; + +#endif /* TC4_DVFS_H */ diff --git a/product/totalcompute/tc4/include/tc4_mock_ppu.h b/product/totalcompute/tc4/include/tc4_mock_ppu.h new file mode 100644 index 000000000..f1f28f12a --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_mock_ppu.h @@ -0,0 +1,20 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for mock PPU module configuration. + */ + +#ifndef TC4_MOCK_PPU_H +#define TC4_MOCK_PPU_H + +enum mock_ppu_static_element_idx { + MOCK_PPU_ELEMENT_IDX_SYS0, + MOCK_PPU_ELEMENT_IDX_GPUCGRP, + MOCK_PPU_ELEMENT_IDX_COUNT +}; + +#endif /* TC4_MOCK_PPU_H */ diff --git a/product/totalcompute/tc4/include/tc4_mock_psu.h b/product/totalcompute/tc4/include/tc4_mock_psu.h new file mode 100644 index 000000000..5673fff34 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_mock_psu.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for mock PSU module configuration. + */ + +#ifndef TC4_MOCK_PSU_H +#define TC4_MOCK_PSU_H + +enum mock_psu_id { + MOCK_PSU_ELEMENT_IDX_NEVIS, + MOCK_PSU_ELEMENT_IDX_GELAS, + MOCK_PSU_ELEMENT_IDX_TRAVIS, + MOCK_PSU_ELEMENT_IDX_GPU, + MOCK_PSU_ELEMENT_IDX_COUNT, +}; + +#endif /* TC4_MOCK_PSU_H */ diff --git a/product/totalcompute/tc4/include/tc4_ppu_v1.h b/product/totalcompute/tc4/include/tc4_ppu_v1.h new file mode 100644 index 000000000..6fbb6a3c7 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_ppu_v1.h @@ -0,0 +1,11 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TC4_PPU_V1_H +#define TC4_PPU_V1_H + +#endif /* TC4_PPU_V1_H */ diff --git a/product/totalcompute/tc4/include/tc4_psu.h b/product/totalcompute/tc4/include/tc4_psu.h new file mode 100644 index 000000000..c6cb315c3 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_psu.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for PSU module configuration. + */ + +#ifndef TC4_PSU_H +#define TC4_PSU_H + +enum psu_id { + PSU_ELEMENT_IDX_NEVIS, + PSU_ELEMENT_IDX_GELAS, + PSU_ELEMENT_IDX_TRAVIS, + PSU_ELEMENT_IDX_GPU, + PSU_ELEMENT_IDX_COUNT, +}; + +#endif /* TC4_PSU_H */ diff --git a/product/totalcompute/tc4/include/tc4_scmi.h b/product/totalcompute/tc4/include/tc4_scmi.h new file mode 100644 index 000000000..7a08a4a24 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_scmi.h @@ -0,0 +1,92 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for SCMI and TRANSPORT module configurations. + */ + +#ifndef SCP_TC4_SCMI_H +#define SCP_TC4_SCMI_H + +/* SCMI agent identifiers */ +enum scp_tc4_scmi_agent_id { + /* 0 is reserved for the platform */ + SCP_SCMI_AGENT_ID_OSPM = 1, + SCP_SCMI_AGENT_ID_PSCI, + SCP_SCMI_AGENT_ID_COUNT +}; + +/* SCMI service indexes */ +enum scp_tc4_scmi_service_idx { + SCP_TC4_SCMI_SERVICE_IDX_PSCI, + SCP_TC4_SCMI_SERVICE_IDX_OSPM_A2P, +#ifdef BUILD_HAS_SCMI_NOTIFICATIONS + SCP_TC4_SCMI_SERVICE_IDX_OSPM_P2A, +#endif + SCP_TC4_SCMI_SERVICE_IDX_COUNT, +}; + +/* SCP<->AP Fast channels indexes */ +enum tc4_plat_fch_idx { + /* Fast channels from 0 - 3 */ + TC4_PLAT_FCH_NEVIS_LEVEL_SET, + TC4_PLAT_FCH_NEVIS_LIMIT_SET, + TC4_PLAT_FCH_NEVIS_LEVEL_GET, + TC4_PLAT_FCH_NEVIS_LIMIT_GET, + + /* Fast channels from 4 - 7 */ + TC4_PLAT_FCH_GELAS_LEVEL_SET, + TC4_PLAT_FCH_GELAS_LIMIT_SET, + TC4_PLAT_FCH_GELAS_LEVEL_GET, + TC4_PLAT_FCH_GELAS_LIMIT_GET, + + /* Fast channels from 8 - 11 */ + TC4_PLAT_FCH_TRAVIS_LEVEL_SET, + TC4_PLAT_FCH_TRAVIS_LIMIT_SET, + TC4_PLAT_FCH_TRAVIS_LEVEL_GET, + TC4_PLAT_FCH_TRAVIS_LIMIT_GET, + + /* Fast chanels from 12 - 15*/ + TC4_PLAT_FCH_GPU_LEVEL_SET, + TC4_PLAT_FCH_GPU_LIMIT_SET, + TC4_PLAT_FCH_GPU_LEVEL_GET, + TC4_PLAT_FCH_GPU_LIMIT_GET, + + TC4_PLAT_FCH_COUNT, +}; + +/* SCP <-> AP Transport channels */ +enum tc4_transport_channel_idx { + TC4_TRANSPORT_SCMI_SERVICE_PSCI, + TC4_TRANSPORT_SCMI_SERVICE_OSPM_A2P, + TC4_TRANSPORT_SCMI_SERVICE_OSPM_P2A, + TC4_TRANSPORT_SCMI_SERVICE_IDX_SCP2RSS, + +#if defined(BUILD_HAS_SCMI_PERF_FAST_CHANNELS) + TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_GET, + + TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_GET, + + TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_GET, + + TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_GET, +#endif + TC4_TRANSPORT_CHANNELS_COUNT, +}; + +#endif /* SCP_TC4_SCMI_H */ diff --git a/product/totalcompute/tc4/include/tc4_timer.h b/product/totalcompute/tc4/include/tc4_timer.h new file mode 100644 index 000000000..19c5657b2 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_timer.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_TIMER_H +#define CONFIG_TIMER_H + +enum config_timer_refclk_sub_element_idx { + TC4_CONFIG_TIMER_DVFS_CPU_NEVIS, + TC4_CONFIG_TIMER_DVFS_CPU_GELAS, + TC4_CONFIG_TIMER_DVFS_CPU_TRAVIS, + TC4_CONFIG_TIMER_DVFS_GPU, +#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + TC4_CONFIG_TIMER_FAST_CHANNEL_TIMER_IDX, +#endif + TC4_CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT, +}; + +#endif /* CONFIG_TIMER_H */ diff --git a/product/totalcompute/tc4/include/tc4_transport.h b/product/totalcompute/tc4/include/tc4_transport.h new file mode 100644 index 000000000..d3c9eb976 --- /dev/null +++ b/product/totalcompute/tc4/include/tc4_transport.h @@ -0,0 +1,25 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for TRANSPORT module configurations. + */ + +#ifndef SCP_TC4_TRANSPORT_H +#define SCP_TC4_TRANSPORT_H + +/* Transport service indexes */ +enum scp_tc4_transport_service_idx { + SCP_TC4_TRANSPORT_SERVICE_IDX_PSCI, + SCP_TC4_TRANSPORT_SERVICE_IDX_OSPM_A2P, +#ifdef BUILD_HAS_SCMI_NOTIFICATIONS + SCP_TC4_TRANSPORT_SERVICE_IDX_OSPM_P2A, +#endif + SCP_TC4_TRANSPORT_SERVICE_IDX_SCP2RSS, + SCP_TC4_TRANSPORT_SERVICE_IDX_COUNT, +}; + +#endif /* SCP_TC4_TRANSPORT_H */ diff --git a/product/totalcompute/tc4/include/tc_core.h b/product/totalcompute/tc4/include/tc_core.h new file mode 100644 index 000000000..974f9220b --- /dev/null +++ b/product/totalcompute/tc4/include/tc_core.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TC_CORE_H +#define TC_CORE_H + +#include + +#define TC4_GROUP_LITTLE_NAME "NEVIS" +#define TC4_GROUP_MID_NAME "GELAS" +#define TC4_GROUP_BIG_NAME "TRAVIS" + +#endif /* TC_CORE_H */ diff --git a/product/totalcompute/tc4/module/tc4_bl1/CMakeLists.txt b/product/totalcompute/tc4/module/tc4_bl1/CMakeLists.txt new file mode 100644 index 000000000..e4c96ddda --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_bl1/CMakeLists.txt @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_tc4_bl1.c") + +target_link_libraries( + ${SCP_MODULE_TARGET} PRIVATE module-bootloader module-power-domain + module-ppu-v1 module-transport) diff --git a/product/totalcompute/tc4/module/tc4_bl1/Module.cmake b/product/totalcompute/tc4/module/tc4_bl1/Module.cmake new file mode 100644 index 000000000..18aca9492 --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_bl1/Module.cmake @@ -0,0 +1,9 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "tc4-bl1") +set(SCP_MODULE_TARGET "module-tc4-bl1") diff --git a/product/totalcompute/tc4/module/tc4_bl1/include/mod_tc4_bl1.h b/product/totalcompute/tc4/module/tc4_bl1/include/mod_tc4_bl1.h new file mode 100644 index 000000000..483a46cc8 --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_bl1/include/mod_tc4_bl1.h @@ -0,0 +1,73 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: TC4 BL1 module. + */ + +#ifndef MOD_TC4_BL1_H +#define MOD_TC4_BL1_H + +#include +#include + +#include +#include + +/*! + * \ingroup GroupTC4BL1 + * \defgroup GroupTC4BL1 BL1 Support + * \{ + */ + +/*! + * \brief Module configuration data. + */ +struct mod_tc4_bl1_config { + /*! Base address of the Application Processor (AP) context area */ + const uintptr_t ap_context_base; + + /*! Size of the AP context area */ + const size_t ap_context_size; + + /*! Element ID of the primary cluster PPU */ + const fwk_id_t id_primary_cluster; + + /*! Element ID of the primary core PPU */ + const fwk_id_t id_primary_core; +}; + +/*! + * \brief Type of the interfaces exposed by the module. + */ +enum mod_tc4_bl1_api_idx { + /*! Interface for transport module */ + MOD_TC4_BL1_API_TRANSPORT_FIRMWARE_SIGNAL_INPUT, + /*! Number of defined interfaces */ + MOD_TC4_BL1_API_IDX_COUNT, +}; + +/*! + * \brief Notification indices. + */ +enum mod_tc4_bl1_notification_idx { + /*! SYSTOP powered on notification */ + MOD_TC4_BL1_NOTIFICATION_IDX_POWER_SYSTOP, + + /*! Number of notifications defined by the module */ + MOD_TC4_BL1_NOTIFICATION_COUNT, +}; + +/*! SYSTOP powered on notification identifier */ +static const fwk_id_t mod_tc4_bl1_notification_id_systop = + FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_TC4_BL1, + MOD_TC4_BL1_NOTIFICATION_IDX_POWER_SYSTOP); + +/*! + * \} + */ + +#endif /* MOD_TC4_BL1_H */ diff --git a/product/totalcompute/tc4/module/tc4_bl1/src/mod_tc4_bl1.c b/product/totalcompute/tc4/module/tc4_bl1/src/mod_tc4_bl1.c new file mode 100644 index 000000000..32cdfdd7d --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_bl1/src/mod_tc4_bl1.c @@ -0,0 +1,225 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tc4_transport.h" + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct tc4_bl1_ctx { + const struct mod_tc4_bl1_config *bl1_config; + struct mod_pd_restricted_api *mod_pd_restricted_api; + struct mod_transport_firmware_api *firmware_api; + unsigned int notification_count; /* Notifications awaiting a response */ +} ctx; + +enum mod_bl1_event { + MOD_BL1_EVENT_RUN, + MOD_BL1_EVENT_RSS_HANDSHAKE, + MOD_BL1_EVENT_COUNT +}; + +static int tc4_signal_error(fwk_id_t service_id) +{ + fwk_unexpected(); + return FWK_E_PANIC; +} + +bool fwk_is_interrupt_context(void); + +static int tc4_signal_message(fwk_id_t service_id) +{ + struct fwk_event event = { + .source_id = FWK_ID_MODULE(FWK_MODULE_IDX_TC4_BL1), + .target_id = FWK_ID_MODULE(FWK_MODULE_IDX_TC4_BL1), + .id = FWK_ID_EVENT(FWK_MODULE_IDX_TC4_BL1, MOD_BL1_EVENT_RSS_HANDSHAKE), + }; + + return fwk_put_event(&event); +} + +static const struct mod_transport_firmware_signal_api + tc4_system_transport_firmware_signal_api = { + .signal_error = tc4_signal_error, + .signal_message = tc4_signal_message, + }; + +static int bl1_deferred_setup(void) +{ + /* Initialize the AP context area by zeroing it */ + memset( + (void *)ctx.bl1_config->ap_context_base, + 0, + ctx.bl1_config->ap_context_size); + + FWK_LOG_INFO("[TC4_BL1] Pinging RSS"); + ctx.firmware_api->trigger_interrupt(FWK_ID_ELEMENT( + FWK_MODULE_IDX_TRANSPORT, SCP_TC4_TRANSPORT_SERVICE_IDX_SCP2RSS)); + + return FWK_SUCCESS; +} + +/* + * Functions fulfilling the framework's module interface + */ + +static int tc4_bl1_init( + fwk_id_t module_id, + unsigned int element_count, + const void *data) +{ + ctx.bl1_config = data; + + if ((ctx.bl1_config->ap_context_base == 0) || + (ctx.bl1_config->ap_context_size == 0)) + return FWK_E_RANGE; + + return FWK_SUCCESS; +} + +static int tc4_bl1_bind(fwk_id_t id, unsigned int round) +{ + int status; + + /* Use second round only (round numbering is zero-indexed) */ + if (round == 1) { + /* Bind to the Power Domain module */ + status = fwk_module_bind( + FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), + FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), + &ctx.mod_pd_restricted_api); + + status = fwk_module_bind( + FWK_ID_ELEMENT( + FWK_MODULE_IDX_TRANSPORT, + SCP_TC4_TRANSPORT_SERVICE_IDX_SCP2RSS), + FWK_ID_API( + FWK_MODULE_IDX_TRANSPORT, MOD_TRANSPORT_API_IDX_FIRMWARE), + &ctx.firmware_api); + if (status != FWK_SUCCESS) + return FWK_E_PANIC; + } + + return FWK_SUCCESS; +} + +static int tc4_bl1_start(fwk_id_t id) +{ + struct fwk_event event = { + .source_id = FWK_ID_MODULE(FWK_MODULE_IDX_TC4_BL1), + .target_id = FWK_ID_MODULE(FWK_MODULE_IDX_TC4_BL1), + .id = FWK_ID_EVENT(FWK_MODULE_IDX_TC4_BL1, MOD_BL1_EVENT_RUN), + }; + + return fwk_put_event(&event); +} + +static int tc4_bl1_process_event( + const struct fwk_event *event, + struct fwk_event *resp) +{ + int status; + + if (fwk_id_get_event_idx(event->id) == MOD_BL1_EVENT_RUN) { + struct mod_pd_power_state_transition_notification_params + *notification_params; + struct fwk_event systop_on_event = { + .response_requested = true, + .id = mod_tc4_bl1_notification_id_systop, + .source_id = FWK_ID_NONE + }; + + /* Notify any subscribers of the SYSTOP power domain state change */ + notification_params = + (struct mod_pd_power_state_transition_notification_params *) + systop_on_event.params; + notification_params->state = MOD_PD_STATE_ON; + + status = + fwk_notification_notify(&systop_on_event, &ctx.notification_count); + if (status != FWK_SUCCESS) + return status; + + return FWK_SUCCESS; + } else if (fwk_id_get_event_idx(event->id) == MOD_BL1_EVENT_RSS_HANDSHAKE) { + FWK_LOG_INFO("[TC4_BL1] Got ACK from RSS"); + + /* Power on the primary cluster and cpu using power domain */ + ctx.mod_pd_restricted_api->set_state( + ctx.bl1_config->id_primary_cluster, + MOD_PD_SET_STATE_NO_RESP, + MOD_PD_STATE_ON); + ctx.mod_pd_restricted_api->set_state( + ctx.bl1_config->id_primary_core, + MOD_PD_SET_STATE_NO_RESP, + MOD_PD_STATE_ON); + } + + return FWK_SUCCESS; +} + +static int tc4_bl1_process_notification( + const struct fwk_event *event, + struct fwk_event *resp_event) +{ + fwk_assert(fwk_id_is_equal(event->id, mod_tc4_bl1_notification_id_systop)); + fwk_assert(event->is_response == true); + + /* At least one notification response must be outstanding */ + if (ctx.notification_count == 0) { + fwk_unexpected(); + return FWK_E_PANIC; + } + + /* Complete remaining setup now that all subscribers have responded */ + if ((--ctx.notification_count) == 0) { + return bl1_deferred_setup(); + } + + return FWK_SUCCESS; +} + +static int tc4_bl1_process_bind_request( + fwk_id_t source_id, + fwk_id_t target_id, + fwk_id_t api_id, + const void **api) +{ + *api = &tc4_system_transport_firmware_signal_api; + return FWK_SUCCESS; +} + +/* Module descriptor */ +const struct fwk_module module_tc4_bl1 = { + .api_count = MOD_TC4_BL1_API_IDX_COUNT, + .type = FWK_MODULE_TYPE_SERVICE, + .event_count = MOD_BL1_EVENT_COUNT, + .notification_count = MOD_TC4_BL1_NOTIFICATION_COUNT, + .init = tc4_bl1_init, + .bind = tc4_bl1_bind, + .start = tc4_bl1_start, + .process_bind_request = tc4_bl1_process_bind_request, + .process_event = tc4_bl1_process_event, + .process_notification = tc4_bl1_process_notification, +}; diff --git a/product/totalcompute/tc4/module/tc4_power_model/CMakeLists.txt b/product/totalcompute/tc4/module/tc4_power_model/CMakeLists.txt new file mode 100644 index 000000000..e126a2f60 --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_power_model/CMakeLists.txt @@ -0,0 +1,16 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_tc4_power_model.c") + +target_link_libraries(${SCP_MODULE_TARGET} + PRIVATE module-thermal-mgmt module-scmi-perf) diff --git a/product/totalcompute/tc4/module/tc4_power_model/Module.cmake b/product/totalcompute/tc4/module/tc4_power_model/Module.cmake new file mode 100644 index 000000000..d57fa7514 --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_power_model/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "tc4-power-model") + +set(SCP_MODULE_TARGET "module-tc4-power-model") diff --git a/product/totalcompute/tc4/module/tc4_power_model/include/mod_tc4_power_model.h b/product/totalcompute/tc4/module/tc4_power_model/include/mod_tc4_power_model.h new file mode 100644 index 000000000..a0582a0bb --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_power_model/include/mod_tc4_power_model.h @@ -0,0 +1,59 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * TC4 Power Model (Thermal Management Driver) + */ + +#ifndef MOD_TC4_POWER_MODEL_H +#define MOD_TC4_POWER_MODEL_H + +//#include + +/*! + * \addtogroup GroupTC4Module TC4 Product Modules + * \{ + */ + +/*! + * \defgroup GroupTC4PowerModel TC4 Power Model + * \{ + */ + +/*! + * \brief TC4 Power Model element configuration + */ +struct mod_tc4_power_model_dev_config { + /*! + * \brief Coefficient to compute the power from level and viceversa. + * + * \details This is an oversimplified example of element configuration. For + * the purpose of code reference, we assume that power and level are + * tied each other by a simple coefficient. + */ + unsigned int coeff; +}; + +/*! + * \brief Number of defined APIs for Power Model. + */ +enum mod_tc4_power_model_api_idx { + /*! API index for the driver interface of the Thermal Management module */ + MOD_TC4_POWER_MODEL_THERMAL_DRIVER_API_IDX, + + /*! Number of exposed interfaces */ + MOD_TC4_POWER_MODEL_API_COUNT, +}; + +/*! + * \} + */ + +/*! + * \} + */ + +#endif /* MOD_TC4_POWER_MODEL_H */ diff --git a/product/totalcompute/tc4/module/tc4_power_model/src/mod_tc4_power_model.c b/product/totalcompute/tc4/module/tc4_power_model/src/mod_tc4_power_model.c new file mode 100644 index 000000000..decf6ca79 --- /dev/null +++ b/product/totalcompute/tc4/module/tc4_power_model/src/mod_tc4_power_model.c @@ -0,0 +1,92 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * TC4 Power Model. + */ + +#include +#include + +#include +#include +#include + +#include + +uint32_t tc4_pm_level_to_power(fwk_id_t pm_id, const uint32_t level) +{ + const struct mod_tc4_power_model_dev_config *config; + + config = fwk_module_get_data(pm_id); + return (config->coeff * level); +} + +uint32_t tc4_pm_power_to_level(fwk_id_t pm_id, const uint32_t power) +{ + const struct mod_tc4_power_model_dev_config *config; + + config = fwk_module_get_data(pm_id); + return (power / config->coeff); +} + +static const struct mod_thermal_mgmt_driver_api tc4_thermal_mgmt_driver_api = { + .level_to_power = tc4_pm_level_to_power, + .power_to_level = tc4_pm_power_to_level, +}; + +/* + * Framework handlers. + */ + +static int tc4_power_model_mod_init( + fwk_id_t module_id, + unsigned int unused, + const void *data) +{ + return FWK_SUCCESS; +} + +static int tc4_power_model_elem_init( + fwk_id_t element_id, + unsigned int sub_element_count, + const void *data) +{ + return FWK_SUCCESS; +} + +static int tc4_power_model_bind(fwk_id_t id, unsigned int round) +{ + return FWK_SUCCESS; +} + +static int tc4_power_model_process_bind_request( + fwk_id_t requester_id, + fwk_id_t pd_id, + fwk_id_t api_id, + const void **api) +{ + fwk_id_t power_model_api_id = FWK_ID_API( + FWK_MODULE_IDX_TC4_POWER_MODEL, + MOD_TC4_POWER_MODEL_THERMAL_DRIVER_API_IDX); + + if (fwk_id_is_equal(api_id, power_model_api_id)) { + *api = &tc4_thermal_mgmt_driver_api; + + return FWK_SUCCESS; + } + + return FWK_E_ACCESS; +} + +const struct fwk_module module_tc4_power_model = { + .type = FWK_MODULE_TYPE_DRIVER, + .api_count = (unsigned int)MOD_TC4_POWER_MODEL_API_COUNT, + .init = tc4_power_model_mod_init, + .element_init = tc4_power_model_elem_init, + .bind = tc4_power_model_bind, + .process_bind_request = tc4_power_model_process_bind_request, +}; diff --git a/product/totalcompute/tc4/product.mk b/product/totalcompute/tc4/product.mk new file mode 100644 index 000000000..5ff0394db --- /dev/null +++ b/product/totalcompute/tc4/product.mk @@ -0,0 +1,9 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_PRODUCT_NAME := tc4 +BS_FIRMWARE_LIST := scp_css diff --git a/product/totalcompute/tc4/scp_css/Buildoptions.cmake b/product/totalcompute/tc4/scp_css/Buildoptions.cmake new file mode 100644 index 000000000..faf8a35be --- /dev/null +++ b/product/totalcompute/tc4/scp_css/Buildoptions.cmake @@ -0,0 +1,22 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +cmake_dependent_option( + SCP_ENABLE_SCMI_PERF_FAST_CHANNELS "Enable the SCMI-perf Fast Channels ?" + "${SCP_ENABLE_SCMI_PERF_FAST_CHANNELS_INIT}" + "DEFINED SCP_ENABLE_SCMI_PERF_FAST_CHANNELS_INIT" + "${SCP_ENABLE_SCMI_PERF_FAST_CHANNELS}") + +if(SCP_ENABLE_SCMI_PERF_FAST_CHANNELS) + option(BUILD_HAS_MOD_TRANSPORT_FC + "SCMI-PERF Fast Channel default implementation is transport based" ON) +endif() + +cmake_dependent_option( + SCP_ENABLE_PLUGIN_HANDLER "Enable the Performance Plugins-Handler ?" + "${SCP_ENABLE_PLUGIN_HANDLER_INIT}" "DEFINED SCP_ENABLE_PLUGIN_HANDLER_INIT" + "${SCP_ENABLE_PLUGIN_HANDLER}") diff --git a/product/totalcompute/tc4/scp_css/CMakeLists.txt b/product/totalcompute/tc4/scp_css/CMakeLists.txt new file mode 100644 index 000000000..f3046c286 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/CMakeLists.txt @@ -0,0 +1,162 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Create the firmware target. +# + +add_executable(scp-css) + +set(CMAKE_TC_DIR "../../") + +# SCP_PLATFORM_VARIANT options: +# - 'TC4_VARIANT_STD' for TC4 standard build +# - 'TC4_VAR_EXPERIMENT_POWER' for TC4 with power/performance/thermal additions +# used for evaluation purpose: +# - TRAFFIC_COP on NEVIS cores +# - MPMM on all cores +# - THERMAL_MANAGEMENT for the entire system, with a simplified/dummy power +# model +# - 'TC4_VAR_MPMM' for TC4 with only the MPMM scmi-perf plugin addition + +target_compile_definitions(scp-css PUBLIC -DTC4_VARIANT_STD=0) +target_compile_definitions(scp-css PUBLIC -DTC4_VAR_EXPERIMENT_POWER=1) +target_compile_definitions(scp-css PUBLIC -DTC4_VAR_MPMM=2) + +if(SCP_ENABLE_PLAT_FVP) + target_compile_definitions(scp-css PUBLIC -DPLAT_FVP=1) +endif() + +if (SCP_PLATFORM_VARIANT STREQUAL "1") + message(NOTICE "SCP_PLATFORM_VARIANT set to: EXPERIMENT_POWER (scp-css)\n") + + target_compile_definitions(scp-css + PUBLIC -DPLATFORM_VARIANT=TC4_VAR_EXPERIMENT_POWER) + + set(SCP_ENABLE_SCMI_NOTIFICATIONS TRUE PARENT_SCOPE) + +# The following list of modules will be appended in Firmware.cmake in the same +# order + + list(APPEND SCP_MODULES "traffic-cop") + target_sources(scp-css PRIVATE "config_traffic_cop.c") + + list(APPEND SCP_MODULES "amu-mmap") + target_sources(scp-css PRIVATE "${CMAKE_TC_DIR}/common/config_amu_mmap.c") + target_include_directories(scp-css PUBLIC + "${CMAKE_SOURCE_DIR}/interface/amu") + + list(APPEND SCP_MODULES "mpmm") + target_sources(scp-css PRIVATE "config_mpmm.c") + + list(APPEND SCP_MODULES "sensor") + target_sources(scp-css PRIVATE "config_sensor.c") + + list(APPEND SCP_MODULES "reg-sensor") + target_sources(scp-css PRIVATE "config_reg_sensor.c") + + list(APPEND SCP_MODULES "thermal-mgmt") + target_sources(scp-css PRIVATE "config_thermal_mgmt.c") + + list(APPEND SCP_MODULES "tc4-power-model") + list(PREPEND SCP_MODULE_PATHS + "${CMAKE_CURRENT_LIST_DIR}/../module/tc4_power_model") + target_sources(scp-css PRIVATE "config_tc4_power_model.c") + +elseif (SCP_PLATFORM_VARIANT STREQUAL "2") + message(NOTICE "SCP_PLATFORM_VARIANT set to: MPMM (scp-css)\n") + + target_compile_definitions(scp-css + PUBLIC -DPLATFORM_VARIANT=TC4_VAR_MPMM) + + set(SCP_ENABLE_SCMI_NOTIFICATIONS TRUE PARENT_SCOPE) + + list(APPEND SCP_MODULES "amu-mmap") + target_sources(scp-css PRIVATE "${CMAKE_TC_DIR}/common/config_amu_mmap.c") + target_include_directories(scp-css PUBLIC + "${CMAKE_SOURCE_DIR}/interface/amu") + + list(APPEND SCP_MODULES "mpmm") + target_sources(scp-css PRIVATE "config_mpmm.c") + +else() + message(NOTICE "SCP_PLATFORM_VARIANT set to: STD (scp-css)\n") + + target_compile_definitions(scp-css + PUBLIC -DPLATFORM_VARIANT=TC4_VARIANT_STD) + +endif() + +if(SCP_ENABLE_RESOURCE_PERMISSIONS) + list(APPEND SCP_MODULES,"resource-perms") +endif() + +target_include_directories( + scp-css PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}" + "${CMAKE_TC_DIR}/tc4/include" + "${CMAKE_TC_DIR}/common" + "${CMAKE_TC_DIR}/common/include") + +# cmake-lint: disable=E1122 + +target_sources( + scp-css + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_atu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_tc4_bl1.c" + "${CMAKE_TC_DIR}/common/config_pl011.c" + "${CMAKE_TC_DIR}/common/config_scmi_power_domain.c" + "${CMAKE_TC_DIR}/common/config_scmi_system_power.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_mhu3.c" + "${CMAKE_TC_DIR}/common/config_scmi_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_system_power.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_power_domain.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_transport.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_ppu_v1.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_sds.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_perf.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_gtimer.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_timer.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_dvfs.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_psu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_ppu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_psu.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_system_pll.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_css_clock.c" + "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c") + +if(SCP_ENABLE_RESOURCE_PERMISSIONS) + target_sources(scp-css PRIVATE "config_resource_perms.c") +endif() + +if(SCP_ENABLE_SCMI_PERF_FAST_CHANNELS) + list(APPEND SCP_MODULES "fch-polled") + target_sources(scp-css PRIVATE "config_fch_polled.c") +endif() + +# +# Some of our firmware includes require CMSIS. +# + +target_link_libraries(scp-css PUBLIC cmsis::core-m) + +# +# We explicitly add the CMSIS include directories to our interface include +# directories. Each module target adds these include directories to their own, +# allowing them to include any firmware includes we expose. +# + +target_include_directories(scp-css + PUBLIC $) + +if(SCP_ENABLE_PLUGIN_HANDLER) + message(NOTICE "SCP_ENABLE_PLUGIN_HANDLER enabled") +endif() + +set(SCP_MODULES ${SCP_MODULES} PARENT_SCOPE) +set(SCP_MODULE_PATHS ${SCP_MODULE_PATHS} PARENT_SCOPE) diff --git a/product/totalcompute/tc4/scp_css/Firmware.cmake b/product/totalcompute/tc4/scp_css/Firmware.cmake new file mode 100644 index 000000000..e09b083f8 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/Firmware.cmake @@ -0,0 +1,80 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# Configure the build system. +# + +set(SCP_FIRMWARE "scp-css") + +set(SCP_FIRMWARE_TARGET "scp-css") + +set(SCP_TOOLCHAIN_INIT "GNU") + +set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) + +set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) + +set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT TRUE) + +set(SCP_ENABLE_IPO_INIT FALSE) + +set(SCP_ENABLE_SCMI_PERF_FAST_CHANNELS_INIT FALSE) + +set(SCP_ENABLE_PLUGIN_HANDLER_INIT FALSE) + +set(SCP_ENABLE_OUTBAND_MSG_SUPPORT_INIT TRUE) + +set(SCP_PLATFORM_VARIANT_INIT "0") #Standard variant by default + +set(SCP_ARCHITECTURE "arm-m") + +set(SCP_ENABLE_ATU_MANAGE TRUE) + +set(SCP_PLATFORM_VARIANT ${SCP_PLATFORM_VARIANT_INIT} CACHE STRING + "Platform variant for the build") + +list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/product/totalcompute/tc4/module/tc4_bl1") + +list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../../common/module/tc_system") + +# The order of the modules in the following list is the order in which the +# modules are initialized, bound, started during the pre-runtime phase. +# any change in the order will cause firmware initialization errors. + +# todo: enable it later +#list(APPEND SCP_MODULES "armv8m-mpu") +list(APPEND SCP_MODULES "atu") +list(APPEND SCP_MODULES "tc4-bl1") +list(APPEND SCP_MODULES "pl011") +list(APPEND SCP_MODULES "gtimer") +list(APPEND SCP_MODULES "timer") +list(APPEND SCP_MODULES "ppu-v1") +list(APPEND SCP_MODULES "mock-ppu") +list(APPEND SCP_MODULES "system-power") +list(APPEND SCP_MODULES "mhu3") +list(APPEND SCP_MODULES "transport") +list(APPEND SCP_MODULES "scmi") +list(APPEND SCP_MODULES "sds") +list(APPEND SCP_MODULES "system-pll") +list(APPEND SCP_MODULES "pik-clock") +list(APPEND SCP_MODULES "css-clock") +list(APPEND SCP_MODULES "clock") +list(APPEND SCP_MODULES "power-domain") +list(APPEND SCP_MODULES "scmi-power-domain") +list(APPEND SCP_MODULES "scmi-system-power") +list(APPEND SCP_MODULES "dvfs") +list(APPEND SCP_MODULES "scmi-clock") +list(APPEND SCP_MODULES "scmi-perf") +list(APPEND SCP_MODULES "mock-psu") +list(APPEND SCP_MODULES "psu") +list(APPEND SCP_MODULES "tc-system") + +if (SCP_PLATFORM_VARIANT STREQUAL "1" OR SCP_PLATFORM_VARIANT STREQUAL "2") + set(SCP_ENABLE_PLUGIN_HANDLER TRUE) + set(SCP_ENABLE_SCMI_PERF_FAST_CHANNELS TRUE) +endif() diff --git a/product/totalcompute/tc4/scp_css/Toolchain-ArmClang.cmake b/product/totalcompute/tc4/scp_css/Toolchain-ArmClang.cmake new file mode 100644 index 000000000..3720e7b6d --- /dev/null +++ b/product/totalcompute/tc4/scp_css/Toolchain-ArmClang.cmake @@ -0,0 +1,20 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cmake-lint: disable=C0301 + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m85+nodsp") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../../cmake/Toolchain/ArmClang-Baremetal.cmake" +) diff --git a/product/totalcompute/tc4/scp_css/Toolchain-Clang.cmake b/product/totalcompute/tc4/scp_css/Toolchain-Clang.cmake new file mode 100644 index 000000000..d0f7a2192 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/Toolchain-Clang.cmake @@ -0,0 +1,17 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m85+nodsp") + +set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../../cmake/Toolchain/Clang-Baremetal.cmake") diff --git a/product/totalcompute/tc4/scp_css/Toolchain-GNU.cmake b/product/totalcompute/tc4/scp_css/Toolchain-GNU.cmake new file mode 100644 index 000000000..3d38c0618 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/Toolchain-GNU.cmake @@ -0,0 +1,18 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include_guard() + +set(CMAKE_SYSTEM_PROCESSOR "cortex-m85+nodsp") +set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") + +set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") +set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") + +include( + "${CMAKE_CURRENT_LIST_DIR}/../../../../cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/totalcompute/tc4/scp_css/config_armv8m_mpu.c b/product/totalcompute/tc4/scp_css/config_armv8m_mpu.c new file mode 100644 index 000000000..5430401b9 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_armv8m_mpu.c @@ -0,0 +1,86 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mod_armv8m_mpu.h" +#include "scp_mmap.h" + +#include +#include + +#include + +static const uint8_t attributes[] = { + /* Device memory, non Gathering, non Re-ordering, non Early Write + Acknowledgement */ + [MPU_ATTR_0] = + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE), + /* Normal memory, non Cacheable */ + [MPU_ATTR_1] = + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE), +}; + +static const ARM_MPU_Region_t regions[] = { + { + /* SCP_CORE_TCM_REGION*/ + .RBAR = ARM_MPU_RBAR( + SCP_CORE_ITCM_REGION_START, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 0 /* XN */), + .RLAR = ARM_MPU_RLAR(SCP_CORE_ITCM_REGION_END, MPU_ATTR_1), + }, + { + /* SCP_CORE_DTCM_REGION*/ + .RBAR = ARM_MPU_RBAR( + SCP_CORE_DTCM_REGION_START, /* BASE */ + ARM_MPU_SH_INNER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(SCP_CORE_DTCM_REGION_END, MPU_ATTR_1), + }, + { + /* SCP_CORE_PERIPHERAL_REGION */ + .RBAR = ARM_MPU_RBAR( + SCP_CORE_PERIPHERAL_REGION_START, /* BASE */ + ARM_MPU_SH_NON, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(SCP_CORE_PERIPHERAL_REGION_END, MPU_ATTR_0), + }, + { + /* SCP_SRAM_REGION*/ + .RBAR = ARM_MPU_RBAR( + SCP_SRAM_REGION_START, /* BASE */ + ARM_MPU_SH_OUTER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(SCP_SRAM_REGION_END, MPU_ATTR_1), + }, + { + /* SCP_DEVICE_REGION */ + .RBAR = ARM_MPU_RBAR( + SCP_DEVICE_REGION_START, /* BASE */ + ARM_MPU_SH_OUTER, /* SH */ + 0, /* RO */ + 0, /* NP */ + 1 /* XN */), + .RLAR = ARM_MPU_RLAR(SCP_DEVICE_REGION_END, MPU_ATTR_0), + }, +}; + +const struct fwk_module_config config_armv8m_mpu = { + .data = &((struct mod_armv8m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + .attributes_count = FWK_ARRAY_SIZE(attributes), + .attributes = attributes, + }), +}; diff --git a/product/totalcompute/tc4/scp_css/config_atu.c b/product/totalcompute/tc4/scp_css/config_atu.c new file mode 100644 index 000000000..7e367887a --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_atu.c @@ -0,0 +1,101 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#ifdef BUILD_HAS_ATU_DELEGATE +# include "scp_platform_transport.h" + +# include +#endif + +#include +#include +#include +#include + +#ifdef BUILD_HAS_ATU_MANAGE +# include "scp_mmap.h" +# include "tc4_atu.h" + +# include + +static const struct atu_region_map atu_regions[] = { + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_GTCLK_AP, + .phy_addr_base = SCP_ATU_PHY_ADDR_GTCLK_AP, + .region_size = SCP_ATU_REG_SIZE_GTCLK_AP, + .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, + }, + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_GTCLK, + .phy_addr_base = SCP_ATU_PHY_ADDR_GTCLK, + .region_size = SCP_ATU_REG_SIZE_GTCLK, + .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, + }, + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_CLUSTER_UTIL, + .phy_addr_base = SCP_ATU_PHY_ADDR_CLUSTER_UTIL, + .region_size = SCP_ATU_REG_SIZE_CLUSTER_UTIL, + .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, + }, + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_SHARED_SRAM, + .phy_addr_base = SCP_ATU_PHY_ADDR_SHARED_SRAM, + .region_size = SCP_ATU_REG_SIZE_SHARED_SRAM, + .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, + }, + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_SHARED_NSRAM, + .phy_addr_base = SCP_ATU_PHY_ADDR_SHARED_NSRAM, + .region_size = SCP_ATU_REG_SIZE_SHARED_NSRAM, + .attributes = ATU_ENCODE_ATTRIBUTES_NON_SECURE_PAS, + }, + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_ROS_SOC_BASE, + .phy_addr_base = SCP_ATU_PHY_ADDR_ROS_SOC, + .region_size = SCP_ATU_REG_SIZE_ROS_SOC, + .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, + }, + { + .region_owner_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_ATU), + .log_addr_base = SCP_ATU_LOG_ADDR_PLL, + .phy_addr_base = SCP_ATU_PHY_ADDR_PLL, + .region_size = SCP_ATU_REG_SIZE_PLL, + .attributes = ATU_ENCODE_ATTRIBUTES_SECURE_PAS, + }, +}; +#endif + +static const struct fwk_element element_table[2] = { + [0] = { + .name = "SCP_ATU", + .data = &(struct mod_atu_device_config) { +#ifdef BUILD_HAS_ATU_MANAGE + .is_atu_delegated = false, + .atu_base = SCP_ATU_BASE, + .atu_region_config_table = atu_regions, + .atu_region_count = FWK_ARRAY_SIZE(atu_regions), +#endif + }, + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +struct fwk_module_config config_atu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_clock.c b/product/totalcompute/tc4/scp_css/config_clock.c new file mode 100644 index 000000000..b38fae10a --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_clock.c @@ -0,0 +1,138 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "config_power_domain.h" +#include "tc4_core.h" + +#include +#include +#include +#include +#include + +#include +#include +#include + +static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { + [CLOCK_IDX_CPU_GROUP_NEVIS] = + { + .name = "CPU_GROUP_NEVIS", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP_NEVIS), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP_GELAS] = + { + .name = "CPU_GROUP_GELAS", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP_GELAS), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP_TRAVIS] = + { + .name = "CPU_GROUP_TRAVIS", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP_TRAVIS), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_DPU] = + { + .name = "DPU", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_DPU), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_PIXEL_0] = + { + .name = "PIXEL_0", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_PIX0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + }), + }, + [CLOCK_IDX_PIXEL_1] = + { + .name = "PIXEL_1", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_PIX1), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + }), + }, + [CLOCK_IDX_GPU] = + { + .name = "GPU", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_GPU), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + }), + }, + { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id) +{ + unsigned int i; + struct mod_clock_dev_config *dev_config; + + for (i = 0; i < CLOCK_IDX_COUNT; i++) { + dev_config = + (struct mod_clock_dev_config *)clock_dev_desc_table[i].data; + dev_config->pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + TC4_NUMBER_OF_CORES + TC4_NUMBER_OF_CLUSTERS + + PD_STATIC_DEV_IDX_SYSTOP); + } + + return clock_dev_desc_table; +} + +const struct fwk_module_config config_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(clock_get_dev_desc_table), + .data = &((struct mod_clock_config){ + .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), + .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION), + }), + +}; diff --git a/product/totalcompute/tc4/scp_css/config_css_clock.c b/product/totalcompute/tc4/scp_css/config_css_clock.c new file mode 100644 index 000000000..7f9676728 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_css_clock.c @@ -0,0 +1,309 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" + +#include +#include +#include + +#include +#include +#include +#include +#include + +static const struct mod_css_clock_rate rate_table_cpu_group_nevis[5] = { + { + /* Super Underdrive */ + .rate = 768 * FWK_MHZ, + .pll_rate = 768 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1153 * FWK_MHZ, + .pll_rate = 1153 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1537 * FWK_MHZ, + .pll_rate = 1537 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 1844 * FWK_MHZ, + .pll_rate = 1844 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2152 * FWK_MHZ, + .pll_rate = 2152 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_gelas[5] = { + { + /* Super Underdrive */ + .rate = 946 * FWK_MHZ, + .pll_rate = 946 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1419 * FWK_MHZ, + .pll_rate = 1419 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1893 * FWK_MHZ, + .pll_rate = 1893 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2271 * FWK_MHZ, + .pll_rate = 2271 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2650 * FWK_MHZ, + .pll_rate = 2650 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_travis[5] = { + { + /* Super Underdrive */ + .rate = 1088 * FWK_MHZ, + .pll_rate = 1088 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1632 * FWK_MHZ, + .pll_rate = 1632 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 2176 * FWK_MHZ, + .pll_rate = 2176 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2612 * FWK_MHZ, + .pll_rate = 2612 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 3047 * FWK_MHZ, + .pll_rate = 3047 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const fwk_id_t member_table_cpu_group_nevis[2] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), +}; + +static const fwk_id_t member_table_cpu_group_gelas[4] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5), +}; + +static const fwk_id_t member_table_cpu_group_travis[2] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7), +}; + +static const fwk_id_t member_table_dpu[1] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_DPU), +}; + +static const struct fwk_element css_clock_element_table[ + CLOCK_CSS_IDX_COUNT + 1] = { + [CLOCK_CSS_IDX_CPU_GROUP_NEVIS] = + { + .name = "CPU_GROUP_NEVIS", + .data = &((struct mod_css_clock_dev_config){ + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_nevis, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_nevis), + .clock_switching_source = + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .pll_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU_NEVIS), + .pll_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_nevis, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_nevis), + .member_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 1537 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP_GELAS] = + { + .name = "CPU_GROUP_GELAS", + .data = &((struct mod_css_clock_dev_config){ + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_gelas, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + .clock_switching_source = + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .pll_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU_GELAS), + .pll_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_gelas, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_gelas), + .member_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 1893 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP_TRAVIS] = + { + .name = "CPU_GROUP_TRAVIS", + .data = &((struct mod_css_clock_dev_config){ + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_travis, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_travis), + .clock_switching_source = + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .pll_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU_TRAVIS), + .pll_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_travis, + .member_count = + FWK_ARRAY_SIZE(member_table_cpu_group_travis), + .member_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2176 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_DPU] = + { + .name = "DPU", + .data = &((struct mod_css_clock_dev_config){ + .clock_type = MOD_CSS_CLOCK_TYPE_NON_INDEXED, + .clock_default_source = + MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, + .clock_switching_source = + MOD_PIK_CLOCK_ACLKDPU_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_DPU), + .pll_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_dpu, + .member_count = FWK_ARRAY_SIZE(member_table_dpu), + .member_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 600 * FWK_MHZ, + .modulation_supported = false, + }), + }, + [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) +{ + return css_clock_element_table; +} + +const struct fwk_module_config config_css_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(css_clock_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_dvfs.c b/product/totalcompute/tc4/scp_css/config_dvfs.c new file mode 100644 index 000000000..4b40b81f2 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_dvfs.c @@ -0,0 +1,255 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "tc4_dvfs.h" +#include "tc4_psu.h" +#include "tc4_timer.h" + +#include +#include + +#include +#include +#include +#include + +/* + * The power cost figures in this file are built using the dynamic power + * consumption formula (P = CfV^2), where C represents the capacitance of one + * processing element in the domain (a core or shader core). This power figure + * is scaled linearly with the number of processing elements in the performance + * domain to give a rough representation of the overall power draw. The + * capacitance constants are given in mW/MHz/V^2 and were taken from the Linux + * device trees, which provide a dynamic-power-coefficient field in uW/MHz/V^2. + * This conversion of units, from uW/MHz/V^2 to mW/MHz/V^2, is done by dividing + * by 1000. + */ + +/* dynamic-power-coeffient/1000 */ +#define NEVIS_DPC 0.230 +#define GELAS_DPC 0.495 +#define TRAVIS_DPC 1.054 + +static struct mod_dvfs_opp operating_points_nevis[6] = { + { + .level = 768 * 1000000UL, + .frequency = 768 * FWK_KHZ, + .voltage = 550, + .power = (uint32_t)(NEVIS_DPC * 768 * 0.550 * 0.550), + }, + { + .level = 1153 * 1000000UL, + .frequency = 1153 * FWK_KHZ, + .voltage = 650, + .power = (uint32_t)(NEVIS_DPC * 1153 * 0.650 * 0.650), + }, + { + .level = 1537 * 1000000UL, + .frequency = 1537 * FWK_KHZ, + .voltage = 750, + .power = (uint32_t)(NEVIS_DPC * 1537 * 0.750 * 0.750), + }, + { + .level = 1844 * 1000000UL, + .frequency = 1844 * FWK_KHZ, + .voltage = 850, + .power = (uint32_t)(NEVIS_DPC * 1844 * 0.850 * 0.850), + }, + { + .level = 2152 * 1000000UL, + .frequency = 2152 * FWK_KHZ, + .voltage = 950, + .power = (uint32_t)(NEVIS_DPC * 2152 * 0.950 * 0.950), + }, + { 0 } +}; + +static struct mod_dvfs_opp operating_points_gelas[6] = { + { + .level = 946 * 1000000UL, + .frequency = 946 * FWK_KHZ, + .voltage = 550, + .power = (uint32_t)(GELAS_DPC * 946 * 0.550 * 0.550), + }, + { + .level = 1419 * 1000000UL, + .frequency = 1419 * FWK_KHZ, + .voltage = 650, + .power = (uint32_t)(GELAS_DPC * 1419 * 0.650 * 0.650), + }, + { + .level = 1893 * 1000000UL, + .frequency = 1893 * FWK_KHZ, + .voltage = 750, + .power = (uint32_t)(GELAS_DPC * 1893 * 0.750 * 0.750), + }, + { + .level = 2271 * 1000000UL, + .frequency = 2271 * FWK_KHZ, + .voltage = 850, + .power = (uint32_t)(GELAS_DPC * 2271 * 0.850 * 0.850), + }, + { + .level = 2650 * 1000000UL, + .frequency = 2650 * FWK_KHZ, + .voltage = 950, + .power = (uint32_t)(GELAS_DPC * 2650 * 0.950 * 0.950), + }, + { 0 } +}; + +static struct mod_dvfs_opp operating_points_travis[6] = { + { + .level = 1088 * 1000000UL, + .frequency = 1088 * FWK_KHZ, + .voltage = 550, + .power = (uint32_t)(TRAVIS_DPC * 1088 * 0.550 * 0.550), + }, + { + .level = 1632 * 1000000UL, + .frequency = 1632 * FWK_KHZ, + .voltage = 650, + .power = (uint32_t)(TRAVIS_DPC * 1632 * 0.650 * 0.650), + }, + { + .level = 2176 * 1000000UL, + .frequency = 2176 * FWK_KHZ, + .voltage = 750, + .power = (uint32_t)(TRAVIS_DPC * 2176 * 0.750 * 0.750), + }, + { + .level = 2612 * 1000000UL, + .frequency = 2612 * FWK_KHZ, + .voltage = 850, + .power = (uint32_t)(TRAVIS_DPC * 2612 * 0.850 * 0.850), + }, + { + .level = 3047 * 1000000UL, + .frequency = 3047 * FWK_KHZ, + .voltage = 950, + .power = (uint32_t)(TRAVIS_DPC * 3047 * 0.950 * 0.950), + }, + { 0 } +}; + +static struct mod_dvfs_opp operating_points_gpu[5] = { + { + .level = 350 * 1000000UL, + .frequency = 350 * FWK_KHZ, + .voltage = 550, + }, + { + .level = 680 * 1000000UL, + .frequency = 680 * FWK_KHZ, + .voltage = 650, + }, + { + .level = 1000 * 1000000UL, + .frequency = 1000 * FWK_KHZ, + .voltage = 750, + }, + { + .level = 1260 * 1000000UL, + .frequency = 1260 * FWK_KHZ, + .voltage = 850, + }, + { 0 } +}; + +static const struct mod_dvfs_domain_config cpu_group_nevis = { + .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_NEVIS), + .clock_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_NEVIS), + .alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + TC4_CONFIG_TIMER_DVFS_CPU_NEVIS), + .retry_ms = 1, + .latency = 1200, + .sustained_idx = 2, + .opps = operating_points_nevis, +}; + +static const struct mod_dvfs_domain_config cpu_group_gelas = { + .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GELAS), + .clock_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_GELAS), + .alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + TC4_CONFIG_TIMER_DVFS_CPU_GELAS), + .retry_ms = 1, + .latency = 1200, + .sustained_idx = 2, + .opps = operating_points_gelas, +}; + +static const struct mod_dvfs_domain_config cpu_group_travis = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_TRAVIS), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_TRAVIS), + .alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + TC4_CONFIG_TIMER_DVFS_CPU_TRAVIS), + .retry_ms = 1, + .latency = 1200, + .sustained_idx = 2, + .opps = operating_points_travis, +}; + +static const struct mod_dvfs_domain_config gpu = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GPU), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_GPU), + .alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + TC4_CONFIG_TIMER_DVFS_GPU), + .retry_ms = 1, + .latency = 1200, + .sustained_idx = 2, + .opps = operating_points_gpu, +}; + +static const struct fwk_element element_table[DVFS_ELEMENT_IDX_COUNT + 1] = { + [DVFS_ELEMENT_IDX_NEVIS] = + { + .name = "CPU_GROUP_NEVIS", + .data = &cpu_group_nevis, + }, + [DVFS_ELEMENT_IDX_GELAS] = + { + .name = "CPU_GROUP_GELAS", + .data = &cpu_group_gelas, + }, + [DVFS_ELEMENT_IDX_TRAVIS] = + { + .name = "CPU_GROUP_TRAVIS", + .data = &cpu_group_travis, + }, + [DVFS_ELEMENT_IDX_GPU] = + { + .name = "GPU", + .data = &gpu, + }, + { 0 }, +}; + +static const struct fwk_element *dvfs_get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +const struct fwk_module_config config_dvfs = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(dvfs_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_fch_polled.c b/product/totalcompute/tc4/scp_css/config_fch_polled.c new file mode 100644 index 000000000..a36103a6e --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_fch_polled.c @@ -0,0 +1,226 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "tc4_dvfs.h" +#include "tc4_scmi.h" +#include "tc4_timer.h" +#include "tc_core.h" + +#include +#include + +#include +#include +#include +#include + +#include + +#define FC_LEVEL_SET_ADDR(PERF_IDX) \ + (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_SET + \ + (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) + +#define FC_LIMIT_SET_ADDR(PERF_IDX) \ + (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_SET + \ + (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) + +#define FC_LEVEL_GET_ADDR(PERF_IDX) \ + (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_GET + \ + (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) + +#define FC_LIMIT_GET_ADDR(PERF_IDX) \ + (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_GET + \ + (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) + +/* get the channel offset by itself and add the AP location */ +#define FC_LEVEL_SET_AP_ADDR(PERF_IDX) \ + (FC_LEVEL_SET_ADDR(PERF_IDX) - SCP_SCMI_PAYLOAD_NS_A2P_BASE + \ + SCP_ATU_PHY_ADDR_SHARED_NSRAM) + +#define FC_LIMIT_SET_AP_ADDR(PERF_IDX) \ + (FC_LIMIT_SET_ADDR(PERF_IDX) - SCP_SCMI_PAYLOAD_NS_A2P_BASE + \ + SCP_ATU_PHY_ADDR_SHARED_NSRAM) + +#define FC_LEVEL_GET_AP_ADDR(PERF_IDX) \ + (FC_LEVEL_GET_ADDR(PERF_IDX) - SCP_SCMI_PAYLOAD_NS_A2P_BASE + \ + SCP_ATU_PHY_ADDR_SHARED_NSRAM) + +#define FC_LIMIT_GET_AP_ADDR(PERF_IDX) \ + (FC_LIMIT_GET_ADDR(PERF_IDX) - SCP_SCMI_PAYLOAD_NS_A2P_BASE + \ + SCP_ATU_PHY_ADDR_SHARED_NSRAM) + +static struct mod_fch_polled_config module_config = { + .fch_alarm_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_TIMER, + 0, + TC4_CONFIG_TIMER_FAST_CHANNEL_TIMER_IDX), + .fch_poll_rate = FCH_MIN_POLL_RATE_US, + .rate_limit = (4 * 1000), + .attributes = 0, +}; + +enum fch_polled_length { + FCH_POLLED_LEVEL_SET_LENGTH = sizeof(uint32_t), + FCH_POLLED_LIMIT_SET_LENGTH = + sizeof(struct mod_scmi_perf_fast_channel_limit), + FCH_POLLED_LEVEL_GET_LENGTH = sizeof(uint32_t), + FCH_POLLED_LIMIT_GET_LENGTH = + sizeof(struct mod_scmi_perf_fast_channel_limit) +}; + +#define FCH_ADDR_INIT(scp_addr, ap_addr, len) \ + &((struct mod_fch_polled_channel_config){ \ + .fch_addr = { \ + .local_view_address = scp_addr, \ + .target_view_address = ap_addr, \ + .length = len, \ + } }) + +static const struct fwk_element fch_polled_element_table[] = { + [TC4_PLAT_FCH_NEVIS_LEVEL_SET] = { + .name = "FCH_NEVIS_LEVEL_SET", + .data = FCH_ADDR_INIT( + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FCH_POLLED_LEVEL_SET_LENGTH + ) + }, + [TC4_PLAT_FCH_NEVIS_LIMIT_SET] = { + .name = "FCH_NEVIS_LIMIT_SET", + .data =FCH_ADDR_INIT( + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FCH_POLLED_LIMIT_SET_LENGTH + ), + }, + [TC4_PLAT_FCH_NEVIS_LEVEL_GET] = { + .name = "FCH_NEVIS_LEVEL_GET", + .data = FCH_ADDR_INIT( + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FCH_POLLED_LEVEL_GET_LENGTH + ) + }, + [TC4_PLAT_FCH_NEVIS_LIMIT_GET] = { + .name = "FCH_NEVIS_LIMIT_GET", + .data = FCH_ADDR_INIT( + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FCH_POLLED_LIMIT_GET_LENGTH + ) + }, + [TC4_PLAT_FCH_GELAS_LEVEL_SET] = { + .name = "FCH_GELAS_LEVEL_SET", + .data = FCH_ADDR_INIT( + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FCH_POLLED_LEVEL_SET_LENGTH + ) + }, + [TC4_PLAT_FCH_GELAS_LIMIT_SET] = { + .name = "FCH_GELAS_LIMIT_SET", + .data =FCH_ADDR_INIT( + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FCH_POLLED_LIMIT_SET_LENGTH + ), + }, + [TC4_PLAT_FCH_GELAS_LEVEL_GET] = { + .name = "FCH_GELAS_LEVEL_GET", + .data = FCH_ADDR_INIT( + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FCH_POLLED_LEVEL_GET_LENGTH + ) + }, + [TC4_PLAT_FCH_GELAS_LIMIT_GET] = { + .name = "FCH_GELAS_LIMIT_GET", + .data = FCH_ADDR_INIT( + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FCH_POLLED_LIMIT_GET_LENGTH + ) + }, + [TC4_PLAT_FCH_TRAVIS_LEVEL_SET] = { + .name = "FCH_TRAVIS_LEVEL_SET", + .data = FCH_ADDR_INIT( + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FCH_POLLED_LEVEL_SET_LENGTH + ) + }, + [TC4_PLAT_FCH_TRAVIS_LIMIT_SET] = { + .name = "FCH_TRAVIS_LIMIT_SET", + .data =FCH_ADDR_INIT( + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FCH_POLLED_LIMIT_SET_LENGTH + ), + }, + [TC4_PLAT_FCH_TRAVIS_LEVEL_GET] = { + .name = "FCH_TRAVIS_LEVEL_GET", + .data = FCH_ADDR_INIT( + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FCH_POLLED_LEVEL_GET_LENGTH + ) + }, + [TC4_PLAT_FCH_TRAVIS_LIMIT_GET] = { + .name = "FCH_TRAVIS_LIMIT_GET", + .data = FCH_ADDR_INIT( + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FCH_POLLED_LIMIT_GET_LENGTH + ) + }, + [TC4_PLAT_FCH_GPU_LEVEL_SET] = { + .name = "FCH_GPU_LEVEL_SET", + .data = FCH_ADDR_INIT( + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_GPU), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + FCH_POLLED_LEVEL_SET_LENGTH + ) + }, + [TC4_PLAT_FCH_GPU_LIMIT_SET] = { + .name = "FCH_GPU_LIMIT_SET", + .data =FCH_ADDR_INIT( + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_GPU), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + FCH_POLLED_LIMIT_SET_LENGTH + ), + }, + [TC4_PLAT_FCH_GPU_LEVEL_GET] = { + .name = "FCH_GPU_LEVEL_GET", + .data = FCH_ADDR_INIT( + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_GPU), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + FCH_POLLED_LEVEL_GET_LENGTH + ) + }, + [TC4_PLAT_FCH_GPU_LIMIT_GET] = { + .name = "FCH_GPU_LIMIT_GET", + .data = FCH_ADDR_INIT( + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_GPU), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_GPU), + FCH_POLLED_LIMIT_GET_LENGTH + ) + }, + + [TC4_PLAT_FCH_COUNT] = {0}, +}; + +static const struct fwk_element *fch_polled_get_element_table( + fwk_id_t module_id) +{ + return fch_polled_element_table; +} + +const struct fwk_module_config config_fch_polled = { + .data = &module_config, + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(fch_polled_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_gtimer.c b/product/totalcompute/tc4/scp_css/config_gtimer.c new file mode 100644 index 000000000..7853d6506 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_gtimer.c @@ -0,0 +1,44 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_mmap.h" + +#include +#include + +#include +#include +#include +#include + +/* + * Generic timer driver config + */ +static const struct fwk_element gtimer_dev_table[2] = { + [0] = { .name = "GTCLK", + .data = &((struct mod_gtimer_dev_config){ + .hw_timer = SCP_GTCLK_CNTBASE0_BASE, + .hw_counter = SCP_GTCLK_CNTCTL_BASE, + .control = SCP_GTCLK_CNTCONTROL_BASE, + .frequency = CLOCK_RATE_GTCLK, + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_NEVIS), + }), + }, + [1] = { 0 }, +}; + +const struct fwk_module_config config_gtimer = { + .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(gtimer_dev_table), +}; + +struct fwk_time_driver fmw_time_driver(const void **ctx) +{ + return mod_gtimer_driver(ctx, config_gtimer.elements.table[0].data); +} diff --git a/product/totalcompute/tc4/scp_css/config_mhu3.c b/product/totalcompute/tc4/scp_css/config_mhu3.c new file mode 100644 index 000000000..a82cac3dc --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_mhu3.c @@ -0,0 +1,96 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "scp_mmap.h" +#include "scp_tc_mhu3.h" + +#include + +#include +#include +#include + +#include + +#include + +struct mod_mhu3_channel_config ap_s_channels[] = { + MOD_MHU3_INIT_DBCH( + /* PBX CH */ 0, + /* FLAG */ 0, + /* MBX CH */ 0, + /* FLAG */ 0), +}; +struct mod_mhu3_channel_config ap_ns_channels[] = { + MOD_MHU3_INIT_DBCH( + /* PBX CH */ 0, + /* FLAG */ 0, + /* MBX CH */ 0, + /* FLAG */ 0), + MOD_MHU3_INIT_DBCH( + /* PBX CH */ 0, + /* FLAG */ 1, + /* MBX CH */ 0, + /* FLAG */ 1), +}; +/* RSS uses final doorbell channel for SCP signalling */ +struct mod_mhu3_channel_config scp_rss_channel_config[1] = { + MOD_MHU3_INIT_DBCH( + /* PBX CH */ SCP_MHU_SCP_RSS_NUM_DBCH - 1, + /* FLAG */ 0, + /* MBX CH */ SCP_MHU_SCP_RSS_NUM_DBCH - 1, + /* FLAG */ 0), +}; + +static const struct fwk_element element_table[ + SCP_TC_MHU3_DEVICE_IDX_COUNT + 1] = { + [SCP_TC_MHU3_DEVICE_IDX_SCP_AP_S] = { + .name = "MHU_SCP_AP_S", + .sub_element_count = 1, + .data = &(struct mod_mhu3_device_config) { + .irq = AP_SCP_MHU0_REC_IRQ, + .in = SCP_MHU_SCP_AP_RCV_S, + .out = SCP_MHU_SCP_AP_SND_S, + .channels = ap_s_channels, + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + .resp_wait_timeout_us = (100 * 1000u), + }, + }, + [SCP_TC_MHU3_DEVICE_IDX_SCP_AP_NS] = { + .name = "MHU_SCP_AP_NS", + .sub_element_count = 2, + .data = &(struct mod_mhu3_device_config) { + .irq = AP_SCP_MHU4_REC_IRQ, + .in = SCP_MHU_SCP_AP_RCV_NS, + .out = SCP_MHU_SCP_AP_SND_NS, + .channels = ap_ns_channels, + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + .resp_wait_timeout_us = (100 * 1000u), + }, + }, + [SCP_TC_MHU3_DEVICE_IDX_SCP_RSS_S] = { + .name = "MHU_SCP_RSS_S", + .sub_element_count = 1, + .data = &(struct mod_mhu3_device_config) { + .irq = RSS_SCP_MHU0_REC_IRQ, + .in = SCP_MHU_SCP_RSS_RCV_S_CLUS0, + .out = SCP_MHU_SCP_RSS_SND_S_CLUS0, + .channels = scp_rss_channel_config, + .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0), + .resp_wait_timeout_us = (100 * 1000u), + }, + }, + [SCP_TC_MHU3_DEVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +const struct fwk_module_config config_mhu3 = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_mock_ppu.c b/product/totalcompute/tc4/scp_css/config_mock_ppu.c new file mode 100644 index 000000000..3902094c7 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_mock_ppu.c @@ -0,0 +1,52 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "tc4_mock_ppu.h" + +#include +#include + +#include + +/* Need to pass an allocated memory region + * to the mock PPU which it can then access. It + * only accesses the first word so that is all + * we need */ +static uint32_t sys0_mock_ppu, gpucgrp_mock_ppu; + +static struct fwk_element \ +mock_ppu_system_element_table[MOCK_PPU_ELEMENT_IDX_COUNT+1] = { + [MOCK_PPU_ELEMENT_IDX_SYS0] = + { + .name = "SYS0", + .data = &((struct mod_mock_ppu_pd_config){ + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = (uintptr_t)&sys0_mock_ppu, + }), + }, + [MOCK_PPU_ELEMENT_IDX_GPUCGRP] = + { + .name = "GPUCGRP", + .data = &((struct mod_mock_ppu_pd_config){ + .pd_type = MOD_PD_TYPE_DEVICE, + .ppu.reg_base = (uintptr_t)&gpucgrp_mock_ppu, + }), + }, + [MOCK_PPU_ELEMENT_IDX_COUNT] = {0}, +}; + +static const struct fwk_element *mock_ppu_get_element_table(fwk_id_t module_id) +{ + return mock_ppu_system_element_table; +} +/* + * Power module configuration data + */ +const struct fwk_module_config config_mock_ppu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(mock_ppu_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_mock_psu.c b/product/totalcompute/tc4/scp_css/config_mock_psu.c new file mode 100644 index 000000000..170985088 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_mock_psu.c @@ -0,0 +1,82 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = { + [MOCK_PSU_ELEMENT_IDX_NEVIS] = { + .name = "DVFS_GROUP_NEVIS", + .data = + &(const struct mod_mock_psu_element_cfg){ + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 550, + }, + }, + [MOCK_PSU_ELEMENT_IDX_GELAS] = { + .name = "DVFS_GROUP_GELAS", + .data = + &(const struct mod_mock_psu_element_cfg){ + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 550, + }, + }, + [MOCK_PSU_ELEMENT_IDX_TRAVIS] = { + .name = "DVFS_GROUP_TRAVIS", + .data = + &(const struct mod_mock_psu_element_cfg){ + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 550, + }, + }, + [MOCK_PSU_ELEMENT_IDX_GPU] = { + .name = "DVFS_GROUP_GPU", + .data = + &(const struct mod_mock_psu_element_cfg){ + .async_alarm_id = FWK_ID_NONE_INIT, + .async_alarm_api_id = FWK_ID_NONE_INIT, + + .async_response_id = FWK_ID_NONE_INIT, + .async_response_api_id = FWK_ID_NONE_INIT, + + .default_enabled = true, + .default_voltage = 550, + }, + }, + { 0 } +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +const struct fwk_module_config config_mock_psu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_mpmm.c b/product/totalcompute/tc4/scp_css/config_mpmm.c new file mode 100644 index 000000000..943346d54 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_mpmm.c @@ -0,0 +1,296 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "tc4_dvfs.h" +#include "tc4_timer.h" +#include "tc_amu.h" + +#include +#include + +#include +#include +#include + +enum cpu_idx { + CORE0_IDX, + CORE1_IDX, + CORE2_IDX, + CORE3_IDX, + CORE4_IDX, + CORE5_IDX, + CORE6_IDX, + CORE7_IDX +}; + +static struct mod_mpmm_pct_table nevis_pct[] = { + { + .cores_online = 2, + .default_perf_limit = 1844 * 1000000UL, + .num_perf_limits = 2, + .threshold_perf = { + { + .threshold_bitmap = 0x22, + .perf_limit = 1844 * 1000000UL, + }, + { + .threshold_bitmap = 0x21, + .perf_limit = 2152 * 1000000UL, + }, + }, + }, + { + .cores_online = 1, + .default_perf_limit = 2152 * 1000000UL, + .num_perf_limits = 1, + .threshold_perf = { + { + .threshold_bitmap = 0x2, + .perf_limit = 2152 * 1000000UL, + }, + }, + }, +}; + +static struct mod_mpmm_pct_table gelas_pct[] = { + { + .cores_online = 4, + .default_perf_limit = 1419 * 1000000UL, + .num_perf_limits = 4, + .threshold_perf = { + { + .threshold_bitmap = 0x2222, + .perf_limit = 1419 * 1000000UL, + }, + { + .threshold_bitmap = 0x2211, + .perf_limit = 1893 * 1000000UL, + }, + { + .threshold_bitmap = 0x2111, + .perf_limit = 2271 * 1000000UL, + }, + { + .threshold_bitmap = 0x1111, + .perf_limit = 2650 * 1000000UL, + }, + }, + }, + { + .cores_online = 3, + .default_perf_limit = 1893 * 1000000UL, + .num_perf_limits = 3, + .threshold_perf = { + { + .threshold_bitmap = 0x222, + .perf_limit = 1893 * 1000000UL, + }, + { + .threshold_bitmap = 0x221, + .perf_limit = 2271 * 1000000UL, + }, + { + .threshold_bitmap = 0x211, + .perf_limit = 2650 * 1000000UL, + }, + }, + }, + { + .cores_online = 2, + .default_perf_limit = 2271 * 1000000UL, + .num_perf_limits = 2, + .threshold_perf = { + { + .threshold_bitmap = 0x21, + .perf_limit = 2271 * 1000000UL, + }, + { + .threshold_bitmap = 0x11, + .perf_limit = 2650 * 1000000UL, + }, + }, + }, + { + .cores_online = 1, + .default_perf_limit = 2650 * 1000000UL, + .num_perf_limits = 1, + .threshold_perf = { + { + .threshold_bitmap = 0x2, + .perf_limit = 2650 * 1000000UL, + }, + }, + }, +}; + +static struct mod_mpmm_pct_table travis_pct[] = { + { + .cores_online = 2, + .default_perf_limit = 2176 * 1000000UL, + .num_perf_limits = 3, + .threshold_perf = { + { + .threshold_bitmap = 0x22, + .perf_limit = 2176 * 1000000UL, + }, + { + .threshold_bitmap = 0x21, + .perf_limit = 2612 * 1000000UL, + }, + { + .threshold_bitmap = 0x11, + .perf_limit = 3047 * 1000000UL, + }, + }, + }, + { + .cores_online = 1, + .default_perf_limit = 3047 * 1000000UL, + .num_perf_limits = 1, + .threshold_perf = { + { + .threshold_bitmap = 0x2, + .perf_limit = 3047 * 1000000UL, + }, + }, + }, +}; + +static const struct mod_mpmm_core_config nevis_core_config[] = { + [0] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE0_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE0_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE0_IDX, AMEVCNTR1_AUX0), + }, + [1] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE1_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE1_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE1_IDX, AMEVCNTR1_AUX0), + }, +}; + +static const struct mod_mpmm_core_config gelas_core_config[] = { + [0] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE2_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE2_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE2_IDX, AMEVCNTR1_AUX0), + }, + [1] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE3_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE3_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE3_IDX, AMEVCNTR1_AUX0), + }, + [2] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE4_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE4_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE4_IDX, AMEVCNTR1_AUX0), + }, + [3] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE5_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE5_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE5_IDX, AMEVCNTR1_AUX0), + }, +}; + +static const struct mod_mpmm_core_config travis_core_config[] = { + [0] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE6_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE6_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE6_IDX, AMEVCNTR1_AUX0), + }, + [1] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE7_IDX), + .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE7_IDX), + .core_starts_online = false, + .base_aux_counter_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_AMU_MMAP, CORE7_IDX, AMEVCNTR1_AUX0), + }, +}; + +static const struct mod_mpmm_domain_config nevis_domain_conf[] = { + [0] = { + .perf_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_NEVIS), + .pct = nevis_pct, + .pct_size = FWK_ARRAY_SIZE(nevis_pct), + .btc = 10, + .num_threshold_counters = 3, + .core_config = nevis_core_config, + }, + [1] = {0}, +}; + +static const struct mod_mpmm_domain_config gelas_domain_conf[] = { + [0] = { + .perf_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GELAS), + .pct = gelas_pct, + .pct_size = FWK_ARRAY_SIZE(gelas_pct), + .btc = 10, + .num_threshold_counters = 3, + .core_config = gelas_core_config, + }, + [1] = {0}, +}; + +static const struct mod_mpmm_domain_config travis_domain_conf[] = { + [0] = { + .perf_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_TRAVIS), + .pct = travis_pct, + .pct_size = FWK_ARRAY_SIZE(travis_pct), + .btc = 10, + .num_threshold_counters = 3, + .core_config = travis_core_config, + }, + [1] = {0}, +}; + +static const struct fwk_element element_table[] = { + [0] = { + .name = "MPMM_NEVIS_ELEM", + .sub_element_count = FWK_ARRAY_SIZE(nevis_core_config), + .data = nevis_domain_conf, + }, + [1] = { + .name = "MPMM_GELAS_ELEM", + .sub_element_count = FWK_ARRAY_SIZE(gelas_core_config), + .data = gelas_domain_conf, + }, + [2] = { + .name = "MPMM_TRAVIS_ELEM", + .sub_element_count = FWK_ARRAY_SIZE(travis_core_config), + .data = travis_domain_conf, + }, + [3] = { 0 }, +}; + +static const struct fwk_element *mpmm_get_element_table(fwk_id_t module_id) +{ + return element_table; +} +const struct fwk_module_config config_mpmm = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(mpmm_get_element_table), + .data = (const void *)(&(fwk_id_t)FWK_ID_API_INIT( + FWK_MODULE_IDX_AMU_MMAP, + MOD_AMU_MMAP_API_IDX_AMU)), +}; diff --git a/product/totalcompute/tc4/scp_css/config_pik_clock.c b/product/totalcompute/tc4/scp_css/config_pik_clock.c new file mode 100644 index 000000000..88d7c3dda --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_pik_clock.c @@ -0,0 +1,267 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "cpu_pik.h" +#include "dpu_pik.h" +#include "scp_pik.h" +#include "system_pik.h" + +#include + +#include +#include +#include +#include + +/* + * Rate lookup tables + */ +static const struct mod_pik_clock_rate rate_table_cpu_group_nevis[1] = { + { + .rate = 1537 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static const struct mod_pik_clock_rate rate_table_cpu_group_gelas[1] = { + { + .rate = 1893 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static const struct mod_pik_clock_rate rate_table_cpu_group_travis[1] = { + { + .rate = 2176 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static const struct mod_pik_clock_rate rate_table_gicclk[1] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_pclkscp[1] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_sysperclk[1] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_uartclk[1] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_dpu[1] = { + { + .rate = 600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via display PLL */ + }, +}; + +static const struct fwk_element pik_clock_element_table[ + CLOCK_PIK_IDX_COUNT + 1] = { + + [CLOCK_PIK_IDX_CLUS0_CPU0] = { + .name = "CLUS0_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[0].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_nevis, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_nevis), + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU1] = { + .name = "CLUS0_CPU1", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[1].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[1].MOD, + .rate_table = rate_table_cpu_group_nevis, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_nevis), + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU2] = { + .name = "CLUS0_CPU2", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[2].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[2].MOD, + .rate_table = rate_table_cpu_group_gelas, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU3] = { + .name = "CLUS0_CPU3", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[3].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[3].MOD, + .rate_table = rate_table_cpu_group_gelas, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU4] = { + .name = "CLUS0_CPU4", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[4].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[4].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[4].MOD, + .rate_table = rate_table_cpu_group_gelas, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU5] = { + .name = "CLUS0_CPU5", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[5].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[5].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[5].MOD, + .rate_table = rate_table_cpu_group_gelas, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU6] = { + .name = "CLUS0_CPU6", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[6].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[6].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[6].MOD, + .rate_table = rate_table_cpu_group_travis, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_travis), + }), + }, + [CLOCK_PIK_IDX_CLUS0_CPU7] = { + .name = "CLUS0_CPU7", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR->CORECLK[7].CTRL, + .divext_reg = &CLUSTER_PIK_PTR->CORECLK[7].DIV, + .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[7].MOD, + .rate_table = rate_table_cpu_group_travis, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_travis), + }), + }, + [CLOCK_PIK_IDX_GIC] = { + .name = "GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, + .rate_table = rate_table_gicclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_PCLKSCP] = { + .name = "PCLKSCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->PCLKSCP_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->PCLKSCP_DIV1, + .rate_table = rate_table_pclkscp, + .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_SYSPERCLK] = { + .name = "SYSPERCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, + .rate_table = rate_table_sysperclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_UARTCLK] = { + .name = "UARTCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->UARTCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->UARTCLK_DIV1, + .rate_table = rate_table_uartclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_DPU] = { + .name = "DPU", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = true, + .control_reg = &DPU_PIK_PTR->ACLKDP_CTRL, + .divsys_reg = &DPU_PIK_PTR->ACLKDP_DIV1, + .divext_reg = &DPU_PIK_PTR->ACLKDP_DIV2, + .rate_table = rate_table_dpu, + .rate_count = FWK_ARRAY_SIZE(rate_table_dpu), + .initial_rate = 600 * FWK_MHZ, + .defer_initialization = true, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) +{ + return pik_clock_element_table; +} + +const struct fwk_module_config config_pik_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_power_domain.c b/product/totalcompute/tc4/scp_css/config_power_domain.c new file mode 100644 index 000000000..aa2aec08b --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_power_domain.c @@ -0,0 +1,125 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_power_domain.h" +#include "tc4_ppu_v1.h" +#include "tc4_core.h" +#include "tc4_mock_ppu.h" +#include "tc_power_domain.h" + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Maximum power domain name size including the null terminator */ +#define PD_NAME_SIZE 12 + +/* Mask of the allowed states for the systop power domain */ +static const uint32_t systop_allowed_state_mask_table[1] = { + [0] = MOD_PD_STATE_ON_MASK +}; + +/* Mask of the allowed states for the gputop power domain depending on the + * system states. + */ +static const uint32_t gputop_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK +}; + +/* + * Mask of the allowed states for the cluster power domain depending on the + * system states. + */ +static const uint32_t cluster_pd_allowed_state_mask_table[2] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = TC_CLUSTER_VALID_STATE_MASK, +}; + +/* Mask of the allowed states for a core depending on the cluster states. */ +static const uint32_t core_pd_allowed_state_mask_table[2] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MOD_PD_STATE_ON] = TC_CORE_VALID_STATE_MASK, +}; + +/* Power module specific configuration data (none) */ +static const struct mod_power_domain_config tc4_power_domain_config = { 0 }; + +static struct fwk_element tc4_power_domain_static_element_table[] = { + [PD_STATIC_DEV_IDX_GPUTOP] = + { + .name = "GPUCGRP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_DEVICE, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_MOCK_PPU, + MOCK_PPU_ELEMENT_IDX_GPUCGRP), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PPU, + 0), + .allowed_state_mask_table = gputop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(gputop_allowed_state_mask_table) }), + }, + [PD_STATIC_DEV_IDX_SYSTOP] = + { + .name = "SYSTOP", + .data = &((struct mod_power_domain_element_config){ + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .parent_idx = PD_STATIC_DEV_IDX_NONE, + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) }), + }, +}; + +/* + * Function definitions with internal linkage + */ +static const struct fwk_element *tc4_power_domain_get_element_table( + fwk_id_t module_id) +{ + return create_power_domain_element_table( + TC4_NUMBER_OF_CORES, + TC4_NUMBER_OF_CLUSTERS, + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER, + core_pd_allowed_state_mask_table, + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table), + cluster_pd_allowed_state_mask_table, + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table), + tc4_power_domain_static_element_table, + FWK_ARRAY_SIZE(tc4_power_domain_static_element_table)); +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_power_domain = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tc4_power_domain_get_element_table), + .data = &tc4_power_domain_config, +}; diff --git a/product/totalcompute/tc4/scp_css/config_ppu_v1.c b/product/totalcompute/tc4/scp_css/config_ppu_v1.c new file mode 100644 index 000000000..c6d9b1dc6 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_ppu_v1.c @@ -0,0 +1,133 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_power_domain.h" +#include "tc4_ppu_v1.h" +#include "scp_mmap.h" +#include "tc4_core.h" + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Maximum PPU core name size including the null terminator */ +#define PPU_CORE_NAME_SIZE 12 + +/* Maximum PPU cluster name size including the null terminator */ +#define PPU_CLUS_NAME_SIZE 6 + +/* Cluster ID for Theodul DSU */ +#define CLUSTER_ID 0 + +/* Module configuration data */ +static struct mod_ppu_v1_config ppu_v1_config_data = { + .pd_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), +}; + +static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) +{ + struct fwk_element *element_table, *element; + struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; + unsigned char core_idx; + unsigned int core_count; + unsigned int cluster_count; + unsigned int core_element_count = 0; + + core_count = TC4_NUMBER_OF_CORES; + cluster_count = TC4_NUMBER_OF_CLUSTERS; + + /* + * Allocate element descriptors based on: + * Number of cores + * + Number of cluster descriptors + * + Number of system power domain descriptors + * + 1 terminator descriptor + */ + element_table = fwk_mm_calloc( + core_count + cluster_count + 1, + sizeof(struct fwk_element)); + if (element_table == NULL) { + return NULL; + } + + pd_config_table = fwk_mm_calloc( + core_count + cluster_count, sizeof(struct mod_ppu_v1_pd_config)); + if (pd_config_table == NULL) { + return NULL; + } + + for (core_idx = 0; + core_idx < TC4_NUMBER_OF_CORES; + core_idx++) { + element = &element_table[core_element_count]; + pd_config = &pd_config_table[core_element_count]; + + element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); + if (element->name == NULL) { + return NULL; + } + + (void)snprintf( + (char *)element->name, PPU_CORE_NAME_SIZE, "CORE%u", core_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CORE; + pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(core_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->cluster_id = + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, core_count); + pd_config->observer_id = FWK_ID_NONE; + core_element_count++; + } + + element = &element_table[core_count]; + pd_config = &pd_config_table[core_count]; + + element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); + if (element->name == NULL) { + return NULL; + } + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CLUSTER; + pd_config->ppu.reg_base = SCP_PPU_CLUSTER_BASE; + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->observer_id = FWK_ID_NONE; + + /* + * Configure pd_source_id with the SYSTOP identifier from the power domain + * module which is dynamically defined based on the number of cores. + */ + ppu_v1_config_data.pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + core_count + cluster_count + PD_STATIC_DEV_IDX_SYSTOP); + + return element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_ppu_v1 = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(ppu_v1_get_element_table), + .data = &ppu_v1_config_data, +}; diff --git a/product/totalcompute/tc4/scp_css/config_psu.c b/product/totalcompute/tc4/scp_css/config_psu.c new file mode 100644 index 000000000..d42206c88 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_psu.c @@ -0,0 +1,70 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +static const struct fwk_element element_table[PSU_ELEMENT_IDX_COUNT + 1] = { + [PSU_ELEMENT_IDX_NEVIS] = { + .name = "PSU_GROUP_NEVIS", + .data = + &(const struct mod_psu_element_cfg){ + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, + MOCK_PSU_ELEMENT_IDX_NEVIS), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER) }, + }, + [PSU_ELEMENT_IDX_GELAS] = { + .name = "PSU_GROUP_GELAS", + .data = + &(const struct mod_psu_element_cfg){ + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, + MOCK_PSU_ELEMENT_IDX_GELAS), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER) }, + }, + [PSU_ELEMENT_IDX_TRAVIS] = { + .name = "PSU_GROUP_TRAVIS", + .data = + &(const struct mod_psu_element_cfg){ + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, + MOCK_PSU_ELEMENT_IDX_TRAVIS), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER) }, + }, + [PSU_ELEMENT_IDX_GPU] = { + .name = "PSU_GROUP_GPU", + .data = + &(const struct mod_psu_element_cfg){ + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, + MOCK_PSU_ELEMENT_IDX_GPU), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER) }, + }, + { 0 } +}; + +static const struct fwk_element *psu_get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +const struct fwk_module_config config_psu = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(psu_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_reg_sensor.c b/product/totalcompute/tc4/scp_css/config_reg_sensor.c new file mode 100644 index 000000000..cec866e28 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_reg_sensor.c @@ -0,0 +1,49 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include + +#include +#include + +static uint64_t fake_sensor_register = UINT64_C(0x0); + +/* + * Register Sensor driver config + */ +static struct mod_sensor_info info_fake_temperature = { + .type = MOD_SENSOR_TYPE_DEGREES_C, + .update_interval = 0, + .update_interval_multiplier = 0, + .unit_multiplier = 0, +}; + +static const struct fwk_element reg_sensor_element_table[] = { + [0] = { + .name = "Fake Temperature Sensor Register", + .data = &((struct mod_reg_sensor_dev_config) { + .reg = (uintptr_t)(&fake_sensor_register), + .info = &info_fake_temperature, + }), + }, + + [1] = { 0 }, /* Termination description */ +}; + +static const struct fwk_element *get_reg_sensor_element_table(fwk_id_t id) +{ + return reg_sensor_element_table; +} + +struct fwk_module_config config_reg_sensor = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_reg_sensor_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_resource_perms.c b/product/totalcompute/tc4/scp_css/config_resource_perms.c new file mode 100644 index 000000000..33db650fe --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_resource_perms.c @@ -0,0 +1,115 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "tc4_scmi.h" + +#include +#include + +#include +#include +#include +#include +#include + +/*! + * If the agent wants to modify permissions at run-time these tables + * must be allocated in writable memory. + */ + +#define AGENT_IDX(agent_id) (agent_id - 1) + +static struct mod_res_agent_protocol_permissions agent_protocol_permissions[2] = { + [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = { + .protocols = MOD_RES_PERMS_SCMI_ALL_PROTOCOLS_ALLOWED, + }, + + /* PSCI agent has no access to clock, perf and sensor protocol */ + [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = { + .protocols = MOD_RES_PERMS_SCMI_CLOCK_PROTOCOL_DENIED | + MOD_RES_PERMS_SCMI_PERF_PROTOCOL_DENIED | + MOD_RES_PERMS_SCMI_SENSOR_PROTOCOL_DENIED, + }, +}; + +/* + * Messages have an index offset from 0x3 as all agents can access + * the VERSION/ATTRIBUTES/MSG_ATTRIBUTES messages for all + * protocols, hence message 0x3 maps to bit[0], message 0x4 maps + * to bit[1], etc. + */ +static struct mod_res_agent_msg_permissions + agent_msg_permissions[2] = { + [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = { + .messages = { + [MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = + 0x0, + [MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = + 0x0, + }, + }, + [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = { + .messages = { + [MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = + 0x0, + [MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = + ((1 + << (MOD_SCMI_PERF_DOMAIN_ATTRIBUTES - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (0 + << (MOD_SCMI_PERF_DESCRIBE_LEVELS - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LIMITS_SET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LIMITS_GET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LEVEL_SET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LEVEL_GET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_NOTIFY_LIMITS - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_NOTIFY_LEVEL - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_DESCRIBE_FAST_CHANNEL - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES))), + /* Clocks, no access */ + [MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0xff, + [MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, + [MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = + 0x0, + }, + }, + }; + +static struct mod_res_agent_permission agent_permissions = { + .agent_protocol_permissions = agent_protocol_permissions, + .agent_msg_permissions = agent_msg_permissions, +}; + +struct fwk_module_config config_resource_perms = { + .data = + &(struct mod_res_resource_perms_config){ + .agent_permissions = (uintptr_t)&agent_permissions, + .agent_count = SCP_SCMI_AGENT_ID_COUNT, + .protocol_count = 6, + }, +}; diff --git a/product/totalcompute/tc4/scp_css/config_scmi.c b/product/totalcompute/tc4/scp_css/config_scmi.c new file mode 100644 index 000000000..b373b4ca1 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_scmi.c @@ -0,0 +1,119 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "tc4_scmi.h" + +#include +#include + +#include +#include +#include +#include +#include + +static const struct fwk_element service_table[ + SCP_TC4_SCMI_SERVICE_IDX_COUNT + 1] = { + [SCP_TC4_SCMI_SERVICE_IDX_PSCI] = { + .name = "PSCI", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_TRANSPORT, + SCP_TC4_SCMI_SERVICE_IDX_PSCI), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_API_IDX_SCMI_TO_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }), + }, + [SCP_TC4_SCMI_SERVICE_IDX_OSPM_A2P] = { + .name = "OSPM_A2P", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_TRANSPORT, + SCP_TC4_SCMI_SERVICE_IDX_OSPM_A2P), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_API_IDX_SCMI_TO_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, +#ifdef BUILD_HAS_SCMI_NOTIFICATIONS + .scmi_p2a_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SCMI, + SCP_TC4_SCMI_SERVICE_IDX_OSPM_P2A), +#else + .scmi_p2a_id = FWK_ID_NONE_INIT, +#endif + }), + }, +#ifdef BUILD_HAS_SCMI_NOTIFICATIONS + [SCP_TC4_SCMI_SERVICE_IDX_OSPM_P2A] = { + .name = "OSPM_P2A", + .data = &(struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_TRANSPORT, + SCP_TC4_SCMI_SERVICE_IDX_OSPM_P2A), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_API_IDX_SCMI_TO_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_TRANSPORT, + MOD_TRANSPORT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }, + }, +#endif + [SCP_TC4_SCMI_SERVICE_IDX_COUNT] = { 0 } +}; + +static const struct fwk_element *get_service_table(fwk_id_t module_id) +{ + return service_table; +} + +#ifndef BUILD_HAS_MOD_RESOURCE_PERMS + +/* PSCI agent has no access to clock, perf and sensor protocol */ +static const uint32_t dis_protocol_list_psci[3] = { + MOD_SCMI_PROTOCOL_ID_SENSOR, + MOD_SCMI_PROTOCOL_ID_CLOCK, + MOD_SCMI_PROTOCOL_ID_PERF, +}; +#endif + +static struct mod_scmi_agent agent_table[SCP_SCMI_AGENT_ID_COUNT] = { + [SCP_SCMI_AGENT_ID_OSPM] = { + .type = SCMI_AGENT_TYPE_OSPM, + .name = "OSPM", + }, + [SCP_SCMI_AGENT_ID_PSCI] = { + .type = SCMI_AGENT_TYPE_PSCI, + .name = "PSCI", + }, +}; + +const struct fwk_module_config config_scmi = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_service_table), + .data = &((struct mod_scmi_config){ + .protocol_count_max = 9, +#ifndef BUILD_HAS_MOD_RESOURCE_PERMS + .dis_protocol_count_psci = FWK_ARRAY_SIZE(dis_protocol_list_psci), + .dis_protocol_list_psci = dis_protocol_list_psci, +#endif + .agent_count = FWK_ARRAY_SIZE(agent_table) - 1, + .agent_table = agent_table, + .vendor_identifier = "arm", + .sub_vendor_identifier = "arm", + }), +}; diff --git a/product/totalcompute/tc4/scp_css/config_scmi_perf.c b/product/totalcompute/tc4/scp_css/config_scmi_perf.c new file mode 100644 index 000000000..996bac26f --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_scmi_perf.c @@ -0,0 +1,123 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "tc4_dvfs.h" +#include "tc4_scmi.h" +#include "tc4_timer.h" + +#include + +#include +#include + +#include +#include + +#include + +static const struct mod_scmi_perf_domain_config + domains[DVFS_ELEMENT_IDX_COUNT] = { + [DVFS_ELEMENT_IDX_NEVIS] = { +# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + .fch_config = (struct scmi_perf_fch_config[]) { + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_GET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_GET), + }, + .supports_fast_channels = true, +# endif + }, + [DVFS_ELEMENT_IDX_GELAS] = { +# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + .fch_config = (struct scmi_perf_fch_config[]) { + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_GET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_GET), + }, + .supports_fast_channels = true, +# endif + }, + [DVFS_ELEMENT_IDX_TRAVIS] = { +# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + .fch_config = (struct scmi_perf_fch_config[]) { + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_GET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_GET), + }, + .supports_fast_channels = true, +# endif + }, + [DVFS_ELEMENT_IDX_GPU] = { +# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + .fch_config = (struct scmi_perf_fch_config[]) { + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_SET), + [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_GET), + [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_GET), + }, + .supports_fast_channels = true, +# endif + }, + }; + +#if (PLATFORM_VARIANT == TC4_VAR_EXPERIMENT_POWER) +static const struct mod_scmi_plugin_config plugins_table[] = { + [0] = { + .id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_TRAFFIC_COP), + .dom_type = PERF_PLUGIN_DOM_TYPE_PHYSICAL, + }, + [1] = { + .id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MPMM), + .dom_type = PERF_PLUGIN_DOM_TYPE_PHYSICAL, + }, + [2] = { + .id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_THERMAL_MGMT), + .dom_type = PERF_PLUGIN_DOM_TYPE_FULL, + }, +}; +#elif (PLATFORM_VARIANT == TC4_VAR_MPMM) +static const struct mod_scmi_plugin_config plugins_table[] = { + [0] = { + .id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MPMM), + .dom_type = PERF_PLUGIN_DOM_TYPE_PHYSICAL, + }, +}; +#else +static const struct mod_scmi_plugin_config plugins_table[] = { +}; +#endif + +const struct fwk_module_config config_scmi_perf = { + .data = &((struct mod_scmi_perf_config){ + .domains = &domains, + .perf_doms_count = FWK_ARRAY_SIZE(domains), +#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + .fast_channels_rate_limit = (4 * 1000), +#endif + .plugins = plugins_table, + .plugins_count = FWK_ARRAY_SIZE(plugins_table), + }), +}; diff --git a/product/totalcompute/tc4/scp_css/config_sds.c b/product/totalcompute/tc4/scp_css/config_sds.c new file mode 100644 index 000000000..8c8735735 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_sds.c @@ -0,0 +1,85 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_mmap.h" +#include "scp_pik.h" +#include "tc_sds.h" + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +static const uint32_t feature_flags = TC_SDS_FEATURE_FIRMWARE_MASK; + +static const struct mod_sds_region_desc sds_module_regions[1] = { + [TC_SDS_REGION_SECURE] = { + .base = (void *)SCP_SDS_MEM_BASE, + .size = SCP_SDS_MEM_SIZE, + }, +}; + +static_assert( + FWK_ARRAY_SIZE(sds_module_regions) == TC_SDS_REGION_COUNT, + "Mismatch between number of SDS regions and number of regions " + "provided by the SDS configuration."); + +const struct mod_sds_config sds_module_config = { + .regions = sds_module_regions, + .region_count = TC_SDS_REGION_COUNT, + .clock_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_NEVIS) +}; + +static struct fwk_element sds_element_table[3] = { + { + .name = "CPU Info", + .data = &((struct mod_sds_structure_desc){ + .id = TC_SDS_CPU_INFO, + .size = TC_SDS_CPU_INFO_SIZE, + .region_id = TC_SDS_REGION_SECURE, + .finalize = true, + }), + }, + { + .name = "Feature Availability", + .data = &((struct mod_sds_structure_desc){ + .id = TC_SDS_FEATURE_AVAILABILITY, + .size = TC_SDS_FEATURE_AVAILABILITY_SIZE, + .payload = &feature_flags, + .region_id = TC_SDS_REGION_SECURE, + .finalize = true, + }), + }, + { 0 }, /* Termination description. */ +}; + +static_assert( + SCP_SDS_MEM_SIZE > TC_SDS_CPU_INFO_SIZE + TC_SDS_FEATURE_AVAILABILITY_SIZE, + "SDS structures too large for SDS SRAM.\n"); + +static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) +{ + static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size"); + + return sds_element_table; +} + +struct fwk_module_config config_sds = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(sds_get_element_table), + .data = &sds_module_config, +}; diff --git a/product/totalcompute/tc4/scp_css/config_sensor.c b/product/totalcompute/tc4/scp_css/config_sensor.c new file mode 100644 index 000000000..c64b2f6f6 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_sensor.c @@ -0,0 +1,44 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * When running on a model at least one fake sensor is required in order to + * properly initialize the entire sensor support. + */ +static const struct fwk_element sensor_element_table[2] = { + [0] = { + .name = "Fake sensor", + .data = &((struct mod_sensor_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_REG_SENSOR, 0), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_REG_SENSOR, 0), + }), + }, + + [1] = { 0 } /* Termination description */ +}; + +static const struct fwk_element *get_sensor_element_table(fwk_id_t module_id) +{ + return sensor_element_table; +} + +struct fwk_module_config config_sensor = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_sensor_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_system_pll.c b/product/totalcompute/tc4/scp_css/config_system_pll.c new file mode 100644 index 000000000..effd4ae75 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_system_pll.c @@ -0,0 +1,139 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_soc.h" +#include "scp_mmap.h" +#include "scp_pik.h" + +#include + +#include +#include +#include +#include + +static const struct fwk_element system_pll_element_table[ + CLOCK_PLL_IDX_COUNT + 1] = + { + [CLOCK_PLL_IDX_CPU_NEVIS] = + { + .name = "CPU_PLL_NEVIS", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_CPU0, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(0), + .initial_rate = 1537 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU_GELAS] = + { + .name = "CPU_PLL_GELAS", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_CPU1, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(4), + .initial_rate = 1893 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU_TRAVIS] = + { + .name = "CPU_PLL_TRAVIS", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_CPU2, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(4), + .initial_rate = 2176 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_SYS] = + { + .name = "SYS_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_SYSPLL, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_SYSPLL_LOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_DPU] = + { + .name = "DPU_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_DISPLAY, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_DISPLAYPLL_LOCK, + .initial_rate = 600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + .defer_initialization = false, + }), + }, + [CLOCK_PLL_IDX_PIX0] = + { + .name = "PIX0_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_PIX0, + .status_reg = NULL, + .initial_rate = 594 * FWK_MHZ, + .min_rate = 12500 * FWK_KHZ, + .max_rate = 594 * FWK_MHZ, + .min_step = 25 * FWK_KHZ, + .defer_initialization = false, + }), + }, + [CLOCK_PLL_IDX_PIX1] = + { + .name = "PIX1_PLL", + .data = &( + (struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_PIX1, + .status_reg = NULL, + .initial_rate = 594 * FWK_MHZ, + .min_rate = 12500 * FWK_KHZ, + .max_rate = 594 * FWK_MHZ, + .min_step = 25 * FWK_KHZ, + .defer_initialization = false, + }), + }, + [CLOCK_PLL_IDX_GPU] = + { + .name = "GPU_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_GPU, + .status_reg = NULL, + .initial_rate = 800 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + .defer_initialization = false, + }), + }, + [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ + }; + +static const struct fwk_element *system_pll_get_element_table( + fwk_id_t module_id) +{ + return system_pll_element_table; +} + +const struct fwk_module_config config_system_pll = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_system_power.c b/product/totalcompute/tc4/scp_css/config_system_power.c new file mode 100644 index 000000000..a4dcfddf6 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_system_power.c @@ -0,0 +1,76 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "tc4_mock_ppu.h" + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +static const uint8_t + system_power_to_sys_ppu0_state[MOD_SYSTEM_POWER_POWER_STATE_COUNT] = { + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_OFF, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, + }; + +static struct fwk_element system_power_element_table[2] = { + [0] = + { + .name = "SYS-PPU-0", + .data = &((struct mod_system_power_dev_config){ + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PPU, + MOCK_PPU_ELEMENT_IDX_SYS0), + .sys_state_table = system_power_to_sys_ppu0_state, + }), + }, + [1] = { 0 }, /* Termination description */ +}; + +static struct mod_system_power_config system_power_config = { + .soc_wakeup_irq = SOC_WAKEUP0_IRQ, + + /* System driver */ + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_TC_SYSTEM), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TC_SYSTEM, + MOD_TC_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER), + + /* Initial system state */ + .initial_system_power_state = MOD_PD_STATE_OFF, +}; + +static const struct fwk_element *tc_system_get_element_table(fwk_id_t unused) +{ + struct mod_system_power_dev_config *dev_config_table; + + dev_config_table = + (struct mod_system_power_dev_config *)system_power_element_table[0] + .data; + dev_config_table->sys_ppu_id = + fwk_id_build_element_id(fwk_module_id_mock_ppu, 0); + + return system_power_element_table; +} + +const struct fwk_module_config config_system_power = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tc_system_get_element_table), + .data = &system_power_config, +}; diff --git a/product/totalcompute/tc4/scp_css/config_tc4_bl1.c b/product/totalcompute/tc4/scp_css/config_tc4_bl1.c new file mode 100644 index 000000000..e09384502 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_tc4_bl1.c @@ -0,0 +1,26 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "tc4_core.h" + +#include + +#include +#include +#include + +const struct fwk_module_config config_tc4_bl1 = { + .data = &((struct mod_tc4_bl1_config){ + .ap_context_base = SCP_AP_CONTEXT_BASE, + .ap_context_size = SCP_AP_CONTEXT_SIZE, + .id_primary_cluster = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + TC4_CORES_PER_CLUSTER), + .id_primary_core = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, 0), + }) +}; diff --git a/product/totalcompute/tc4/scp_css/config_tc4_power_model.c b/product/totalcompute/tc4/scp_css/config_tc4_power_model.c new file mode 100644 index 000000000..4a43f1f1e --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_tc4_power_model.c @@ -0,0 +1,36 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +static const struct fwk_element pm_elem_table[] = { + [0] = { + .name = "Power Model 0", + .data = &(struct mod_tc4_power_model_dev_config){ + .coeff = 1, + }, + }, + [1] = { + .name = "Power Model 1", + .data = &(struct mod_tc4_power_model_dev_config){ + .coeff = 1, + }, + }, + [2] = { 0 } /* Termination description */ +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return pm_elem_table; +}; + +const struct fwk_module_config config_tc4_power_model = { + .data = NULL, + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_thermal_mgmt.c b/product/totalcompute/tc4/scp_css/config_thermal_mgmt.c new file mode 100644 index 000000000..2f05ce568 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_thermal_mgmt.c @@ -0,0 +1,71 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include +#include +#include + +#include +#include + +static struct mod_thermal_mgmt_actor_config actor_table_domain0[2] = { + [0] = { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC4_POWER_MODEL, 0), + .dvfs_domain_id = + FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_NEVIS), + .weight = 100, + }, + [1] = { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC4_POWER_MODEL, 1), + .dvfs_domain_id = + FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GELAS), + .weight = 100, + }, +}; + +static const struct fwk_element thermal_mgmt_domains_elem_table[2] = { + [0] = { + .name = "Thermal Domain 0", + .data = &((struct mod_thermal_mgmt_dev_config){ + .slow_loop_mult = 25, + .tdp = 10, + .cold_state_power = 11, + .pid_controller = { + .switch_on_temperature = 50, + .control_temperature = 60, + .integral_cutoff = 0, + .integral_max = 100, + .k_p_undershoot = 1, + .k_p_overshoot = 1, + .k_integral = 1, + }, + .sensor_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SENSOR, 0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TC4_POWER_MODEL, + MOD_TC4_POWER_MODEL_THERMAL_DRIVER_API_IDX), + .thermal_actors_table = actor_table_domain0, + .thermal_actors_count = FWK_ARRAY_SIZE(actor_table_domain0), + }), + }, + [1] = { 0 } /* Termination description */ +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return thermal_mgmt_domains_elem_table; +} + +struct fwk_module_config config_thermal_mgmt = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_timer.c b/product/totalcompute/tc4/scp_css/config_timer.c new file mode 100644 index 000000000..65e38e9cf --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_timer.c @@ -0,0 +1,42 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "tc4_timer.h" + +#include + +#include +#include +#include +#include + +#include + +/* + * Timer HAL config + */ +static const struct fwk_element timer_dev_table[2] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config){ + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = SOC_SYS_TIM0_S_IRQ, + }), + /* Number of alarms */ + .sub_element_count = TC4_CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT, + }, + [1] = { 0 }, +}; + +static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) +{ + return timer_dev_table; +} + +const struct fwk_module_config config_timer = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(timer_get_dev_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_traffic_cop.c b/product/totalcompute/tc4/scp_css/config_traffic_cop.c new file mode 100644 index 000000000..023d0c292 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_traffic_cop.c @@ -0,0 +1,96 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "scp_mmap.h" +#include "tc4_dvfs.h" +#include "tc4_timer.h" + +#include + +#include +#include +#include + +enum cpu_idx { + CORE0_PD_IDX, + CORE1_PD_IDX, + CORE2_PD_IDX, + CORE3_PD_IDX, + CORE4_PD_IDX, + CORE5_PD_IDX, + CORE6_PD_IDX, + CORE7_PD_IDX +}; + +static struct mod_tcop_pct_table nevis_pct[3] = { + { + /* + * Perf limit for 4 cores online. + * The first entry must be the maximum number of cores in this domain. + */ + .cores_online = 4, + .perf_limit = 1537 * 1000000UL, + }, + { + /* Perf limit for 2 cores online. */ + .cores_online = 3, + .perf_limit = 1844 * 1000000UL, + }, + { + /* Perf limit for 2 cores online. */ + .cores_online = 2, + .perf_limit = 2152 * 1000000UL, + }, +}; + +static const struct mod_tcop_core_config nevis_core_config[4] = { + [0] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE0_PD_IDX), + .core_starts_online = true, + }, + [1] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE1_PD_IDX), + .core_starts_online = false, + }, + [2] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE2_PD_IDX), + .core_starts_online = false, + }, + [3] = { + .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE3_PD_IDX), + .core_starts_online = false, + }, +}; + +static const struct mod_tcop_domain_config nevis_domain_conf[2] = { + [0] = { + .perf_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_DVFS, + DVFS_ELEMENT_IDX_NEVIS), + .pct = nevis_pct, + .pct_size = FWK_ARRAY_SIZE(nevis_pct), + .core_config = nevis_core_config, + }, + [1] = { { 0 } }, +}; + +static const struct fwk_element element_table[2] = { + [0] = { + .name = "TCOP_NEVIS", + .sub_element_count = 4, + .data = nevis_domain_conf, + }, + [1] = { 0 }, +}; + +static const struct fwk_element *tcop_get_element_table(fwk_id_t module_id) +{ + return element_table; +} +const struct fwk_module_config config_traffic_cop = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tcop_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/config_transport.c b/product/totalcompute/tc4/scp_css/config_transport.c new file mode 100644 index 000000000..230cce090 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/config_transport.c @@ -0,0 +1,419 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_power_domain.h" +#include "scp_mmap.h" +#include "scp_tc_mhu3.h" +#include "tc4_core.h" +#include "tc4_scmi.h" +#include "tc4_transport.h" + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +static const struct fwk_element transport_element_table[ +#ifdef BUILD_HAS_MOD_TRANSPORT_FC + TC4_TRANSPORT_CHANNELS_COUNT + 1] = { + [TC4_TRANSPORT_SCMI_SERVICE_PSCI] = { +#else + SCP_TC4_TRANSPORT_SERVICE_IDX_COUNT + 1] = { + [SCP_TC4_TRANSPORT_SERVICE_IDX_PSCI] = { +#endif + .name = "PSCI", + .data = &(( + struct mod_transport_channel_config){ + .channel_type = MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .policies = + MOD_TRANSPORT_POLICY_INIT_MAILBOX | + MOD_TRANSPORT_POLICY_SECURE, + .out_band_mailbox_address = (uintptr_t) + SCP_SCMI_PAYLOAD_S_A2P_BASE, + .out_band_mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU3, + SCP_TC_MHU3_DEVICE_IDX_SCP_AP_S, + 0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU3, + 0), + }), + }, +#ifdef BUILD_HAS_MOD_TRANSPORT_FC + [TC4_TRANSPORT_SCMI_SERVICE_OSPM_A2P] = { +#else + [SCP_TC4_TRANSPORT_SERVICE_IDX_OSPM_A2P] = { +#endif + .name = "OSPM_A2P", + .data = &(( + struct mod_transport_channel_config){ + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .policies = + MOD_TRANSPORT_POLICY_INIT_MAILBOX, + .out_band_mailbox_address = (uintptr_t) + SCP_SCMI_PAYLOAD_NS_A2P_BASE, + .out_band_mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU3, + SCP_TC_MHU3_DEVICE_IDX_SCP_AP_NS, + 0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU3, + 0), + }), + }, +#ifdef BUILD_HAS_SCMI_NOTIFICATIONS +# ifdef BUILD_HAS_MOD_TRANSPORT_FC + [TC4_TRANSPORT_SCMI_SERVICE_OSPM_P2A] = { +# else + [SCP_TC4_SCMI_SERVICE_IDX_OSPM_P2A] = { +# endif + .name = "OSPM_P2A", + .data = &(( + struct mod_transport_channel_config){ + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_REQUESTER, + .policies = + MOD_TRANSPORT_POLICY_INIT_MAILBOX, + .out_band_mailbox_address = (uintptr_t) + SCP_SCMI_PAYLOAD_NS_P2A_BASE, + .out_band_mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU3, + SCP_TC_MHU3_DEVICE_IDX_SCP_AP_NS, + 1), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU3, + 0), + }), + }, +#endif +#ifdef BUILD_HAS_MOD_TRANSPORT_FC + [TC4_TRANSPORT_SCMI_SERVICE_IDX_SCP2RSS] = { +#else + [SCP_TC4_TRANSPORT_SERVICE_IDX_SCP2RSS] = { +#endif + .name = "SCP2RSS_EVENT", + .data = &(( + struct mod_transport_channel_config) { + .transport_type = MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_NONE, + .signal_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TC4_BL1, + MOD_TC4_BL1_API_TRANSPORT_FIRMWARE_SIGNAL_INPUT), + .driver_id = + FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU3, + SCP_TC_MHU3_DEVICE_IDX_SCP_RSS_S, + 0), + .driver_api_id = + FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU3, + MOD_MHU3_API_IDX_TRANSPORT_DRIVER), + }), + }, +#ifdef BUILD_HAS_MOD_TRANSPORT_FC + [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_SET] = { + .name = "FCH_NEVIS_LEVEL_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_NEVIS_LEVEL_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_SET] = { + .name = "FCH_NEVIS_LIMIT_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_NEVIS_LIMIT_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_GET] = { + .name = "FCH_NEVIS_LEVEL_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_NEVIS_LEVEL_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_GET] = { + .name = "FCH_NEVIS_LIMIT_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_NEVIS_LIMIT_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_SET] = { + .name = "FCH_GELAS_LEVEL_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GELAS_LEVEL_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_SET] = { + .name = "FCH_GELAS_LIMIT_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GELAS_LIMIT_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_GET] = { + .name = "FCH_GELAS_LEVEL_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GELAS_LEVEL_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_GET] = { + .name = "FCH_GELAS_LIMIT_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GELAS_LIMIT_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_SET] = { + .name = "FCH_TRAVIS_LEVEL_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_TRAVIS_LEVEL_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_SET] = { + .name = "FCH_TRAVIS_LIMIT_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_TRAVIS_LIMIT_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_GET] = { + .name = "FCH_TRAVIS_LEVEL_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_TRAVIS_LEVEL_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_GET] = { + .name = "FCH_TRAVIS_LIMIT_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_TRAVIS_LIMIT_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_SET] = { + .name = "FCH_GPU_LEVEL_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GPU_LEVEL_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_SET] = { + .name = "FCH_GPU_LIMIT_SET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GPU_LIMIT_SET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_GET] = { + .name = "FCH_GPU_LEVEL_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GPU_LEVEL_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, + [TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_GET] = { + .name = "FCH_GPU_LIMIT_GET", + .data = &(( + struct mod_transport_channel_config){ + .transport_type = + MOD_TRANSPORT_CHANNEL_TRANSPORT_TYPE_FAST_CHANNELS, + .channel_type = + MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_FCH_POLLED, + TC4_PLAT_FCH_GPU_LIMIT_GET), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_FCH_POLLED, + MOD_FCH_POLLED_API_IDX_TRANSPORT), + }), + }, +#endif +#ifdef BUILD_HAS_MOD_TRANSPORT_FC + [TC4_TRANSPORT_CHANNELS_COUNT] = { 0 }, +#else + [SCP_TC4_TRANSPORT_SERVICE_IDX_COUNT] = { 0 }, +#endif +}; + +static const struct fwk_element *transport_get_element_table(fwk_id_t module_id) +{ + unsigned int idx; + struct mod_transport_channel_config *config; + +#ifdef BUILD_HAS_MOD_TRANSPORT_FC + for (idx = 0; idx < TC4_TRANSPORT_CHANNELS_COUNT; idx++) { +#else + for (idx = 0; idx < SCP_TC4_TRANSPORT_SERVICE_IDX_SCP2RSS; idx++) { +#endif + config = + (struct mod_transport_channel_config *)(transport_element_table[idx] + .data); + config->pd_source_id = FWK_ID_ELEMENT( + FWK_MODULE_IDX_POWER_DOMAIN, + TC4_NUMBER_OF_CORES + TC4_NUMBER_OF_CLUSTERS + + PD_STATIC_DEV_IDX_SYSTOP); + } + + return transport_element_table; +} + +const struct fwk_module_config config_transport = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(transport_get_element_table), +}; diff --git a/product/totalcompute/tc4/scp_css/fmw_memory.h b/product/totalcompute/tc4/scp_css/fmw_memory.h new file mode 100644 index 000000000..b6b418f99 --- /dev/null +++ b/product/totalcompute/tc4/scp_css/fmw_memory.h @@ -0,0 +1,22 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Runtime firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "scp_mmap.h" + +#define FMW_MEM_MODE ARCH_MEM_MODE_SINGLE_REGION + +/* Runtime FW memory */ +#define FMW_MEM0_BASE SCP_BOOT_BASE +#define FMW_MEM0_SIZE SCP_BOOT_SIZE + +#endif /* FMW_MEMORY_H */ diff --git a/product/totalcompute/tc4/scp_css/fmw_notification.h b/product/totalcompute/tc4/scp_css/fmw_notification.h new file mode 100644 index 000000000..c40b2d0ea --- /dev/null +++ b/product/totalcompute/tc4/scp_css/fmw_notification.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware notification configuration. + */ + +#ifndef FMW_NOTIFICATION_H +#define FMW_NOTIFICATION_H + +#define FMW_NOTIFICATION_MAX 128 + +#endif /* FMW_NOTIFICATION_H */ -- GitLab From 7f557008408117f237eb85e21584511e9c6c81c7 Mon Sep 17 00:00:00 2001 From: Jing Han Date: Mon, 25 Dec 2023 10:17:14 +0000 Subject: [PATCH 02/13] tc4: Subscribe notification from tc4_bl1 in ppu This logic is copied from scp_boot to scp_css. The ppu is the sole subscriber for tc4_bl1. In tc4_bl1, it will communicate with rss after it receives response from the subscriber. Signed-off-by: Jing Han --- product/totalcompute/tc4/scp_css/config_ppu_v1.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/product/totalcompute/tc4/scp_css/config_ppu_v1.c b/product/totalcompute/tc4/scp_css/config_ppu_v1.c index c6d9b1dc6..e9d37e925 100644 --- a/product/totalcompute/tc4/scp_css/config_ppu_v1.c +++ b/product/totalcompute/tc4/scp_css/config_ppu_v1.c @@ -12,6 +12,7 @@ #include #include +#include #include #include @@ -37,8 +38,9 @@ /* Module configuration data */ static struct mod_ppu_v1_config ppu_v1_config_data = { .pd_notification_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_POWER_DOMAIN, - MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), + FWK_MODULE_IDX_TC4_BL1, + MOD_TC4_BL1_NOTIFICATION_IDX_POWER_SYSTOP), + .pd_source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_TC4_BL1), }; static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) @@ -113,14 +115,6 @@ static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) pd_config->ppu.irq = FWK_INTERRUPT_NONE; pd_config->observer_id = FWK_ID_NONE; - /* - * Configure pd_source_id with the SYSTOP identifier from the power domain - * module which is dynamically defined based on the number of cores. - */ - ppu_v1_config_data.pd_source_id = fwk_id_build_element_id( - fwk_module_id_power_domain, - core_count + cluster_count + PD_STATIC_DEV_IDX_SYSTOP); - return element_table; } -- GitLab From 71b30122be193d5d72420537b8e3b1df6af39448 Mon Sep 17 00:00:00 2001 From: Jing Han Date: Tue, 9 Jan 2024 16:24:46 +0000 Subject: [PATCH 03/13] tc4: (1/2) copy module tc_system from common to tc4 for modifications The primary cluster and core is powered on from tc4_bl1 when it receives message from rss. Do not power on the primary cluster and core in module tc_system. This initial commit is to copy module tc_system from common to tc4 directory. Signed-off-by: Jing Han Signed-off-by: Noe Galea-Sevilla --- .../tc4/module/tc_system/CMakeLists.txt | 17 ++ .../tc4/module/tc_system/Module.cmake | 10 + .../module/tc_system/include/mod_tc_system.h | 64 +++++ .../tc4/module/tc_system/src/mod_tc_system.c | 237 ++++++++++++++++++ .../totalcompute/tc4/scp_css/Firmware.cmake | 2 +- 5 files changed, 329 insertions(+), 1 deletion(-) create mode 100644 product/totalcompute/tc4/module/tc_system/CMakeLists.txt create mode 100644 product/totalcompute/tc4/module/tc_system/Module.cmake create mode 100644 product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h create mode 100644 product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c diff --git a/product/totalcompute/tc4/module/tc_system/CMakeLists.txt b/product/totalcompute/tc4/module/tc_system/CMakeLists.txt new file mode 100644 index 000000000..e085dc81d --- /dev/null +++ b/product/totalcompute/tc4/module/tc_system/CMakeLists.txt @@ -0,0 +1,17 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +add_library(${SCP_MODULE_TARGET} SCP_MODULE) + +target_include_directories(${SCP_MODULE_TARGET} + PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") + +target_sources(${SCP_MODULE_TARGET} + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_tc_system.c") + +target_link_libraries(${SCP_MODULE_TARGET} + PRIVATE module-clock module-sds module-power-domain module-ppu-v1 + module-scmi module-system-power) diff --git a/product/totalcompute/tc4/module/tc_system/Module.cmake b/product/totalcompute/tc4/module/tc_system/Module.cmake new file mode 100644 index 000000000..fe7d3fcf8 --- /dev/null +++ b/product/totalcompute/tc4/module/tc_system/Module.cmake @@ -0,0 +1,10 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(SCP_MODULE "tc-system") + +set(SCP_MODULE_TARGET "module-tc-system") diff --git a/product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h b/product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h new file mode 100644 index 000000000..c88c2ffc7 --- /dev/null +++ b/product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * TC System Support + */ + +#ifndef MOD_TC_SYSTEM_H +#define MOD_TC_SYSTEM_H + +#include + +/*! + * \addtogroup GroupTCModule TC Product Modules + * \{ + */ + +/*! + * \defgroup GroupTCSystem TC System Support + * \{ + */ + +/*! + * \brief Additional TC system power states. + */ +enum mod_tc_system_power_states { + MOD_TC_SYSTEM_POWER_STATE_SLEEP0 = MOD_PD_STATE_COUNT, + MOD_TC_SYSTEM_POWER_STATE_SLEEP1, + MOD_TC_SYSTEM_POWER_STATE_COUNT +}; + +/*! + * \brief System power state masks. + */ +enum mod_tc_system_power_state_masks { + MOD_TC_SYSTEM_POWER_STATE_SLEEP0_MASK = + (1 << MOD_TC_SYSTEM_POWER_STATE_SLEEP0), + MOD_TC_SYSTEM_POWER_STATE_SLEEP1_MASK = + (1 << MOD_TC_SYSTEM_POWER_STATE_SLEEP1), +}; + +/*! + * \brief Indices of the interfaces exposed by the module. + */ +enum mod_tc_system_api_idx { + /*! API index for the driver interface of the SYSTEM POWER module */ + MOD_TC_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER, + + /*! Number of exposed interfaces */ + MOD_TC_SYSTEM_API_COUNT +}; + +/*! + * \} + */ + +/*! + * \} + */ + +#endif /* MOD_TC_SYSTEM_H */ diff --git a/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c b/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c new file mode 100644 index 000000000..19f8344b7 --- /dev/null +++ b/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c @@ -0,0 +1,237 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * TC System Support. + */ + +#include "clock_soc.h" +#include "scp_pik.h" +#include "tc_core.h" +#include "tc_scmi.h" +#include "tc_sds.h" + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/* SCMI services required to enable the messaging stack */ +static unsigned int scmi_notification_table[1] = { + (unsigned int)SCP_TC_SCMI_SERVICE_IDX_PSCI, +}; + +/* Module context */ +struct tc_system_ctx { + /* Pointer to the Interrupt Service Routine API of the PPU_V1 module */ + const struct ppu_v1_isr_api *ppu_v1_isr_api; + + /* Power domain module restricted API pointer */ + struct mod_pd_restricted_api *mod_pd_restricted_api; + + /* SDS API pointer */ + const struct mod_sds_api *sds_api; +}; + +struct tc_system_isr { + unsigned int interrupt; + void (*handler)(void); +}; + +static struct tc_system_ctx mod_ctx; + +static const uint32_t feature_flags = + (TC_SDS_FEATURE_FIRMWARE_MASK | TC_SDS_FEATURE_DMC_MASK | + TC_SDS_FEATURE_MESSAGING_MASK); + +static fwk_id_t sds_feature_availability_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, 1); + +/* + * SCMI Messaging stack + */ + +static int messaging_stack_ready(void) +{ + const struct mod_sds_structure_desc *sds_structure_desc = + fwk_module_get_data(sds_feature_availability_id); + + /* + * Write SDS Feature Availability to signal the completion of the messaging + * stack + */ + return mod_ctx.sds_api->struct_write( + sds_structure_desc->id, + 0, + (void *)(&feature_flags), + sds_structure_desc->size); +} + +/* + * System power's driver API + */ + +static int tc_system_shutdown(enum mod_pd_system_shutdown system_shutdown) +{ + NVIC_SystemReset(); + + return FWK_E_DEVICE; +} + +static const struct mod_system_power_driver_api + tc_system_system_power_driver_api = { + .system_shutdown = tc_system_shutdown, + }; + +/* + * Functions fulfilling the framework's module interface + */ + +static int tc_system_mod_init( + fwk_id_t module_id, + unsigned int unused, + const void *unused2) +{ + return FWK_SUCCESS; +} + +static int tc_system_bind(fwk_id_t id, unsigned int round) +{ + int status; + + if (round > 0) { + return FWK_SUCCESS; + } + + status = fwk_module_bind( + FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), + FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), + &mod_ctx.mod_pd_restricted_api); + if (status != FWK_SUCCESS) { + return status; + } + + status = fwk_module_bind( + FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1), + FWK_ID_API(FWK_MODULE_IDX_PPU_V1, MOD_PPU_V1_API_IDX_ISR), + &mod_ctx.ppu_v1_isr_api); + if (status != FWK_SUCCESS) { + return status; + } + + return fwk_module_bind( + fwk_module_id_sds, FWK_ID_API(FWK_MODULE_IDX_SDS, 0), &mod_ctx.sds_api); +} + +static int tc_system_process_bind_request( + fwk_id_t requester_id, + fwk_id_t pd_id, + fwk_id_t api_id, + const void **api) +{ + *api = &tc_system_system_power_driver_api; + return FWK_SUCCESS; +} + +static int tc_system_start(fwk_id_t id) +{ + int status; + unsigned int i; + + /* + * Subscribe to these SCMI channels in order to know when they have all + * initialized. + * At that point we can consider the SCMI stack to be initialized from + * the point of view of the PSCI agent. + */ + for (i = 0; i < FWK_ARRAY_SIZE(scmi_notification_table); i++) { + status = fwk_notification_subscribe( + mod_scmi_notification_id_initialized, + fwk_id_build_element_id( + fwk_module_id_scmi, scmi_notification_table[i]), + id); + if (status != FWK_SUCCESS) { + return status; + } + } + + /* + * Subscribe to the SDS initialized notification so we can correctly let the + * PSCI agent know that the SCMI stack is initialized. + */ + status = fwk_notification_subscribe( + mod_sds_notification_id_initialized, fwk_module_id_sds, id); + if (status != FWK_SUCCESS) { + return status; + } + + return mod_ctx.mod_pd_restricted_api->set_state( + FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), + MOD_PD_SET_STATE_NO_RESP, + MOD_PD_COMPOSITE_STATE( + MOD_PD_LEVEL_2, + 0, + MOD_PD_STATE_ON, + MOD_PD_STATE_ON, + MOD_PD_STATE_ON)); +} + +static int tc_system_process_notification( + const struct fwk_event *event, + struct fwk_event *resp_event) +{ + static unsigned int scmi_notification_count = 0; + static bool sds_notification_received = false; + + fwk_assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE)); + + if (fwk_id_is_equal(event->id, mod_scmi_notification_id_initialized)) { + scmi_notification_count++; + } else if (fwk_id_is_equal( + event->id, mod_sds_notification_id_initialized)) { + sds_notification_received = true; + } else { + return FWK_E_PARAM; + } + + if ((scmi_notification_count == FWK_ARRAY_SIZE(scmi_notification_table)) && + sds_notification_received) { + messaging_stack_ready(); + + scmi_notification_count = 0; + sds_notification_received = false; + } + + return FWK_SUCCESS; +} + +const struct fwk_module module_tc_system = { + .type = FWK_MODULE_TYPE_DRIVER, + .api_count = MOD_TC_SYSTEM_API_COUNT, + .init = tc_system_mod_init, + .bind = tc_system_bind, + .process_bind_request = tc_system_process_bind_request, + .process_notification = tc_system_process_notification, + .start = tc_system_start, +}; + +const struct fwk_module_config config_tc_system = { 0 }; diff --git a/product/totalcompute/tc4/scp_css/Firmware.cmake b/product/totalcompute/tc4/scp_css/Firmware.cmake index e09b083f8..137f67123 100644 --- a/product/totalcompute/tc4/scp_css/Firmware.cmake +++ b/product/totalcompute/tc4/scp_css/Firmware.cmake @@ -40,7 +40,7 @@ set(SCP_PLATFORM_VARIANT ${SCP_PLATFORM_VARIANT_INIT} CACHE STRING list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/product/totalcompute/tc4/module/tc4_bl1") -list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../../common/module/tc_system") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/product/totalcompute/tc4/module/tc_system") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. -- GitLab From 41e72b1f7774bb682b6fd7f600a1e455923fdf41 Mon Sep 17 00:00:00 2001 From: Jing Han Date: Tue, 9 Jan 2024 16:28:59 +0000 Subject: [PATCH 04/13] tc4: (2/2) in tc_system module, do not power on the primary cluster and core The primary cluster and core is powered on from tc4_bl1 when it receives message from rss. Signed-off-by: Jing Han --- product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c b/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c index 19f8344b7..c3c5ccf6a 100644 --- a/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c +++ b/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c @@ -191,8 +191,8 @@ static int tc_system_start(fwk_id_t id) MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON, - MOD_PD_STATE_ON, - MOD_PD_STATE_ON)); + MOD_PD_STATE_OFF, + MOD_PD_STATE_OFF)); } static int tc_system_process_notification( -- GitLab From 1b5e6b21212f37bcfa3ae8705aebf08b8d5365ce Mon Sep 17 00:00:00 2001 From: Noe Galea-Sevilla Date: Mon, 9 Sep 2024 15:42:54 +0100 Subject: [PATCH 05/13] tc4: Add macro to rename CPUs The current SCP code contains hard-coded CPU names in different places. This commmit adds macros to centralize all core renaming needs. Signed-off-by: Noe Galea-Sevilla --- product/totalcompute/tc4/include/clock_soc.h | 32 +++--- product/totalcompute/tc4/include/tc4_core.h | 4 + product/totalcompute/tc4/include/tc4_dvfs.h | 6 +- .../totalcompute/tc4/include/tc4_mock_psu.h | 6 +- product/totalcompute/tc4/include/tc4_psu.h | 6 +- product/totalcompute/tc4/include/tc4_scmi.h | 50 ++++----- product/totalcompute/tc4/include/tc4_timer.h | 6 +- product/totalcompute/tc4/include/tc_core.h | 6 +- .../totalcompute/tc4/scp_css/CMakeLists.txt | 2 +- .../totalcompute/tc4/scp_css/config_clock.c | 18 +-- .../tc4/scp_css/config_css_clock.c | 90 +++++++-------- .../totalcompute/tc4/scp_css/config_dvfs.c | 106 +++++++++--------- .../tc4/scp_css/config_fch_polled.c | 96 ++++++++-------- .../totalcompute/tc4/scp_css/config_gtimer.c | 2 +- .../tc4/scp_css/config_mock_psu.c | 13 ++- .../totalcompute/tc4/scp_css/config_mpmm.c | 60 +++++----- .../tc4/scp_css/config_pik_clock.c | 44 ++++---- product/totalcompute/tc4/scp_css/config_psu.c | 18 +-- .../tc4/scp_css/config_scmi_perf.c | 49 ++++---- product/totalcompute/tc4/scp_css/config_sds.c | 5 +- .../tc4/scp_css/config_system_pll.c | 12 +- .../tc4/scp_css/config_thermal_mgmt.c | 4 +- .../tc4/scp_css/config_traffic_cop.c | 18 +-- .../tc4/scp_css/config_transport.c | 72 ++++++------ 24 files changed, 366 insertions(+), 359 deletions(-) diff --git a/product/totalcompute/tc4/include/clock_soc.h b/product/totalcompute/tc4/include/clock_soc.h index fdf9868e8..7cb6897e9 100644 --- a/product/totalcompute/tc4/include/clock_soc.h +++ b/product/totalcompute/tc4/include/clock_soc.h @@ -22,9 +22,9 @@ * PLL clock indexes. */ enum clock_pll_idx { - CLOCK_PLL_IDX_CPU_NEVIS, - CLOCK_PLL_IDX_CPU_GELAS, - CLOCK_PLL_IDX_CPU_TRAVIS, + CLOCK_PLL_IDX_CPU_GROUP_LITTLE, + CLOCK_PLL_IDX_CPU_GROUP_MID, + CLOCK_PLL_IDX_CPU_GROUP_BIG, CLOCK_PLL_IDX_SYS, CLOCK_PLL_IDX_DPU, CLOCK_PLL_IDX_PIX0, @@ -58,28 +58,28 @@ enum clock_pik_idx { */ enum mod_clusclock_source_tc4 { /*! The clock is gated */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_GATED = 0x0, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_GATED = 0x0, /*! The clock source is set to the system reference clock */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_SYSREFCLK = 0x1, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_SYSREFCLK = 0x1, /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0 = 0x2, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0 = 0x2, /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1 = 0x4, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1 = 0x4, /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2 = 0x8, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2 = 0x8, /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL3 = 0x10, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL3 = 0x10, /*! Number of valid clock sources */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_MAX + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_MAX }; /* * CSS clock indexes. */ enum clock_css_idx { - CLOCK_CSS_IDX_CPU_GROUP_NEVIS, - CLOCK_CSS_IDX_CPU_GROUP_GELAS, - CLOCK_CSS_IDX_CPU_GROUP_TRAVIS, + CLOCK_CSS_IDX_CPU_GROUP_GROUP_LITTLE, + CLOCK_CSS_IDX_CPU_GROUP_GROUP_MID, + CLOCK_CSS_IDX_CPU_GROUP_GROUP_BIG, CLOCK_CSS_IDX_DPU, CLOCK_CSS_IDX_COUNT }; @@ -88,9 +88,9 @@ enum clock_css_idx { * Clock indexes. */ enum clock_idx { - CLOCK_IDX_CPU_GROUP_NEVIS, - CLOCK_IDX_CPU_GROUP_GELAS, - CLOCK_IDX_CPU_GROUP_TRAVIS, + CLOCK_IDX_CPU_GROUP_GROUP_LITTLE, + CLOCK_IDX_CPU_GROUP_GROUP_MID, + CLOCK_IDX_CPU_GROUP_GROUP_BIG, CLOCK_IDX_DPU, CLOCK_IDX_PIXEL_0, CLOCK_IDX_PIXEL_1, diff --git a/product/totalcompute/tc4/include/tc4_core.h b/product/totalcompute/tc4/include/tc4_core.h index 5f1c2a2c5..3a3d6096e 100644 --- a/product/totalcompute/tc4/include/tc4_core.h +++ b/product/totalcompute/tc4/include/tc4_core.h @@ -10,6 +10,10 @@ #include +#define TC4_GROUP_LITTLE_NAME "GROUP_LITTLE" +#define TC4_GROUP_MID_NAME "GROUP_MID" +#define TC4_GROUP_BIG_NAME "GROUP_BIG" + #define TC4_CORES_PER_CLUSTER (8) #define TC4_NUMBER_OF_CLUSTERS (1) #define TC4_NUMBER_OF_CORES (TC4_CORES_PER_CLUSTER * TC4_NUMBER_OF_CLUSTERS) diff --git a/product/totalcompute/tc4/include/tc4_dvfs.h b/product/totalcompute/tc4/include/tc4_dvfs.h index 90c61f635..3e23ab5b4 100644 --- a/product/totalcompute/tc4/include/tc4_dvfs.h +++ b/product/totalcompute/tc4/include/tc4_dvfs.h @@ -12,9 +12,9 @@ #define TC4_DVFS_H enum dvfs_element_idx { - DVFS_ELEMENT_IDX_NEVIS, - DVFS_ELEMENT_IDX_GELAS, - DVFS_ELEMENT_IDX_TRAVIS, + DVFS_ELEMENT_IDX_GROUP_LITTLE, + DVFS_ELEMENT_IDX_GROUP_MID, + DVFS_ELEMENT_IDX_GROUP_BIG, DVFS_ELEMENT_IDX_GPU, DVFS_ELEMENT_IDX_COUNT }; diff --git a/product/totalcompute/tc4/include/tc4_mock_psu.h b/product/totalcompute/tc4/include/tc4_mock_psu.h index 5673fff34..8c0725417 100644 --- a/product/totalcompute/tc4/include/tc4_mock_psu.h +++ b/product/totalcompute/tc4/include/tc4_mock_psu.h @@ -12,9 +12,9 @@ #define TC4_MOCK_PSU_H enum mock_psu_id { - MOCK_PSU_ELEMENT_IDX_NEVIS, - MOCK_PSU_ELEMENT_IDX_GELAS, - MOCK_PSU_ELEMENT_IDX_TRAVIS, + MOCK_PSU_ELEMENT_IDX_GROUP_LITTLE, + MOCK_PSU_ELEMENT_IDX_GROUP_MID, + MOCK_PSU_ELEMENT_IDX_GROUP_BIG, MOCK_PSU_ELEMENT_IDX_GPU, MOCK_PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/totalcompute/tc4/include/tc4_psu.h b/product/totalcompute/tc4/include/tc4_psu.h index c6cb315c3..3fd16e222 100644 --- a/product/totalcompute/tc4/include/tc4_psu.h +++ b/product/totalcompute/tc4/include/tc4_psu.h @@ -12,9 +12,9 @@ #define TC4_PSU_H enum psu_id { - PSU_ELEMENT_IDX_NEVIS, - PSU_ELEMENT_IDX_GELAS, - PSU_ELEMENT_IDX_TRAVIS, + PSU_ELEMENT_IDX_GROUP_LITTLE, + PSU_ELEMENT_IDX_GROUP_MID, + PSU_ELEMENT_IDX_GROUP_BIG, PSU_ELEMENT_IDX_GPU, PSU_ELEMENT_IDX_COUNT, }; diff --git a/product/totalcompute/tc4/include/tc4_scmi.h b/product/totalcompute/tc4/include/tc4_scmi.h index 7a08a4a24..997fec682 100644 --- a/product/totalcompute/tc4/include/tc4_scmi.h +++ b/product/totalcompute/tc4/include/tc4_scmi.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -32,22 +32,22 @@ enum scp_tc4_scmi_service_idx { /* SCP<->AP Fast channels indexes */ enum tc4_plat_fch_idx { /* Fast channels from 0 - 3 */ - TC4_PLAT_FCH_NEVIS_LEVEL_SET, - TC4_PLAT_FCH_NEVIS_LIMIT_SET, - TC4_PLAT_FCH_NEVIS_LEVEL_GET, - TC4_PLAT_FCH_NEVIS_LIMIT_GET, + TC4_PLAT_FCH_GROUP_LITTLE_LEVEL_SET, + TC4_PLAT_FCH_GROUP_LITTLE_LIMIT_SET, + TC4_PLAT_FCH_GROUP_LITTLE_LEVEL_GET, + TC4_PLAT_FCH_GROUP_LITTLE_LIMIT_GET, /* Fast channels from 4 - 7 */ - TC4_PLAT_FCH_GELAS_LEVEL_SET, - TC4_PLAT_FCH_GELAS_LIMIT_SET, - TC4_PLAT_FCH_GELAS_LEVEL_GET, - TC4_PLAT_FCH_GELAS_LIMIT_GET, + TC4_PLAT_FCH_GROUP_MID_LEVEL_SET, + TC4_PLAT_FCH_GROUP_MID_LIMIT_SET, + TC4_PLAT_FCH_GROUP_MID_LEVEL_GET, + TC4_PLAT_FCH_GROUP_MID_LIMIT_GET, /* Fast channels from 8 - 11 */ - TC4_PLAT_FCH_TRAVIS_LEVEL_SET, - TC4_PLAT_FCH_TRAVIS_LIMIT_SET, - TC4_PLAT_FCH_TRAVIS_LEVEL_GET, - TC4_PLAT_FCH_TRAVIS_LIMIT_GET, + TC4_PLAT_FCH_GROUP_BIG_LEVEL_SET, + TC4_PLAT_FCH_GROUP_BIG_LIMIT_SET, + TC4_PLAT_FCH_GROUP_BIG_LEVEL_GET, + TC4_PLAT_FCH_GROUP_BIG_LIMIT_GET, /* Fast chanels from 12 - 15*/ TC4_PLAT_FCH_GPU_LEVEL_SET, @@ -66,20 +66,20 @@ enum tc4_transport_channel_idx { TC4_TRANSPORT_SCMI_SERVICE_IDX_SCP2RSS, #if defined(BUILD_HAS_SCMI_PERF_FAST_CHANNELS) - TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_SET, - TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_SET, - TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_GET, - TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LEVEL_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LIMIT_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LEVEL_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LIMIT_GET, - TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_SET, - TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_SET, - TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_GET, - TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LEVEL_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LIMIT_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LEVEL_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LIMIT_GET, - TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_SET, - TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_SET, - TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_GET, - TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LEVEL_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LIMIT_SET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LEVEL_GET, + TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LIMIT_GET, TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_SET, TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_SET, diff --git a/product/totalcompute/tc4/include/tc4_timer.h b/product/totalcompute/tc4/include/tc4_timer.h index 19c5657b2..0fb9ecfaf 100644 --- a/product/totalcompute/tc4/include/tc4_timer.h +++ b/product/totalcompute/tc4/include/tc4_timer.h @@ -9,9 +9,9 @@ #define CONFIG_TIMER_H enum config_timer_refclk_sub_element_idx { - TC4_CONFIG_TIMER_DVFS_CPU_NEVIS, - TC4_CONFIG_TIMER_DVFS_CPU_GELAS, - TC4_CONFIG_TIMER_DVFS_CPU_TRAVIS, + TC4_CONFIG_TIMER_DVFS_CPU_GROUP_LITTLE, + TC4_CONFIG_TIMER_DVFS_CPU_GROUP_MID, + TC4_CONFIG_TIMER_DVFS_CPU_GROUP_BIG, TC4_CONFIG_TIMER_DVFS_GPU, #ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS TC4_CONFIG_TIMER_FAST_CHANNEL_TIMER_IDX, diff --git a/product/totalcompute/tc4/include/tc_core.h b/product/totalcompute/tc4/include/tc_core.h index 974f9220b..d56339513 100644 --- a/product/totalcompute/tc4/include/tc_core.h +++ b/product/totalcompute/tc4/include/tc_core.h @@ -10,8 +10,8 @@ #include -#define TC4_GROUP_LITTLE_NAME "NEVIS" -#define TC4_GROUP_MID_NAME "GELAS" -#define TC4_GROUP_BIG_NAME "TRAVIS" +#define TC4_GROUP_LITTLE_NAME "GROUP_LITTLE" +#define TC4_GROUP_MID_NAME "GROUP_MID" +#define TC4_GROUP_BIG_NAME "GROUP_BIG" #endif /* TC_CORE_H */ diff --git a/product/totalcompute/tc4/scp_css/CMakeLists.txt b/product/totalcompute/tc4/scp_css/CMakeLists.txt index f3046c286..0518f632a 100644 --- a/product/totalcompute/tc4/scp_css/CMakeLists.txt +++ b/product/totalcompute/tc4/scp_css/CMakeLists.txt @@ -17,7 +17,7 @@ set(CMAKE_TC_DIR "../../") # - 'TC4_VARIANT_STD' for TC4 standard build # - 'TC4_VAR_EXPERIMENT_POWER' for TC4 with power/performance/thermal additions # used for evaluation purpose: -# - TRAFFIC_COP on NEVIS cores +# - TRAFFIC_COP on LITTLE cores # - MPMM on all cores # - THERMAL_MANAGEMENT for the entire system, with a simplified/dummy power # model diff --git a/product/totalcompute/tc4/scp_css/config_clock.c b/product/totalcompute/tc4/scp_css/config_clock.c index b38fae10a..0254fdbbf 100644 --- a/product/totalcompute/tc4/scp_css/config_clock.c +++ b/product/totalcompute/tc4/scp_css/config_clock.c @@ -20,37 +20,37 @@ #include static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = { - [CLOCK_IDX_CPU_GROUP_NEVIS] = + [CLOCK_IDX_CPU_GROUP_GROUP_LITTLE] = { - .name = "CPU_GROUP_NEVIS", + .name = "CPU_GROUP_" TC4_GROUP_LITTLE_NAME, .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_NEVIS), + CLOCK_CSS_IDX_CPU_GROUP_GROUP_LITTLE), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), }), }, - [CLOCK_IDX_CPU_GROUP_GELAS] = + [CLOCK_IDX_CPU_GROUP_GROUP_MID] = { - .name = "CPU_GROUP_GELAS", + .name = "CPU_GROUP_" TC4_GROUP_MID_NAME, .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_GELAS), + CLOCK_CSS_IDX_CPU_GROUP_GROUP_MID), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), }), }, - [CLOCK_IDX_CPU_GROUP_TRAVIS] = + [CLOCK_IDX_CPU_GROUP_GROUP_BIG] = { - .name = "CPU_GROUP_TRAVIS", + .name = "CPU_GROUP_" TC4_GROUP_BIG_NAME, .data = &((struct mod_clock_dev_config){ .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_TRAVIS), + CLOCK_CSS_IDX_CPU_GROUP_GROUP_BIG), .api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_CSS_CLOCK, MOD_CSS_CLOCK_API_TYPE_CLOCK), diff --git a/product/totalcompute/tc4/scp_css/config_css_clock.c b/product/totalcompute/tc4/scp_css/config_css_clock.c index 7f9676728..2d932d316 100644 --- a/product/totalcompute/tc4/scp_css/config_css_clock.c +++ b/product/totalcompute/tc4/scp_css/config_css_clock.c @@ -17,12 +17,12 @@ #include #include -static const struct mod_css_clock_rate rate_table_cpu_group_nevis[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_little[5] = { { /* Super Underdrive */ .rate = 768 * FWK_MHZ, .pll_rate = 768 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -32,7 +32,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_nevis[5] = { /* Underdrive */ .rate = 1153 * FWK_MHZ, .pll_rate = 1153 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -42,7 +42,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_nevis[5] = { /* Nominal */ .rate = 1537 * FWK_MHZ, .pll_rate = 1537 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -52,7 +52,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_nevis[5] = { /* Overdrive */ .rate = 1844 * FWK_MHZ, .pll_rate = 1844 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -62,7 +62,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_nevis[5] = { /* Super Overdrive */ .rate = 2152 * FWK_MHZ, .pll_rate = 2152 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -70,12 +70,12 @@ static const struct mod_css_clock_rate rate_table_cpu_group_nevis[5] = { }, }; -static const struct mod_css_clock_rate rate_table_cpu_group_gelas[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_mid[5] = { { /* Super Underdrive */ .rate = 946 * FWK_MHZ, .pll_rate = 946 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -85,7 +85,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_gelas[5] = { /* Underdrive */ .rate = 1419 * FWK_MHZ, .pll_rate = 1419 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -95,7 +95,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_gelas[5] = { /* Nominal */ .rate = 1893 * FWK_MHZ, .pll_rate = 1893 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -105,7 +105,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_gelas[5] = { /* Overdrive */ .rate = 2271 * FWK_MHZ, .pll_rate = 2271 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -115,7 +115,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_gelas[5] = { /* Super Overdrive */ .rate = 2650 * FWK_MHZ, .pll_rate = 2650 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -123,12 +123,12 @@ static const struct mod_css_clock_rate rate_table_cpu_group_gelas[5] = { }, }; -static const struct mod_css_clock_rate rate_table_cpu_group_travis[5] = { +static const struct mod_css_clock_rate rate_table_cpu_group_big[5] = { { /* Super Underdrive */ .rate = 1088 * FWK_MHZ, .pll_rate = 1088 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -138,7 +138,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_travis[5] = { /* Underdrive */ .rate = 1632 * FWK_MHZ, .pll_rate = 1632 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -148,7 +148,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_travis[5] = { /* Nominal */ .rate = 2176 * FWK_MHZ, .pll_rate = 2176 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -158,7 +158,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_travis[5] = { /* Overdrive */ .rate = 2612 * FWK_MHZ, .pll_rate = 2612 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -168,7 +168,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_travis[5] = { /* Super Overdrive */ .rate = 3047 * FWK_MHZ, .pll_rate = 3047 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .clock_div = 1, .clock_mod_numerator = 1, @@ -176,19 +176,19 @@ static const struct mod_css_clock_rate rate_table_cpu_group_travis[5] = { }, }; -static const fwk_id_t member_table_cpu_group_nevis[2] = { +static const fwk_id_t member_table_cpu_group_little[2] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), }; -static const fwk_id_t member_table_cpu_group_gelas[4] = { +static const fwk_id_t member_table_cpu_group_mid[4] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5), }; -static const fwk_id_t member_table_cpu_group_travis[2] = { +static const fwk_id_t member_table_cpu_group_big[2] = { FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6), FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7), }; @@ -199,23 +199,23 @@ static const fwk_id_t member_table_dpu[1] = { static const struct fwk_element css_clock_element_table[ CLOCK_CSS_IDX_COUNT + 1] = { - [CLOCK_CSS_IDX_CPU_GROUP_NEVIS] = + [CLOCK_CSS_IDX_CPU_GROUP_GROUP_LITTLE] = { - .name = "CPU_GROUP_NEVIS", + .name = "CPU_GROUP_LITTLE", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_nevis, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_nevis), + .rate_table = rate_table_cpu_group_little, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little), .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_NEVIS), + CLOCK_PLL_IDX_CPU_GROUP_LITTLE), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_nevis, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_nevis), + .member_table = member_table_cpu_group_little, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_little), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), @@ -223,23 +223,23 @@ static const struct fwk_element css_clock_element_table[ .modulation_supported = true, }), }, - [CLOCK_CSS_IDX_CPU_GROUP_GELAS] = + [CLOCK_CSS_IDX_CPU_GROUP_GROUP_MID] = { - .name = "CPU_GROUP_GELAS", + .name = "CPU_GROUP_MID", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_gelas, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + .rate_table = rate_table_cpu_group_mid, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_GELAS), + CLOCK_PLL_IDX_CPU_GROUP_MID), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_gelas, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_gelas), + .member_table = member_table_cpu_group_mid, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_mid), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), @@ -247,24 +247,24 @@ static const struct fwk_element css_clock_element_table[ .modulation_supported = true, }), }, - [CLOCK_CSS_IDX_CPU_GROUP_TRAVIS] = + [CLOCK_CSS_IDX_CPU_GROUP_GROUP_BIG] = { - .name = "CPU_GROUP_TRAVIS", + .name = "CPU_GROUP_BIG", .data = &((struct mod_css_clock_dev_config){ .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_travis, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_travis), + .rate_table = rate_table_cpu_group_big, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big), .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, .pll_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_TRAVIS), + CLOCK_PLL_IDX_CPU_GROUP_BIG), .pll_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_travis, + .member_table = member_table_cpu_group_big, .member_count = - FWK_ARRAY_SIZE(member_table_cpu_group_travis), + FWK_ARRAY_SIZE(member_table_cpu_group_big), .member_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), diff --git a/product/totalcompute/tc4/scp_css/config_dvfs.c b/product/totalcompute/tc4/scp_css/config_dvfs.c index 4b40b81f2..95446dfe6 100644 --- a/product/totalcompute/tc4/scp_css/config_dvfs.c +++ b/product/totalcompute/tc4/scp_css/config_dvfs.c @@ -6,6 +6,7 @@ */ #include "clock_soc.h" +#include "tc4_core.h" #include "tc4_dvfs.h" #include "tc4_psu.h" #include "tc4_timer.h" @@ -31,108 +32,108 @@ */ /* dynamic-power-coeffient/1000 */ -#define NEVIS_DPC 0.230 -#define GELAS_DPC 0.495 -#define TRAVIS_DPC 1.054 +#define GROUP_LITTLE_DPC 0.230 +#define GROUP_MID_DPC 0.495 +#define GROUP_BIG_DPC 1.054 -static struct mod_dvfs_opp operating_points_nevis[6] = { +static struct mod_dvfs_opp operating_points_group_little[6] = { { .level = 768 * 1000000UL, .frequency = 768 * FWK_KHZ, .voltage = 550, - .power = (uint32_t)(NEVIS_DPC * 768 * 0.550 * 0.550), + .power = (uint32_t)(GROUP_LITTLE_DPC * 768 * 0.550 * 0.550), }, { .level = 1153 * 1000000UL, .frequency = 1153 * FWK_KHZ, .voltage = 650, - .power = (uint32_t)(NEVIS_DPC * 1153 * 0.650 * 0.650), + .power = (uint32_t)(GROUP_LITTLE_DPC * 1153 * 0.650 * 0.650), }, { .level = 1537 * 1000000UL, .frequency = 1537 * FWK_KHZ, .voltage = 750, - .power = (uint32_t)(NEVIS_DPC * 1537 * 0.750 * 0.750), + .power = (uint32_t)(GROUP_LITTLE_DPC * 1537 * 0.750 * 0.750), }, { .level = 1844 * 1000000UL, .frequency = 1844 * FWK_KHZ, .voltage = 850, - .power = (uint32_t)(NEVIS_DPC * 1844 * 0.850 * 0.850), + .power = (uint32_t)(GROUP_LITTLE_DPC * 1844 * 0.850 * 0.850), }, { .level = 2152 * 1000000UL, .frequency = 2152 * FWK_KHZ, .voltage = 950, - .power = (uint32_t)(NEVIS_DPC * 2152 * 0.950 * 0.950), + .power = (uint32_t)(GROUP_LITTLE_DPC * 2152 * 0.950 * 0.950), }, { 0 } }; -static struct mod_dvfs_opp operating_points_gelas[6] = { +static struct mod_dvfs_opp operating_points_group_mid[6] = { { .level = 946 * 1000000UL, .frequency = 946 * FWK_KHZ, .voltage = 550, - .power = (uint32_t)(GELAS_DPC * 946 * 0.550 * 0.550), + .power = (uint32_t)(GROUP_MID_DPC * 946 * 0.550 * 0.550), }, { .level = 1419 * 1000000UL, .frequency = 1419 * FWK_KHZ, .voltage = 650, - .power = (uint32_t)(GELAS_DPC * 1419 * 0.650 * 0.650), + .power = (uint32_t)(GROUP_MID_DPC * 1419 * 0.650 * 0.650), }, { .level = 1893 * 1000000UL, .frequency = 1893 * FWK_KHZ, .voltage = 750, - .power = (uint32_t)(GELAS_DPC * 1893 * 0.750 * 0.750), + .power = (uint32_t)(GROUP_MID_DPC * 1893 * 0.750 * 0.750), }, { .level = 2271 * 1000000UL, .frequency = 2271 * FWK_KHZ, .voltage = 850, - .power = (uint32_t)(GELAS_DPC * 2271 * 0.850 * 0.850), + .power = (uint32_t)(GROUP_MID_DPC * 2271 * 0.850 * 0.850), }, { .level = 2650 * 1000000UL, .frequency = 2650 * FWK_KHZ, .voltage = 950, - .power = (uint32_t)(GELAS_DPC * 2650 * 0.950 * 0.950), + .power = (uint32_t)(GROUP_MID_DPC * 2650 * 0.950 * 0.950), }, { 0 } }; -static struct mod_dvfs_opp operating_points_travis[6] = { +static struct mod_dvfs_opp operating_points_group_big[6] = { { .level = 1088 * 1000000UL, .frequency = 1088 * FWK_KHZ, .voltage = 550, - .power = (uint32_t)(TRAVIS_DPC * 1088 * 0.550 * 0.550), + .power = (uint32_t)(GROUP_BIG_DPC * 1088 * 0.550 * 0.550), }, { .level = 1632 * 1000000UL, .frequency = 1632 * FWK_KHZ, .voltage = 650, - .power = (uint32_t)(TRAVIS_DPC * 1632 * 0.650 * 0.650), + .power = (uint32_t)(GROUP_BIG_DPC * 1632 * 0.650 * 0.650), }, { .level = 2176 * 1000000UL, .frequency = 2176 * FWK_KHZ, .voltage = 750, - .power = (uint32_t)(TRAVIS_DPC * 2176 * 0.750 * 0.750), + .power = (uint32_t)(GROUP_BIG_DPC * 2176 * 0.750 * 0.750), }, { .level = 2612 * 1000000UL, .frequency = 2612 * FWK_KHZ, .voltage = 850, - .power = (uint32_t)(TRAVIS_DPC * 2612 * 0.850 * 0.850), + .power = (uint32_t)(GROUP_BIG_DPC * 2612 * 0.850 * 0.850), }, { .level = 3047 * 1000000UL, .frequency = 3047 * FWK_KHZ, .voltage = 950, - .power = (uint32_t)(TRAVIS_DPC * 3047 * 0.950 * 0.950), + .power = (uint32_t)(GROUP_BIG_DPC * 3047 * 0.950 * 0.950), }, { 0 } }; @@ -161,56 +162,57 @@ static struct mod_dvfs_opp operating_points_gpu[5] = { { 0 } }; -static const struct mod_dvfs_domain_config cpu_group_nevis = { - .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_NEVIS), - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_NEVIS), +static const struct mod_dvfs_domain_config cpu_group_little = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GROUP_LITTLE), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_GROUP_LITTLE), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC4_CONFIG_TIMER_DVFS_CPU_NEVIS), + TC4_CONFIG_TIMER_DVFS_CPU_GROUP_LITTLE), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_nevis, + .opps = operating_points_group_little, }; -static const struct mod_dvfs_domain_config cpu_group_gelas = { - .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GELAS), - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_GELAS), +static const struct mod_dvfs_domain_config cpu_group_mid = { + .psu_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GROUP_MID), + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_GROUP_MID), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC4_CONFIG_TIMER_DVFS_CPU_GELAS), + TC4_CONFIG_TIMER_DVFS_CPU_GROUP_MID), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_gelas, + .opps = operating_points_group_mid, }; -static const struct mod_dvfs_domain_config cpu_group_travis = { +static const struct mod_dvfs_domain_config cpu_group_big = { .psu_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_TRAVIS), + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GROUP_BIG), .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_TRAVIS), + CLOCK_IDX_CPU_GROUP_GROUP_BIG), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, - TC4_CONFIG_TIMER_DVFS_CPU_TRAVIS), + TC4_CONFIG_TIMER_DVFS_CPU_GROUP_BIG), .retry_ms = 1, .latency = 1200, .sustained_idx = 2, - .opps = operating_points_travis, + .opps = operating_points_group_big, }; static const struct mod_dvfs_domain_config gpu = { - .psu_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GPU), - .clock_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_GPU), + .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_GPU), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_GPU), .alarm_id = FWK_ID_SUB_ELEMENT_INIT( FWK_MODULE_IDX_TIMER, 0, @@ -222,20 +224,20 @@ static const struct mod_dvfs_domain_config gpu = { }; static const struct fwk_element element_table[DVFS_ELEMENT_IDX_COUNT + 1] = { - [DVFS_ELEMENT_IDX_NEVIS] = + [DVFS_ELEMENT_IDX_GROUP_LITTLE] = { - .name = "CPU_GROUP_NEVIS", - .data = &cpu_group_nevis, + .name = "CPU_GROUP_" TC4_GROUP_LITTLE_NAME, + .data = &cpu_group_little, }, - [DVFS_ELEMENT_IDX_GELAS] = + [DVFS_ELEMENT_IDX_GROUP_MID] = { - .name = "CPU_GROUP_GELAS", - .data = &cpu_group_gelas, + .name = "CPU_GROUP_" TC4_GROUP_MID_NAME, + .data = &cpu_group_mid, }, - [DVFS_ELEMENT_IDX_TRAVIS] = + [DVFS_ELEMENT_IDX_GROUP_BIG] = { - .name = "CPU_GROUP_TRAVIS", - .data = &cpu_group_travis, + .name = "CPU_GROUP_" TC4_GROUP_BIG_NAME, + .data = &cpu_group_big, }, [DVFS_ELEMENT_IDX_GPU] = { diff --git a/product/totalcompute/tc4/scp_css/config_fch_polled.c b/product/totalcompute/tc4/scp_css/config_fch_polled.c index a36103a6e..5bef971c8 100644 --- a/product/totalcompute/tc4/scp_css/config_fch_polled.c +++ b/product/totalcompute/tc4/scp_css/config_fch_polled.c @@ -82,99 +82,99 @@ enum fch_polled_length { } }) static const struct fwk_element fch_polled_element_table[] = { - [TC4_PLAT_FCH_NEVIS_LEVEL_SET] = { - .name = "FCH_NEVIS_LEVEL_SET", + [TC4_PLAT_FCH_GROUP_LITTLE_LEVEL_SET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LEVEL_SET", .data = FCH_ADDR_INIT( - FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_NEVIS), - FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), FCH_POLLED_LEVEL_SET_LENGTH ) }, - [TC4_PLAT_FCH_NEVIS_LIMIT_SET] = { - .name = "FCH_NEVIS_LIMIT_SET", + [TC4_PLAT_FCH_GROUP_LITTLE_LIMIT_SET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LIMIT_SET", .data =FCH_ADDR_INIT( - FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_NEVIS), - FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), FCH_POLLED_LIMIT_SET_LENGTH ), }, - [TC4_PLAT_FCH_NEVIS_LEVEL_GET] = { - .name = "FCH_NEVIS_LEVEL_GET", + [TC4_PLAT_FCH_GROUP_LITTLE_LEVEL_GET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LEVEL_GET", .data = FCH_ADDR_INIT( - FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_NEVIS), - FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), FCH_POLLED_LEVEL_GET_LENGTH ) }, - [TC4_PLAT_FCH_NEVIS_LIMIT_GET] = { - .name = "FCH_NEVIS_LIMIT_GET", + [TC4_PLAT_FCH_GROUP_LITTLE_LIMIT_GET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LIMIT_GET", .data = FCH_ADDR_INIT( - FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_NEVIS), - FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_NEVIS), + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_LITTLE), FCH_POLLED_LIMIT_GET_LENGTH ) }, - [TC4_PLAT_FCH_GELAS_LEVEL_SET] = { - .name = "FCH_GELAS_LEVEL_SET", + [TC4_PLAT_FCH_GROUP_MID_LEVEL_SET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LEVEL_SET", .data = FCH_ADDR_INIT( - FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_GELAS), - FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), FCH_POLLED_LEVEL_SET_LENGTH ) }, - [TC4_PLAT_FCH_GELAS_LIMIT_SET] = { - .name = "FCH_GELAS_LIMIT_SET", + [TC4_PLAT_FCH_GROUP_MID_LIMIT_SET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LIMIT_SET", .data =FCH_ADDR_INIT( - FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_GELAS), - FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), FCH_POLLED_LIMIT_SET_LENGTH ), }, - [TC4_PLAT_FCH_GELAS_LEVEL_GET] = { - .name = "FCH_GELAS_LEVEL_GET", + [TC4_PLAT_FCH_GROUP_MID_LEVEL_GET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LEVEL_GET", .data = FCH_ADDR_INIT( - FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_GELAS), - FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), FCH_POLLED_LEVEL_GET_LENGTH ) }, - [TC4_PLAT_FCH_GELAS_LIMIT_GET] = { - .name = "FCH_GELAS_LIMIT_GET", + [TC4_PLAT_FCH_GROUP_MID_LIMIT_GET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LIMIT_GET", .data = FCH_ADDR_INIT( - FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_GELAS), - FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_GELAS), + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_MID), FCH_POLLED_LIMIT_GET_LENGTH ) }, - [TC4_PLAT_FCH_TRAVIS_LEVEL_SET] = { - .name = "FCH_TRAVIS_LEVEL_SET", + [TC4_PLAT_FCH_GROUP_BIG_LEVEL_SET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LEVEL_SET", .data = FCH_ADDR_INIT( - FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), - FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LEVEL_SET_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), + FC_LEVEL_SET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), FCH_POLLED_LEVEL_SET_LENGTH ) }, - [TC4_PLAT_FCH_TRAVIS_LIMIT_SET] = { - .name = "FCH_TRAVIS_LIMIT_SET", + [TC4_PLAT_FCH_GROUP_BIG_LIMIT_SET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LIMIT_SET", .data =FCH_ADDR_INIT( - FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), - FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LIMIT_SET_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), + FC_LIMIT_SET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), FCH_POLLED_LIMIT_SET_LENGTH ), }, - [TC4_PLAT_FCH_TRAVIS_LEVEL_GET] = { - .name = "FCH_TRAVIS_LEVEL_GET", + [TC4_PLAT_FCH_GROUP_BIG_LEVEL_GET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LEVEL_GET", .data = FCH_ADDR_INIT( - FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), - FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LEVEL_GET_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), + FC_LEVEL_GET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), FCH_POLLED_LEVEL_GET_LENGTH ) }, - [TC4_PLAT_FCH_TRAVIS_LIMIT_GET] = { - .name = "FCH_TRAVIS_LIMIT_GET", + [TC4_PLAT_FCH_GROUP_BIG_LIMIT_GET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LIMIT_GET", .data = FCH_ADDR_INIT( - FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_TRAVIS), - FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_TRAVIS), + FC_LIMIT_GET_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), + FC_LIMIT_GET_AP_ADDR(DVFS_ELEMENT_IDX_GROUP_BIG), FCH_POLLED_LIMIT_GET_LENGTH ) }, diff --git a/product/totalcompute/tc4/scp_css/config_gtimer.c b/product/totalcompute/tc4/scp_css/config_gtimer.c index 7853d6506..017807973 100644 --- a/product/totalcompute/tc4/scp_css/config_gtimer.c +++ b/product/totalcompute/tc4/scp_css/config_gtimer.c @@ -28,7 +28,7 @@ static const struct fwk_element gtimer_dev_table[2] = { .frequency = CLOCK_RATE_GTCLK, .clock_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_NEVIS), + CLOCK_IDX_CPU_GROUP_GROUP_LITTLE), }), }, [1] = { 0 }, diff --git a/product/totalcompute/tc4/scp_css/config_mock_psu.c b/product/totalcompute/tc4/scp_css/config_mock_psu.c index 170985088..5d4c05825 100644 --- a/product/totalcompute/tc4/scp_css/config_mock_psu.c +++ b/product/totalcompute/tc4/scp_css/config_mock_psu.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include @@ -13,8 +14,8 @@ #include static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = { - [MOCK_PSU_ELEMENT_IDX_NEVIS] = { - .name = "DVFS_GROUP_NEVIS", + [MOCK_PSU_ELEMENT_IDX_GROUP_LITTLE] = { + .name = "DVFS_GROUP_" TC4_GROUP_LITTLE_NAME, .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, @@ -27,8 +28,8 @@ static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = .default_voltage = 550, }, }, - [MOCK_PSU_ELEMENT_IDX_GELAS] = { - .name = "DVFS_GROUP_GELAS", + [MOCK_PSU_ELEMENT_IDX_GROUP_MID] = { + .name = "DVFS_GROUP_" TC4_GROUP_MID_NAME, .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, @@ -41,8 +42,8 @@ static const struct fwk_element element_table[MOCK_PSU_ELEMENT_IDX_COUNT + 1] = .default_voltage = 550, }, }, - [MOCK_PSU_ELEMENT_IDX_TRAVIS] = { - .name = "DVFS_GROUP_TRAVIS", + [MOCK_PSU_ELEMENT_IDX_GROUP_BIG] = { + .name = "DVFS_GROUP_" TC4_GROUP_BIG_NAME, .data = &(const struct mod_mock_psu_element_cfg){ .async_alarm_id = FWK_ID_NONE_INIT, diff --git a/product/totalcompute/tc4/scp_css/config_mpmm.c b/product/totalcompute/tc4/scp_css/config_mpmm.c index 943346d54..724a79b46 100644 --- a/product/totalcompute/tc4/scp_css/config_mpmm.c +++ b/product/totalcompute/tc4/scp_css/config_mpmm.c @@ -28,7 +28,7 @@ enum cpu_idx { CORE7_IDX }; -static struct mod_mpmm_pct_table nevis_pct[] = { +static struct mod_mpmm_pct_table group_little_pct[] = { { .cores_online = 2, .default_perf_limit = 1844 * 1000000UL, @@ -57,7 +57,7 @@ static struct mod_mpmm_pct_table nevis_pct[] = { }, }; -static struct mod_mpmm_pct_table gelas_pct[] = { +static struct mod_mpmm_pct_table group_mid_pct[] = { { .cores_online = 4, .default_perf_limit = 1419 * 1000000UL, @@ -128,7 +128,7 @@ static struct mod_mpmm_pct_table gelas_pct[] = { }, }; -static struct mod_mpmm_pct_table travis_pct[] = { +static struct mod_mpmm_pct_table group_big_pct[] = { { .cores_online = 2, .default_perf_limit = 2176 * 1000000UL, @@ -161,7 +161,7 @@ static struct mod_mpmm_pct_table travis_pct[] = { }, }; -static const struct mod_mpmm_core_config nevis_core_config[] = { +static const struct mod_mpmm_core_config group_little_core_config[] = { [0] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE0_IDX), .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE0_IDX), @@ -178,7 +178,7 @@ static const struct mod_mpmm_core_config nevis_core_config[] = { }, }; -static const struct mod_mpmm_core_config gelas_core_config[] = { +static const struct mod_mpmm_core_config group_mid_core_config[] = { [0] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE2_IDX), .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE2_IDX), @@ -209,7 +209,7 @@ static const struct mod_mpmm_core_config gelas_core_config[] = { }, }; -static const struct mod_mpmm_core_config travis_core_config[] = { +static const struct mod_mpmm_core_config group_big_core_config[] = { [0] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE6_IDX), .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE6_IDX), @@ -226,60 +226,60 @@ static const struct mod_mpmm_core_config travis_core_config[] = { }, }; -static const struct mod_mpmm_domain_config nevis_domain_conf[] = { +static const struct mod_mpmm_domain_config group_little_domain_conf[] = { [0] = { .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_NEVIS), - .pct = nevis_pct, - .pct_size = FWK_ARRAY_SIZE(nevis_pct), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GROUP_LITTLE), + .pct = group_little_pct, + .pct_size = FWK_ARRAY_SIZE(group_little_pct), .btc = 10, .num_threshold_counters = 3, - .core_config = nevis_core_config, + .core_config = group_little_core_config, }, [1] = {0}, }; -static const struct mod_mpmm_domain_config gelas_domain_conf[] = { +static const struct mod_mpmm_domain_config group_mid_domain_conf[] = { [0] = { .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GELAS), - .pct = gelas_pct, - .pct_size = FWK_ARRAY_SIZE(gelas_pct), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GROUP_MID), + .pct = group_mid_pct, + .pct_size = FWK_ARRAY_SIZE(group_mid_pct), .btc = 10, .num_threshold_counters = 3, - .core_config = gelas_core_config, + .core_config = group_mid_core_config, }, [1] = {0}, }; -static const struct mod_mpmm_domain_config travis_domain_conf[] = { +static const struct mod_mpmm_domain_config group_big_domain_conf[] = { [0] = { .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_TRAVIS), - .pct = travis_pct, - .pct_size = FWK_ARRAY_SIZE(travis_pct), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GROUP_BIG), + .pct = group_big_pct, + .pct_size = FWK_ARRAY_SIZE(group_big_pct), .btc = 10, .num_threshold_counters = 3, - .core_config = travis_core_config, + .core_config = group_big_core_config, }, [1] = {0}, }; static const struct fwk_element element_table[] = { [0] = { - .name = "MPMM_NEVIS_ELEM", - .sub_element_count = FWK_ARRAY_SIZE(nevis_core_config), - .data = nevis_domain_conf, + .name = "MPMM_GROUP_LITTLE_ELEM", + .sub_element_count = FWK_ARRAY_SIZE(group_little_core_config), + .data = group_little_domain_conf, }, [1] = { - .name = "MPMM_GELAS_ELEM", - .sub_element_count = FWK_ARRAY_SIZE(gelas_core_config), - .data = gelas_domain_conf, + .name = "MPMM_GROUP_MID_ELEM", + .sub_element_count = FWK_ARRAY_SIZE(group_mid_core_config), + .data = group_mid_domain_conf, }, [2] = { - .name = "MPMM_TRAVIS_ELEM", - .sub_element_count = FWK_ARRAY_SIZE(travis_core_config), - .data = travis_domain_conf, + .name = "MPMM_GROUP_BIG_ELEM", + .sub_element_count = FWK_ARRAY_SIZE(group_big_core_config), + .data = group_big_domain_conf, }, [3] = { 0 }, }; diff --git a/product/totalcompute/tc4/scp_css/config_pik_clock.c b/product/totalcompute/tc4/scp_css/config_pik_clock.c index 88d7c3dda..7cf8a7393 100644 --- a/product/totalcompute/tc4/scp_css/config_pik_clock.c +++ b/product/totalcompute/tc4/scp_css/config_pik_clock.c @@ -21,28 +21,28 @@ /* * Rate lookup tables */ -static const struct mod_pik_clock_rate rate_table_cpu_group_nevis[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_little[1] = { { .rate = 1537 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL0, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, /* Rate adjusted via CPU PLL */ }, }; -static const struct mod_pik_clock_rate rate_table_cpu_group_gelas[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_mid[1] = { { .rate = 1893 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL1, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL1, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, /* Rate adjusted via CPU PLL */ }, }; -static const struct mod_pik_clock_rate rate_table_cpu_group_travis[1] = { +static const struct mod_pik_clock_rate rate_table_cpu_group_big[1] = { { .rate = 2176 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC4_PLL2, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC_PLL2, .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, .divider = 1, /* Rate adjusted via CPU PLL */ }, @@ -104,8 +104,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[0].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_nevis, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_nevis), + .rate_table = rate_table_cpu_group_little, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little), }), }, [CLOCK_PIK_IDX_CLUS0_CPU1] = { @@ -116,8 +116,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[1].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_nevis, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_nevis), + .rate_table = rate_table_cpu_group_little, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little), }), }, [CLOCK_PIK_IDX_CLUS0_CPU2] = { @@ -128,8 +128,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[2].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_gelas, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + .rate_table = rate_table_cpu_group_mid, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), }), }, [CLOCK_PIK_IDX_CLUS0_CPU3] = { @@ -140,8 +140,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[3].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_gelas, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + .rate_table = rate_table_cpu_group_mid, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), }), }, [CLOCK_PIK_IDX_CLUS0_CPU4] = { @@ -152,8 +152,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[4].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[4].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[4].MOD, - .rate_table = rate_table_cpu_group_gelas, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + .rate_table = rate_table_cpu_group_mid, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), }), }, [CLOCK_PIK_IDX_CLUS0_CPU5] = { @@ -164,8 +164,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[5].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[5].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[5].MOD, - .rate_table = rate_table_cpu_group_gelas, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_gelas), + .rate_table = rate_table_cpu_group_mid, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_mid), }), }, [CLOCK_PIK_IDX_CLUS0_CPU6] = { @@ -176,8 +176,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[6].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[6].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[6].MOD, - .rate_table = rate_table_cpu_group_travis, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_travis), + .rate_table = rate_table_cpu_group_big, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big), }), }, [CLOCK_PIK_IDX_CLUS0_CPU7] = { @@ -188,8 +188,8 @@ static const struct fwk_element pik_clock_element_table[ .control_reg = &CLUSTER_PIK_PTR->CORECLK[7].CTRL, .divext_reg = &CLUSTER_PIK_PTR->CORECLK[7].DIV, .modulator_reg = &CLUSTER_PIK_PTR->CORECLK[7].MOD, - .rate_table = rate_table_cpu_group_travis, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_travis), + .rate_table = rate_table_cpu_group_big, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big), }), }, [CLOCK_PIK_IDX_GIC] = { diff --git a/product/totalcompute/tc4/scp_css/config_psu.c b/product/totalcompute/tc4/scp_css/config_psu.c index d42206c88..73d28b008 100644 --- a/product/totalcompute/tc4/scp_css/config_psu.c +++ b/product/totalcompute/tc4/scp_css/config_psu.c @@ -17,32 +17,32 @@ #include static const struct fwk_element element_table[PSU_ELEMENT_IDX_COUNT + 1] = { - [PSU_ELEMENT_IDX_NEVIS] = { - .name = "PSU_GROUP_NEVIS", + [PSU_ELEMENT_IDX_GROUP_LITTLE] = { + .name = "PSU_GROUP_" TC4_GROUP_LITTLE_NAME, .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_NEVIS), + MOCK_PSU_ELEMENT_IDX_GROUP_LITTLE), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, }, - [PSU_ELEMENT_IDX_GELAS] = { - .name = "PSU_GROUP_GELAS", + [PSU_ELEMENT_IDX_GROUP_MID] = { + .name = "PSU_GROUP_" TC4_GROUP_MID_NAME, .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_GELAS), + MOCK_PSU_ELEMENT_IDX_GROUP_MID), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, }, - [PSU_ELEMENT_IDX_TRAVIS] = { - .name = "PSU_GROUP_TRAVIS", + [PSU_ELEMENT_IDX_GROUP_BIG] = { + .name = "PSU_GROUP_" TC4_GROUP_BIG_NAME, .data = &(const struct mod_psu_element_cfg){ .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOCK_PSU_ELEMENT_IDX_TRAVIS), + MOCK_PSU_ELEMENT_IDX_GROUP_BIG), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_MOCK_PSU, MOD_MOCK_PSU_API_IDX_DRIVER) }, diff --git a/product/totalcompute/tc4/scp_css/config_scmi_perf.c b/product/totalcompute/tc4/scp_css/config_scmi_perf.c index 996bac26f..254af601b 100644 --- a/product/totalcompute/tc4/scp_css/config_scmi_perf.c +++ b/product/totalcompute/tc4/scp_css/config_scmi_perf.c @@ -21,53 +21,53 @@ static const struct mod_scmi_perf_domain_config domains[DVFS_ELEMENT_IDX_COUNT] = { - [DVFS_ELEMENT_IDX_NEVIS] = { -# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + [DVFS_ELEMENT_IDX_GROUP_LITTLE] = { +#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS .fch_config = (struct scmi_perf_fch_config[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_SET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LEVEL_SET), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_SET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LIMIT_SET), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_GET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LEVEL_GET), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_GET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LIMIT_GET), }, .supports_fast_channels = true, -# endif +#endif }, - [DVFS_ELEMENT_IDX_GELAS] = { -# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + [DVFS_ELEMENT_IDX_GROUP_MID] = { +#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS .fch_config = (struct scmi_perf_fch_config[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_SET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LEVEL_SET), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_SET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LIMIT_SET), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_GET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LEVEL_GET), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_GET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LIMIT_GET), }, .supports_fast_channels = true, -# endif +#endif }, - [DVFS_ELEMENT_IDX_TRAVIS] = { -# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS + [DVFS_ELEMENT_IDX_GROUP_BIG] = { +#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS .fch_config = (struct scmi_perf_fch_config[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_SET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LEVEL_SET), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_SET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LIMIT_SET), [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_GET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LEVEL_GET), [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_GET), + FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LIMIT_GET), }, .supports_fast_channels = true, -# endif +#endif }, [DVFS_ELEMENT_IDX_GPU] = { -# ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS +#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS .fch_config = (struct scmi_perf_fch_config[]) { [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LEVEL_SET), @@ -79,7 +79,7 @@ static const struct mod_scmi_perf_domain_config FCH_INIT(TC4_TRANSPORT_SCMI_PERF_FCH_GPU_LIMIT_GET), }, .supports_fast_channels = true, -# endif +#endif }, }; @@ -106,8 +106,7 @@ static const struct mod_scmi_plugin_config plugins_table[] = { }, }; #else -static const struct mod_scmi_plugin_config plugins_table[] = { -}; +static const struct mod_scmi_plugin_config plugins_table[] = {}; #endif const struct fwk_module_config config_scmi_perf = { diff --git a/product/totalcompute/tc4/scp_css/config_sds.c b/product/totalcompute/tc4/scp_css/config_sds.c index 8c8735735..99df859e4 100644 --- a/product/totalcompute/tc4/scp_css/config_sds.c +++ b/product/totalcompute/tc4/scp_css/config_sds.c @@ -39,8 +39,9 @@ static_assert( const struct mod_sds_config sds_module_config = { .regions = sds_module_regions, .region_count = TC_SDS_REGION_COUNT, - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_NEVIS) + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_CPU_GROUP_GROUP_LITTLE) }; static struct fwk_element sds_element_table[3] = { diff --git a/product/totalcompute/tc4/scp_css/config_system_pll.c b/product/totalcompute/tc4/scp_css/config_system_pll.c index effd4ae75..37f1da535 100644 --- a/product/totalcompute/tc4/scp_css/config_system_pll.c +++ b/product/totalcompute/tc4/scp_css/config_system_pll.c @@ -19,9 +19,9 @@ static const struct fwk_element system_pll_element_table[ CLOCK_PLL_IDX_COUNT + 1] = { - [CLOCK_PLL_IDX_CPU_NEVIS] = + [CLOCK_PLL_IDX_CPU_GROUP_LITTLE] = { - .name = "CPU_PLL_NEVIS", + .name = "CPU_PLL_GROUP_LITTLE", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU0, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], @@ -32,9 +32,9 @@ static const struct fwk_element system_pll_element_table[ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, }), }, - [CLOCK_PLL_IDX_CPU_GELAS] = + [CLOCK_PLL_IDX_CPU_GROUP_MID] = { - .name = "CPU_PLL_GELAS", + .name = "CPU_PLL_GROUP_MID", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU1, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], @@ -45,9 +45,9 @@ static const struct fwk_element system_pll_element_table[ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, }), }, - [CLOCK_PLL_IDX_CPU_TRAVIS] = + [CLOCK_PLL_IDX_CPU_GROUP_BIG] = { - .name = "CPU_PLL_TRAVIS", + .name = "CPU_PLL_GROUP_BIG", .data = &((struct mod_system_pll_dev_config){ .control_reg = (void *)SCP_PLL_CPU2, .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], diff --git a/product/totalcompute/tc4/scp_css/config_thermal_mgmt.c b/product/totalcompute/tc4/scp_css/config_thermal_mgmt.c index 2f05ce568..9f56134e9 100644 --- a/product/totalcompute/tc4/scp_css/config_thermal_mgmt.c +++ b/product/totalcompute/tc4/scp_css/config_thermal_mgmt.c @@ -22,14 +22,14 @@ static struct mod_thermal_mgmt_actor_config actor_table_domain0[2] = { .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC4_POWER_MODEL, 0), .dvfs_domain_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_NEVIS), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GROUP_LITTLE), .weight = 100, }, [1] = { .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC4_POWER_MODEL, 1), .dvfs_domain_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GELAS), + FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_GROUP_MID), .weight = 100, }, }; diff --git a/product/totalcompute/tc4/scp_css/config_traffic_cop.c b/product/totalcompute/tc4/scp_css/config_traffic_cop.c index 023d0c292..963890fc5 100644 --- a/product/totalcompute/tc4/scp_css/config_traffic_cop.c +++ b/product/totalcompute/tc4/scp_css/config_traffic_cop.c @@ -26,7 +26,7 @@ enum cpu_idx { CORE7_PD_IDX }; -static struct mod_tcop_pct_table nevis_pct[3] = { +static struct mod_tcop_pct_table group_little_pct[3] = { { /* * Perf limit for 4 cores online. @@ -47,7 +47,7 @@ static struct mod_tcop_pct_table nevis_pct[3] = { }, }; -static const struct mod_tcop_core_config nevis_core_config[4] = { +static const struct mod_tcop_core_config group_little_core_config[4] = { [0] = { .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE0_PD_IDX), .core_starts_online = true, @@ -66,23 +66,23 @@ static const struct mod_tcop_core_config nevis_core_config[4] = { }, }; -static const struct mod_tcop_domain_config nevis_domain_conf[2] = { +static const struct mod_tcop_domain_config group_little_domain_conf[2] = { [0] = { .perf_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_DVFS, - DVFS_ELEMENT_IDX_NEVIS), - .pct = nevis_pct, - .pct_size = FWK_ARRAY_SIZE(nevis_pct), - .core_config = nevis_core_config, + DVFS_ELEMENT_IDX_GROUP_LITTLE), + .pct = group_little_pct, + .pct_size = FWK_ARRAY_SIZE(group_little_pct), + .core_config = group_little_core_config, }, [1] = { { 0 } }, }; static const struct fwk_element element_table[2] = { [0] = { - .name = "TCOP_NEVIS", + .name = "TCOP_" TC4_GROUP_LITTLE_NAME, .sub_element_count = 4, - .data = nevis_domain_conf, + .data = group_little_domain_conf, }, [1] = { 0 }, }; diff --git a/product/totalcompute/tc4/scp_css/config_transport.c b/product/totalcompute/tc4/scp_css/config_transport.c index 230cce090..7c23818bd 100644 --- a/product/totalcompute/tc4/scp_css/config_transport.c +++ b/product/totalcompute/tc4/scp_css/config_transport.c @@ -128,8 +128,8 @@ static const struct fwk_element transport_element_table[ }), }, #ifdef BUILD_HAS_MOD_TRANSPORT_FC - [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_SET] = { - .name = "FCH_NEVIS_LEVEL_SET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LEVEL_SET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LEVEL_SET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -138,14 +138,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_NEVIS_LEVEL_SET), + TC4_PLAT_FCH_GROUP_LITTLE_LEVEL_SET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_SET] = { - .name = "FCH_NEVIS_LIMIT_SET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LIMIT_SET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LIMIT_SET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -154,14 +154,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_NEVIS_LIMIT_SET), + TC4_PLAT_FCH_GROUP_LITTLE_LIMIT_SET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LEVEL_GET] = { - .name = "FCH_NEVIS_LEVEL_GET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LEVEL_GET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LEVEL_GET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -170,14 +170,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_NEVIS_LEVEL_GET), + TC4_PLAT_FCH_GROUP_LITTLE_LEVEL_GET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_NEVIS_LIMIT_GET] = { - .name = "FCH_NEVIS_LIMIT_GET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_LITTLE_LIMIT_GET] = { + .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LIMIT_GET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -186,14 +186,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_NEVIS_LIMIT_GET), + TC4_PLAT_FCH_GROUP_LITTLE_LIMIT_GET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_SET] = { - .name = "FCH_GELAS_LEVEL_SET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LEVEL_SET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LEVEL_SET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -202,14 +202,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_GELAS_LEVEL_SET), + TC4_PLAT_FCH_GROUP_MID_LEVEL_SET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_SET] = { - .name = "FCH_GELAS_LIMIT_SET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LIMIT_SET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LIMIT_SET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -218,14 +218,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_GELAS_LIMIT_SET), + TC4_PLAT_FCH_GROUP_MID_LIMIT_SET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LEVEL_GET] = { - .name = "FCH_GELAS_LEVEL_GET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LEVEL_GET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LEVEL_GET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -234,14 +234,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_GELAS_LEVEL_GET), + TC4_PLAT_FCH_GROUP_MID_LEVEL_GET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_GELAS_LIMIT_GET] = { - .name = "FCH_GELAS_LIMIT_GET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_MID_LIMIT_GET] = { + .name = "FCH_" TC4_GROUP_MID_NAME "_LIMIT_GET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -250,14 +250,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_GELAS_LIMIT_GET), + TC4_PLAT_FCH_GROUP_MID_LIMIT_GET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_SET] = { - .name = "FCH_TRAVIS_LEVEL_SET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LEVEL_SET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LEVEL_SET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -266,14 +266,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_TRAVIS_LEVEL_SET), + TC4_PLAT_FCH_GROUP_BIG_LEVEL_SET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_SET] = { - .name = "FCH_TRAVIS_LIMIT_SET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LIMIT_SET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LIMIT_SET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -282,14 +282,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_TRAVIS_LIMIT_SET), + TC4_PLAT_FCH_GROUP_BIG_LIMIT_SET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LEVEL_GET] = { - .name = "FCH_TRAVIS_LEVEL_GET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LEVEL_GET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LEVEL_GET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -298,14 +298,14 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_TRAVIS_LEVEL_GET), + TC4_PLAT_FCH_GROUP_BIG_LEVEL_GET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), }), }, - [TC4_TRANSPORT_SCMI_PERF_FCH_TRAVIS_LIMIT_GET] = { - .name = "FCH_TRAVIS_LIMIT_GET", + [TC4_TRANSPORT_SCMI_PERF_FCH_GROUP_BIG_LIMIT_GET] = { + .name = "FCH_" TC4_GROUP_BIG_NAME "_LIMIT_GET", .data = &(( struct mod_transport_channel_config){ .transport_type = @@ -314,7 +314,7 @@ static const struct fwk_element transport_element_table[ MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, .driver_id = FWK_ID_ELEMENT_INIT( FWK_MODULE_IDX_FCH_POLLED, - TC4_PLAT_FCH_TRAVIS_LIMIT_GET), + TC4_PLAT_FCH_GROUP_BIG_LIMIT_GET), .driver_api_id = FWK_ID_API_INIT( FWK_MODULE_IDX_FCH_POLLED, MOD_FCH_POLLED_API_IDX_TRANSPORT), -- GitLab From ab6ed01fd461d44fc644589355ff66a5331327df Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Wed, 22 May 2024 15:17:14 +0100 Subject: [PATCH 06/13] tc4: Statically initialise PPU_V1 configuration This configuration can easily be statically configured as nothing about it needs to be determined dynamically. To facilitate this, add FOR_EACH macros for the clusters and cores. Use these to initialise the structure. We also add a new enum for the PPU elements in a similar way to other modules. This will be used to make for easier tracking of the PPU elements (currently they just use immediate values). Signed-off-by: Jackson Cooper-Driver --- product/totalcompute/tc4/include/tc4_core.h | 13 +++ product/totalcompute/tc4/include/tc4_ppu_v1.h | 23 ++++ .../totalcompute/tc4/scp_css/config_ppu_v1.c | 104 +++++------------- 3 files changed, 63 insertions(+), 77 deletions(-) diff --git a/product/totalcompute/tc4/include/tc4_core.h b/product/totalcompute/tc4/include/tc4_core.h index 3a3d6096e..af2afc0bd 100644 --- a/product/totalcompute/tc4/include/tc4_core.h +++ b/product/totalcompute/tc4/include/tc4_core.h @@ -18,4 +18,17 @@ #define TC4_NUMBER_OF_CLUSTERS (1) #define TC4_NUMBER_OF_CORES (TC4_CORES_PER_CLUSTER * TC4_NUMBER_OF_CLUSTERS) +#define TC4_FOR_EACH_CORE(_func) \ + _func(0), \ + _func(1), \ + _func(2), \ + _func(3), \ + _func(4), \ + _func(5), \ + _func(6), \ + _func(7) + +#define TC4_FOR_EACH_CLUSTER(_func) \ + _func(0) + #endif /* TC4_CORE_H */ diff --git a/product/totalcompute/tc4/include/tc4_ppu_v1.h b/product/totalcompute/tc4/include/tc4_ppu_v1.h index 6fbb6a3c7..332322455 100644 --- a/product/totalcompute/tc4/include/tc4_ppu_v1.h +++ b/product/totalcompute/tc4/include/tc4_ppu_v1.h @@ -8,4 +8,27 @@ #ifndef TC4_PPU_V1_H #define TC4_PPU_V1_H +#include "scp_mmap.h" +#include "config_power_domain.h" +#include "tc4_core.h" + +#define PPU_V1_ENUM_CORE_GEN(_core_num) \ + PPU_V1_ELEMENT_IDX_CORE##_core_num + +#define PPU_V1_ENUM_CLUSTER_GEN(_cluster_num) \ + PPU_V1_ELEMENT_IDX_CLUSTER##_cluster_num + +/* Elements in the PPU_V1 module. One for each: + * - Core + * - Cluster + */ +enum ppu_v1_dev_idx { + TC4_FOR_EACH_CORE(PPU_V1_ENUM_CORE_GEN), + TC4_FOR_EACH_CLUSTER(PPU_V1_ENUM_CLUSTER_GEN), + PPU_V1_ELEMENT_IDX_MAX +}; + +#undef PPU_V1_ENUM_CORE_GEN +#undef PPU_V1_ENUM_CLUSTER_GEN + #endif /* TC4_PPU_V1_H */ diff --git a/product/totalcompute/tc4/scp_css/config_ppu_v1.c b/product/totalcompute/tc4/scp_css/config_ppu_v1.c index e9d37e925..b028ee94d 100644 --- a/product/totalcompute/tc4/scp_css/config_ppu_v1.c +++ b/product/totalcompute/tc4/scp_css/config_ppu_v1.c @@ -26,14 +26,34 @@ #include #include -/* Maximum PPU core name size including the null terminator */ -#define PPU_CORE_NAME_SIZE 12 +#define CORE_PPU_ELEMENT_INIT(_core_num) \ + [PPU_V1_ELEMENT_IDX_CORE##_core_num] = { \ + .name = "CORE" #_core_num, \ + .data = &((struct mod_ppu_v1_pd_config){ \ + .pd_type = MOD_PD_TYPE_CORE, \ + .ppu.reg_base = SCP_PPU_CORE_BASE(_core_num), \ + .ppu.irq = FWK_INTERRUPT_NONE, \ + .cluster_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, PPU_V1_ELEMENT_IDX_CLUSTER0), \ + .observer_id = FWK_ID_NONE_INIT, \ + }), \ + } -/* Maximum PPU cluster name size including the null terminator */ -#define PPU_CLUS_NAME_SIZE 6 +#define CLUSTER_PPU_ELEMENT_INIT(_cluster_num) \ + [PPU_V1_ELEMENT_IDX_CLUSTER##_cluster_num] = { \ + .name = "CLUSTER" #_cluster_num, \ + .data = &((struct mod_ppu_v1_pd_config){ \ + .pd_type = MOD_PD_TYPE_CLUSTER, \ + .ppu.reg_base = SCP_PPU_CLUSTER_BASE, \ + .ppu.irq = FWK_INTERRUPT_NONE, \ + .observer_id = FWK_ID_NONE_INIT, \ + }), \ + } -/* Cluster ID for Theodul DSU */ -#define CLUSTER_ID 0 +static const struct fwk_element ppu_v1_element_table[] = { + TC4_FOR_EACH_CORE(CORE_PPU_ELEMENT_INIT), + TC4_FOR_EACH_CLUSTER(CLUSTER_PPU_ELEMENT_INIT), + { 0 } +}; /* Module configuration data */ static struct mod_ppu_v1_config ppu_v1_config_data = { @@ -45,77 +65,7 @@ static struct mod_ppu_v1_config ppu_v1_config_data = { static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) { - struct fwk_element *element_table, *element; - struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; - unsigned char core_idx; - unsigned int core_count; - unsigned int cluster_count; - unsigned int core_element_count = 0; - - core_count = TC4_NUMBER_OF_CORES; - cluster_count = TC4_NUMBER_OF_CLUSTERS; - - /* - * Allocate element descriptors based on: - * Number of cores - * + Number of cluster descriptors - * + Number of system power domain descriptors - * + 1 terminator descriptor - */ - element_table = fwk_mm_calloc( - core_count + cluster_count + 1, - sizeof(struct fwk_element)); - if (element_table == NULL) { - return NULL; - } - - pd_config_table = fwk_mm_calloc( - core_count + cluster_count, sizeof(struct mod_ppu_v1_pd_config)); - if (pd_config_table == NULL) { - return NULL; - } - - for (core_idx = 0; - core_idx < TC4_NUMBER_OF_CORES; - core_idx++) { - element = &element_table[core_element_count]; - pd_config = &pd_config_table[core_element_count]; - - element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); - if (element->name == NULL) { - return NULL; - } - - (void)snprintf( - (char *)element->name, PPU_CORE_NAME_SIZE, "CORE%u", core_idx); - - element->data = pd_config; - - pd_config->pd_type = MOD_PD_TYPE_CORE; - pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(core_idx); - pd_config->ppu.irq = FWK_INTERRUPT_NONE; - pd_config->cluster_id = - FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, core_count); - pd_config->observer_id = FWK_ID_NONE; - core_element_count++; - } - - element = &element_table[core_count]; - pd_config = &pd_config_table[core_count]; - - element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); - if (element->name == NULL) { - return NULL; - } - - element->data = pd_config; - - pd_config->pd_type = MOD_PD_TYPE_CLUSTER; - pd_config->ppu.reg_base = SCP_PPU_CLUSTER_BASE; - pd_config->ppu.irq = FWK_INTERRUPT_NONE; - pd_config->observer_id = FWK_ID_NONE; - - return element_table; + return ppu_v1_element_table; } /* -- GitLab From a34d6620ef3c7369ef56d819ae02c71a027f9327 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Thu, 6 Jun 2024 13:53:37 +0100 Subject: [PATCH 07/13] tc4: Add SYSTOP0/1 to PPU config Add these two power domains to the PPU_V1 configuration. These are required to be enabled prior to the use of any features external to the SCP (including accessing system registers). Note that default_power_on is set to true which forces the PPU module to power them on during the initialisation stage. Signed-off-by: Jackson Cooper-Driver --- product/totalcompute/tc4/include/scp_mmap.h | 2 ++ product/totalcompute/tc4/include/tc4_ppu_v1.h | 14 ++++++++++++++ .../totalcompute/tc4/scp_css/config_ppu_v1.c | 17 +++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/product/totalcompute/tc4/include/scp_mmap.h b/product/totalcompute/tc4/include/scp_mmap.h index cb3acbafc..8ecb2829b 100644 --- a/product/totalcompute/tc4/include/scp_mmap.h +++ b/product/totalcompute/tc4/include/scp_mmap.h @@ -65,6 +65,8 @@ (SCP_ATU_LOG_ADDR_CLUSTER_UTIL) #define SCP_PPU_CLUSTER_BASE (SCP_UTILITY_BUS_BASE + 0x30000) #define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + (n * 0x100000)) +#define SCP_PPU_SYS0_BASE 0x5B800000 +#define SCP_PPU_SYS1_BASE 0x5B810000 /* AMEVCNTR1 address offset from AMU base address */ #define SCP_AMU_AMEVCNTR1_OFFSET 0x100 diff --git a/product/totalcompute/tc4/include/tc4_ppu_v1.h b/product/totalcompute/tc4/include/tc4_ppu_v1.h index 332322455..0f846cb83 100644 --- a/product/totalcompute/tc4/include/tc4_ppu_v1.h +++ b/product/totalcompute/tc4/include/tc4_ppu_v1.h @@ -12,19 +12,33 @@ #include "config_power_domain.h" #include "tc4_core.h" +/* TC4 contains two SYSTOP power domains: + * - SYSTOP0: This manages all system logic + * except the MCN slices + * - SYSTOP1: This manages the MCN slices + */ +#define PPU_V1_FOR_EACH_SYSTOP(_func) \ + _func(0), \ + _func(1) + #define PPU_V1_ENUM_CORE_GEN(_core_num) \ PPU_V1_ELEMENT_IDX_CORE##_core_num #define PPU_V1_ENUM_CLUSTER_GEN(_cluster_num) \ PPU_V1_ELEMENT_IDX_CLUSTER##_cluster_num +#define PPU_V1_ENUM_SYSTOP_GEN(_systop_num) \ + PPU_V1_ELEMENT_IDX_SYSTOP##_systop_num + /* Elements in the PPU_V1 module. One for each: * - Core * - Cluster + * - SYSTOP power domain */ enum ppu_v1_dev_idx { TC4_FOR_EACH_CORE(PPU_V1_ENUM_CORE_GEN), TC4_FOR_EACH_CLUSTER(PPU_V1_ENUM_CLUSTER_GEN), + PPU_V1_FOR_EACH_SYSTOP(PPU_V1_ENUM_SYSTOP_GEN), PPU_V1_ELEMENT_IDX_MAX }; diff --git a/product/totalcompute/tc4/scp_css/config_ppu_v1.c b/product/totalcompute/tc4/scp_css/config_ppu_v1.c index b028ee94d..21cd08f92 100644 --- a/product/totalcompute/tc4/scp_css/config_ppu_v1.c +++ b/product/totalcompute/tc4/scp_css/config_ppu_v1.c @@ -49,9 +49,26 @@ }), \ } +#define SYSTOP_PPU_ELEMENT_INIT(_systop_num) \ + [PPU_V1_ELEMENT_IDX_SYSTOP##_systop_num] = { \ + .name = "SYSTOP" #_systop_num, \ + .data = &((struct mod_ppu_v1_pd_config){ \ + .pd_type = MOD_PD_TYPE_SYSTEM, \ + .ppu.reg_base = SCP_PPU_SYS##_systop_num##_BASE, \ + .observer_id = FWK_ID_NONE_INIT, \ + .ppu.irq = FWK_INTERRUPT_NONE, \ + /* Force the PPU module to power this on during*/ \ + /* the initialisation stage, this is required */ \ + /* before accessing any registers external to */ \ + /* the SCP */ \ + .default_power_on = true, \ + }), \ + } + static const struct fwk_element ppu_v1_element_table[] = { TC4_FOR_EACH_CORE(CORE_PPU_ELEMENT_INIT), TC4_FOR_EACH_CLUSTER(CLUSTER_PPU_ELEMENT_INIT), + PPU_V1_FOR_EACH_SYSTOP(SYSTOP_PPU_ELEMENT_INIT), { 0 } }; -- GitLab From 1877b29e90e934529d9e9dec7f52d2f607b331a5 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Thu, 6 Jun 2024 14:32:54 +0100 Subject: [PATCH 08/13] tc4: Add SYSTOP1 to mod_system_power and use PPU Previously, the underlying driver used by the mod_system_power was the mock power domain module. This is replaced with the PPU_V1 module as per the hardware. SYSTOP1 is also added to the system power module. Note that the power_domain module does not change as only a single SYSTOP power domain is exposed to it from the system power module. Signed-off-by: Jackson Cooper-Driver --- .../tc4/scp_css/config_power_domain.c | 5 +++ .../tc4/scp_css/config_system_power.c | 36 +++++++++++-------- 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/product/totalcompute/tc4/scp_css/config_power_domain.c b/product/totalcompute/tc4/scp_css/config_power_domain.c index aa2aec08b..468ede8c8 100644 --- a/product/totalcompute/tc4/scp_css/config_power_domain.c +++ b/product/totalcompute/tc4/scp_css/config_power_domain.c @@ -81,6 +81,11 @@ static struct fwk_element tc4_power_domain_static_element_table[] = { .allowed_state_mask_table_size = FWK_ARRAY_SIZE(gputop_allowed_state_mask_table) }), }, + /* Note that on TC4, there are actually two separate SYSTOP PDs, SYSTOP0 + * which powers all system logic except the MCN slices and SYSTOP1 which + * controls the MCN slices. In mod_power_domain, however, this is + * abstracted out into a single SYSTOP PD. Requests to mod_system_power + * will be applied to both SYSTOP0 and SYSTOP1. */ [PD_STATIC_DEV_IDX_SYSTOP] = { .name = "SYSTOP", diff --git a/product/totalcompute/tc4/scp_css/config_system_power.c b/product/totalcompute/tc4/scp_css/config_system_power.c index a4dcfddf6..2297b986b 100644 --- a/product/totalcompute/tc4/scp_css/config_system_power.c +++ b/product/totalcompute/tc4/scp_css/config_system_power.c @@ -1,11 +1,11 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include "tc4_mock_ppu.h" +#include "tc4_ppu_v1.h" #include #include @@ -30,18 +30,34 @@ static const uint8_t [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, }; -static struct fwk_element system_power_element_table[2] = { +static struct fwk_element system_power_element_table[] = { [0] = { .name = "SYS-PPU-0", .data = &((struct mod_system_power_dev_config){ + .sys_ppu_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PPU_V1, + PPU_V1_ELEMENT_IDX_SYSTOP0), .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_MOCK_PPU, - MOCK_PPU_ELEMENT_IDX_SYS0), + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), .sys_state_table = system_power_to_sys_ppu0_state, }), }, - [1] = { 0 }, /* Termination description */ + [1] = + { + .name = "SYS-PPU-1", + .data = &((struct mod_system_power_dev_config){ + .sys_ppu_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PPU_V1, + PPU_V1_ELEMENT_IDX_SYSTOP1), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu0_state, + }), + }, + { 0 }, /* Termination description */ }; static struct mod_system_power_config system_power_config = { @@ -59,14 +75,6 @@ static struct mod_system_power_config system_power_config = { static const struct fwk_element *tc_system_get_element_table(fwk_id_t unused) { - struct mod_system_power_dev_config *dev_config_table; - - dev_config_table = - (struct mod_system_power_dev_config *)system_power_element_table[0] - .data; - dev_config_table->sys_ppu_id = - fwk_id_build_element_id(fwk_module_id_mock_ppu, 0); - return system_power_element_table; } -- GitLab From aa8576c9e9c2e9b9b933d991304d2d5fac34d4b7 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Thu, 11 Jul 2024 13:20:21 +0100 Subject: [PATCH 09/13] tc4: Deduplicate tc_system module This module is essentially the same between TC2/3 and TC4 except that the initial core and cluster state is different. Deduplicate this module and use a header file which each platform defines to resolve any differences. Signed-off-by: Jackson Cooper-Driver --- .../tc4/include/plat_mod_tc_system.h | 6 +- .../tc4/module/tc_system/CMakeLists.txt | 17 -- .../tc4/module/tc_system/Module.cmake | 10 - .../module/tc_system/include/mod_tc_system.h | 64 ----- .../tc4/module/tc_system/src/mod_tc_system.c | 237 ------------------ .../totalcompute/tc4/scp_css/Firmware.cmake | 2 +- 6 files changed, 3 insertions(+), 333 deletions(-) delete mode 100644 product/totalcompute/tc4/module/tc_system/CMakeLists.txt delete mode 100644 product/totalcompute/tc4/module/tc_system/Module.cmake delete mode 100644 product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h delete mode 100644 product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c diff --git a/product/totalcompute/tc4/include/plat_mod_tc_system.h b/product/totalcompute/tc4/include/plat_mod_tc_system.h index 6af984a39..2609f54d7 100644 --- a/product/totalcompute/tc4/include/plat_mod_tc_system.h +++ b/product/totalcompute/tc4/include/plat_mod_tc_system.h @@ -10,9 +10,7 @@ #include -#include - -#define PD_INIT_STATE_PRIMARY_CLUSTER (MOD_PD_STATE_OFF) -#define PD_INIT_STATE_PRIMARY_CORE (MOD_PD_STATE_OFF) +#define PD_INIT_STATE_PRIMARY_CLUSTER (MOD_PD_STATE_OFF) +#define PD_INIT_STATE_PRIMARY_CORE (MOD_PD_STATE_OFF) #endif /* PLAT_MOD_TC_SYSTEM_H */ diff --git a/product/totalcompute/tc4/module/tc_system/CMakeLists.txt b/product/totalcompute/tc4/module/tc_system/CMakeLists.txt deleted file mode 100644 index e085dc81d..000000000 --- a/product/totalcompute/tc4/module/tc_system/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# -add_library(${SCP_MODULE_TARGET} SCP_MODULE) - -target_include_directories(${SCP_MODULE_TARGET} - PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") - -target_sources(${SCP_MODULE_TARGET} - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_tc_system.c") - -target_link_libraries(${SCP_MODULE_TARGET} - PRIVATE module-clock module-sds module-power-domain module-ppu-v1 - module-scmi module-system-power) diff --git a/product/totalcompute/tc4/module/tc_system/Module.cmake b/product/totalcompute/tc4/module/tc_system/Module.cmake deleted file mode 100644 index fe7d3fcf8..000000000 --- a/product/totalcompute/tc4/module/tc_system/Module.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -set(SCP_MODULE "tc-system") - -set(SCP_MODULE_TARGET "module-tc-system") diff --git a/product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h b/product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h deleted file mode 100644 index c88c2ffc7..000000000 --- a/product/totalcompute/tc4/module/tc_system/include/mod_tc_system.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * TC System Support - */ - -#ifndef MOD_TC_SYSTEM_H -#define MOD_TC_SYSTEM_H - -#include - -/*! - * \addtogroup GroupTCModule TC Product Modules - * \{ - */ - -/*! - * \defgroup GroupTCSystem TC System Support - * \{ - */ - -/*! - * \brief Additional TC system power states. - */ -enum mod_tc_system_power_states { - MOD_TC_SYSTEM_POWER_STATE_SLEEP0 = MOD_PD_STATE_COUNT, - MOD_TC_SYSTEM_POWER_STATE_SLEEP1, - MOD_TC_SYSTEM_POWER_STATE_COUNT -}; - -/*! - * \brief System power state masks. - */ -enum mod_tc_system_power_state_masks { - MOD_TC_SYSTEM_POWER_STATE_SLEEP0_MASK = - (1 << MOD_TC_SYSTEM_POWER_STATE_SLEEP0), - MOD_TC_SYSTEM_POWER_STATE_SLEEP1_MASK = - (1 << MOD_TC_SYSTEM_POWER_STATE_SLEEP1), -}; - -/*! - * \brief Indices of the interfaces exposed by the module. - */ -enum mod_tc_system_api_idx { - /*! API index for the driver interface of the SYSTEM POWER module */ - MOD_TC_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER, - - /*! Number of exposed interfaces */ - MOD_TC_SYSTEM_API_COUNT -}; - -/*! - * \} - */ - -/*! - * \} - */ - -#endif /* MOD_TC_SYSTEM_H */ diff --git a/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c b/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c deleted file mode 100644 index c3c5ccf6a..000000000 --- a/product/totalcompute/tc4/module/tc_system/src/mod_tc_system.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * TC System Support. - */ - -#include "clock_soc.h" -#include "scp_pik.h" -#include "tc_core.h" -#include "tc_scmi.h" -#include "tc_sds.h" - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -/* SCMI services required to enable the messaging stack */ -static unsigned int scmi_notification_table[1] = { - (unsigned int)SCP_TC_SCMI_SERVICE_IDX_PSCI, -}; - -/* Module context */ -struct tc_system_ctx { - /* Pointer to the Interrupt Service Routine API of the PPU_V1 module */ - const struct ppu_v1_isr_api *ppu_v1_isr_api; - - /* Power domain module restricted API pointer */ - struct mod_pd_restricted_api *mod_pd_restricted_api; - - /* SDS API pointer */ - const struct mod_sds_api *sds_api; -}; - -struct tc_system_isr { - unsigned int interrupt; - void (*handler)(void); -}; - -static struct tc_system_ctx mod_ctx; - -static const uint32_t feature_flags = - (TC_SDS_FEATURE_FIRMWARE_MASK | TC_SDS_FEATURE_DMC_MASK | - TC_SDS_FEATURE_MESSAGING_MASK); - -static fwk_id_t sds_feature_availability_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, 1); - -/* - * SCMI Messaging stack - */ - -static int messaging_stack_ready(void) -{ - const struct mod_sds_structure_desc *sds_structure_desc = - fwk_module_get_data(sds_feature_availability_id); - - /* - * Write SDS Feature Availability to signal the completion of the messaging - * stack - */ - return mod_ctx.sds_api->struct_write( - sds_structure_desc->id, - 0, - (void *)(&feature_flags), - sds_structure_desc->size); -} - -/* - * System power's driver API - */ - -static int tc_system_shutdown(enum mod_pd_system_shutdown system_shutdown) -{ - NVIC_SystemReset(); - - return FWK_E_DEVICE; -} - -static const struct mod_system_power_driver_api - tc_system_system_power_driver_api = { - .system_shutdown = tc_system_shutdown, - }; - -/* - * Functions fulfilling the framework's module interface - */ - -static int tc_system_mod_init( - fwk_id_t module_id, - unsigned int unused, - const void *unused2) -{ - return FWK_SUCCESS; -} - -static int tc_system_bind(fwk_id_t id, unsigned int round) -{ - int status; - - if (round > 0) { - return FWK_SUCCESS; - } - - status = fwk_module_bind( - FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), - FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), - &mod_ctx.mod_pd_restricted_api); - if (status != FWK_SUCCESS) { - return status; - } - - status = fwk_module_bind( - FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1), - FWK_ID_API(FWK_MODULE_IDX_PPU_V1, MOD_PPU_V1_API_IDX_ISR), - &mod_ctx.ppu_v1_isr_api); - if (status != FWK_SUCCESS) { - return status; - } - - return fwk_module_bind( - fwk_module_id_sds, FWK_ID_API(FWK_MODULE_IDX_SDS, 0), &mod_ctx.sds_api); -} - -static int tc_system_process_bind_request( - fwk_id_t requester_id, - fwk_id_t pd_id, - fwk_id_t api_id, - const void **api) -{ - *api = &tc_system_system_power_driver_api; - return FWK_SUCCESS; -} - -static int tc_system_start(fwk_id_t id) -{ - int status; - unsigned int i; - - /* - * Subscribe to these SCMI channels in order to know when they have all - * initialized. - * At that point we can consider the SCMI stack to be initialized from - * the point of view of the PSCI agent. - */ - for (i = 0; i < FWK_ARRAY_SIZE(scmi_notification_table); i++) { - status = fwk_notification_subscribe( - mod_scmi_notification_id_initialized, - fwk_id_build_element_id( - fwk_module_id_scmi, scmi_notification_table[i]), - id); - if (status != FWK_SUCCESS) { - return status; - } - } - - /* - * Subscribe to the SDS initialized notification so we can correctly let the - * PSCI agent know that the SCMI stack is initialized. - */ - status = fwk_notification_subscribe( - mod_sds_notification_id_initialized, fwk_module_id_sds, id); - if (status != FWK_SUCCESS) { - return status; - } - - return mod_ctx.mod_pd_restricted_api->set_state( - FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), - MOD_PD_SET_STATE_NO_RESP, - MOD_PD_COMPOSITE_STATE( - MOD_PD_LEVEL_2, - 0, - MOD_PD_STATE_ON, - MOD_PD_STATE_OFF, - MOD_PD_STATE_OFF)); -} - -static int tc_system_process_notification( - const struct fwk_event *event, - struct fwk_event *resp_event) -{ - static unsigned int scmi_notification_count = 0; - static bool sds_notification_received = false; - - fwk_assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE)); - - if (fwk_id_is_equal(event->id, mod_scmi_notification_id_initialized)) { - scmi_notification_count++; - } else if (fwk_id_is_equal( - event->id, mod_sds_notification_id_initialized)) { - sds_notification_received = true; - } else { - return FWK_E_PARAM; - } - - if ((scmi_notification_count == FWK_ARRAY_SIZE(scmi_notification_table)) && - sds_notification_received) { - messaging_stack_ready(); - - scmi_notification_count = 0; - sds_notification_received = false; - } - - return FWK_SUCCESS; -} - -const struct fwk_module module_tc_system = { - .type = FWK_MODULE_TYPE_DRIVER, - .api_count = MOD_TC_SYSTEM_API_COUNT, - .init = tc_system_mod_init, - .bind = tc_system_bind, - .process_bind_request = tc_system_process_bind_request, - .process_notification = tc_system_process_notification, - .start = tc_system_start, -}; - -const struct fwk_module_config config_tc_system = { 0 }; diff --git a/product/totalcompute/tc4/scp_css/Firmware.cmake b/product/totalcompute/tc4/scp_css/Firmware.cmake index 137f67123..7812fb2e4 100644 --- a/product/totalcompute/tc4/scp_css/Firmware.cmake +++ b/product/totalcompute/tc4/scp_css/Firmware.cmake @@ -40,7 +40,7 @@ set(SCP_PLATFORM_VARIANT ${SCP_PLATFORM_VARIANT_INIT} CACHE STRING list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/product/totalcompute/tc4/module/tc4_bl1") -list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/product/totalcompute/tc4/module/tc_system") +list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/product/totalcompute/common/module/tc_system") # The order of the modules in the following list is the order in which the # modules are initialized, bound, started during the pre-runtime phase. -- GitLab From 446ffa481cedb782ec4ab20acf963c29620448b0 Mon Sep 17 00:00:00 2001 From: Tintu Thomas Date: Tue, 16 Jul 2024 11:09:55 +0100 Subject: [PATCH 10/13] tc4: Modify fch, transport configs * Split the common part of fch config to tc_scmi_perf header * Clean up transport config structure definition Signed-off-by: Tintu Thomas --- .../tc4/scp_css/config_fch_polled.c | 38 +------------------ .../tc4/scp_css/config_transport.c | 16 ++------ 2 files changed, 4 insertions(+), 50 deletions(-) diff --git a/product/totalcompute/tc4/scp_css/config_fch_polled.c b/product/totalcompute/tc4/scp_css/config_fch_polled.c index 5bef971c8..3b5f4d755 100644 --- a/product/totalcompute/tc4/scp_css/config_fch_polled.c +++ b/product/totalcompute/tc4/scp_css/config_fch_polled.c @@ -5,38 +5,19 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "scp_mmap.h" #include "tc4_dvfs.h" #include "tc4_scmi.h" #include "tc4_timer.h" #include "tc_core.h" +#include "tc_scmi_perf.h" #include -#include #include #include #include #include -#include - -#define FC_LEVEL_SET_ADDR(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_SET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - -#define FC_LIMIT_SET_ADDR(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_SET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - -#define FC_LEVEL_GET_ADDR(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_GET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - -#define FC_LIMIT_GET_ADDR(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_GET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - /* get the channel offset by itself and add the AP location */ #define FC_LEVEL_SET_AP_ADDR(PERF_IDX) \ (FC_LEVEL_SET_ADDR(PERF_IDX) - SCP_SCMI_PAYLOAD_NS_A2P_BASE + \ @@ -64,23 +45,6 @@ static struct mod_fch_polled_config module_config = { .attributes = 0, }; -enum fch_polled_length { - FCH_POLLED_LEVEL_SET_LENGTH = sizeof(uint32_t), - FCH_POLLED_LIMIT_SET_LENGTH = - sizeof(struct mod_scmi_perf_fast_channel_limit), - FCH_POLLED_LEVEL_GET_LENGTH = sizeof(uint32_t), - FCH_POLLED_LIMIT_GET_LENGTH = - sizeof(struct mod_scmi_perf_fast_channel_limit) -}; - -#define FCH_ADDR_INIT(scp_addr, ap_addr, len) \ - &((struct mod_fch_polled_channel_config){ \ - .fch_addr = { \ - .local_view_address = scp_addr, \ - .target_view_address = ap_addr, \ - .length = len, \ - } }) - static const struct fwk_element fch_polled_element_table[] = { [TC4_PLAT_FCH_GROUP_LITTLE_LEVEL_SET] = { .name = "FCH_" TC4_GROUP_LITTLE_NAME "_LEVEL_SET", diff --git a/product/totalcompute/tc4/scp_css/config_transport.c b/product/totalcompute/tc4/scp_css/config_transport.c index 7c23818bd..b3bf08432 100644 --- a/product/totalcompute/tc4/scp_css/config_transport.c +++ b/product/totalcompute/tc4/scp_css/config_transport.c @@ -24,12 +24,10 @@ #include -static const struct fwk_element transport_element_table[ +static const struct fwk_element transport_element_table[] = { #ifdef BUILD_HAS_MOD_TRANSPORT_FC - TC4_TRANSPORT_CHANNELS_COUNT + 1] = { [TC4_TRANSPORT_SCMI_SERVICE_PSCI] = { #else - SCP_TC4_TRANSPORT_SERVICE_IDX_COUNT + 1] = { [SCP_TC4_TRANSPORT_SERVICE_IDX_PSCI] = { #endif .name = "PSCI", @@ -385,11 +383,7 @@ static const struct fwk_element transport_element_table[ }), }, #endif -#ifdef BUILD_HAS_MOD_TRANSPORT_FC - [TC4_TRANSPORT_CHANNELS_COUNT] = { 0 }, -#else - [SCP_TC4_TRANSPORT_SERVICE_IDX_COUNT] = { 0 }, -#endif + { 0 }, }; static const struct fwk_element *transport_get_element_table(fwk_id_t module_id) @@ -397,11 +391,7 @@ static const struct fwk_element *transport_get_element_table(fwk_id_t module_id) unsigned int idx; struct mod_transport_channel_config *config; -#ifdef BUILD_HAS_MOD_TRANSPORT_FC - for (idx = 0; idx < TC4_TRANSPORT_CHANNELS_COUNT; idx++) { -#else - for (idx = 0; idx < SCP_TC4_TRANSPORT_SERVICE_IDX_SCP2RSS; idx++) { -#endif + for (idx = 0; idx < FWK_ARRAY_SIZE(transport_element_table) - 1; idx++) { config = (struct mod_transport_channel_config *)(transport_element_table[idx] .data); -- GitLab From 0a05cea86cf87e57eabac54a4ed1a30db10b8ac2 Mon Sep 17 00:00:00 2001 From: Quoc Khanh Le Date: Thu, 19 Sep 2024 12:19:46 +0100 Subject: [PATCH 11/13] tc4: Add CME power domain configuration Add power domain configuration for TC4 CMEs. As the PPUs for the CME are not fully implemented on FVP, we add use a mock PPU. In the case of FPGA, we make use of the PPU V1 in the same way as with the cores and cluster. Signed-off-by: Jackson Cooper-Driver Signed-off-by: Quoc Khanh Le --- .../tc4/include/config_power_domain.h | 5 +++ product/totalcompute/tc4/include/scp_mmap.h | 44 +++++++++---------- product/totalcompute/tc4/include/tc4_core.h | 27 +++++------- .../totalcompute/tc4/include/tc4_mock_ppu.h | 7 +++ product/totalcompute/tc4/include/tc4_ppu_v1.h | 15 ++++--- .../tc4/scp_css/config_mock_ppu.c | 22 ++++++++-- .../tc4/scp_css/config_power_domain.c | 35 ++++++++++++++- .../totalcompute/tc4/scp_css/config_ppu_v1.c | 21 ++++++++- 8 files changed, 126 insertions(+), 50 deletions(-) diff --git a/product/totalcompute/tc4/include/config_power_domain.h b/product/totalcompute/tc4/include/config_power_domain.h index e9ba4dc02..e3c483f7c 100644 --- a/product/totalcompute/tc4/include/config_power_domain.h +++ b/product/totalcompute/tc4/include/config_power_domain.h @@ -8,8 +8,12 @@ #ifndef CONFIG_POWER_DOMAIN_H #define CONFIG_POWER_DOMAIN_H +#include + #include +#define PD_STATIC_CME_INIT(_cme) PD_STATIC_DEV_IDX_CME##_cme + /* * Power domain indices for the statically defined domains used for: * - Indexing the domains in the tc4_power_domain_static_element_table @@ -19,6 +23,7 @@ * core_count + cluster_count + pd_static_dev_idx */ enum pd_static_dev_idx { + TC4_FOR_EACH_CME(PD_STATIC_CME_INIT), PD_STATIC_DEV_IDX_GPUTOP, PD_STATIC_DEV_IDX_SYSTOP, PD_STATIC_DEV_IDX_COUNT, diff --git a/product/totalcompute/tc4/include/scp_mmap.h b/product/totalcompute/tc4/include/scp_mmap.h index 8ecb2829b..183ce8801 100644 --- a/product/totalcompute/tc4/include/scp_mmap.h +++ b/product/totalcompute/tc4/include/scp_mmap.h @@ -11,22 +11,22 @@ #include "tc4_atu.h" /* SCP TCM size */ -#define SCP_ITCM_SIZE (256 * 1024) -#define SCP_DTCM_SIZE (256 * 1024) +#define SCP_ITCM_SIZE (256 * 1024) +#define SCP_DTCM_SIZE (256 * 1024) /* SCP TCM base addresses */ -#define SCP_ITCM_NS_BASE 0x00000000 -#define SCP_ITCM_S_BASE 0x10000000 -#define SCP_DTCM_NS_BASE 0x20000000 -#define SCP_DTCM_S_BASE 0x30000000 +#define SCP_ITCM_NS_BASE 0x00000000 +#define SCP_ITCM_S_BASE 0x10000000 +#define SCP_DTCM_NS_BASE 0x20000000 +#define SCP_DTCM_S_BASE 0x30000000 /* SCP Boot and Runtime base addresses */ -#define SCP_BOOT_BASE SCP_ITCM_S_BASE -#define SCP_RUNTIME_BASE SCP_DTCM_NS_BASE +#define SCP_BOOT_BASE SCP_ITCM_S_BASE +#define SCP_RUNTIME_BASE SCP_DTCM_NS_BASE /* SCP Boot and Runtime maximum sizes */ -#define SCP_BOOT_SIZE SCP_ITCM_SIZE -#define SCP_RUNTIME_SIZE SCP_DTCM_SIZE +#define SCP_BOOT_SIZE SCP_ITCM_SIZE +#define SCP_RUNTIME_SIZE SCP_DTCM_SIZE /* SCP trusted and non-trusted RAM base address */ #define SCP_TRUSTED_RAM_BASE (SCP_ATU_LOG_ADDR_SHARED_SRAM) @@ -51,7 +51,7 @@ #define SCP_UART_BOARD_BASE (0x4A040000) -#define SCP_PIK_SCP_BASE (SCP_PIK_SYSTEM_BASE + 0x200000) +#define SCP_PIK_SCP_BASE (SCP_PIK_SYSTEM_BASE + 0x200000) #define SCP_GTCLK_CNTCONTROL_BASE (SCP_ATU_LOG_ADDR_GTCLK) #define SCP_GTCLK_CNTCTL_BASE (SCP_ATU_LOG_ADDR_GTCLK_AP) @@ -61,12 +61,12 @@ #define SCP_PIK_DPU_BASE (SCP_PIK_SYSTEM_BASE + 0x7C0000) #define SCP_PIK_GPU_BASE (SCP_PIK_SYSTEM_BASE + 0x80000) -#define SCP_UTILITY_BUS_BASE \ - (SCP_ATU_LOG_ADDR_CLUSTER_UTIL) +#define SCP_UTILITY_BUS_BASE (SCP_ATU_LOG_ADDR_CLUSTER_UTIL) #define SCP_PPU_CLUSTER_BASE (SCP_UTILITY_BUS_BASE + 0x30000) -#define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + (n * 0x100000)) +#define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + ((n)*0x100000)) #define SCP_PPU_SYS0_BASE 0x5B800000 #define SCP_PPU_SYS1_BASE 0x5B810000 +#define SCP_PPU_CME_BASE(n) (SCP_PPU_CORE_BASE((n) + 8)) /* AMEVCNTR1 address offset from AMU base address */ #define SCP_AMU_AMEVCNTR1_OFFSET 0x100 @@ -79,16 +79,16 @@ #define SCP_AMU_AMEVCNTR1X(CPU_IDX) \ (SCP_AMU_CORE_BASE(CPU_IDX) + SCP_AMU_AMEVCNTR1_OFFSET) -#define SCP_MHU_SCP_AP_RCV_NS UINT32_C(0x401f0000) -#define SCP_MHU_SCP_AP_SND_NS UINT32_C(0x401e0000) -#define SCP_MHU_SCP_AP_RCV_S UINT32_C(0x40170000) -#define SCP_MHU_SCP_AP_SND_S UINT32_C(0x40160000) +#define SCP_MHU_SCP_AP_RCV_NS UINT32_C(0x401f0000) +#define SCP_MHU_SCP_AP_SND_NS UINT32_C(0x401e0000) +#define SCP_MHU_SCP_AP_RCV_S UINT32_C(0x40170000) +#define SCP_MHU_SCP_AP_SND_S UINT32_C(0x40160000) #if defined(PLAT_FVP) -#define SCP_MHU_SCP_RSS_RCV_S_CLUS0 0x5a010000 -#define SCP_MHU_SCP_RSS_SND_S_CLUS0 0x5a000000 +# define SCP_MHU_SCP_RSS_RCV_S_CLUS0 0x5a010000 +# define SCP_MHU_SCP_RSS_SND_S_CLUS0 0x5a000000 -#define SCP_MHU_SCP_RSS_NUM_DBCH (4) +# define SCP_MHU_SCP_RSS_NUM_DBCH (4) #endif #define SCP_PLL_BASE (SCP_ATU_LOG_ADDR_PLL) @@ -128,7 +128,7 @@ #define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE) #define SCP_SCMI_PAYLOAD_NS_P2A_BASE \ - (SCP_SCMI_PAYLOAD_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) + (SCP_SCMI_PAYLOAD_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) #define SCMI_FAST_CHANNEL_BASE \ (SCP_SCMI_PAYLOAD_NS_P2A_BASE + (3 * SCP_SCMI_PAYLOAD_SIZE)) diff --git a/product/totalcompute/tc4/include/tc4_core.h b/product/totalcompute/tc4/include/tc4_core.h index af2afc0bd..e55eeb0a1 100644 --- a/product/totalcompute/tc4/include/tc4_core.h +++ b/product/totalcompute/tc4/include/tc4_core.h @@ -10,25 +10,22 @@ #include -#define TC4_GROUP_LITTLE_NAME "GROUP_LITTLE" -#define TC4_GROUP_MID_NAME "GROUP_MID" -#define TC4_GROUP_BIG_NAME "GROUP_BIG" +#define TC4_GROUP_LITTLE_NAME "GROUP_LITTLE" +#define TC4_GROUP_MID_NAME "GROUP_MID" +#define TC4_GROUP_BIG_NAME "GROUP_BIG" #define TC4_CORES_PER_CLUSTER (8) +#define TC4_CMES_PER_CLUSTER (2) #define TC4_NUMBER_OF_CLUSTERS (1) -#define TC4_NUMBER_OF_CORES (TC4_CORES_PER_CLUSTER * TC4_NUMBER_OF_CLUSTERS) +#define TC4_NUMBER_OF_CORES (TC4_CORES_PER_CLUSTER * TC4_NUMBER_OF_CLUSTERS) +#define TC4_NUMBER_OF_CMES (TC4_CMES_PER_CLUSTER * TC4_NUMBER_OF_CLUSTERS) #define TC4_FOR_EACH_CORE(_func) \ - _func(0), \ - _func(1), \ - _func(2), \ - _func(3), \ - _func(4), \ - _func(5), \ - _func(6), \ - _func(7) - -#define TC4_FOR_EACH_CLUSTER(_func) \ - _func(0) + _func(0), _func(1), _func(2), _func(3), _func(4), _func(5), _func(6), \ + _func(7) + +#define TC4_FOR_EACH_CME(_func) _func(0), _func(1) + +#define TC4_FOR_EACH_CLUSTER(_func) _func(0) #endif /* TC4_CORE_H */ diff --git a/product/totalcompute/tc4/include/tc4_mock_ppu.h b/product/totalcompute/tc4/include/tc4_mock_ppu.h index f1f28f12a..ac3211f8e 100644 --- a/product/totalcompute/tc4/include/tc4_mock_ppu.h +++ b/product/totalcompute/tc4/include/tc4_mock_ppu.h @@ -11,7 +11,14 @@ #ifndef TC4_MOCK_PPU_H #define TC4_MOCK_PPU_H +#include + +#define MOCK_PPU_ENUM_CME_GEN(_cme) MOCK_PPU_ELEMENT_IDX_CME##_cme + enum mock_ppu_static_element_idx { +#if defined(PLAT_FVP) + TC4_FOR_EACH_CME(MOCK_PPU_ENUM_CME_GEN), +#endif MOCK_PPU_ELEMENT_IDX_SYS0, MOCK_PPU_ELEMENT_IDX_GPUCGRP, MOCK_PPU_ELEMENT_IDX_COUNT diff --git a/product/totalcompute/tc4/include/tc4_ppu_v1.h b/product/totalcompute/tc4/include/tc4_ppu_v1.h index 0f846cb83..5c626e030 100644 --- a/product/totalcompute/tc4/include/tc4_ppu_v1.h +++ b/product/totalcompute/tc4/include/tc4_ppu_v1.h @@ -8,8 +8,8 @@ #ifndef TC4_PPU_V1_H #define TC4_PPU_V1_H -#include "scp_mmap.h" #include "config_power_domain.h" +#include "scp_mmap.h" #include "tc4_core.h" /* TC4 contains two SYSTOP power domains: @@ -17,27 +17,30 @@ * except the MCN slices * - SYSTOP1: This manages the MCN slices */ -#define PPU_V1_FOR_EACH_SYSTOP(_func) \ - _func(0), \ - _func(1) +#define PPU_V1_FOR_EACH_SYSTOP(_func) _func(0), _func(1) -#define PPU_V1_ENUM_CORE_GEN(_core_num) \ - PPU_V1_ELEMENT_IDX_CORE##_core_num +#define PPU_V1_ENUM_CORE_GEN(_core_num) PPU_V1_ELEMENT_IDX_CORE##_core_num #define PPU_V1_ENUM_CLUSTER_GEN(_cluster_num) \ PPU_V1_ELEMENT_IDX_CLUSTER##_cluster_num +#define PPU_V1_ENUM_CME_GEN(_cme_num) PPU_V1_ELEMENT_IDX_CME##_cme_num + #define PPU_V1_ENUM_SYSTOP_GEN(_systop_num) \ PPU_V1_ELEMENT_IDX_SYSTOP##_systop_num /* Elements in the PPU_V1 module. One for each: * - Core * - Cluster + * - CME * - SYSTOP power domain */ enum ppu_v1_dev_idx { TC4_FOR_EACH_CORE(PPU_V1_ENUM_CORE_GEN), TC4_FOR_EACH_CLUSTER(PPU_V1_ENUM_CLUSTER_GEN), +#if !defined(PLAT_FVP) + TC4_FOR_EACH_CME(PPU_V1_ENUM_CME_GEN), +#endif PPU_V1_FOR_EACH_SYSTOP(PPU_V1_ENUM_SYSTOP_GEN), PPU_V1_ELEMENT_IDX_MAX }; diff --git a/product/totalcompute/tc4/scp_css/config_mock_ppu.c b/product/totalcompute/tc4/scp_css/config_mock_ppu.c index 3902094c7..713f6f79e 100644 --- a/product/totalcompute/tc4/scp_css/config_mock_ppu.c +++ b/product/totalcompute/tc4/scp_css/config_mock_ppu.c @@ -13,14 +13,30 @@ #include +#define CME_MOCK_PPU_ELEMENT_INIT(_cme) \ + [MOCK_PPU_ELEMENT_IDX_CME##_cme] = { \ + .name = "CME" #_cme, \ + .data = &((struct mod_mock_ppu_pd_config){ \ + .pd_type = MOD_PD_TYPE_DEVICE, \ + .ppu.reg_base = (uintptr_t)&cme##_cme##_mock_ppu, \ + }), \ + } + /* Need to pass an allocated memory region * to the mock PPU which it can then access. It * only accesses the first word so that is all * we need */ static uint32_t sys0_mock_ppu, gpucgrp_mock_ppu; -static struct fwk_element \ -mock_ppu_system_element_table[MOCK_PPU_ELEMENT_IDX_COUNT+1] = { +#if defined(PLAT_FVP) +static uint32_t cme0_mock_ppu, cme1_mock_ppu; +#endif + +static struct fwk_element +mock_ppu_system_element_table[] = { +#if defined(PLAT_FVP) + TC4_FOR_EACH_CME(CME_MOCK_PPU_ELEMENT_INIT), +#endif [MOCK_PPU_ELEMENT_IDX_SYS0] = { .name = "SYS0", @@ -37,7 +53,7 @@ mock_ppu_system_element_table[MOCK_PPU_ELEMENT_IDX_COUNT+1] = { .ppu.reg_base = (uintptr_t)&gpucgrp_mock_ppu, }), }, - [MOCK_PPU_ELEMENT_IDX_COUNT] = {0}, + {0}, }; static const struct fwk_element *mock_ppu_get_element_table(fwk_id_t module_id) diff --git a/product/totalcompute/tc4/scp_css/config_power_domain.c b/product/totalcompute/tc4/scp_css/config_power_domain.c index 468ede8c8..5438a5244 100644 --- a/product/totalcompute/tc4/scp_css/config_power_domain.c +++ b/product/totalcompute/tc4/scp_css/config_power_domain.c @@ -6,16 +6,16 @@ */ #include "config_power_domain.h" -#include "tc4_ppu_v1.h" #include "tc4_core.h" #include "tc4_mock_ppu.h" +#include "tc4_ppu_v1.h" #include "tc_power_domain.h" #include +#include #include #include -#include #include #include @@ -62,10 +62,41 @@ static const uint32_t core_pd_allowed_state_mask_table[2] = { [MOD_PD_STATE_ON] = TC_CORE_VALID_STATE_MASK, }; +#if defined(PLAT_FVP) +# define PD_CME_POWER_DOMAIN_INIT(_cme) \ + [PD_STATIC_DEV_IDX_CME##_cme] = { \ + .name = "CME" #_cme, \ + .data = &((struct mod_power_domain_element_config){ \ + .attributes.pd_type = MOD_PD_TYPE_DEVICE, \ + .driver_id = FWK_ID_ELEMENT_INIT( \ + FWK_MODULE_IDX_MOCK_PPU, MOCK_PPU_ELEMENT_IDX_CME##_cme), \ + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MOCK_PPU, 0), \ + .allowed_state_mask_table = core_pd_allowed_state_mask_table, \ + .allowed_state_mask_table_size = \ + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table) }), \ + } +#else +# define PD_CME_POWER_DOMAIN_INIT(_cme) \ + [PD_STATIC_DEV_IDX_CME##_cme] = { \ + .name = "CME" #_cme, \ + .data = &((struct mod_power_domain_element_config){ \ + .attributes.pd_type = MOD_PD_TYPE_DEVICE, \ + .driver_id = FWK_ID_ELEMENT_INIT( \ + FWK_MODULE_IDX_PPU_V1, PPU_V1_ELEMENT_IDX_CME##_cme), \ + .api_id = FWK_ID_API_INIT( \ + FWK_MODULE_IDX_PPU_V1, \ + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), \ + .allowed_state_mask_table = core_pd_allowed_state_mask_table, \ + .allowed_state_mask_table_size = \ + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table) }), \ + } +#endif + /* Power module specific configuration data (none) */ static const struct mod_power_domain_config tc4_power_domain_config = { 0 }; static struct fwk_element tc4_power_domain_static_element_table[] = { + TC4_FOR_EACH_CME(PD_CME_POWER_DOMAIN_INIT), [PD_STATIC_DEV_IDX_GPUTOP] = { .name = "GPUCGRP", diff --git a/product/totalcompute/tc4/scp_css/config_ppu_v1.c b/product/totalcompute/tc4/scp_css/config_ppu_v1.c index 21cd08f92..7f9434959 100644 --- a/product/totalcompute/tc4/scp_css/config_ppu_v1.c +++ b/product/totalcompute/tc4/scp_css/config_ppu_v1.c @@ -6,9 +6,9 @@ */ #include "config_power_domain.h" -#include "tc4_ppu_v1.h" #include "scp_mmap.h" #include "tc4_core.h" +#include "tc4_ppu_v1.h" #include #include @@ -33,7 +33,21 @@ .pd_type = MOD_PD_TYPE_CORE, \ .ppu.reg_base = SCP_PPU_CORE_BASE(_core_num), \ .ppu.irq = FWK_INTERRUPT_NONE, \ - .cluster_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, PPU_V1_ELEMENT_IDX_CLUSTER0), \ + .cluster_id = FWK_ID_ELEMENT_INIT( \ + FWK_MODULE_IDX_PPU_V1, PPU_V1_ELEMENT_IDX_CLUSTER0), \ + .observer_id = FWK_ID_NONE_INIT, \ + }), \ + } + +#define CME_PPU_ELEMENT_INIT(_cme_num) \ + [PPU_V1_ELEMENT_IDX_CME##_cme_num] = { \ + .name = "CME" #_cme_num, \ + .data = &((struct mod_ppu_v1_pd_config){ \ + .pd_type = MOD_PD_TYPE_DEVICE, \ + .ppu.reg_base = SCP_PPU_CME_BASE(_cme_num), \ + .ppu.irq = FWK_INTERRUPT_NONE, \ + .cluster_id = FWK_ID_ELEMENT_INIT( \ + FWK_MODULE_IDX_PPU_V1, PPU_V1_ELEMENT_IDX_CLUSTER0), \ .observer_id = FWK_ID_NONE_INIT, \ }), \ } @@ -68,6 +82,9 @@ static const struct fwk_element ppu_v1_element_table[] = { TC4_FOR_EACH_CORE(CORE_PPU_ELEMENT_INIT), TC4_FOR_EACH_CLUSTER(CLUSTER_PPU_ELEMENT_INIT), +#if !defined(PLAT_FVP) + TC4_FOR_EACH_CME(CME_PPU_ELEMENT_INIT), +#endif PPU_V1_FOR_EACH_SYSTOP(SYSTOP_PPU_ELEMENT_INIT), { 0 } }; -- GitLab From 4f27f62df4e3208dc88c973f84d859b55e29c213 Mon Sep 17 00:00:00 2001 From: Quoc Khanh Le Date: Mon, 7 Oct 2024 09:49:54 +0100 Subject: [PATCH 12/13] tc4: ppu_v1: set cluster opmode to 7 The configuration changes the cluster to use PPU opmode 7 which enables all the caches Signed-off-by: Jackson Cooper-Driver Signed-off-by: Quoc Khanh Le --- product/totalcompute/tc4/scp_css/config_ppu_v1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/product/totalcompute/tc4/scp_css/config_ppu_v1.c b/product/totalcompute/tc4/scp_css/config_ppu_v1.c index 7f9434959..4ec37cf8a 100644 --- a/product/totalcompute/tc4/scp_css/config_ppu_v1.c +++ b/product/totalcompute/tc4/scp_css/config_ppu_v1.c @@ -60,6 +60,7 @@ .ppu.reg_base = SCP_PPU_CLUSTER_BASE, \ .ppu.irq = FWK_INTERRUPT_NONE, \ .observer_id = FWK_ID_NONE_INIT, \ + .opmode = 7, \ }), \ } -- GitLab From 163637afab84ad140b38847211b96aeef5a32e50 Mon Sep 17 00:00:00 2001 From: Quoc Khanh Le Date: Thu, 10 Oct 2024 17:00:14 +0100 Subject: [PATCH 13/13] tc4: Add opmode for SLC on Signed-off-by: Vishnu Satheesh Signed-off-by: Jackson Cooper-Driver Signed-off-by: Quoc Khanh Le --- product/totalcompute/tc4/scp_css/config_ppu_v1.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/product/totalcompute/tc4/scp_css/config_ppu_v1.c b/product/totalcompute/tc4/scp_css/config_ppu_v1.c index 4ec37cf8a..b8a7da733 100644 --- a/product/totalcompute/tc4/scp_css/config_ppu_v1.c +++ b/product/totalcompute/tc4/scp_css/config_ppu_v1.c @@ -26,6 +26,9 @@ #include #include +#define SCP_PPU_SYS0_OPMODE (0) +#define SCP_PPU_SYS1_OPMODE (4) + #define CORE_PPU_ELEMENT_INIT(_core_num) \ [PPU_V1_ELEMENT_IDX_CORE##_core_num] = { \ .name = "CORE" #_core_num, \ @@ -77,6 +80,7 @@ /* before accessing any registers external to */ \ /* the SCP */ \ .default_power_on = true, \ + .opmode = SCP_PPU_SYS##_systop_num##_OPMODE, \ }), \ } -- GitLab