diff --git a/ethosu/regor/compiler/scheduler.cpp b/ethosu/regor/compiler/scheduler.cpp
index fc61376b3fa3f342ca239ae1d0ecd9ac96846591..62e8bd0aec8ab4295ce691aec96da8be33d5045a 100644
--- a/ethosu/regor/compiler/scheduler.cpp
+++ b/ethosu/regor/compiler/scheduler.cpp
@@ -1098,7 +1098,7 @@ void Scheduler::ProposeWeightBuffering(SchedulerConnection *weights, SchedulerCo
     {
         // To be refined and architecture specific depending on mem2mem characteristics and prebuffering
         float bwRatio = std::round(
-            fullTransferCycles /
+            double(fullTransferCycles) /
             _arch->Performance()->MinReadCycles(weightTens->memArea.memory, fullWeightsBytes, TensorUsage::Weights,
                 schedOp->Type(), weightFormat % WeightFormat::Fast));
         needsDMA = (cost->elementAccess.weightsRefetch > 2) || (cost->elementAccess.weightsRefetch == 2 && bwRatio < 2);