From 28590d75a4770bf6b9cc261a37cacec85e3c25d0 Mon Sep 17 00:00:00 2001
From: Fredrik Svedberg <fredrik.svedberg@arm.com>
Date: Wed, 26 Mar 2025 11:21:44 +0100
Subject: [PATCH] MLBEDSW-10608 [MLCE] Seg Fault on 16-bit DepthwiseConv

Added missing case for slicing int64 bias, which was used
for int16 DepthWise.

Change-Id: I4932a5de401f3d726c206a3f24c3241c4df5ca10
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
---
 ethosu/regor/compiler/scheduler_decompose.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/ethosu/regor/compiler/scheduler_decompose.cpp b/ethosu/regor/compiler/scheduler_decompose.cpp
index c8918d00..bd02b241 100644
--- a/ethosu/regor/compiler/scheduler_decompose.cpp
+++ b/ethosu/regor/compiler/scheduler_decompose.cpp
@@ -555,6 +555,8 @@ Slice(SchedulerTensor *tensor, const Shape &offset, const Shape &shape, Shape re
             return SliceT<uint8_t>(tensor, offset, shape, readShape, stepXY);
         case DataType::Int32:
             return SliceT<int32_t>(tensor, offset, shape, readShape, stepXY);
+        case DataType::Int64:
+            return SliceT<int64_t>(tensor, offset, shape, readShape, stepXY);
         case DataType::Int48:
         {
             auto slice = SliceT<int48_t, int64_t>(tensor, offset, shape, readShape, stepXY);
-- 
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