Sahil authored Aug 11, 2022 and Sahil committed Jun 19, 2023

This patch adds a function to poll Nor flash memory's status register
bit (WIP bit) to wait for an erase/write operation to complete.
The polling timeout is set to 1 second.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ie678b7586671964ae0f8506a0542d73cbddddfe4

Sahil authored May 02, 2022 and Sahil committed Jun 19, 2023

Signed-off-by: sahil <sahil@arm.com>
Change-Id: If448ad95b2e72cef31ce1e1e5ab2504d607f0545

Sahil authored May 02, 2022 and Sahil committed Jun 19, 2023

Enable persistent storage on QSPI flash device.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I403113bb885d1d411d433a7f266715d007509a5e

Sahil authored May 02, 2022 and Sahil committed Jun 19, 2023

Add NOR flash DXE driver, this brings up NV storage on
QSPI's flash device using FVB protocol.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ica383c2be6d1805daa19afd98d28b943816218dd

Sahil authored May 02, 2022 and Sahil committed Jun 19, 2023

Add NOR flash library, this library provides APIs for getting the list
of NOR flash devices on the platform.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I39ad4143b7fad7e33b3b151a019a74f23e0ed441

Sahil authored May 02, 2022 and Sahil committed Jun 19, 2023

Enable SCP QSPI flash region access by adding it in the PlatformLibMem

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005

Himanshu Sharma authored May 30, 2022 and Sahil committed Jun 19, 2023

In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the
IPI0 trigger method to "level", which prevented SGI0 to be enabled
again after a CPU offline/online cycle.

This patch fixes the above issue by assigning a reserved IRQ ID
for the Debug UART, other than 0 and also routing it to use IOFPGA
UART1 by unsharing it from currently using serial terminal.

Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: Ib35fecc57f1d8c496135c18dbebd0be0a4b76041

Sahil authored Mar 17, 2022 and Sahil committed Jun 19, 2023

NT_FW_CONFIG DTB contains platform information passed by
Tf-A boot stage.
This information is used for Virtual memory map generation
during PEI phase and passed on to DXE phase as a HOB, where
it is used in ConfigurationManagerDxe.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I54a86277719607eb00d4a472fae8f13c180eafca

Fix some errors in the Readme file.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

When 0 address protection is enabled,
0-4k memory needs to be preallocated to
prevent UEFI applications from allocating use,
such as grub.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Regardless of the long standing desire to resume involvement
in the project, I'm unable to double the time in a day.
That's why I'm removing myself from sbsa-ref maintainers.

Signed-off-by: Radoslaw Biernacki <rad@semihalf.com>

Add 2 drivers (IntelVTdCorePei, IntelVTdCoreDxe)
for pre-boot DMA protection feature.

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Reviewed-by: Jenny Huang <jenny.huang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Robert Kowalewski <robert.kowalewski@intel.com>

MSFT:*_*_*_CC_FLAGS = /Od will disable build optimization.

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Reviewed-by: Jenny Huang <jenny.huang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Robert Kowalewski <robert.kowalewski@intel.com>

Today the delay is 10us but the QSP simulates the multiprocessor
by dividing time into segments and serializing processors within a
segment.
The length of the segment is configurable and Simics open board
is configured using 100us.

But the firmware configures the delay between INIT and SIPI is 10us.
That results a possible senarino that BSP sends a INIT and SIPI in one
segment (100us) while APs are still in SMM environment. The INIT is
queued but SIPI is ignored by Simics, resulting all APs being put in
wait-for-SIPI state when they receive INIT.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

This adds support SMBIOS Tables Type 16, 17, 19 for information of
Physical Memory, Memory Device and Memory Array Mapped Address.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

This refactor is derrived from ArmPkg/SMBIOS and customize to adapt
with platform. These changes help to separate each Type of SMBIOS table
into individual modules. It makes the structure of SmbiosPlatformDxe
module clear and easier to add new type of table.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

This implementation helps SMBIOS Table (Type 0, 1, 2, 3, 13, 32)
of Altra and AltraMax platform to utilize framework from ArmPkg.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

This corrects "PcdSmbiosTables1MajorVersion" and
"PcdSmbiosTables1MinorVersion" of SMBIOS Type 1,
these PCDs should be for Type 0.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

This enables NVMe Hot Plug feature after finishing PCIe set up. This
helps to detect NVMe disk when it's removed or inserted into its slot.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

This adds necessary changes of ACPI tables and defines the memory region
between OS and Trusted Firmware-A for supporting Hot Plug of Ampere
Altra Max.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

This adds necessary changes of ACPI tables and defines the memory region
between OS and Trusted Firmware-A for supporting Hot Plug of Ampere
Altra.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

As AMBA_LINK_TIMEOUT_OFF spec, it impacts OS Hot Plug removal delay.
The greater value the longer delay it is. Per experiments, set it 2 from
beginning of Root Port initialization for stable operation.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

In order to detect the NVMe after OS boots successfully but that NVMe's
not present previously. Hot Plug Slot Capable will help PCI Linux driver
to initialize its slot iomem resource which is used for detecting the
disk when it's inserted.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

This adds PCIe Hot Plug library to support Hot Plug feature and specific
procedures for setting different Portmap tables (GPIO pins used for PCIe
reset).

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>

Add PCIe link retry logic. If the card is detected to be present, allow
a retry for 3 times.

When the link is down, check if the LTSSMEN bit is cleared.  Based on
Altra PCIe IP, the LTSSMEN bit is cleared from 1 to 0 if there is a
surprising link down.  This indicates that a card is present.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>
Reviewed-by: Nhi Pham <nhi@os.amperecomputing.com>

Currently, the implementation starts link training and put device
out-of-reset right away. This make LinkStat and BlockEventStat registers
indicate that link is not up yet (LinkStat: 0x300 and BlockEventStat:
0x0).  This fix will start link training after putting device
out-of-reset.  The values of LinkStat and BlockEventStat registers after
this fix are respectively 0x1103 and 0x1 (Link is up).

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>
Reviewed-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
Reviewed-by: Nhi Pham <nhi@os.amperecomputing.com>

Because PCIe Auto bifurcation feature doesn't depend on the default
Devmap mode so that "DevMapModeAuto" is unnecessary in retrieving
the PCIe Devmap default mode.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>
Reviewed-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
Reviewed-by: Nhi Pham <nhi@os.amperecomputing.com>

The GIC addresses as currently declared as FixedPcd for SbsaQemu.
Change them to dynamic, to enable future patches to support these
being determined at runtime.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Graeme Gregory <graeme@xora.org.uk>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

gArmTokenSpaceGuid.PcdGicDistributorBase and
gArmTokenSpaceGuid.PcdGicRedistributorsBase are both defined as UINT64 in
ArmPkg.dec, but SbsaQemuAcpiDxe and its exported header file use
PcdGet32. While this currently works, it will break once these Pcds are
made dynamic - so fix.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Graeme Gregory <graeme@xora.org.uk>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

The patch moves the CpuPageTableLib reference from CoreDxeLib.dsc
to CoreCommonLib.dsc since now not only DxeMpInitLib but also CpuMpPei
depends on it.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

The loongarch qemu tcg code section is 16K aligned by default.
When UEFI keep 4K alignment, the code section and data section
of UEFI are loaded into the same page by qemu, and when the data
is written to the page containing the code section, it will cause
qemu to refresh TB, resulting in qemu running slowly.Therefore,
setting Dxe to 16K alignment can ensure that the code section is
loaded into a page separately, avoid qemu repeatedly refreshing TB,
and speed up the execution speed of qemu.

The following shows the impact of Dxe 4K alignment and 16K alignment
on image size:

DXE 4k alignment:
DXEFV.FV 7.2M
After compression:
FVMAIN_COMPACT.Fv 3.4M
QEMU_EFI.fd 3.7M

DXE 16k alignment:
DXEFV.FV 9.5M
After compression:
FVMAIN_COMPACT.Fv 3.4M
QEMU_EFI.fd 3.7M

Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Use debug print level DEBUG_MANAGEABILITY in
ManageabilityPkg.

Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Abdul Lateef Attar <abdattar@amd.com>
Cc: Nickle Wang <nicklew@nvidia.com>
Cc: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
Reviewed-by: Nickle Wang <nicklew@nvidia.com>
Reviewed-by: Abdul Lateef Attar <abdattar@amd.com>

Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Abdul Lateef Attar <abdattar@amd.com>
Cc: Nickle Wang <nicklew@nvidia.com>
Cc: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
Reviewed-by: Nickle Wang <nicklew@nvidia.com>
Reviewed-by: Abdul Lateef Attar <abdattar@amd.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4428



Calculating CRC based on each ACPI table.
Update HWSignature field in FACS based on CRC while ACPI table changed.

Change-Id: Ic0ca66ff10cda0fbcd0683020fab1bc9aea9b78c
Signed-off-by: VincentX Ke <vincentx.ke@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ankit Sinha<ankit.sinha@intel.com>
Signed-off-by: VincentX Ke <vincentx.ke@intel.com>
Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>
Reviewed-by: Ray Ni <Ray.ni@intel.com>

Customize PeiReportFvLib library for AMD platforms by
adding below changes.
  Installs Advanced Security FV.
  Adds facility to install FV above 4GB address space.

Cc: Abner Chang <abner.chang@amd.com>

Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>

Implements PCI hotplug init protocol.
Adds resources padding based on PCD values.

Cc: Abner Chang <abner.chang@amd.com>

Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>

DriverBindingSupport() is called lots of time during post.
If it's also included in the perf logging, it's very easy to use all
the FPDT table memory pre-allocated at EndOfDxe because the
driver binding connect process happens after EndOfDxe.

PcdExtFpdtBootRecordPadSize was added for holding the
perf-logging records after EndOfDxe. But the DriverBindingSupport
records are just too many. For example, SimicsOpenBoardPkg has
to set this PCD to almost 100x bigger than the default value in order
to hold all the perf-logging records.

Platform developers are usually not aware of missing some records
after EndOfDxe because those records are all about driverbinding
support/start/stop. But if we add more perf-logging inside SMM,
those SMM records will be missed in the final FPDT table because
DxeCorePerformanceLib collects those SMM records at ReadyToBoot
event. Since the FPDT cannot hold all driverbinding records, it
definitely cannot hold those SMM records as well.

So in order to hold all SMM perf loggings, either platform should
set PcdExtFpdtBootRecordPadSize to a large enough value, or
as what this patch does, to disable the driverbinding support
perf-logging.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang@liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang@liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>

build_bios.py supports caller to pass in "--performance" flag but the
script implemnetation just ignores this flag.

The patch adds the missing logic to invoke build.py with
"--pcd gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable=True"
when "--performance" is supplied.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang@liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>